Imaging systems and method of operating the imaging systems

Abstract

An imaging system includes a pixel array configured to generate a plurality of image charge-voltage signals in response to incident light, and a readout circuit system coupled to the pixel array, the readout circuit system comprising a plurality of row cells. Each row cell includes at least one of a plurality of comparators, wherein each comparator is coupled to receive a ramp signal from a ramp generator via a ramp signal line. Each row cell also includes a compensation current unit coupled to the ramp signal line, each compensation current unit including a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line.

Description

Distributed Ramp Linear Compensation Circuit This disclosure generally relates to image sensors, and more particularly but not exclusively to complementary metal oxide semiconductor (CMOS) image sensors. Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and the like of such image sensors in as many ways as possible (e.g., resolution, power consumption, dynamic range) through both device architecture design and image acquisition processing. The technology for manufacturing image sensors has continued to progress rapidly. For example, the demand for higher resolution and lower power consumption has promoted further miniaturization and integration of such devices. A typical image sensor operates in response to image light incident on the image sensor from an external scene. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes), which absorb a portion of the incident image light and immediately generate image charges after absorbing the image light. The image charges generated by the pixels can be measured as analog output image signals on row bit lines, which vary as a function of the incident image light. In other words, the amount of the generated image charges is proportional to the intensity of the image light, and the image charges are read out as analog image signals from the bit lines and converted into digital values to generate a digital image (e.g., image data) representing the external scene. The analog image signals on the bit lines are coupled to readout circuits, which include an input stage having analog-to-digital conversion (ADC) circuits to convert those analog image signals from the pixel array into digital image signals. An example of an imaging system having compensation current units distributed in a readout circuit is disclosed, the compensation current units providing improved ramp linearity. In the following description, numerous specific details are set forth to provide a thorough understanding of the example. However, those skilled in the art will recognize that the techniques described herein may be practiced without one or more of the specific details or may be practiced using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. References throughout this specification to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the disclosure. Thus, the appearances of the phrases "in an example" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples. Spatial relative terms, such as "beneath", "below", "upper", "lower", "above", "over", "top", "bottom", "left", "right", "center", "middle", and the like, may be used herein for ease of description to explain the relationship of one element or feature to another (other) element or feature illustrated in the figures. It will be understood that these spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, an element described as "beneath" or "below" or "under" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary terms "beneath" and "below" can encompass both an above and a below orientation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly. Additionally, it will be understood that when an element is referred to as being "between" two other elements, the element can be the only element between the two other elements, or there can also be one or more intervening elements. Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they pertain, unless specifically defined herein otherwise or the context in which they are used will clearly imply otherwise. It should be noted that in this document, element names and symbols may be used interchangeably (e.g., Si and silicon); however, both have the same meaning. As will be discussed, various examples of an imaging system having compensation current units dispersed in a readout circuit are disclosed, the compensation current units providing improved ramp linearity. In various examples, a readout circuit includes a plurality of row unit cells coupled to a ramp signal line to receive a ramp signal from a ramp generator, each row unit cell including a compensation current unit and one or more comparators. Each compensation current unit may include a compensation current source and a compensation current switch, the compensation current switch being bistable switchable during a readout period. In an image sensor using a single-slope analog-to-digital converter (ADC), non-linearity in the ramp signal is detrimental to the performance of the image sensor. In a conventional imaging system, when the ramp signal starts to rise or fall (depending on the polarity of the ramp signal), there is a large linear error near the start of the ADC. Existing methods for solving this error include adding a step signal to the ramp signal and compensating for the steady error in the ramp signal. However, one cause of the linear error is the metal wiring resistance ("parasitic resistance") inherent in the ramp signal line through which the ramp signal propagates, and the aforementioned methods involve changing the operation of the ramp generator, so the parasitic resistance remains a problem. As the size of the image sensor increases with large format sensors, this metal wiring resistance of the ramp signal line cannot be ignored. In various examples of the present disclosure, a plurality of compensation current units are dispersed in a readout circuit such that one compensation current unit is included in each row of unit cells. In various examples, one compensation current unit is shared among multiple rows of unit cells. Each compensation current unit can be controlled (e.g., via a switch included in the compensation current unit) to locally draw current from or supply current to a ramp signal. In various examples, a local parasitic capacitance is locally charged by the current. In various examples, the charging current is localized and does not actually flow through the parasitic resistance, thereby reducing the IR drop across the ramp signal line. In various examples, an imaging system includes a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and a readout circuitry coupled to the pixel array, the readout circuitry including a plurality of row unit cells. Each row unit cell includes at least one of a plurality of comparators (e.g., one comparator, two comparators, three comparators, etc.), where each comparator is coupled to receive a corresponding one of the image charge voltage signals from the pixel array via a row bit line, compare the corresponding one of the image charge voltage signals with a ramp signal from a ramp generator, and provide a digital representation of the corresponding one of the image charge voltage signals in response, and where each comparator is coupled to receive the ramp signal from the ramp generator via a ramp signal line. Each row unit cell also includes a compensation current unit coupled to the ramp signal line, each compensation current unit including a compensation current source and a compensation current switch coupled to the compensation current source, where the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line. For illustrative purposes, FIG. 1 shows an example of an imaging system 100 having a readout circuit 106 according to the teachings of the present disclosure, the readout circuit including row unit cells 122. Specifically, FIG. The example illustrated in FIG. 1 shows an imaging system 100 including a pixel array 102, bit lines 112, a control circuit 110, a readout circuit 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array of a plurality of pixel circuits 104 (e.g., P1, P2,..., Pn), the plurality of pixel circuits being configured in a number of columns (e.g., R1 to Ry) and a number of rows (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., the image data then being usable to reproduce an image of a person, place, object, etc. In various examples, the readout circuit 106 can be configured to read out the image charge voltage signal via the row bit lines 112. As will be discussed, in various examples, the readout circuit 106 can include an analog-to-digital converter (ADC). As shown in the illustrated example, the ADC 118 is coupled to the row bit lines 112 and is configured to convert the analog signal from the row bit lines 112 into a digital signal. In various examples, row amplifiers can also be included, and the row amplifiers can be coupled to the row bit lines 112 to amplify the analog signal received from the row bit lines 112 for conversion into a digital signal by the ADC 118. In various examples, the ADC 118 includes a ramp generator 114 and row cell elements 122. The ramp generator 114 has a ramp generator output, and a ramp signal is provided from the ramp generator output to the row cell elements 122 via a ramp signal line 120. In an example, the digital image data value generated by the row cell elements 122 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or otherwise). In one example, the control circuit 110 is coupled to the pixel array 102 to control the operation of a plurality of photodiodes in the pixel array 102. For example, the control circuit 110 can generate a rolling shutter or a shutter signal for controlling image acquisition. In other examples, the image acquisition is synchronized with an illumination effect such as a flash. In one example, the imaging system 100 can be included in a digital camera, a mobile phone, a laptop computer, an endoscope, a security camera, or an imaging device for an automobile or the like. Additionally, the imaging system 100 can be coupled to other hardware components, such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), illumination / flash, electrical inputs (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware components can deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100. Figure 2 illustrates a schematic diagram of a portion of an exemplary readout circuit 206 including a compensation current unit 230 in accordance with the teachings of the present disclosure. It should be understood that Figure the readout circuit 206 of FIG. Figure 2 can be an example of the readout circuit 106 included in the imaging system 100 shown in FIG. The readout circuit 206 may include a global ramp generator 214 configured to generate a ramp signal. The ramp signal is provided to a plurality of row cell elements 222 via a ramp signal line 220. In the illustrated embodiment, each row cell element 222 includes at least one of a plurality of comparators 216. Thus, in one embodiment, each row cell element 222 includes one comparator 216. In another embodiment, each row cell element 222 may include two comparators 216, etc. Each comparator 216 may be coupled to receive an image charge voltage signal from a pixel array 202 via one of a plurality of bit lines 212, and receive the ramp signal from one of a plurality of nodes 228a, 228b, … 228n (collectively referred to as "nodes 228") along or on the ramp signal line 220. As shown in the illustrated example, the ramp signal line 220 spans several rows of the pixel array 202 to provide the ramp signal to the plurality of row cell elements 222. Each comparator 216 then compares the image charge voltage signal with the ramp signal and provides a digital representation of the image charge voltage signal in response. Each row cell element 222 may include a compensation current unit (CCU) 230 and a representative local parasitic capacitance 242, each coupled to a respective one of the nodes 228 on the ramp signal line 220. The output of each comparator 216 is coupled to a counter 226 configured to respond to when the comparator 216 flips, thereby indicating when the image charge voltage signal from the bit line 212 intersects the ramp signal from the ramp signal line 220. In various examples, each row cell element 222 may further include a local ramp buffer coupled between the respective node 228 and the comparator 216. In the illustrated embodiment, the row cell elements 222 are coupled to different ones of the nodes 228 on the ramp signal line 220. In fact, the ramp signal line 220 has an inherent metal wiring resistance ("parasitic resistance") R along its length P 240. When the ramp signal starts to rise or fall (depending on the polarity of the ramp signal), this parasitic resistance R P 240 may cause a linear error in the ramp signal near the start of the ADC. For row cell elements 222 coupled further along the ramp signal line 220, this linear error is greater. As will be elaborated further below, in accordance with the teachings of the present disclosure, the compensation current units 230 distributed among the row cell elements 222 along the ramp signal line 220 spanning the pixel array 202 may be controlled to locally draw current from or supply current to the ramp signal and reduce the current flowing along the ramp signal line 220 through the parasitic resistance R PChange in current of 240. Figure FIG. 3 illustrates a schematic diagram of a portion of an exemplary read circuit 306 including a compensation current unit 330 in accordance with the teachings of the present disclosure. It should be understood that Figure the compensation current unit 330 of FIG. 3 can be an example of one of the compensation current units 230 shown in Figure FIG. 2, and elements with similar names and numbers described above are similarly coupled and operative hereinafter. In the illustrated embodiment, the compensation current unit 330 and a representative local parasitic capacitance C P 342 can be included in a row of unit cells. A ramp signal generated by a ramp generator 314 can propagate along a ramp signal line 320 to an output node VO 315, which can be coupled to an input of a comparator (e.g., Figure the comparator 216 illustrated in FIG. 2). The compensation current unit 330 can include a compensation current source 334 and a compensation current switch 332 coupled to the compensation current source 334. The compensation current source 334 and the compensation current switch 332 are coupled between a first node 328 on the ramp signal line 320 and a second node 339 coupled to ground 338. When the compensation current switch 332 is off, the compensation current source 334 is part of an open circuit, so no current flows. When the compensation current switch 332 is on, the compensation current source 334 can draw current I C 336 from or supply the current to the ramp signal line to locally charge / discharge the local parasitic capacitance 342. Since both the compensation current unit 330 and the local parasitic capacitance 342 are coupled to the ramp signal line 320 and ground 338, the current I C 336 only flows locally and there is virtually no current flowing to ground 338 or along the ramp signal line 320 through the parasitic resistance R P 340. Specifically, reducing the current flow to ground 338 can reduce power line noise (e.g., linear or horizontal noise going to ground 338), which can affect image quality. Figure FIG. 4 illustrates a schematic diagram of a portion of an exemplary read circuit 406 including a compensation current unit 430 in accordance with the teachings of the present disclosure. It should be understood that Figure The compensation current unit 430 of 4 can be an example of the compensation current unit 230 shown in FIG. 2, and components with similar names and numbers described above are similarly coupled and function hereinafter. In the illustrated embodiment, each of the compensation current units 430 in the compensation current unit and the representative local parasitic capacitance C P 442 can be included in a row of unit cells. Each compensation current unit 430 can include a compensation current source 434 and a compensation current switch 432 coupled to the compensation current source 434. The compensation current source 434 and the compensation current switch 432 are coupled between a first node 428a / b / … / m / n and a second node 439. The first node is on a ramp signal line 420 that is coupled to propagate a ramp signal generated by a ramp generator 414. The second node is coupled to ground 438. The compensation current switch 432 can be configured to be controlled by a switch signal Ramp_en 462. In the illustrated embodiment, all the compensation current switches 432 are configured to be controlled by the same switch signal Ramp_en 462. When the compensation current switch 432 is off, the compensation current source 434 is part of an open circuit, so no current flows. When the compensation current switch 432 is on, the compensation current source 434 can draw current I C 436 from the ramp signal line 420 or supply the current to the ramp signal line to charge / discharge the local parasitic capacitance 442. Since both the compensation current unit 430 and the local parasitic capacitance 442 are coupled to the ramp signal line 420 and ground 438, the current I C 436 only flows locally and there is actually no current flowing to ground 438 or along the ramp signal line 420 through the parasitic resistance R P 440. FIG. 5 illustrates a read cycle timing diagram of a compensation current unit in an exemplary read circuit according to the teachings of the present disclosure. It should be understood that FIG. The timing diagram of 5 can be a timing diagram for operating an example such as FIG. 4 shows an exemplary timing diagram of the compensation current unit 430, and components with similar names and numbers described above are similarly coupled and function hereinafter. In the timing diagram illustrated, the switch signal Ramp_en 562 is configured to remain off prior to the ramp signal's linear period (i.e., between times t1 and t2). At time t1, the switch signal Ramp_en 562 is toggled to on, enabling a compensation current source (e.g., FIG the compensation current source 434 illustrated in FIG. 4) to draw current I from a ramp signal line (e.g., ramp signal line 420) C 536 or supply the current to the ramp signal line to charge a local parasitic capacitance (e.g., local parasitic capacitance 442) as the ramp signal decreases. The switch signal Ramp_en 562 can be configured to remain on throughout the linear period and toggled to off at time t2, causing the current I C 536 to drop back to zero as the ramp signal returns to its nominal voltage level. As discussed above with respect to FIG 3 and FIG 4, by locally drawing current I C 536 from or supplying the current to the ramp signal line, the local parasitic capacitance can be locally charged and current flow through the parasitic resistance on the ramp signal line can be effectively avoided. Thus, the linear error at the start of the linear period can be reduced. Additionally, there is a negligible IR drop along the ramp signal line, such that the voltage values at various nodes along the ramp signal line (e.g., Vramp 528a, Vramp<m> 528m, Vramp<n> 528n) can be equal throughout the ADC cycle, as FIG 5 shows. In other embodiments, it should be understood that, in accordance with the teachings of this disclosure, the polarity of the ramp signal and the polarities of the corresponding circuit elements can be reversed such that the ramp signal begins to rise at time t1. FIG 6A, FIG 6B, and FIG 6C illustrate schematic diagrams of three exemplary compensation current units 630 in accordance with the teachings of this disclosure. It should be understood that FIG 6A, FIG 6B, and FIG The compensation current unit 630 of 6C can be an example of the compensation current unit 230 shown in FIG. 2, and components with similar names and numbers described above are similarly coupled and operative hereinafter. Referring first to FIG. 6A, the compensation current unit 630 includes a compensation current source NB 634 and a first compensation current switch SWA 632 between an output node Vramp<n> 628 coupled to a ramp signal line (e.g., FIG. 4) and ground 638. The compensation current source NB 634 can be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to a bias voltage source VBN 686. The first compensation current switch SWA 632 can be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to be controlled by a first switch signal Ramp_en 662. When the first switch signal Ramp_en 662 is toggled to on, the compensation current source NB 634 can draw or supply current I C 636 to the output node. In various examples, the compensation current unit 630 may also include a first stacking device NCA 678 coupled to the first compensation current switch SWA 632 such that the compensation current source NB 634, the first compensation current switch SWA 632, and the first stacking device NCA 678 are coupled between the output node Vramp<n> 628 and ground 638. The first stacking device NCA 678 can be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to a bias voltage source VCN 676. During a read cycle, the first stacking device NCA 678 can at least partially decouple (i.e., electrically isolate) the first compensation current switch SWA 632 from the output node Vramp<n> 628 on the ramp signal line such that the channel capacitance of the first compensation current switch SWA 632 does not affect the stability of the ramp signal at the output node Vramp<n> 628. In various examples, the first stacking device NCA 678 can alternatively be coupled between the compensation current source NB 634 and the first compensation current switch SWA 632. In various examples, the compensation current unit 630 may further include a first sample and hold circuit (SHC) 670 coupled between a bias voltage source VCN 676 and a first stacked device NCA 678. The first SHC may include a capacitor 674 coupled between the stacked device NCA 678 and ground 638 and an SHC switch 672 coupled between the bias voltage source VCN 676 and the first stacked device NCA 678. In various examples, the compensation current unit 630 may further include a second SHC 680 coupled between a bias voltage source VBN 686 and a compensation current source NB 634. The second SHC may include a capacitor 684 coupled between the compensation current source NB 634 and ground 638 and an SHC switch 682 coupled between the bias voltage source VBN 686 and the compensation current source NB 634. Each of the first SHC 670 and the second SHC 680 may be configured to at least partially decouple the output node Vramp<n> 628 from the bias voltage source VCN 676 or the bias voltage source VBN 686, respectively, such that noise does not propagate from the bias voltage source to the output during a read cycle. Next, referring to Figure 6B, the compensation current unit 630 is generally similar to the embodiment illustrated in Figure 6A, but has an additional "branch" to a node coupled between the compensation current source NB 634 and the first compensation current switch SWA 632. The branch includes a second compensation current switch SWB 692 coupled between the compensation current source NB 634 and a power line VDD 664. The second compensation current switch SWB 692 may be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to be controlled by a second switch signal Swb_en 696. In various embodiments, the branch may further include a second stacked device NCB 698 coupled to the second compensation current switch SWB 692. The second stacked device NCB 698 may be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to the same bias voltage source VCN 676 as the first stacked device NCA 678. In other embodiments, the first stacked device NCA 678 and the second stacked device NCB 698 may have gate terminals coupled to different bias voltage sources. The second compensation current switch SWB 692 may be switched bi-statically to allow a pre-charge current I CB 690 to flow to the compensation current source NB 634. As will be described below with respect to Figure More specifically, the branch can reduce the current I during the read cycle. C One of the delays in 636. Next, refer to Figure 6C, the compensation current unit 630 and Figure The embodiment illustrated in 6B is generally similar, but in which the second stacking device NCB 698 is "incorporated" into the first stacking device NCA 678. In addition, the stacking device NCA 678 is coupled between the compensation current source NB 634 and each of the first compensation current switch SWA 632 and the second compensation current switch SWB 692. In various examples, the ground 638 can be replaced by a non-zero voltage source, as will be described in more detail below with respect to Figure 8 and Figure 9. Thus, the compensation current source NB 634, the first compensation current switch SWA 632, and the second compensation current switch SWB 692 and / or the first stacking device NCA 678 and the second stacking device NCB 698 can be PMOS transistors. Figure 7 illustrates a read cycle timing diagram of a compensation current unit in an exemplary read circuit according to the teachings of the present disclosure. It should be understood that Figure The timing diagram of 7 can be used for operating an example such as Figure An exemplary timing diagram of the compensation current unit 630 shown in 6B, and the similarly named and numbered components described above are coupled and function similarly below. In the illustrated timing diagram, a second switch signal Swb_en 796 can be configured to be pulsed before the ramp period (i.e., between times t1 and t2). Thus, a precharge current I CB 790 can flow to a compensation current source (e.g., Figure The compensation current source NB 634 illustrated in 6B). At time t1, the second switch signal Swb_en 796 can be toggled off, and a first switch signal Ramp_en 762 can be toggled on to allow the compensation current source to draw current I from a corresponding node Vramp 728a, Vramp<m> 728m, Vramp<n> 728n on the ramp signal line. C 736 or supply the current to the corresponding node. At time t2 (i.e., at the end of the uniform change period), the first switch signal Ramp_en 762 can be bistatically switched to off, which causes the current I C 736 to drop back to zero as the ramp signal returns to its nominal voltage level. Figure 6B and Figure The circuit system and timing diagram illustrated in Figure 7 respectively provide an advantage over Figure the circuit system illustrated in Figure 6A. Referring back to Figure 6A, although the first switch signal Ramp_en 662 remains off before the uniform change period, the voltage level at the drain terminal of the compensation current source 634 can be pulled down to ground because the compensation current source is still configured to conduct current. When the first switch signal Ramp_en 662 is bistatically switched to on at time t1, the voltage level at the drain terminal of the compensation current source 634 starts to increase (or decrease, depending on the polarity) and eventually reaches a specific voltage level at which the compensation current source 634 can draw or supply the ideal current I C 636 for compensation. However, while the voltage level at the drain terminal of the compensation current source 634 is changing, the first stacked device NCA 678 can draw an excessive current and cause an undesired interference on the node Vramp<n> 628 on the ramp signal line. Figure The additional "branch" illustrated in Figure 6B can solve this problem. As Figure shown in Figure 7, pulsing the second switch signal Swb_en 696 / 796 before the uniform change period allows the compensation current source NB 634 to draw a precharge current I CB 690, which can precharge the drain terminal of the compensation current source 634 before the uniform change period. Then, at time t1, when the second switch signal Swb_en 696 / 796 is bistatically switched to off and the first switch signal Ramp_en 662 / 762 is bistatically switched to on, the compensation current source NB 634 can be switched to draw or supply the current I C 636 with a smaller change in the voltage level at the drain terminal of the compensation current source 634, thereby reducing the optimal current I C Delay one of the 636 and reduce any unwanted interference on the node Vramp<n> 628 on the ramp signal line. Figure FIG. 8 illustrates a schematic diagram of a part of an exemplary read circuit including a compensation current unit according to the teachings of the present disclosure. It should be understood that Figure The compensation current unit 830 of FIG. 8 can be an example of the compensation current unit 230 shown in Figure FIG. 2, and components with similar names and numbers described above are similarly coupled and operative hereinafter. In the illustrated embodiment, each of the compensation current units 830 in the compensation current unit and the representative local parasitic capacitance C P 842 can be included in a row of unit cells. Each compensation current unit 830 can include a compensation current source 834 and a compensation current switch 832 coupled to the compensation current source 834. The compensation current source 834 and the compensation current switch 832 are coupled between a first node 828a / b / … / m / n on a ramp signal line 820 coupled to a ramp generator 814 and a second node 839, and the second node is coupled to a non-zero voltage source (i.e., a power line) VDD 838. The compensation current switch 832 can be configured to be controlled by an inverted switch signal Ramp_en_ 863. The inverted switch signal Ramp_en_ 863 can be an inverted signal of a non-inverted switch signal Ramp_en 862 (e.g., via an inverter 868). In the illustrated embodiment, all the compensation current switches 832 are configured to be controlled by the same inverted switch signal Ramp_en_ 863. Figure FIG. 9 illustrates a read cycle timing diagram of a compensation current unit in an exemplary read circuit according to the teachings of the present disclosure. It should be understood that Figure The timing diagram of FIG. 9 can be a timing diagram for operating an example of the compensation current unit 830 shown in Figure FIG. 8, and components with similar names and numbers described above are similarly coupled and operative hereinafter. In the timing diagram illustrated, the inverted switch signal Ramp_en_963 is the inverted form of the non-inverted switch signal Ramp_en 962. Before the ramp period (i.e., before time t1), the inverted switch signal Ramp_en_963 can be configured to remain on, allowing a compensation current source (e.g., compensation current source 834) to draw current I C 936 from a power line (e.g., VDD 838) and supply the current I C 936 to a ramp generator (e.g., ramp generator 814). Then at time t1 (i.e., the start of the ramp period), the inverted switch signal Ramp_en_963 can be toggled off, deactivating the compensation current unit (e.g., compensation current unit 830) and allowing the ramp generator to charge a local parasitic capacitance (e.g., local parasitic capacitance 842). At time t2 (i.e., the end of the ramp period), the inverted switch signal Ramp_en_963 can be toggled back on, allowing the current I C 936 to flow again. As compared with FIG 3 to FIG 7 of the illustrated embodiments, FIG 8 and FIG 9 of the illustrated embodiments may have several disadvantages. One disadvantage is that, since the compensation current unit 830 and the local parasitic capacitance 842 are coupled to different voltage levels (i.e., VDD 838 and ground respectively), toggling the inverted switch signal Ramp_en_863 / 963 can change the currents at their respective voltage level nodes, resulting in power line noise (e.g., linear or horizontal noise) that affects image quality. Another disadvantage is that, since the current I C 936 flows before time t1, there may be an IR drop along the ramp signal line 820, as FIG is illustrated by the changing voltage levels at nodes Vramp<n> 928n, Vramp<m> 928m, and Vramp 928a in FIG. 9. However, in various examples, the IR drop can remain constant during the ADC cycle because the charging current supplied by the ramp generator 814 during the ADC cycle can be configured to be equal to the current I supplied to the ramp generator 814 during non-ADC cycles (e.g., before time t1). C 836 / 936, thereby reducing or eliminating changes in the current flowing through the ramp signal line 820. FIG. 8 and FIG. One advantage of the illustrated embodiment in FIGS. 8 and 9 is that the compensation current source 834 is disabled during the ADC cycle, so the design does not need to account for random noise, current matching, etc., because the ramp signal and the current conducted by the compensation current source flow through the readout circuit simultaneously. Another advantage is that in various embodiments, the settling time can be shortened. The above description of the illustrated examples of the present disclosure, which includes the content set forth in the abstract of the invention, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific examples of the present disclosure have been illustrated herein for purposes of explanation, as those skilled in the art will recognize, various modifications can be made within the scope of the present disclosure. Such modifications to the present disclosure can be made in light of the above detailed description. The terms used in the appended claims should not be construed as limiting the present disclosure to the specific examples disclosed in the specification. Rather, the scope of the present disclosure will be determined entirely by the appended claims, which are to be construed in accordance with the principles of claim construction. 100: Imaging system 102: Pixel array 104: Pixel circuit 106: Readout circuit 108: Functional logic 110: Control circuit 112: Bit line / Row bit line 114: Ramp generator 118: Analog-to-digital converter 120: Ramp signal line 122: Row cell unit 202: Pixel array 206: Readout circuit 212: Bit line 214: Global ramp generator 216: Comparator 220: Ramp signal line 222: Row cell unit 226: Counter 228a - 228n: Nodes 230: Compensation current unit 240: Intrinsic metal wiring resistance / Parasitic resistance 242: Representative local parasitic capacitance 306: Readout circuit 314: Ramp generator 315: Output node 320: Ramp signal line 328: First node 330: Compensation current unit 332: Compensation current switch 334: Compensation current source 336: Current 338: Ground 339: Second node 340: Parasitic resistance 342: Representative local parasitic capacitance / Local parasitic capacitance 406: Readout circuit 414: Ramp generator 420: Ramp signal line 428a - 428n: First node 430: Compensation current unit 432: Compensation current switch 434: Compensation current source 436: Current 438: Ground 439: Second node 440: Parasitic resistance 442: Representative local parasitic capacitance / Local parasitic capacitance 462: Switch signal 528a: Node 528m: Node 528n: Node 536: Current 562: Switch signal 628: Output node / Node 630: Compensation current unit 632: First compensation current switch 634: Compensation current source 636: Current / Ideal current / Optimal current 638: Ground 662: First switch signal 664: Power line 670: First sample and hold circuit 672: Sample and hold circuit switch 674: Capacitor 676: Bias voltage source 678: First stacked device / Stacked device 680: Second sample and hold circuit 682: Sample and hold circuit switch 684: Capacitor 686: Bias voltage source 690: Precharge current 692: Second compensation current switch 696: Second switch signal 698: Second stacked device 728a: Corresponding node 728m: Corresponding node 728n: Corresponding node 736: Current 762: First switch signal 790: Precharge current 796: Second switch signal 814: Ramp generator 828a - 828n: First node 830: Compensation current unit 832: Compensation current switch 834: Compensation current source 836: Current 838: Non-zero voltage source / Power line 839: Second node 842: Representative local parasitic capacitance / Local parasitic capacitance 862: Non-inverting switch signal 863: Inverted switch signal 868: Inverter928a: Node 928m: Node 928n: Node 936: Current 962: Non-inverted switch signal 963: Inverted switch signal C1-Cx: Row C P : Representative local parasitic capacitance I C : Current / Ideal current / Optimal current I cb : Precharge current NB: Compensation current source NCA: First stacked device / Stacked device NCB: Second stacked device P1-Pn: Pixel circuit R1-Ry: Column Ramp_en: Switch signal / First switch signal / Non-inverted switch signal Ramp_en_: Inverted switch signal R P : Intrinsic metal wiring resistance / Parasitic resistance SWA: First compensation current switch SWB: Second compensation current switch Swb_en: Second switch signal t1: Time t2: Time VBN: Bias voltage source VCN: Bias voltage source VDD: Non-zero voltage source / Power line V O : Output node Vramp: Node / Corresponding node Vramp<m>: Node / Corresponding node Vramp<n>: Node / Output node / Corresponding node Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, in which like reference numerals refer to like components throughout the views, unless otherwise specified. Figure 1 illustrates an example of an imaging system including a pixel array according to the teachings of the present disclosure. Figure 2 illustrates a schematic diagram of an exemplary readout circuit including a compensation current unit according to the teachings of the present disclosure. Figure 3 illustrates a schematic diagram of an exemplary readout circuit including a compensation current unit according to the teachings of the present disclosure. Figure 4 illustrates a schematic diagram of an exemplary readout circuit including a compensation current unit according to the teachings of the present disclosure. Figure 5 illustrates a readout cycle timing diagram of a compensation current unit in an exemplary readout circuit according to the teachings of the present disclosure. Figure 6A, Figure 6B and Figure FIG. 6 is a schematic diagram illustrating three exemplary compensation current units according to the teachings of the present disclosure. FIG FIG. 7 is a timing diagram illustrating a read cycle of a compensation current unit in an exemplary readout circuit according to the teachings of the present disclosure. FIG FIG. 8 is a schematic diagram illustrating a portion of an exemplary readout circuit including a compensation current unit according to the teachings of the present disclosure. FIG FIG. 9 is a timing diagram illustrating a read cycle of a compensation current unit in an exemplary readout circuit according to the teachings of the present disclosure. Throughout several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in each figure may be enlarged relative to other elements to help improve the understanding of the various embodiments of the present disclosure. Additionally, common and well-known elements that are useful or necessary in a commercially viable embodiment are typically not shown to facilitate an unobstructed view of these various embodiments of the present disclosure. 202: Pixel array 206: Readout circuit 212: Bit line 214: Global ramp generator 216: Comparator 220: Ramp signal line 222: Row cell 226: Counter 228a - 228n: Node 230: Compensation current unit 240: Intrinsic metal wiring resistance / parasitic resistance 242: Representative local parasitic capacitance R P : Intrinsic metal wiring resistance / parasitic resistance

Claims

1. An imaging system comprising: A pixel array configured to generate a plurality of image charge voltage signals in response to incident light; The system includes a readout circuitry coupled to the pixel array, the readout circuitry comprising a plurality of row cells, each row cell including: at least one of a plurality of comparators, each comparator being coupled to receive a corresponding image charge voltage signal from the pixel array, compare the corresponding image charge voltage signal with a ramp signal from a ramp generator, and in response provide a digital representation of the corresponding image charge voltage signal, and wherein each comparator is coupled to receive the ramp signal from the ramp generator via a ramp signal line; and a compensation current unit coupled to the ramp signal line, including: a compensation current source; and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line.

2. The imaging system of claim 1, wherein each row cell further includes a local parasitic capacitance coupled to the first node, wherein each compensation current cell is configured to locally conduct current through the local parasitic capacitance of the respective row cell.

3. The imaging system of claim 1, wherein each compensation current unit further includes a sample and hold circuit coupled between the compensation current source and a bias voltage source.

4. The imaging system of claim 1, wherein each compensation current unit further includes a stacking device coupled to the compensation current switch, wherein the compensation current source, the stacking device and the compensation current switch are coupled between the first node and the second node.

5. The imaging system of claim 4, wherein the overlay device is coupled between the first node and the compensation current switch.

6. The imaging system of claim 4, wherein each compensation current unit further includes a sample and hold circuit coupled between the stacking device and a bias voltage source.

7. The imaging system of claim 1, wherein the compensation current switch is a first compensation current switch, and wherein each compensation current unit further includes a second compensation current switch coupled between the compensation current source and a power line.

8. The imaging system of claim 7, wherein each compensation current unit further includes a stacking device coupled to the second compensation current switch, wherein the stacking device, the second compensation current switch and the compensation current source are coupled between the power line and the second node.

9. The imaging system of claim 1, wherein each second node is coupled to ground.

10. The imaging system of claim 1, wherein each second node is coupled to a non-zero voltage value.

11. The imaging system of claim 1, wherein the compensation current unit of each row cell is separate from the ramp generator.

12. The imaging system of claim 1, wherein the compensation current unit of each row cell is configured to draw current from or supply current to the ramp signal line when started.

13. The imaging system of claim 1, wherein the compensation current unit of each row cell is configured to locally conduct current when started, such that a negligible amount of current flows through a parasitic resistance on the ramp signal line.

14. A method of operating an imaging system, comprising: A plurality of row cell units are coupled to a pixel array, wherein each row cell unit includes: at least one of a plurality of comparators, wherein each comparator is coupled to receive a ramp signal from a ramp generator via a ramp signal line; and a compensation current unit coupled to the ramp signal line, including: a compensation current source; and a compensation current switch coupled to the compensation current source, wherein the compensation current switch is configured to be controlled by a switch signal, and wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line; a bi-state switching is performed on each switch signal at the beginning of one of the uniformity cycles; and a bi-state switching is performed on each switch signal at the end of one of the uniformity cycles, thereby causing the compensation current source to generate a compensation current.

15. The method of claim 14, wherein each row cell further includes a local parasitic capacitance coupled to the first node, and wherein bi-state switching of each switching signal at the beginning and end of the uniform cycle causes the compensation current to be locally conducted through the local parasitic capacitance in each individual row cell.

16. The method of claim 14, wherein the compensation current switch is a first compensation current switch, wherein the switch signal is a first switch signal, wherein each compensation current unit further includes a second compensation current switch coupled between the compensation current source and a power line, wherein the second compensation current switch is configured to be controlled by a second switch signal, the method further comprising: A pulse is applied to the second switching signal before the start of the uniform change cycle, thereby pre-charging the compensation current source and reducing the delay of the compensation current before the start of the uniform change cycle.

17. The method of claim 16, pulse the second switching signal including turning off the second switching signal at the beginning of the uniformity period.

18. The method of claim 14, wherein each second node is coupled to ground, wherein performing a dual-state switching of the switch signal at the beginning of the uniform change cycle includes turning on the switch signal at the beginning of the uniform change cycle, and wherein performing a dual-state switching of the switch signal at the end of the uniform change cycle includes turning off the switch signal at the end of the uniform change cycle.

19. The method of claim 14, wherein each second node is coupled to a non-zero voltage value, wherein performing a dual-state switching of the switching signal at the beginning of the uniform-changing period includes turning off the switching signal at the beginning of the uniform-changing period, and wherein performing a dual-state switching of the switching signal at the end of the uniform-changing period includes turning on the switching signal at the end of the uniform-changing period.

20. An imaging system comprising: One-pixel array; The system includes a readout circuitry coupled to the pixel array, the readout circuitry comprising a plurality of row cells, each of the plurality of row cells being coupled to receive a ramp signal from a ramp generator via a ramp signal line, wherein each row cell includes a comparator configured to compare an image charge voltage signal received from the pixel array with the ramp signal received from the ramp generator, and a compensation current unit having (a) a compensation current source and (b) a compensation current switch configured to selectively couple the compensation current source to the ramp signal line.

Images