MEMS device built using the beol metal layers of a solid state semiconductor process

Abstract

This invention discloses a MEMS device formed using BEOL material in a CMOS process, wherein a post-processing and backing of a vHF process are applied to form the MEMS device, and wherein the overall size of the MEMS device is between 50 μm and 150 μm. This MEMS device can be implemented as an inertial sensor and other applications.

Description

A microelectromechanical device formed using a back-end process metal layer of a solid-state semiconductor process This application as a whole relates to MEMS devices, and more particularly, to techniques for manufacturing MEMS devices. An integrated circuit is a semiconductor device having a substrate with a semiconductor material, and a series of layers are deposited on the substrate using photolithography techniques. These layers are doped and polarized such that electrical components (e.g., resistors, capacitors, or impedances) or electronic components (e.g., diodes or transistors) are produced. Subsequently, other layers are deposited, which form the structure of the interconnect layers required for electrical connections. Microelectromechanical or microelectromechanical systems (MEMS) are small electromechanical devices formed using layer deposition techniques based on photolithography. MEMS can provide cavities or hollow spaces inside them, which can be filled with liquids or gases. Conventional integrated circuits are completely solid devices, i.e., without any type of void. A void can be defined as a cavity larger than the void at the atomic or subatomic scale. Inside the MEMS, there can be movable elements. The movable elements can be connected to the rest of the MEMS structure by one of their ends, or can be completely loose inside a housing (i.e., not physically attached to its surroundings), and the housing is at least partially closed (to prevent the loose part from "escaping" from the MEMS). A wafer can contain a MEMS device and an integrated circuit (IC), where the IC can control the MEMS. Currently, the main problem with MEMS devices is the need for a certain manufacturing process. Solid-state electronic devices do not achieve this. Solid-state electronic devices have tended to follow a manufacturing standard known as complementary metal-oxide semiconductor (CMOS), which has many variants, mainly classified according to its nodes. This is the minimum feature size that can be resolved in the front-end process (FEOL). In fact, most MEMS ICs found on the market today consist of a package with two dies inside. One of these dies is sourced from a CMOS wafer, and the other is sourced from a MEMS wafer produced by a certain manufacturing process. The dies inside the package are usually wire-bonded and encapsulated using a plastic package. For a combined IC that requires several MEMS devices, there may need to be more than two dies inside the package, one being a CMOS with control electronics, and several MEMS dies, each of which is fabricated in a different process. This requirement for a proprietary process for each MEMS manufacturer and each type of MEMS device has several problems: cost, size, time to market, performance, and mass production capacity. Since 90% of the semiconductor industry consists of solid-state ICs, i.e., without MEMS, and most of them use CMOS processing for fabrication, most semiconductor companies use the so-called fabless model, outsourcing all products to large CMOS foundries, whose business is only focused on producing CMOS wafers. Compared with the largest MEMS foundries, this generally brings 100 times or even higher economies of scale globally. This is the reason why the cost of MEMS processing is more expensive than the cost of CMOS wafers. However, the cost of a MEMS wafer can be lower than the cost of a CMOS wafer, especially when considering lower nodes, because the complexity of a CMOS process is greatly increased compared to MEMS. But for the same level of complexity, the cost of CMOS will be much lower than any MEMS process. If the same CMOS process can be used to build MEMS, the cost of the entire IC will be significantly reduced. This is because we don't need two dies from the beginning, and only one is needed inside the package. Therefore, we will eliminate the MEMS die and simplify the package. There is a desire to reduce the size of the IC, especially for applications such as smart phones, and particularly in applications where space is very limited, such as wearable devices and specifically earbuds. The best packaging technology currently used to minimize the overall size of the IC is wafer-level chip-scale packaging (WLCSP). This essentially involves depositing a sealing layer on top of the wafer to protect the wafer, the bumping process of the solder pads, and then dicing the wafer, and performing an optional backgrinding beforehand. There may be additional steps in the process, such as RDL (redistribution layer), but they are not necessary or mandatory in all implementations. However, if more than one die needs to be packaged, WLCSP cannot be used. If MEMS can be built in the same CMOS die, we will be able to apply WLCSP to package it, thus greatly reducing the overall packaged die, and if possible, different types of MEMS devices can be implemented in the same CMOS process. Then, a manufacturer may be able to build a combined chip packaged with WLCSP. Compared with the multi-die plastic packaging counterparts currently used, this will result in a greater reduction. When developing a new MEMS device, a new process needs to be developed to build the new MEMS device. Since the volume to be processed in this process is typical for the MEMS market for consumers and is therefore very large, and in order to minimize costs and expect a high yield, this is a complex project that usually takes several years and is costly. If the same existing CMOS process can be used to build MEMS and is ready for high-volume production at a relatively low cost, the time to market will be very short because only the device needs to be developed. There is no need to spend time (and cost) developing a certain manufacturing process. Due to the different economies of scale between a CMOS process and a MEMS process, the equipment used in the CMOS process is the current state-of-the-art technology, while for the MEMS process, they are usually old equipment to reduce the cost of setting up such MEMS processes. This means that the minimum feature size (also known as the critical dimension) of the CMOS process is usually smaller than that of the MEMS process. Therefore, if CMOS processes can be used to fabricate MEMS, they will be able to manufacture MEMS devices with small feature sizes. This will help improve device performance because softer springs / diaphragms and smaller gaps can be created. In addition, if MEMS can be fabricated using CMOS processes, they will minimize the parasitic capacitance that occurs when connecting MEMS to the electronic interface (usually sensing / driving) circuits in a CMOS die. This is usually done via wire bonding inside a plastic package, which typically adds about 1 pF to 10 pF of capacitance. If MEMS are fabricated inside the same CMOS process, this parasitic capacitance resulting from the connection between the MEMS and the electronic device will typically be reduced to 1 fF to 10 fF. This is a 100-fold to 1000-fold reduction. Since parasitic capacitance degrades the performance of MEMS devices, reducing the parasitic capacitance can improve the performance of MEMS ICs because the parasitic capacitance masks the capacitance of the MEMS device. Improving performance means increasing the sensitivity of the sensor, reducing its power consumption, or a combination of both. Furthermore, as already mentioned, mainstream CMOS foundries have high-volume production capabilities, which are more than 100 times that of major MEMS foundries. Therefore, if we can use CMOS processing to fabricate MEMS devices, we will benefit from this greater high-volume production capacity. This will allow us to address new markets such as the Internet of Things (IoT), which would otherwise be impossible. Currently, due to the limited high-volume production capabilities of MEMS suppliers, it is difficult for MEMS suppliers to serve the existing MEMS market. The IoT is expected to increase the current MEMS market size by 100 times or more. Currently, this can only be achieved when fabricating MEMS devices using a mainstream CMOS foundry. Some companies use a monolithic solution to fabricate MEMS together with CMOS. At the end of the process, this leaves a single die with both CMOS and MEMS. Two options for creating this are to bond the MEMS and CMOS wafers together after separate fabrication, or to fabricate the MEMS wafer on top of a completed CMOS wafer instead of starting from a blank silicon wafer. In both cases, a certain MEMS process is required. These monolithic solutions reduce the size of the IC because wire bonding is not needed, and WLCSP can be used with them. Also, due to the lower parasitic interconnect capacitance between the MEMS and CMOS (usually as low as between 100 fF and 1 pF), their performance is also improved. However, prior methods still have problems with cost, time to market, and high-volume production capabilities because they always require a complete custom MEMS process. Similarly, it would still be much better if we could build MEMS using a CMOS process while reducing size and increasing performance. Because in terms of size, the profile will always be larger because essentially, we are placing two dies stacked on top of each other. But for CMOS, it is one die, and this can be backgrinded. In terms of performance, this is a 10-fold reduction in parasitic capacitance compared to the conventional two-die packaging solution, but building a MEMS device using a CMOS process will reduce it by 100 times. And finally, if we only have a single MEMS device or sensor, these monolithic solutions are effective. If we need a combination chip of different types of sensors, this can no longer be used. But by building all these MEMS devices using a CMOS process, we maintain a single-die solution that can be backgrinded. Therefore, when we turn to combination chips, the cost and size advantages of building MEMS using a CMOS process will increase significantly. The reduction in cost and size, especially when we turn to combination chips, is partly due to the reduction of many bond pads that are no longer needed. Given the known advantages, if we can use a CMOS process to build MEMS devices, several solutions have been proposed. The initial solution was to propose modifying the CMOS process to add some steps to build MEMS devices. Depending on whether these are performed at the beginning, middle, or end of the CMOS process, the solutions are called pre-processing, in-processing, or post-processing. Because MEMS devices need to modify the CMOS process, if they need to perform a mechanical movement, they need to leave some space inside the IC to perform this movement. And this space cannot be produced by CMOS. Another reason for the modification is to add different materials or layers with different mechanical properties that are not found in the CMOS process. Given the huge cost of implementing modern CMOS processes in mainstream foundries, and the cost of keeping them stable to maintain extremely high yields while maintaining extremely high volumes, pre-process and in-process modifications have been abandoned. The only remaining option is CMOS post-processing to implement MEMS. CMOS post-processing means that after the manufacture of the CMOS wafer is completed, it goes through several additional manufacturing steps where MEMS is implemented. However, unlike the monolithic methods of wafer bonding or building MEMS on top of the CMOS wafer explained previously, in this case, we only create the space required to allow the mechanical movement of MEMS. And then we build MEMS using the materials existing inside the CMOS wafer. Although one possibility is to implement MEMS using polysilicon, this requires a deep etching from the top of the wafer to reach there, so first etching all backend processes (BEOL) or etching from the backside requires a deep etching through the silicon substrate. This requires a complex process, which will not be cost-effective. Then the only remaining solution is to implement MEMS using the materials present in the BEOL of CMOS. Since the BEOL is the topmost part of the CMOS die, this will require the least post-processing and thus the minimum cost. For this, different solutions have been proposed, for example, using a combination of plasma and / or wet etching with HF and other chemicals. These processes are difficult to mass-produce with a high yield, especially when wet etching is involved. A simple post-processing method previously proposed involves using a single vapor HF (vHF) maskless post-processing step. vHF etches away the silicon oxide present between the metal layers of the BEOL and it retains all the metals. This was proposed by Baolab. Due to its simplicity, it is the lowest-cost CMOS post-processing method. In addition, it can be implemented in the same CMOS foundry or in a packaging or assembly room. In this method, MEMS devices are built using metal layers (usually Al or AlCu and W), but there can also be other metal layers similar to Cu. Proper design can trap the oxide inside the metal shell. Other materials can be used, but they must be present in the CMOS BEOL. Most previous methods use a special packaging, such as a laminate packaging (e.g., LGA), in order to protect the MEMS. This increases the cost and size, thus minimizing or eliminating the size and cost advantages, in other cases where we would use CMOS processes to build the MEMS. Baolab suggests using the topmost metal layer to protect the MEMS while leaving small holes to allow vHF to enter the inside of the MEMS cavity. Later, a second set of post-processing steps consisting of Al sputtering and patterning will be applied to properly seal the MEMS device. This usually increases the cost of the CMOS process by 10%. This simplifies the packaging requirements and no longer requires the use of a laminate or other special packaging. Instead, any standard packaging technique, such as QFN or others, can be used. This reduces the cost and size of the final IC. In addition to the top metal layer, the bottom metal layer is used to complete the metal cavity for positioning the MEMS device. Considering that most CMOS processes have a doped silicon oxide (which is the bottommost metal layer) below M1, this is achieved to limit the vHF etching towards the bottom. The doped silicon oxide reacts very strongly to vHF, rapidly increasing the etching rate and leaving very poor residues that are difficult to remove. This makes the design portable to most CMOS processes, in other cases, it would only be applicable to special processes that do not have doped silicon oxide below the bottommost metal layer of the BEOL. Like other solutions for implementing MEMS devices using materials in the BEOL, Baolab's solution surrounds the MEMS device with metal walls that define the MEMS cavity within the ASIC die. In this way, the electronic devices are placed around it. The implementation of these metal walls is formed by a stack of a metal layer (usually made of aluminum) and vias (usually tungsten). However, if we use a lower CMOS node of a process below 0.18 um, the materials can be different, mainly copper. In principle, this is not a vertically straight wall because DRC rules require the metal layer to extend beyond the edge of the via. However, if we are concerned about increasing the lateral area exposed on the wall (for example, in the case of a planar capacitor sensor), some exceptions can be made to this. This will be a DRV that the foundry has to accept. Using Baolab's solution, the vertical metal walls can, in principle, connect the top and bottom metal planes, thus shorting all the MEMS cavities electrically. Usually, we don't concern ourselves with this, or at least it doesn't occur at any position in all the cavities. To solve this problem, Baolab uses a vertically staggered anchor structure. These structures force the vHF to move up and down on the silicon oxide layer until it is exhausted, thus leaving some unetched silicon oxide. In this way, we obtain a mechanically consistent wall without shorting the top and bottom metal plates electrically. One reason this is particularly effective is that, usually, the silicon oxide layer deposited between the metal layers in the BEOL of a CMOS process consists of two different sub-layers, each with a different oxide density. Therefore, one of these layers is etched more slowly by vHF than the other. Thus, it is more difficult (i.e., takes more time) to etch the silicon oxide in the vertical direction with vHF than in the horizontal direction because the etching then propagates faster along one of the silicon oxide sub-layers. With these anchor structures, we force the vHF to etch on all the slow etching rate sub-layers and cannot propagate quickly through the fast sub-layer. These staggered anchors can also be used to add rows or columns at different positions in the MEMS to provide more consistency with the top metal plane. Given that subsequent sealing is usually supported by Al sputtering, it is particularly important that the top metal plane does not bend, which would ultimately damage or render unusable the MEMS device. The main problem with these anchor walls is that, although they provide mechanical stability while keeping the top and bottom metal planes electrically disconnected, the capacitance between them is very large. This is because of the large surfaces placed close to each other inside the staggered anchor structure, one surface connected to the top and the other to the bottom plate, and worse still, a large part of this is filled with silicon oxide. Another problem related to the previous one is that this parasitic capacitance between the top metal plate and the bottom metal plate presents a critical trade-off between production yield and reliability. To minimize this parasitic capacitance, we can minimize the length of the anchor structure, reduce the number and / or the height of the fingers, and / or we can increase the etching time. Thus, if we desire to minimize this parasitic capacitance, we will have a smaller anchor structure and after vHF etching, there will be little silicon oxide left inside these structures. However, this will be a very weak structure, due to mechanical shock, vibration, or simply mechanical failure that can easily occur when sealing or packaging the device. It will also reduce the yield. Since a slight over-etching will completely remove the silicon oxide inside the anchor structure, resulting in the collapse of the top and bottom parts and rendering the device completely unusable. In production, we need to avoid this requirement for a critical vHF etching because it will always lead to a lower yield. The reason is that the etching rate and the silicon oxide etched inside the MEMS cavity depend on both the vHF machine and the applied recipe, as well as the CMOS process. Although we can strictly control the vHF machine and its recipe, we cannot control the CMOS process, which usually has a tolerance of about 30%. In addition to potentially requiring all metal layers to implement MEMS devices, special packaging procedures are therefore needed, requiring a special CMOS process without doped silicon oxide under the bottom-most metal plate and with a large parasitic capacitance. Two main problems with using the materials in CMOS BEOL to implement the MEMS solution are yield and reliability. When we use the Baolab method, these problems are more critical in the case of the top and bottom metal planes. However, if we do not use them, the process will become more complex and expensive, thus losing the cost advantage, as well as the mass production, time-to-market, and even performance advantages. One of the main problems found when implementing MEMS devices using the BEOL metal of a CMOS process is the vertical stress gradient. This is minimized in a customized MEMS process. However, in a CMOS, since these metal lines (not intended to implement mechanical structures but only for electrical connection) in a solid-state IC are surrounded by silicon oxide, there is no concern about residual stress, which usually results in a larger value. In addition to the larger residual stress, we usually find a larger vertical stress gradient. This causes the metal to bend or curl (usually upwards), but depending on the layer, it can be downwards, especially on the top layer. When we use the top and bottom metal planes, this bending is a big problem. Because the available vertical clearance distances above and below the device are very small, and it can easily touch them. When the MEMS device touches the top or bottom metal plane, it will become unusable. This results in poor yield and reliability. One possibility to slightly reduce this problem is to increase this vertical gap distance, thereby reducing the number of metal layers for the MEMS device itself. However, since the gap becomes larger, this will reduce the out-of-plane performance, and thus, the relative capacitance change for a given sensor for the same displacement will be reduced. Similarly, in the case of an inertial sensor, we will be forced to use a smaller proof mass and cannot use all available metal layers, thereby reducing the performance even more. Moreover, reducing the number of metal layers used to build the movable part of the device (such as the proof mass in the case of an inertial sensor) will even increase its curvature more, as explained below. Therefore, it is necessary to minimize the curvature height of the MEMS device. This is defined as the maximum vertical displacement in the out-of-plane direction along any metal layer of all MEMS devices or one of its specific components. A known solution to solve this problem is to stack two or more metal layers. In this way, we increase the radius of curvature of the resulting metal structure and thus reduce the total curvature height. However, and although this is a good solution for designing some parts of the MEMS device (such as the proof mass of an inertial sensor), we want to make them as large as possible during manufacturing to improve the sensitivity of the sensor, but for other parts (such as springs), it results in extremely high stiffness, thereby significantly reducing the sensitivity. In fact, the stiffness is inversely proportional to the cube of the length and thickness. Therefore, increasing the thickness quickly leads to very stiff springs. This means that the sensitivity of the sensor is very low and the driving voltage of the actuator is very high. In addition, the number of metal layers in the process limits the stacking of many layers, and if it is necessary to modify or use a CMOS process with a larger number of metal layers in the BEOL, this will quickly increase its cost. In summary, it is necessary to find the correct design of implementing MEMS devices by reusing the BEOL materials existing in a standard CMOS process, using vHF to etch away part of the silicon oxide in the MEMS cavity (which can be packaged with WLCSP later), and by virtue of these devices, having a very high yield, reliability, and performance. Another problem with using a vHF etching post-treatment step after CMOS is that the SiN passivation layer is deposited and patterned on top of the CMOS wafer, which is partially etched away by vHF. This means that, in fact, unless a very short vHF etching step is performed, the SiN passivation layer will be largely or completely etched away. This will leave poor residues in the wafer and will expose all wafers with ASIC regions where the silicon oxide should not be etched. One known solution to prevent this is to increase the silicon content of the passivation layer, typically by measuring the refractive index or RI of the layer. Although technically this is not complex, it requires a process fine-tuning, and for large mainstream foundries, it is very challenging for them to receive this fine-tuning. Ultimately, this requirement means that we will no longer be able to use a completely standard CMOS process, and thus we will lose the advantages of low cost, short time to market, and high mass production capacity to some extent. In various embodiments, the application addresses defects associated with manufacturing MEMS devices. In various aspects, the system, device, and method originate from vHF etching or use vHF etching to etch away a portion of the silicon oxide in the BEOL of a CMOS process, thus releasing the materials present in the BEOL that will form the MEMS device. The method of the present invention uses a bottom metal plane and a top metal plane having an array of small holes to allow vHF to enter the inside of the MEMS cavity. A key inventive concept is to limit the entire MEMS size on the layout between 50 µm and 150 µm, and preferably less than 100 µm. For a given radius of curvature of a MEMS device or component, the total curvature height depends on the horizontal dimension. Thus, if the device is small enough, then despite having a large vertical stress gradient, the curvature height will be limited. A second inventive concept is the design of the springs. In order to have good performance on these small devices, small and soft springs are needed, while also maintaining a small curvature height. These seemingly contradictory requirements. Short springs mean that they will be very stiff, thus reducing the sensitivity (performance) of these MEMS sensors. To have soft springs, we will need to minimize their thickness, which means minimizing the metal stack or not using it at all. But this will increase the vertical stress gradient, thus rapidly increasing the total curvature height. A preferred inventive solution to the spring design problem is to use a set of at least three springs instead of one, which are evenly distributed around the device, rotating around the central axis of the device, such that by symmetry, the MEMS device cannot tilt after being released by the vHF etching. In the case of an inertial sensor, the MEMS device may include a central verification mass made of several metal stacks, such that it is relatively flat compared to the springs around it. To have sufficient sensitivity, this verification mass can also be larger than the springs. If the spring or the springs holding it are bent, then if the verification mass tilts, although the verification mass itself is relatively flat, ultimately it will still have a large curvature height. However, if the springs are evenly positioned around it and there are at least three such springs, then due to the curvature of the springs, the verification mass will experience a small vertical displacement, but it will be flat, and thus will not contribute to the total vertical height due to its larger size. In a particular embodiment, the center mass will have a circular shape, and the springs around it will have a helical shape and be made of a stack of only one metal layer or only two metal layers. If a stack of two metal layers is used, we will connect them with a via layer between them. In a preferred embodiment, this via layer will have the same linear or helical shape as the metal layers above and below it, but in principle it will be slightly narrower in the lateral direction to satisfy the DRC rules at each point in at least one horizontal direction. Throughout this application, when we say that we use a stack of a particular set of metal layers, it should be understood that we will use the via layers between them to keep them connected. Using circular and rounded shapes for the proof mass, the springs, and generally for as much as possible of the MEMS device avoids the higher mechanical stresses that would otherwise accumulate at the right angles of the device geometry. These rounded shapes then facilitate the balancing of the stress in the springs, and when we use an array of at least three evenly distributed springs around it, it causes a horizontal tilt of the center mass that we need. One aspect includes a MEMS device formed using materials of the BEOL of a CMOS process, where a post-processing and post-lithography of vHF is applied to form the MEMS device, and a total size of the MEMS device is between 50 um and 150 um. The total size of the MEMS device can be less than 100 um. In some embodiments, the total size of the MEMS device is less than or equal to 50 um. The MEMS device can include a set of at least three springs that are evenly distributed around the MEMS device and rotate around a central axis of the MEMS device or one of its movable parts. The device shape can be circular, and the springs can have a helical shape. The springs can be made of a stack of a single metal layer or at least two metal layers. The MEMS device can include an inertial sensor. The MEMS device can include a proof mass. The proof mass can be formed or made of a stack of four metal layers and the springs, where the springs are connected to a top metal layer of the proof mass forming the stack, or to two top metal layers of the stack. The springs can be connected to an outer ring such that after the vHF etching, a part of the outer ring remains buried in the silicon oxide at its outer edge. In some embodiments, the MEMS device has a top metal plane and a bottom metal plane smaller than the top metal plane. The width of the outer ring of the bottom metal plane can be less than or equal to 10% to 50% of the width of the outer ring of the top metal plane. The width of the outer ring of the bottom metal plane can be about 30% of the width of the outer ring of the top metal plane. The MEMS device can be formed in a MEMS cavity that does not contain a metal filling structure. In some embodiments, a MEMS device is configured to have a larger capacitance so that (for example) more conventional sensing circuits can be used to measure the MEMS capacitance. An array of MEMS devices connected in parallel can be utilized to establish the MEMS device. Each of these MEMS devices will have its own passivation opening and will be completely disconnected except for the lines / traces for electrical connection. In another aspect, a MEMS device includes a set of at least three springs that are evenly distributed around the MEMS device and rotate around a central axis of the MEMS device. The shape of the device can be circular, and the springs can have a helical shape. The springs can be made of a single metal layer or a stack of at least two metal layers. The MEMS device can include an inertial sensor. The MEMS device can include a proof mass, where the proof mass is made of a stack of four metal layers and the springs, and where the springs are connected to a top metal layer of the proof mass forming the stack, or to two top metal layers of the stack. In a further aspect, a MEMS device includes springs, where the ratio of the maximum displacement to the spring length is at least 1%. The MEMS device can include a proof mass, where the proof mass is made of a stack of four metal layers and the springs, and where the springs are connected to a top metal layer of the proof mass forming the stack, or to two top metal layers of the stack. The springs can be connected to an outer ring such that after vHF etching, a portion of the outer ring remains buried in silicon oxide on its outer edge. The MEMS device can include top and bottom metal planes, where the width of the outer ring of the bottom metal plane is less than or equal to 10% to 50% of the width of the outer ring of the top metal plane. Another aspect is a method for manufacturing a MEMS device using materials for BEOL of a CMOS process, which includes: applying a post-treatment and post-liner of vHF to form the MEMS device, where the total size of the MEMS device is between 50 um and 150 um. The total size of the MEMS device can be less than 100 um. The method can further include forming a set of at least three springs that are evenly distributed around the MEMS device and rotate around a central axis of the MEMS device. The method may include forming a device shape that is circular and forming the springs having a helical shape. The method may include fabricating the springs with a stack of either a single metal layer or at least two metal layers. The method may form a MEMS device including an inertial sensor. The method may include forming a proof mass, where the proof mass is fabricated with a stack of four metal layers and the springs, and where the springs are connected to a top metal layer of the stack forming the proof mass, or to two top metal layers of the stack. The method may include connecting the springs to an outer ring such that after the vHF etching, a portion of the outer ring remains buried in silicon oxide at its outer edge. The method may include forming the MEMS device having a top metal plane and a bottom metal plane smaller than the top metal plane. The method may include forming an outer ring width of the bottom metal plane that is less than or equal to 10% to 50% of the width of the outer ring of the top metal plane. The method may include forming the outer ring width of the bottom metal plane to be about 30% of the width of the outer ring of the top metal plane. The method may include forming the MEMS device within a MEMS cavity that does not include a metal fill structure. In a further aspect, a method of manufacturing a MEMS device includes forming a set of at least three springs that are evenly distributed around the MEMS device or its movable part and rotate around a central axis of the MEMS device or its movable part. The method may include forming a shape of the MEMS device that is circular and forming the springs having a helical shape. The method may include fabricating the springs with a stack of either a single metal layer or at least two metal layers. The method may include forming the MEMS device including an inertial sensor. The method may include forming a proof mass, where the proof mass is fabricated with a stack of four metal layers and the springs, and where the springs are connected to a top metal layer of the stack forming the proof mass, or to two top metal layers of the stack. In yet a further aspect, a method for manufacturing a MEMS device includes forming springs where the ratio of the maximum displacement to the spring length is at least 1%. The method may include forming a proof mass having a stack of four metal layers and the springs, where the springs are connected to a top metal layer of the stack forming the proof mass, or to two top metal layers of the stack. The method may include connecting the springs to an outer ring such that after the vHF etching, a portion of the outer ring remains buried in silicon oxide at its outer edge. The method may include forming an outer ring width of a bottom metal plane that is less than or equal to 10% to 50% of the width of an outer ring of a top metal plane. In a further aspect, a smartphone, wearable device, earbud, or Internet of Things (IoT) device includes a MEMS device according to the foregoing aspects. Although applicable in principle to CMOS, all of the inventive concepts described in this paragraph and throughout this application may also be applicable to the BEOL of any other solid-state semiconductor process, such as BiCMOS, GaAs, SiGe, GaN, SOI, etc. Any two or more features described in this specification (including this invention content paragraph) may be combined to form an embodiment not specifically described in this specification. Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings and from the claims of the invention. References to Related Applications This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 133,596, filed on January 4, 2021, entitled "MEMS Device Built Using the BEOL Metal Layers of a Solid State Semiconductor Process", U.S. Provisional Patent Application No. 62 / 958,369, filed on January 8, 2020, entitled "Leverage Ultrasound Transducer (LUT) using MEMS", U.S. Provisional Patent Application No. 63 / 000,195, filed on March 26, 2020, entitled "Systems and Methods for Inertial Sensors Having an Array of Spiral Springs", and U.S. Provisional Patent Application No. 63 / 000,199, filed on March 26, 2020, entitled "Systems and Methods for an Air Compliance Barometer using MEMS CMOS Devices". The entire contents of the patent applications cited above are incorporated herein by reference. In various aspects, the present application addresses deficiencies associated with the manufacture and / or structure of MEMS devices. In various aspects, the systems, devices, and methods originate from or use vHF etching to etch away portions of silicon oxide in the BEOL of a CMOS process, thereby releasing the materials present in the BEOL that will form the MEMS device. The method of the present invention uses a bottom metal plane and a top metal plane having an array of small holes to allow vHF to enter the inner side of the MEMS cavity. A key inventive concept is to limit the overall MEMS size on the layout to between 50 µm and 150 µm, and preferably less than 100 µm. For a given radius of curvature of a MEMS device or component, the total curvature height depends on the horizontal dimension. Thus, if the device is small enough, the curvature height will be limited despite having a large vertical stress gradient. A second inventive concept is the design of the springs. For good performance on these small devices, small and soft springs are needed while also maintaining a small curvature height. These seem to be conflicting requirements. Short springs mean they will be very stiff, thus reducing the sensitivity (performance) of these MEMS sensors. To have soft springs, we would need to minimize their thickness, which means minimizing the metal stack or not using it at all. But this will increase the vertical stress gradient, thus rapidly increasing the total curvature height. A preferred inventive solution to the spring design problem is to use a set of at least three springs instead of one, which are evenly distributed around the device, rotating around the central axis of the device, such that by symmetry, the MEMS device cannot tilt after being released by the vHF etching. In the case of an inertial sensor, the MEMS device includes a central proof mass made of several metal stacks, such that it is relatively flat compared to the springs around it. To have sufficient sensitivity, this proof mass can also be larger than the springs. If the spring or springs holding it are bent, then if the proof mass tilts, although the proof mass itself is relatively flat, ultimately it will still have a large curvature height. However, if the springs are evenly positioned around it and there are at least 3 of them, then due to the curvature of the springs, the proof mass will experience a small vertical displacement, but it will be flat and thus will not contribute to the total vertical height by virtue of its larger size. Figure 1 shows a center and / or proof mass 100 of a MEMS device having three springs 102, 104, and 106, which springs are connected to and / or made as part of the circumference of the device and are evenly spaced around the circumference. The proof mass 100 also includes an array of etched holes 108. In a particular embodiment, the center mass 100 will have a circular shape, and the springs 102, 104, and 106 around it will have a helical shape and be made from a stack of only one metal layer or only two metal layers or more than two layers. Using circular and rounded shapes for the proof mass 100, the springs 102, 104, and 106, and generally for as much of the MEMS device as possible, avoids the higher mechanical stresses that would otherwise accumulate at the right angles of the device geometry. Next, these rounded shapes promote a balance of the stresses in the springs 102, 104, and 106, which, when we use an array of at least three evenly distributed springs 102, 104, and 106 around it, results in a horizontal tilt of the center mass 100 that we need. Although the number of springs can be increased such that we can use four or more, and this will further help to achieve the horizontal tilt of the center proof mass 100, a particular embodiment has only three springs because in other cases the overall stiffness of the MEMS device will increase proportionally with the number of springs, thus reducing its sensitivity. In this application, we will use the term "inertial sensor" to refer to various devices that sense acceleration. This can include at least an accelerometer, a motion detector, and a bone conduction sensor. Their physical operating principles are the same, but their differences lie in the frequencies they detect. Therefore, their bandwidths and whether they need to sense direct current (DC), as well as their resolution and / or sensitivity requirements. Another embodiment can use a straight pair of springs located on opposite sides of the proof mass 100 such that each pair of springs lies on the same straight line. This solution is effective because in most CMOS processes, the residual stress of the metal wires is found to be tensile, sometimes except for the topmost metal layer. As such, the curvature is minimized. However, this solution results in a relatively high stiffness, which also highly depends on the device temperature. Therefore, this is a solution that can be applied to some MEMS devices, especially when a higher mechanical resonance frequency is required and the temperature dependence of the spring stiffness is not important. If the proof mass (e.g., in the case of an inertial sensor) of the MEMS device attached to the springs or the center part is thicker than the springs and is thus made from a larger metal layer stack, then a preferred embodiment is to use the upper metal layer to make the springs if no one connects the center part or the proof mass of the MEMS to the top metal plane. This will minimize the parasitic capacitance of the springs and support the outer ring towards the lower metal plate. FIG. 2 is an exploded view of the metal and via layers of a MEMS device 200, not showing the SiO 2 , passivation layer, and substrate. FIG. 2 depicts an out-of-plane inertial sensor. It is built using a 6-metal BEOL CMOS process. The metal layers are numbered M1 (bottom) to M6 (top). There are 5 via layers, numbered V1 (between M1 and M2) to V5 (between M5 and M6), although V1 is not used in this particular design. The proof mass has a circular structure with three helical springs evenly placed around it and the diameter of the proof mass plus the springs is 50 μm. The proof mass is made of a stack of metal layers M2 to M5 and the springs of stacked metal layers M4 and M5. The proof mass has concentric rings made of via layers V2 to V4, which stop at etched holes that vertically cross the proof mass. The top metal plane has the same diameter, plus an outer ring with a width of 20 μm around it, which is equivalent to a circle with a diameter of 90 μm. In both the X and Y directions, there is an array of 0.8-μm holes spaced approximately 5 μm apart between the centers of every two holes. The springs have a surrounding ring with a width of 20 μm around them, which is built on the same layers M4 and M5. There is an array of concentric vias connecting these rings and the top metal plane on these rings. That is, they are implemented at layers V4 and V5. There is a circular bottom metal plane made of M1, and also with a diameter of 50 μm plus an outer ring with a width of 6 μm, so it is smaller than the outer ring of the top layer of the top metal plane and the support of the springs. The inner circle and the outer ring together are equivalent to a circle with a diameter of 62 μm. The difference between the inner circle and the outer ring comes from the fact that after vHF etching, the outer ring is partially etched and the edges remain buried (and subjected) to silicon oxide. The top passivation layer is opened in a circular shape with a diameter of 50 μm, which is above the MEMS device. The MEMS device 200 includes an M6 layer 202, a V5 layer 204, an M5 layer 206, a V4 layer 208, an M4 layer 210, a V3 layer 212, an M3 layer 214, a V2 layer 216, an M2 layer 218, and an M1 layer 220. The M6 layer 202 includes a top plate 222 having etched holes configured in an array and connected to an ASIC. The V5 layer 204 includes an array of concentric through-hole rings 224 extending above the external metal. The M5 layer 206 includes a verification mass top cover 226 having an array of etched holes. Layer 206 also includes a portion of a helical spring 228 and an external metal ring 230. The V4 layer 208 includes an array of concentric through-hole rings 232 extending above the external metal, a portion of the helical spring 228 extending in the V4 layer 208, and an array of concentric through-hole rings 236 extending over the verification mass and stopping at the etched hole positions while surrounding the hole positions with a square ring. The M4 layer 210 includes a verification mass plane 238 having an array of etched holes, a portion of the helical spring 228, and a portion of the external metal ring 230. The V3 layer 212 includes an array of concentric through-hole rings 244 extending over the verification mass and stopping at the etched hole positions while surrounding the hole positions with a square ring. The M3 layer 214 includes a verification mass metal plane 246 having an array of etched holes. The V2 layer 216 includes an array of concentric through-hole rings 248 extending over the verification mass, stopping at the etched hole positions and surrounding them with a square ring. The M2 layer 218 includes a verification mass metal bottom cover 250 which includes an array of etched holes. The M1 layer 220 includes a bottom metal plane 252 which includes a connection to the ASIC. A preferred embodiment of an accelerometer using a 6-metal layer process is as follows, where the M1 layer 220 is the bottom layer and the M6 layer 202 is the top layer. The M1 layer 220 will be used to implement the bottom plane, and the M6 layer 202 is used to implement the top metal plane, which will be shorted to the verification mass and the spring. The verification mass will be implemented using a stack of the M2 layer 218 to the M5 layer 206. And the helical spring 228 will be implemented using only the M5 layer 206 or a stack of the M4 layer 210 and the M5 layer 206. If we set the total diameter of the verification mass plus the spring, then the length or maximum angle of the spring rotation is an optimal value. Longer springs (longer total angles) mean they will be softer, but the verification mass will be smaller. Shorter springs will allow a larger verification mass, but the springs will be stiffer. Therefore, there is always an optimal value, which will depend on the specific design and procedural nature. However, generally speaking, it is difficult to use springs with angles greater than 360° to build a reliable device with a good yield. That is, preferably, each individual spring does not complete one turn around a circular verification mass. Another parameter that affects design yield, performance, and reliability is the spacing around the spring. That is, the horizontal spacing or gap present at each point of the spring (except at the edges of the spring, as they start and end by fusing with the outer ring or anchor / wall and the proof mass or other MEMS parts) in the absence of any other spring, proof mass, anchor, or any part of the device. Clearly, this needs to be at least equal to the minimum spacing set by the design rule check (DRC) of the process. However, in practice, we set it to a higher value, between 2 times and 10 times this minimum spacing set by the DRC of the process. A preferred value is 5 times. For example, in the case of an 180 nm process with a minimum gap DRC of 300 nm between metals, we preferably set this horizontal spacing of the spring to 1.5 μm. The trade-off here is that for very large spacings, we will reduce sensitivity and / or performance because we will reduce the proof mass area and thus the mass for the same spring length (and thus achieve a given softness / stiffness of the spring). But reducing this horizontal spacing between the springs will result in poor yield and reliability. Another key aspect of the springs (which is particularly important when they are softer), compared to displacement (both vertical (i.e., out-of-plane) and horizontal (i.e., in-plane)), such as in the case where we use a set of three or more helical springs evenly distributed around a central proof mass, is to make them short enough. Since we have a small proof mass and we need very soft springs to achieve sufficient sensitivity, in principle, this easily gives rise to stiction problems, which will result in poor reliability of these MEMS devices. Figure 3 is a scaled view 300 of layer M4 210 of the MEMS device of Figure 2. Layer M4 210 includes: a 50 μm circular metal plane 302 inside the proof mass; helical springs 306; an external 20 μm wide ring 304 that is partially buried in silicon oxide at the outer part after vHF etching to support the springs and thus the proof mass; and an array 308 of etching holes that pass through the proof mass. Figure 4 is a scaled view 400 of layer M5 206 of the MEMS device of Figure 2. Layer M5 400 includes a proof mass lid 402 with an array of etching holes, helical springs 404, and an external metal ring 406. Figure 5 is a scaled view 500 of layer V4 208 of the MEMS device of Figure 2. Layer V4 500 includes an array 502 of concentric through-hole rings that extend over the proof mass, stop at the positions of each etching hole 504, and surround each hole 504 with a square ring. Layer 500 also includes an array 508 of concentric through-hole rings that extend over the external metal. FIG. 6 is an exploded 3D view 600 of the metal layer (showing the remaining silicon oxide, passivation layer, and substrate, such as M6 layer 202) of the MEMS device of FIG. 2 that includes etched holes 602, an outer ring 604, and a connection 606 to the ASIC (upper electrode and verification mass). M1 layer 220 includes a lower electrode connection 608 to the ASIC. FIG. 7 shows a side view 700 of the metal layers M1 to M6 and via layers V2 to V5 (since V1 is empty) of the MEMS device of FIG. 2, which include connections 702 to the ASIC (upper electrode and verification mass), a top metal plane 704, an outer ring 706, a verification mass 708, a bottom metal plane 710, and a lower electrode connection 712 to the ASIC. FIG. 8 is a cross-sectional schematic view 800 of the MEMS device of FIGS. 2, 6, and 7. FIG. 800 shows a passivation layer 802, a passivation opening 804, a spring 806, an etched hole array 808, an external metal ring 810, an M6 layer 812, a V5 layer 814, an M5 layer 816, a V4 layer 818, an M4 layer 820, SiO 2 deposition layer 822, an M1 layer 824, a V3 layer 826, an M3 layer 828, a V2 layer 830, an M2 layer 832, a bottom metal plane 834, a verification mass 836, a concentric via ring array 838 inside the verification mass 836, and a concentric via ring array 840 along the external metal ring 810. The MEMS device is designed to operate in the linear region. This is because they have large dimensions, have large springs to make them soft enough (regardless of their thickness), and the maximum displacement they can have is very small, covering all the gaps above, below, in front of, or on one side of them. Thus, the MEMS spring follows Hooke's law with a constant stiffness, and the constant stiffness produces a mechanical restoring force proportional to the displacement. In a specific example, if the displacement is large compared to the spring length, the mechanical restoring force starts to be proportional to the displacement, but after a given initial displacement, it is no longer linear and it increases faster. Thus, although the spring is soft for small displacements around the equilibrium point (i.e., where the sensor will operate and thus has very good sensitivity), in case the verification mass undergoes a larger displacement, for example, if it is subjected to a shock or strong vibration and touches the surrounding walls, roof, or floor, the mechanical restoring force at this time will be greater. Thus, due to this increased mechanical restoring force at the contact point, the MEMS device returns to the equilibrium position and breaks free from static friction. In a more detailed view of this phenomenon, all springs are non-linear. However, while other MEMS devices only experience small displacements, the devices described herein can experience larger displacements such that they enter the non-linear region of the mechanical restoring force relative to the displacement before contacting the surrounding walls, roof, or floor. We can calculate the length of a spring in two ways. One is the straight-line distance from one end to the other. The second measure is the total distance along the entire length of the spring following its twists and curves. We will consider the longest of these measurements as the "length" of the spring. In the embodiments described herein, the shortest ratio between the minimum displacement that can cause the spring to contact the surrounding walls, roof, or floor and the length of any spring is at least 1%, and in some designs, it can be 5% or even 10%. This principle can also apply to lower ratios, but the stability may be insufficient. However, depending on the specific process and overall implementation, 0.5% or even 0.1% can provide sufficient results. This short ratio is one factor (not found in other MEMS designs) of the MEMS devices described herein, which allows for the implementation of soft springs and short gaps to achieve high-performance devices that can be packaged using all packaging technologies including WLCSP while having high yield and reliability. Another inventive concept involves the design of vertical walls, or more precisely, involves the definition of the MEMS region, or the limitation of the lateral etching of silicon oxide, and the mechanical anchors or supports of the MEMS. As previously explained, other designs use vertical metal walls or anchors. In the first case, using vertical metal walls, we cannot use a top metal layer and / or a bottom metal layer to seal the device to the top and / or bottom. This means that we will need a special CMOS process with undoped silicon below the lowest metal layer of the BEOL, and / or a special, more expensive packaging technology (such as a laminated substrate) to properly protect the MEMS cavity from the top, and usually a more expensive post-processing etching sequence. This situation can be avoided in whole or in part if the MEMS device is allowed to electrically short the top and bottom metal planes to the surrounding walls, which is usually not possible. The second option uses anchors, which, although they electrically disconnect the top and bottom metal layers, create a large parasitic capacitance between these layers, which reduces the device performance. In addition, any attempt to improve the effectiveness of reducing this parasitic capacitance by reducing the anchor structure or increasing the vHF etching time reduces the device yield and reliability. The device of the present invention neither has a vertical metal wall connecting the top and bottom metal planes nor has a capacitive anchor. Instead, these devices use two different solutions. One solution is to extend a portion of the MEMS device located between the top and bottom metal planes or electrodes (such as springs), but it can also be other electrodes, such that they are ultimately buried in silicon oxide and are sufficiently spaced apart in the horizontal direction that cannot be achieved at vHF. In fact, we have seen that a long distance is not required. For a 180 nm CMOS node, having 20 µm of metal around the MEMS device is sufficient. Therefore, metal is placed around the released MEMS device, and the metal holds the device because the outer edges of the device have silicon oxide that has not been etched away around and / or adjacent to it. Preferably, this surrounding metal has a circular shape on its outer edge, but other shapes can be implemented. In the previous solutions, we had at least three electrically disconnected portions, where the top metal plane, the bottom metal plane, and the portion of the MEMS device between them were electrically disconnected, and more portions could be electrically disconnected. An alternative implementation can be applied in cases where there are only two rather than three or more electrically disconnected portions. In this example, a portion of the MEMS device can be attached to one of them by a vertical metal wall between the top and bottom metal planes and not attached to the other. In some embodiments, the MEMS device is connected to the top metal plane. This is because the top metal layer is generally more uneven and more curved than the bottom metal layer. This is because the bottom metal layer is not detached from the underlying silicon oxide. To increase the mechanical consistency of these outer rings, we can use an array of vias to connect them. To make them even stronger, we can use a concentric via ring array instead of a regular square via array, such as those used inside the verification mass. However, in this case, different from the case of the verification mass, there will be no holes passing through these outer rings, so the rings do not have to be broken and they can be continuous. Another embodiment aspect applicable to these last two options is that since we neither use vertical metal walls to short-circuit the top and bottom metal planes nor use capacitive anchors to connect them, we can reduce the size of the bottom metal plane compared to the size of the top metal plane, which would otherwise be larger. The reason for this is that the lateral over-etching of the top metal will be greater than that of the bottom metal layer because in order to etch the bottom metal layer, the vHF needs to first etch downwards to reach that position first. The lateral over-etching is the distance from the outermost edge of the passivation opening window above the MEMS device that we need to release to the outermost position of the etched silicon oxide after the vHF post-processing step. That is, since we do not use metal vertical walls that short-circuit from top to bottom nor capacitive anchors, instead, we surround the MEMS device with a metal region that extends around the silicon oxide. Part of this metal region etches away the surrounding silicon oxide during the vHF step, and beyond a certain point in time, it is no longer etched. By this method, in the case of using the second method disclosed above (i.e., when we shorten the portion between the top and bottom metal planes with one of these vertical planes or connections), we reduce the parasitic capacitance between the top and bottom metal planes, which is also the parasitic capacitance between the top or bottom metal plane and the movable part of the MEMS device. This reduction in parasitic capacitance results in an improvement in device sensitivity or performance. The reduced size of the outer ring width at the lower metal plate compared to the top metal plate will depend on the CMOS process and the overall design. However, in some embodiments, it will be between 10% and 50%, with a preferred value of 30%. In some embodiments, the width of one of the outer rings at the top metal plate is 20 μm, which means that the outer ring width at the bottom metal plate can have a preferred size of 6 μm. If the central disk (verification mass plus spring) has a diameter of 50 µm, then the total size of the top plate can have a diameter of 90 µm, and the diameter of the entire bottom plate can have a diameter of 62 µm. If we anchor a portion between the top and bottom metal planes, where the metal region extending around this portion is ultimately buried in unetched silicon oxide, we can also fabricate them with a dimension that is smaller than the top metal plane but larger than the bottom metal plane. Since in this case they are over-etched, they will be slightly present between the top and bottom metal planes. In some embodiments, the outer ring width of this (these) intermediate plates will be between 30% and 70% of the width of the ring of the top metal plane. In one embodiment, this value will be 50%. However, this will ultimately depend on the specific CMOS process and the overall design. If the top metal plane has a circular shape, it can include an inner disk adjacent to an outer ring around it. The inner disk can have an array of holes therein to allow vHF to enter the inside of the MEMS cavity, while the outer ring is solid (the possible exception explained below is used to create a groove to electrically isolate most of this outer ring). In principle, the extension of the inner disk is the extension of the MEMS that we expect to release with vHF. However, another inventive concept is to reduce the extension of the inner disk, so that release holes are not placed around the outer part of the MEMS that does not need to be released. Since vHF can travel a relatively long distance, all MEMS will be released, and we will minimize the over-etching on the outer ring in all metal layers, thus being able to reduce the size of these outer rings. This will reduce the parasitic capacitance between the top and bottom metal plates, thus improving the performance of the MEMS. If this reduced extension is used for the release holes, the passivation opening can also be reduced, because we only need to open the passivation opening above the area with the hole array. The reduction of the inner disk that we can implement will depend on the CMOS process, but in a specific embodiment, it will be between 2 µm and 20 µm on each side, with a preferred value of 6 µm. That is, the disk diameter will be reduced between 4 μm and 40 μm, with a preferred diameter reduction of 12 µm. Implementing this reduction of the inner disk can reduce the outer ring to the same value in all metal layers having such outer rings. For clarity, although the inner disk and the outer ring are discussed, in fact, the layout of the top metal layer will be a single disk. Then, the etched hole array will be positioned in the center, covering an area defined by the size of the inner disk. Therefore, the surrounding solid area without etched holes can be called the outer ring. Also for clarity, when we say we reduce the inner disk, this does not affect the verification quality, the spring, or the dimensions of other parts of the MEMS device that need to be released. The inner disk here only defines the area above the MEMS device or the part that needs to be released with an array of etched holes. The above description is also valid in the case where there are several electrically disconnected parts between the top and bottom metal layers. In these examples, each person will bury their own metal extensions in the silicon oxide, and they will all be electrically disconnected from each other, although there will always be some electrical parasitic capacitance. Although the preferred method is to have this outer metal region support the MEMS portion between the top and bottom metal planes, surrounding all released MEMS on the inside to provide better mechanical consistency, this is not absolutely necessary. This is especially useful in the situations disclosed above, where there are two or more electrically disconnected MEMS portions between the top and bottom metal layers. An example of this is a planar inertial sensor where there are several lateral electrodes positioned to sense acceleration in different directions. Another variant to reduce the parasitic capacitance between the top metal plane (and the middle portion of the MEMS device when it is electrically shorted by (for example) a vertical metal connection to it) and the bottom metal plane is to add a very short groove around the entire top metal plane at a specific distance from the MEMS that needs to be released. In some embodiments, this groove is positioned at half of the over-etch distance. In one configuration, this is about 10 μm because the total length of this metal region around the MEMS is about 20 μm. However, the distance can be made shorter, less than 5 μm or even less than zero. Preferably, it will be positioned at a distance between 5 μm and 15 μm. And the extension of the top metal plate can be a distance of about 20 μm. However, it can be between 5 μm and 30 μm, depending on the specific CMOS process characteristics and the overall MEMS design as well as the required vHF characteristics and formulation. As permitted by the process, the width of the groove should be minimized. This width can be 0.8 μm, but in some embodiments, it will fall between 0.5 μm and 2 μm, depending on the process and especially the thickness of the top metal layer. A metal ring can be implemented outside of this groove to maintain passivation. With this groove, the outer ring is divided into two parts that will be electrically disconnected and also mechanically disconnected, one inside the other. Although there will be some parasitic capacitance between them and they will ultimately be connected to silicon oxide so that they will not move relative to each other. Therefore, one may question why we need to retain the outer part of this separate outer ring. The reason is that over-etching will occur during the vHF post-processing step, such that the silicon oxide positioned between the passivation layer and this top metal layer will be etched away, making the passivation layer very fragile. Therefore, it is better to keep the outermost metal ring in case the passivation breaks so that it can be supported. However, depending on the process characteristics and the overall design, only this outer part of the outer ring can be removed instead of creating a groove in the outer ring, just reducing its diameter. This will further reduce the parasitic capacitance. A preferred embodiment will have a shorter vertical metal wall surrounding the MEMS device and connected to the top metal plane. This vertical metal wall may or may not be connected to a moving part of the MEMS, such as a spring anchor, positioned between the top and bottom metal planes. The purpose of this shorter (i.e., not extending down to the bottom metal plane) wall is to prevent vHF from etching horizontally under the top metal plane towards its outer edge, thus forcing the vHF to first go down along the vertical wall and then back up again in order to be able to etch outwards under the top metal plane towards the outer edge. Depending on the embodiment, this shorter vertical metal wall may also provide mechanical integrity and / or an electrical connection to other parts of the MEMS device, such as for example the anchor of a spring. Another embodiment for achieving a mechanical connection without electrically shorting two parts of the MEMS without using a capacitive anchor is to use a MIM layer in the MEMS process. This layer is typically not etched away with vHF, or at least etched slowly, although it depends on the particular CMOS process. This provides a more compact solution than a capacitive anchor. However, the capacitance tends to be larger and the mechanical stability may be insufficient. However, it may still be useful in some embodiments, depending on the MEMS device, process, and overall design. For some embodiments, it may also be useful to use a horizontal capacitive anchor instead of a vertical one. In some configurations, a hybrid design can be implemented, implementing feedthroughs to transfer connections across MEMS metal walls or planes using the same design principle (such as any type or combination of types of capacitive anchors). The array of holes at the top plate 222 will be as small as possible. They can be smaller than what is allowed by the DRC of the process, but large enough to ensure that they are open for all top metal thicknesses. This minimum size will depend on the particular CMOS process and especially on the top metal thickness. In some embodiments, the width of the size is 0.8 μm. Below this, it is usually difficult to open them fully, which will result in a lower production yield. As will be explained later, when we apply the sealing layer, larger values may not be filled correctly. Therefore, there is a trade-off, and we can neither have small holes that will not open when patterning the top metal layer during the CMOS process nor have overly large holes that will not seal properly during packaging later. Therefore, in some embodiments, the hole size will be between 0.5 µm and 1.5 µm, with a preferred value of 0.8 µm. However, depending on the CMOS process, top metal thickness, and the sealing material, thickness, and process used, the etched hole size can vary. If the holes are too small in some embodiments, they will be drawn as square holes because in practice, any other shape will not make a difference as we will enforce the resolution of the process, and during device manufacturing, they will be rounded off anyway. The separation between holes on the top metal plane (e.g., the top plate 222) can be similar to the vertical length of the vertical distance from the top metal layer M1 to the bottom metal layer M6. In some configurations, the etched holes are horizontally spaced on the top plate 222 by up to a distance that is at least one-half of this vertical distance between M1 and M6. In some embodiments, due to multiple oxide sub-layers having different densities and etching rates, if vHF etches slowly in the vertical direction compared to the horizontal direction, the distance can be greater. Because the goal is to ensure that we properly etch all volumes inside the MEMS cavity, the holes can be placed close enough, but at the same time, as much as possible, prevent the formation of a weak top metal plane with too many holes and almost no remaining metal, which cannot withstand the seal on its top when packaging the device, as explained later in this document. Experimentally, we have found that a sufficient value is to space the etched holes by a distance between 50% and 200% of the height of the metal stack. This height is calculated from the lowest point of the bottom metal layer M1 upwards to the highest point of the top metal layer (e.g., M6). A preferred value is to separate the holes by a distance equal to this height (e.g., 100%). The hole pitch is measured from the center of one hole to the center of another hole in both the horizontal (X) and vertical (Y) directions. To allow the vHF to reach the lowest level for silicon oxide so that all the silicon oxide that needs to be removed is properly etched in all cavities, the same hole array is implemented through all MEMS devices inside the cavity. This can be laterally offset relative to the holes on the top metal plane, although the preferred implementation would be to place them only in the same position. If these holes pass through structures that trap silicon oxide inside (e.g., verification mass), then these holes can be surrounded by via walls to prevent vHF from entering through these holes into the interior and etching the silicon oxide that we expect to remain unetched. Given the relatively small size of these holes, which are preferably made to have a square shape, these via barrier layers can be implemented as square rings. A fourth inventive concept is to use the sealing layer (also known as re-passivation) present in the WLCSP process, which is typically made of polyimide (PI), but it can also be benzocyclobutene (BCB) or other materials, to seal the MEMS cavity. This avoids the need for a specific aluminum sputtering and patterning process, thereby reducing the complexity and cost of post-processing, only further reducing the complexity and cost in the vHF etching and back-end processes. In addition to this, it has been seen that using PI or BCB provides a better seal, thus better covering the hole array on the top metal layer. In contrast, aluminum sputtering requires a very thick deposition, and even then, due to the conformality of the deposition, some holes may still not be properly sealed. This does not happen with PI, which firmly seals all holes. In an example involving another type of packaging that is not WLCSP, a process can still apply PI or BCB or other coatings and patterning (even aluminum sputtering, although it is not ideal, but it can be done with sufficient thickness and an appropriate set of parameters), and then continue with any packaging process. Another key inventive concept involves not using metal fill structures within the MEMS cavity. To compensate for metal residual stress, the CMOS design requires a constant metal density across all regions of the ASIC. To achieve this, once the ASIC design is complete, an automated process called "metal fill" is performed, which fills all the blank areas with random small metal shapes in order to achieve the desired target metal density. This metal fill cannot be performed within the MEMS cavity. Otherwise, after applying vHF, all these tiny metal fill structures will be released and they will adhere to the MEMS device by adhesion, thus preventing its normal operation or making it inoperable altogether. All explanations given in this application can be applied to different CMOS nodes, different metal stacks, and even different solid-state semiconductor processes. Similarly, when we describe the top metal layer and the bottom metal layer, they are typically the topmost and bottommost metal layers in the process layer stack. However, it can apply to other metal layers. In the case of building an inertial sensor in a 6-metal layer process, we will typically need all the available metal layers in order to maximize the thickness and thus maximize the quality of the sensor verification quality. However, if the process has more available metal layers, or if we build another type of MEMS device, or even for an inertial sensor, if we can manage to obtain the required specifications, then we may not need to use all the available metal layers in the metal stack. In this case, we will preferably use the metal layer located at the top, thus reserving the metal layer located at the bottom for the ASIC to form an electrical connection with the ASIC. In this case, there will not be any dedicated area to implement the MEMS, but rather the MEMS will be implemented above the ASIC. In all cases, the active area (FEOL) under the MEMS can be used to implement the ASIC. However, if there are no metal layers available for connection because they are all used to implement the MEMS, it will be difficult to implement a useful portion of the ASIC under the MEMS. However, depending on the process and the specific ASIC design, implementing large transistors or other circuits that require very little wiring can be useful, and / or polysilicon wires (if available) can be used for this wiring. When not all the metal layers of the process stack are used to implement the MEMS, all explanations of this application should be understood in the following way. The "top" and "bottom" metal layers are not the topmost and bottommost of the metal stack, but they are the topmost and bottommost of the metal layers used to implement the MEMS device. Although the preferred embodiments include the use of circular and rounded shapes, the disclosed invention can be applied to other types of shapes. Another key inventive concept involves sensing electronics that interface with MEMS when they are capacitive MEMS sensors (such as, but not limited to, accelerometers, bone conduction sensors, motion detectors, ultrasonic sensors, or any other capacitive sensor). In certain embodiments, the MEMS capacitive sensors herein include a unique small capacitor. This is due to the small size unique feature and the minimal parasitic capacitance, stemming from several concepts explained previously. Similarly, due to the proximity of the ASIC attached to the MEMS edge, and without the need to connect the MEMS wiring to another die that locates the ASIC, and not even to the top of the wafer where the ASIC will be placed in a wafer bonding scheme, or in the case of building the MEMS above the ASIC CMOS wafer. In some embodiments, the capacitance of this MEMS sensor is about 10 fF to 100 fF, or about 50 fF. This is 100 times smaller than commercial MEMS devices used in consumer electronics. This allows for the implementation of a completely different sensing scheme that would not be feasible for other MEMS devices because it would imply excessive power consumption. In some configurations, sensing of the MEMS capacitance is accomplished by creating a ring oscillator where at least one of the capacitances in the loop is a MEMS device as described herein. This ring oscillator will provide a counter that will be read and reset at each sampling period. The output of the counter will already be digital, and it will output the capacitance value. This method has many technical advantages. First, aside from the ring oscillator, its simplified analog design is all digital. This means that there are many analog blocks that we would need in other cases and avoid here, such as a transconductance amplifier, a programmable gain amplifier, an A / D converter, an analog filter, a chopper, and capacitor mismatch compensation, etc. This simplification has many technical advantages: smaller ASIC area, lower production cost, less design time, faster time to market, lower development cost, ease of porting to other CMOS nodes and processes, and lower power consumption. Lower power consumption stems from avoiding many power-consuming analog blocks. However, in exchange for these blocks, the process will involve continuously charging and discharging the MEMS sensor capacitance at a very high frequency, which can be between 10 MHz and 100 MHz, but depends on the MEMS design, the CMOS process, and the target specifications of the sensor. For a conventional capacitance of about a few pF, this would consume excessive power. But for this MEMS sensor with a capacitance less than 100 times or smaller, aside from the other advantages mentioned for this sensing scheme above, this does not mean more but actually less power consumption, making the sensor of the present invention very power efficient. An annular oscillator can vary its frequency depending on many factors such as power supply voltage and its noise, temperature, and process variations. To compensate for this, a second annular oscillator can be implemented which uses another MEMS device very close to the one built by the first MEMS device such that it can be seen to have almost the same process, voltage, and temperature variations. This second MEMS device (or several devices if more than one MEMS is included in the annular oscillator loop) will be slightly different, with a stiffer spring. Preferably, this will be achieved using a wider and / or thicker (i.e., using more metal stacks) spring. Thus, the capacitance readings from the counter connected to this second sensor will be attributed to very little movement of the quantity measured by the sensor (e.g., acceleration in the case of an accelerometer), and it will be attributed to all other factors (such as power supply voltage, process, and temperature variations) changing in the same way as the first sensor. In one embodiment, two annular oscillators each drive a different counter until the second reaches a predetermined value. In this case, we will read the first counter which will give us the value of the quantity sensed, and then we will reset both counters and start counting again. This predetermined value can be programmable such that we can define different sampling frequencies. When the sampling frequency is low, the annular oscillator and / or the counter will be deactivated between samples to minimize power consumption. In some embodiments, a third digital counter with a very slow digital clock is included to start the device each time a new sample needs to be acquired. In some embodiments, to increase the verification mass without increasing the footprint of the verification mass, metal walls are built and / or formed around all the perimeters of the MEMS device. Thus, silicon oxide is trapped inside the verification mass and it will not be etched away by vHF. Additionally, the verification mass has a large number of vias as these are made of tungsten which has a higher density than silicon oxide and the aluminum which is the material of the metal layer. To further increase the effective density and the total mass of the verification mass, an array of vias larger and closer than what the DRC of the process allows can be implemented. In the case of a circular verification mass, we can also use concentric via rings which are spaced at a distance equal to the ring thickness, preferably making this distance and the ring width equal to the via size and via pitch defined by the CMOS process DRC. Incidentally, although the vias of a CMOS process typically need to be a square of a fixed size, in reality we can stretch these vias in one dimension, but at least we need to maintain the specified via size in the other dimension. Otherwise, the wafer cannot be properly fabricated. Since we will need to punch holes across the verification mass, these circular rings may have to be interrupted around the holes. Other shapes can be implemented for both the verification mass and the ring or via fill structures inside it. Another key inventive concept involves modification of the bond pads. This is because there are passivation openings not only above the MEMS device but also above each bond pad (i.e., vertically aligned with the bond pad). This is the reason for the existence of a passivation opening in the CMOS process. This means that when vHF is applied after processing, the oxide below the passivation layer (i.e., between the passivation layer and the top metal layer) will be etched away. If the top metal layer at the bond pad is not large enough, the silicon etching will go beyond it and etch below the passivation layer without metal beneath. If this occurs, a lot of silicon oxide around the pad will be etched away, and ultimately there will be no oxide below the top passivation layer. As a result, the passivation layer can crack, and a large amount of silicon oxide can also be etched away, thus damaging part of the ASIC electronic circuit. One implementation to solve this technical problem is to extend the top metal layer at least more than a conventional bond pad design (and it is even better to extend more or all other metal layers to provide better consistency). This extension will depend on the specific process and the details of the applied vHF etching. In some implementations, the metal will have a lateral extension between 15 μm and 25 μm beyond the passivation opening in all directions. In one implementation, this extension will be 20 μm. There is no need to use a rounded shape, so in various implementations, the bond pad will maintain a square design with respect to the passivation opening and the metal defining it. However, other shapes will also be implemented. Most of the inventive concepts disclosed herein can be applied to many different devices, including but not limited to inertial sensors, gyroscopes, pressure sensors, ultrasonic sensors and transducers such as CMUTs, speakers, magnetometers and compasses, microphones, RF switches, tunable capacitors, RF inductors, temperature sensors, and so on. To avoid requiring a CMOS foundry to increase the silicon content of the passivation layer, we can use (for example) a special formulation and / or equipment developed by (for example) Memsstar (Scotland). After the vHF etching step, we bake the wafer to sublimate the fluorine residues. Due to the smaller size, cost, and higher performance of the MEMS devices disclosed herein, together with their high-volume production capacity and shorter time to market, the inventive concept enables the creation of smaller and higher-performance smartphones, wearable devices, and earbuds, and has more functionality, longer life, and autonomy due to having more space for a larger battery. These sensors are also a contributing factor to many Internet of Things (IoT) applications in high-volume production, where ultra-low-cost and small sensors are required, along with very low power consumption (high performance). Another example of an application is RFID embedded with sensors. FIG. 9 is an exploded view of the metal and via layers of a MEMS device 900 that includes lateral electrodes. FIG. 9 shows a variant of the embodiment of FIG. 2 that senses acceleration in the sensing plane and includes lateral electrodes around the bottom portion of the proof mass where there are no springs. That is, the proof mass is composed of four metal layers M2 to M5. The springs are made of metal layers M4 and M5, which have outer metal rings that support them. Thus, the proof mass does not use metal around it at layers M2 and M3. In this way, we can use layers M2 and M3 to create the lateral electrodes for the proof mass. The shape of these lateral electrodes is essentially similar to the outer rings of the above-mentioned metal layers (M4 and M5), but instead of being a whole ring, there are two half-rings. Each of these half-rings is made of two available metal layers (M2 and M3) stacked together, which means there are a large number of vias inside to connect them. The shape of these vias is an array of concentric half-rings. The outer diameter of these lateral electrodes is shorter than the outer ring of the upper metal layer. In this design, it is made to be also shorter than the bottom metal plane, but an improvement is to make the diameter of the bottom metal plane smaller than the outer diameter of these lateral electrodes. Since we maintain a bottom metal plane, we can still sense out-of-plane acceleration. Thus, the MEMS device has several electrodes that allow sensing of 1, 2, or even 3 axes simultaneously with the same device. This is achieved when these lateral electrodes are divided into quarter-rings instead of half-rings. In addition, for the X and Y axes (i.e., in-plane acceleration), differential capacitance can be implemented. Although this design is for an inertial sensor, the same design principles (electrodes, spring supports, etc.) can be used to implement other types of capacitive sensors and actuators. The MEMS device 900 includes an M6 layer 902, a V5 layer 904, an M5 layer 906, a V4 layer 908, an M4 layer 910, a V3 layer 912, an M3 layer 914, a V2 layer 916, an M2 layer 918, and an M1 layer 920. The M6 layer 902 includes a top plate 922 having etched holes configured in an array and connected to an ASIC. The V5 layer 904 includes an array of concentric through-hole rings 924 extending above the external metal. The M5 layer 906 includes a verification mass top cover 926 having an array of etched holes. The layer 906 also includes a portion of a spiral spring 928 and an external metal ring 930. The V4 layer 908 includes an array of concentric through-hole rings 932 extending above the external metal, a portion of the spiral spring 928 extending in the V4 layer 908, and an array of concentric through-hole rings 936 extending on the verification mass and stopping at the etched hole positions and surrounding them with a square ring. The M4 layer 910 includes a verification mass plane 938, a portion of the spiral spring 928, and a portion of the external metal ring 930. The V3 layer 912 includes an array of concentric through-hole rings 944 extending on the verification mass and stopping at the etched hole positions while surrounding the hole positions with a square ring. The M3 layer 914 includes a verification mass metal plane 946 having an array of etched holes and lateral electrodes 954 having connections to the ASIC. The V2 layer 916 includes an array of concentric through-hole rings 948 extending on the verification mass, stopping at the etched hole positions and surrounding them with a square ring. The V2 layer 916 also includes an array of concentric through-hole half-rings 956 extending above the lateral electrodes. The M2 layer 918 includes a verification mass metal bottom cover 950 having an array of etched holes. The M2 layer 918 also includes lateral electrodes 958. The M1 layer 920 includes a bottom metal plane 952 that includes a connection to the ASIC. The elements or steps of the different embodiments described may be combined to form other embodiments not specifically set forth previously. An element or step may be excluded from the previously described systems or procedures without adversely affecting their operation or generally the operation of the system. Additionally, the various individual elements or steps may be combined into one or more individual elements or steps to perform the functions described in this specification. Other embodiments not specifically described in this specification are also within the scope of the following claims for patent of the invention. 100: Verification mass 102: Spring 104: Spring 106: Spring 108: Etched hole 200: MEMS device 202: M6 layer 204: V5 layer 206: M5 layer 208: V4 layer 210: M4 layer 212: V3 layer 214: M3 layer 216: V2 layer 218: M2 layer 220: M1 layer 222: Top plate 224: Concentric through-hole ring 226: Verification mass top cover 228: Helical spring 230: Outer metal ring 232: Array of concentric through-hole rings 236: Array of concentric through-hole rings 238: Verification mass plane 244: Concentric through-hole ring 246: Verification mass metal plane 248: An array of concentric through-hole rings 250: Verification mass metal bottom cover 252: Bottom metal plane 300: Zoomed view 302: Circular metal plane 304: Outer 20 μm wide ring 306: Helical spring 308: Array of etched holes 400: M5 layer 402: Verification mass top cover 404: Helical spring 406: Outer metal ring 500: V4 layer 502: An array of concentric through-hole rings 504: Etched hole 508: An array of concentric through-hole rings 600: Undecomposed 3D view 602: Array of etched holes 604: Outer ring 606: Connection 608: Lower electrode connection 700: Side view 702: Connection 704: Top metal plane 706: Outer ring 708: Verification mass 710: Bottom metal plane 712: Lower electrode connection 800: Cross-sectional schematic diagram 802: Passivation layer 804: Passivation opening 806: Spring 808: Array of etched holes 810: Outer metal ring 812: M6 layer 814: V5 layer 816: M5 layer 818: V4 layer 820: M4 layer 822: SiO 2 Deposition layer 824: M1 layer 826: V3 layer 828: M3 layer 830: V2 layer 832: M2 layer 834: Bottom metal plane 836: Verification mass 838: Array of concentric through-hole rings 840: Array of concentric through-hole rings 900: MEMS device 902: M6 layer 904: V5 layer 906: M5 layer 908: V4 layer 910: M4 layer 912: V3 layer 914: M3 layer 916: V2 layer 918: M2 layer 920: M1 layer 922: Top plate 924: Concentric through-hole ring 926: Verification mass top cover 928: Helical spring 930: Outer metal ring 932: Array of concentric through-hole rings 936: Concentric through-hole ring 938: Verification mass plane 944: Concentric through-hole ring 946: Verification mass metal plane 948: An array of concentric through-hole rings 950: Verification mass metal bottom cover 952: Bottom metal plane 954: Lateral electrode 956: Array of concentric through-hole half-rings 958: Lateral electrode Figure 1 shows a proof mass of a MEMS device with one of three springs, the springs being connected to the circumference of the device and evenly spaced around the circumference; Figure 2 is an exploded view of the metal and vias layer of a MEMS device, not showing the SiO 2 , passivation layer, and substrate; Figure 3 is a scaled view of the M4 layer of the MEMS device of Figure 2; Figure 4 is a scaled view of the M5 layer of the MEMS device of Figure 2; Figure 5 is a scaled view of the V4 layer of the MEMS device of Figure 2; Figure 6 is a three-dimensional view of the MEMS device of Figure 2; Figure 7 shows a side view of the metal layer of the MEMS device of Figure 2; Figure 8 is a schematic cross-sectional view of the MEMS device of Figures 2, 6, and 7; and Figure 9 is an exploded view of the metal and vias layer of a MEMS device including a lateral electrode. Like reference numerals in different figures indicate like elements. 200: MEMS device 202: M6 layer 204: V5 layer 206: M5 layer 208: V4 layer 210: M4 layer 212: V3 layer 214: M3 layer 216: V2 layer 218: M2 layer 220: M1 layer 222: Top plate 224: Concentric via ring 226: Proof mass lid 228: Helical spring 230: External metal ring 232: Array of concentric via rings 236: Array of concentric via rings 238: Proof mass plane 244: Concentric via ring 246: Proof mass metal plane 248: Array of concentric via rings 250: Proof mass metal bottom cover 252: Bottom metal plane

Claims

1. A MEMS device formed using materials formed by a solid-state semiconductor back-end process (BEOL), wherein: The MEMS device is formed by post-processing and backing with vapor hydrogen fluoride (vHF), and the overall size of the MEMS device is between 50 μm and 150 μm; three springs are evenly distributed around the MEMS device and rotate around the central axis of the MEMS device; the MEMS device is circular and the springs have a helical shape.

2. The MEMS device as claimed in claim 1, wherein the total size of the MEMS device is less than 100 μm.

3. The MEMS device of claim 1, wherein the springs are made of a single metal layer and one of at least two stacked metal layers.

4. The MEMS device as claimed in claim 3, wherein the MEMS device is an inertial sensor.

5. The MEMS device of claim 4, comprising a proof mass, wherein the proof mass is made of one of four metal layers stacked together and springs thereof, wherein the springs are one of being made and connected to one of the top metal layers of the proof mass forming the stack, and connected to two of the top metal layers of the stack.

6. The MEMS device of claim 4, wherein the springs are connected to an outer ring such that, after the vapor hydrogen fluoride etching, a portion of the outer ring remains embedded in silicon oxide at its outer edge.

7. The MEMS device of claim 1, wherein the MEMS device has a top metal plane and a bottom metal plane smaller than the top metal plane.

8. The MEMS device of claim 7, wherein the width of one outer ring of the bottom metal plane is less than or equal to 10% to 50% of the width of one outer ring of the top metal plane.

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