Semiconductor device and methods of forming same

Abstract

A method for forming a semiconductor device includes: forming epitaxial source / drain regions in a substrate; forming a first interlayer dielectric over the epitaxial source / drain regions; forming a gate stack over the substrate and adjacent to the first interlayer dielectric; forming a gate mask over the gate stack; forming a source / drain plug that passes through the first interlayer dielectric and is electrically connected to the epitaxial source / drain regions; depositing a dielectric layer over the gate mask and the first interlayer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second interlayer dielectric over the dielectric layer; etching an opening through the second interlayer dielectric and the dielectric layer, the opening exposing the source / drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature being electrically connected to the source / drain plug.

Description

Technical Field

[0001] none Prior Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit elements and components thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional challenges arise that may need to be addressed. Summary of the Invention

[0004] none Simple diagram description

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates an example of a FinFET in three-dimensional view according to some embodiments. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8A, Figure 8B, Figure 9A, Figure 9B, Figure 10A, Figure 10B, Figure 10C, Figure 10D, Figure 11A, Figure 11B, Figure 12A, Figure 12B, Figure 13A, Figure 13B, Figure 14A, Figure 14B, Figure 14C, Figure 15A, Figure 15B, Figure 16A, Figure 16B, Figure 17A, Figure 17B, Figure 18A, Figure 18B, Figure 19A, Figure 19B, Figure 20A, Figure 20B, 21A, 21B, 22A, 22B, 23A, 23B, 24A, 24B, 25A, 25B, 25C, 25D, 25E, 25F, 26A, 26B, 26C, 26D, 26E, 26F, 27A, 27B, 27C, 27D, 27E, and 27F are cross-sectional views of intermediate stages of fabricating FinFET elements according to some embodiments. 25G and 26G are schematic plan views illustrating intermediate stages of fabricating a FinFET device according to some embodiments. 26H and 261 are diagrams of various devices at intermediate stages in the fabrication of a FinFET device according to some embodiments. Implementation Method

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific embodiments or examples are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, for ease of description, spatially relative terms (such as "below," "beneath," "bottom," "above," "upper," and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of an element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0008] Embodiments are described in the specific context of integrated circuit dies containing fin field-effect transistors (finFETs). However, various embodiments may be applied to dies containing other types of transistors (e.g., nanoFETs (such as nanowire FETs, nanosheet FETs, or the like), planar transistors, or the like) instead of or in combination with finFETs. Furthermore, various embodiments presented herein are discussed in the context of fin field-effect transistor (FinFET) devices formed using a gate-last process. In other embodiments, a gate-first process may be used.

[0009] Embodiments herein provide methods for forming contact plug structures for semiconductor devices and methods for forming the same. According to some embodiments, an etch stop layer comprising a dielectric material is formed above a gate stack of a semiconductor device. The dielectric material is selected to have a high etch selectivity, wherein a gate mask overlies the gate stack. One or more dielectric layers may be formed above the etch stop layer. Openings are etched in the overlying dielectric layer, and conductive features are formed above and electrically connected to source / drain contact plugs. The conductive features may be formed to have shapes that improve electrical connection to the corresponding source / drain contact plugs and reduce electrical resistance. The high selectivity of the etch stop layer facilitates the formation of the openings (and the conductive features therein), allowing the gate mask to remain unetched and reducing leakage between the gate stack and the conductive features (and the source / drain contact plugs). The various embodiments discussed herein allow for a variety of conductive feature shapes (including some extending directly above the gate stack) while improving the electrical performance of the semiconductor device.

[0010] FIG. 1 illustrates, in three dimensions, an example of a FinFET according to some embodiments. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in substrate 50, and fin 52 protrudes above and between adjacent isolation regions 56. Although isolation regions 56 are described / illustrated as being separate from substrate 50, as used herein, the term "substrate" may be used to refer solely to the semiconductor substrate or the semiconductor substrate including the isolation regions. Additionally, although fin 52 is described as being a single, continuous material of substrate 50, fin 52 and / or substrate 50 may comprise a single material or multiple materials. In this context, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0011] A gate dielectric layer 92 is disposed along the sidewalls of the fin 52 and above the top surface of the fin 52, and a gate electrode 94 is disposed above the gate dielectric layer 92. The source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. FIG. 1 further illustrates the reference cross-sections used in subsequent figures. Cross-section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section BB is perpendicular to cross-section AA and along the longitudinal axis of the fin 52 and in the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section CC is parallel to cross-section AA and extends through the source / drain regions 82 of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0012] Figures 2 through 27F are cross-sectional, plan, and diagrams illustrating intermediate stages of fabricating a FinFET device according to some embodiments. In addition to multiple fins / FinFETs, Figures 2 through 7 illustrate cross-sectional views along reference cross section AA illustrated in Figure 1. In addition to multiple fins / FinFETs, Figures 8A through 24A, 25A, 25C, 25E, 26A, 26C, 26E, 27A, 27C, and 27E illustrate cross-sectional views along reference cross section AA illustrated in Figure 1. In addition to multiple gates, Figures 8B through 24B, 14C, 25B, 25D, 25F, 26B, 26D, 26F, 27B, 27D, and 27F illustrate cross-sectional views along reference cross section BB illustrated in Figure 1. In addition to multiple fins / FinFETs, FIG. 10C and FIG. 10D are illustrated along reference cross section CC illustrated in FIG. FIG. 25G and FIG. 26G illustrate schematic top views (e.g., plan views). FIG. 26H and FIG. 26I illustrate various elements formed around and electrically connected to a FinFET element, according to some embodiments.

[0013] In FIG. 2 , a substrate 50 is provided. Substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate can be doped (e.g., doped with p-type or n-type dopants) or undoped. Substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of substrate 50 can include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0014] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type FinFET. Region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type FinFET. Region 50N can be physically separated from region 50P (as indicated by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between region 50N and region 50P.

[0015] In FIG. 3 , fins 52 are formed in substrate 50 . Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50 . The etching process can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, or the like. The etching process can be anisotropic.

[0016] Fins 52 can be formed using any suitable method. For example, fins 52 can be formed using one or more lithography processes, including double or multi-patterning processes. Typically, double or multi-patterning processes combine photolithography with self-aligned processes, allowing for the creation of patterns with a finer pitch than can be achieved using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over substrate 50 and patterned using a photolithography process. Spacers are then formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is subsequently removed, and the remaining spacers can then be used as a mask to form fins 52.

[0017] In FIG. 4 , insulating material 54 is formed over substrate 50 and between adjacent fins 52. Insulating material 54 may be an oxide, such as silicon oxide, a nitride, a combination thereof, or the like, and may be formed using high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it to another material, such as an oxide), a combination thereof, or the like. Other insulating materials formed using any acceptable process may be used. In the illustrated embodiment, insulating material 54 is silicon oxide formed using an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, insulating material 54 is formed such that excess insulating material 54 covers fins 52. Although insulating material 54 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of substrate 50 and fins 52. Thereafter, a fill material, such as those discussed above, may be formed over the liner.

[0018] In FIG. 5 , a removal process is applied to insulating material 54 to remove excess portions of insulating material 54 above fin 52. In some embodiments, a planarization process, such as a chemical mechanical polish (CMP) process, an etch-back process, a combination thereof, or the like, may be utilized. The planarization process exposes fin 52 such that, after the planarization process is complete, the top surface of fin 52 and the top surface of insulating material 54 are substantially coplanar or flush (within the process variation of the planarization process).

[0019] In FIG. 6 , insulating material 54 (see FIG. 5 ) is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. Furthermore, the top surface of STI regions 56 can have a flat surface, a convex surface, a concave surface (such as a dished surface), or a combination thereof, as illustrated. The top surface of STI regions 56 can be formed to be flat, convex, and / or concave using a suitable etch. STI regions 56 can be recessed using an acceptable etch process, such as one that is selective for the material of insulating material 54 (e.g., etches insulating material 54 at a faster rate than the material of fins 52). For example, chemical oxide removal using a suitable etch process, such as dilute hydrofluoric acid (dHF), can be used.

[0020] The process described with reference to Figures 2 through 6 is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed using an epitaxial growth process. For example, a dielectric layer may be formed above the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for the fin. For example, fin 52 in Figure 5 may be recessed, and a material different from fin 52 may be epitaxially grown above the recessed fin 52. In such embodiments, the fin includes a recessed material and an epitaxially grown material disposed above the recessed material. In further embodiments, a dielectric layer may be formed above the top surface of substrate 50, and a trench may be etched through the dielectric layer. Subsequently, a heteroepitaxial structure can be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form a fin. In some embodiments of epitaxial growth of homoepitaxial or heteroepitaxial structures, although in-situ doping and implantation doping can be used together, the epitaxially grown material can be doped in-situ during growth, which can avoid prior and subsequent implantation.

[0021] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N than in region 50P. In various embodiments, the upper portion of fin 52 may be formed of silicon germanium (Si x Ge 1-x , where x may range from 0 to 1), silicon carbide, pure or substantially pure germanium, Group III-V compound semiconductors, Group II-VI compound semiconductors, or the like. For example, usable materials for forming Group III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

[0022] Furthermore, in FIG. 6 , appropriate wells (not shown) may be formed in fins 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, either a P-well or an N-well is formed in both region 50N and region 50P. In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for regions 50N and 50P. For example, a first photoresist may be formed over fins 52 and STI regions 56 in both regions 50N and 50P. The first photoresist is patterned to expose region 50P of substrate 50. The first photoresist may be formed using a spin-on coating technique and patterned using acceptable photolithography techniques. Once the first photoresist is patterned, n-type impurity implantation is performed in region 50P, while the remaining portion of the first photoresist acts as a mask to substantially prevent n-type impurities from being implanted into region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like, and may be implanted into region 50P at a dose equal to or less than 10 15 cm -2, such as between approximately 10 12 cm -2 and approximately 10 15 cm -2. In some embodiments, the n-type impurity may be implanted at an implantation energy of approximately 1 keV to approximately 10 keV. After implantation, the first photoresist is removed, such as by an acceptable ashing process followed by a wet cleaning process.

[0023] After implanting region 50P, a second photoresist is formed over fins 52 and STI regions 56 in both region 50P and region 50N. The second photoresist is patterned to expose region 50N of substrate 50. The second photoresist can be formed using a spin-on coating technique and can be patterned using acceptable photolithography techniques. Once the second photoresist is patterned, a p-type impurity implant is performed in region 50N, with the remaining portion of the second photoresist acting as a mask to substantially prevent the implantation of the p-type impurity into region 50P. The p-type impurity can be boron, BF2, indium, or the like, and the dose implanted into region 50N is equal to or less than 10 15 cm-2, such as between approximately 10 12 cm-2 and approximately 10 15 cm-2. In some embodiments, the p-type impurity can be implanted at an implant energy of approximately 1 keV to approximately 10 keV. After implantation, the second photoresist can be removed, such as using an acceptable ashing process followed by a wet clean.

[0024] After implantation of regions 50N and 50P, an annealing process may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, although in-situ doping and implantation doping may be used together, the growth material of the epitaxial fin may be in-situ doped during growth, which may avoid implantation.

[0025] In FIG. 7 , a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layer 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layer 60 and then planarized using, for example, a CMP process. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive material selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. Dummy gate layer 62 can be deposited using physical vapor deposition (PVD), CVD, sputtering, or other techniques known in the art for depositing conductive materials. Dummy gate layer 62 can be made of a material having a higher etch selectivity than the material of STI region 56. Mask layer 64 can include, for example, one or more layers of silicon oxide, SiN, SiON, combinations thereof, or the like. In some embodiments, mask layer 64 can include a silicon nitride layer and a silicon oxide layer overlying the silicon nitride layer. In some embodiments, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. It should be noted that dummy dielectric layer 60 is shown covering only fin 52 for illustrative purposes only. In some embodiments, dummy dielectric layer 60 can be deposited such that it covers STI region 56, thereby extending between dummy gate layer 62 and STI region 56.

[0026] Figures 8A through 26F illustrate various additional steps in fabricating FinFET devices according to some embodiments. These figures illustrate features in either region 50N or region 50P. For example, the illustrated structures may apply to both region 50N and region 50P. Structural differences between region 50N and region 50P, if any, are described in the text for each figure.

[0027] In Figures 8A and 8B, mask layer 64 (see Figure 7) can be patterned using acceptable photolithography and etching techniques to form mask 74. In some embodiments, the etching technique can include one or more anisotropic etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, or the like. Subsequently, the pattern of mask 74 can be transferred to dummy gate layer 62 (see Figure 7) to form dummy gates 72. In some embodiments, the pattern of mask 74 can also be transferred to dummy dielectric layer 60 using acceptable etching techniques. Dummy gates 72 overlie channel regions 58 of fins 52. The pattern of mask 74 can be used to physically separate each of dummy gates 72 from adjacent dummy gates. Dummy gates 72 can also have a length that is substantially perpendicular to the length of a corresponding one of fins 52. As described in more detail below, dummy gates 72 are sacrificial gates that are subsequently replaced by replacement gates. Therefore, the dummy gate 72 can also be called a sacrificial gate. In other embodiments, some of the dummy gates 72 are not replaced but remain in the final structure of the FinFET device of the embodiment.

[0028] Furthermore, in Figures 8A and 8B, gate sealing spacers 80 may be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. Gate sealing spacers 80 may be formed by thermal oxidation or deposition followed by anisotropic etching. Gate sealing spacers 80 may include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, combinations thereof, or the like. After forming gate sealing spacers 80, implantation of lightly doped source / drain (LDD) regions (not explicitly illustrated) may be performed. In embodiments with different device types, similar to the implantation discussed above in Figure 6, a mask such as a photoresist may be formed over region 50N, while exposing region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the exposed fin 52 in region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, can be formed over region 50P, while exposing region 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the exposed fin 52 in region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have an impurity dose of approximately 10 12 cm -2 to approximately 10 16 cm -2. In some embodiments, the appropriate impurity can be implanted at an implant energy of approximately 1 keV to approximately 10 keV. Annealing can be used to activate the implanted impurities.

[0029] In Figures 9A and 9B, gate spacers 86 are formed on gate sealing spacers 80 along the sidewalls of dummy gate 72 and mask 74. Gate spacers 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of gate spacers 86 may include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, combinations thereof, or the like. In some embodiments, gate spacers 86 may include multiple layers (not shown), such that the layers include different materials.

[0030] It should be noted that the above disclosure generally describes processes for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., gate seal spacer 80 may not be etched prior to forming gate spacer 86, thereby creating an "L-shaped" gate seal spacer, spacers may be formed and removed, and / or the like). Furthermore, different structures and steps may be used to form n-type and p-type devices. For example, LDD regions for n-type devices may be formed prior to forming gate seal spacer 80, while LDD regions for p-type devices may be formed after forming gate seal spacer 80.

[0031] In Figures 10A and 10B, epitaxial source / drain regions 82 are formed in fins 52 to apply stress to the corresponding channel regions 58, thereby improving device performance. The epitaxial source / drain regions 82 are formed in fins 52 such that each dummy gate 72 is positioned between a corresponding adjacent pair of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into the fins 52 or may penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the FinFET device of the embodiment.

[0032] Epitaxial source / drain regions 82 in region 50N can be formed by masking region 50P and etching the source / drain regions of fin 52 in region 50N to form recesses in fin 52. Subsequently, epitaxial source / drain regions 82 in region 50N are epitaxially grown in the recesses. Epitaxial source / drain regions 82 can comprise any acceptable material, such as a material suitable for n-type FinFETs. For example, if fin 52 is silicon, epitaxial source / drain regions 82 in region 50N can comprise a material that imparts tensile strain in channel region 58, such as silicon, SiC, SiCP, SiP, combinations thereof, or the like. Epitaxial source / drain regions 82 in region 50N can have surfaces that are raised from corresponding surfaces of fin 52 and can be faceted.

[0033] Epitaxial source / drain regions 82 in region 50P can be formed by masking region 50N and etching the source / drain regions of fin 52 in region 50P to form recesses in fin 52. Subsequently, epitaxial source / drain regions 82 in region 50P are epitaxially grown in the recesses. Epitaxial source / drain regions 82 can comprise any acceptable material, such as a material suitable for p-type FinFETs. For example, if fin 52 is silicon, epitaxial source / drain regions 82 in region 50P can comprise a material that imparts compressive strain in channel region 58, such as SiGe, SiGeB, Ge, GeSn, combinations thereof, or the like. Epitaxial source / drain regions 82 in region 50P can also have surfaces that are raised from corresponding surfaces of fin 52 and can be faceted.

[0034] The epitaxial source / drain regions 82 and / or fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions 82 may have an impurity concentration between approximately 10 19 cm −3 and approximately 10 21 cm −3 . The n-type and / or p-type impurities used in the epitaxial source / drain regions 82 may be any of the impurities previously discussed. In some embodiments, the epitaxial source / drain regions 82 may be doped in situ during growth.

[0035] As a result of the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of epitaxial source / drain regions 82 have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 82 of the same FinFET to merge, as illustrated in FIG. 10C . In other embodiments, adjacent epitaxial source / drain regions 82 remain separated after the epitaxial process is completed, as illustrated in FIG. 10D . In the embodiments illustrated in FIG. 10C and FIG. 10D , gate spacers 86 are formed to cover a portion of the sidewalls of fin 52 extending above STI region 56, thereby blocking epitaxial growth. In other embodiments, the spacer etch used to form gate spacers 86 can be tailored to remove spacer material from the sidewalls of fin 52, allowing the epitaxial growth region to extend to the surface of STI region 56.

[0036] In Figures 11A and 11B, an ILD 88 is deposited over the structure illustrated in Figures 10A and 10B. ILD 88 can be formed of a dielectric material and can be deposited using any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, combinations thereof, or the like. The dielectric material can include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), combinations thereof, or the like. Other insulating materials formed using any acceptable process can also be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between ILD 88 and the epitaxial source / drain regions 82, mask 74, and gate spacers 86. The CESL 87 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or the like, that has a different etch rate than the material of the overlying ILD 88 .

[0037] In Figures 12A and 12B, a planarization process, such as a CMP process, may be performed to make the top surface of ILD 88 flush with the top surface of dummy gate 72 or mask 74 (see Figures 11A and 11B). The planarization process may also remove mask 74 on dummy gate 72 and portions of gate seal spacer 80 and gate spacer 86 along the sidewalls of mask 74. After the planarization process, within the process variation of the planarization process, the top surfaces of dummy gate 72, gate seal spacer 80, gate spacer 86, and ILD 88 are substantially coplanar or flush with each other. Thus, the top surface of dummy gate 72 is exposed through ILD 88. In some embodiments, mask 74 may remain, in which case the planarization process makes the top surface of ILD 88 flush with the top surface of mask 74.

[0038] In Figures 13A and 13B, dummy gates 72 and mask 74 (if present) are removed during an etching step, forming openings 90. In some embodiments, portions of dummy dielectric layer 60 within openings 90 may also be removed. In other embodiments, only dummy gates 72 are removed, and dummy dielectric layer 60 remains and is exposed by openings 90. In some embodiments, dummy dielectric layer 60 is removed from openings 90 in a first region of the die (e.g., the core logic region) and remains within openings 90 in a second region of the die (e.g., the input / output region). In some embodiments, dummy gates 72 are removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches dummy gates 72 without etching ILD 88 or gate spacers 86. Each opening 90 exposes the channel region 58 of a corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During the removal process, the dummy dielectric layer 60 can serve as an etch stop layer when etching the dummy gate 72. Subsequently, after removing the dummy gate 72, the dummy dielectric layer 60 can be removed as appropriate.

[0039] In Figures 14A and 14B, an interface layer 91, a gate dielectric layer 92, and a gate electrode 94 (see Figures 13A and 13B) are formed in opening 90 to form a gate stack 96. Gate stack 96 may also be referred to as a replacement gate stack. Figure 14C illustrates a detailed view of region 89 of Figure 14B. In some embodiments, interface layer 91 is formed in opening 90 (see Figures 13A and 13B). Interface layer 91 may include silicon oxide and may be formed using a chemical deposition process such as ALD, CVD, or the like, or using an oxidation process. In some embodiments where interface layer 91 is formed using a deposition process, interface layer 91 extends along the exposed surfaces of fin 52, STI region 56, and gate seal spacer 80. In some embodiments where interface layer 91 is formed using an oxidation process, interface layer 91 extends along the exposed surfaces of fin 52 and does not extend along the exposed surfaces of STI region 56 and gate seal spacer 80. In some embodiments, the interface layer 91 has a thickness of less than about 20 Å.

[0040] In some embodiments, a gate dielectric layer 92 is deposited in the opening 90 above the interface layer 91. The gate dielectric layer 92 may also be formed on the top surface of the ILD 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material. In these embodiments, the gate dielectric layer 92 may have a k value greater than approximately 7.0 and may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The gate dielectric layer 92 may be formed by molecular-beam deposition (MBD), ALD, PECVD, combinations thereof, or the like.

[0041] Furthermore, in Figures 14A and 14B, a gate electrode 94 is deposited over gate dielectric layer 92 and fills the remaining portion of opening 90 (see Figures 13A and 13B). Although a single-layer gate electrode 94 is illustrated in Figure 14B, gate electrode 94 may include any number of liner layers 94A, any number of work function regulating layers 94B, and a conductive filler layer 94C, as illustrated in Figure 14C. Liner layer 94A may include TiN, TiO, TaN, TaC, combinations thereof, multiple layers thereof, or the like, and may be formed using PVD, CVD, ALD, combinations thereof, or the like. In region 50N, work function regulating layer 94B may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multiple layers thereof, or the like, and may be formed using PVD, CVD, ALD, combinations thereof, or the like. In region 50P, work function regulating layer 94B may include TiN, WN, TaN, Ru, Co, combinations thereof, multilayers thereof, or the like, and may be formed using PVD, CVD, ALD, combinations thereof, or the like. In some embodiments, conductive filler layer 94C may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, multilayers thereof, or the like, and may be formed using PVD, CVD, ALD, electroplating, combinations thereof, or the like.

[0042] After filling opening 90 (see FIG. 13A and FIG. 13B ), a planarization process such as CMP may be performed to remove excess portions of gate dielectric layer 92, gate electrode 94, and / or interface layer 91 that are above the top surface of ILD 88. Thus, the remaining portions of gate electrode 94, gate dielectric layer 92, and interface layer 91 form a gate stack 96 of the embodiment FinFET device. Gate stack 96 may extend along the sidewalls of channel region 58 of fin 52.

[0043] The formation of gate dielectric layer 92 in region 50N and region 50P can occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material. In other embodiments, gate dielectric layer 92 in each region can be formed using different processes, such that gate dielectric layer 92 in different regions can be formed of different materials. The formation of conductive fill layer 94C in region 50N and region 50P can occur simultaneously, such that conductive fill layer 94C in each region is formed of the same material. In other embodiments, conductive fill layer 94C in each region can be formed using different processes, such that conductive fill layer 94C in different regions can be formed of different materials. When different processes are used, various masking steps can be used to mask and expose appropriate regions.

[0044] In Figures 15A and 15B, gate stack 96 is recessed below the top surface of ILD 88 to form recess 98. In some embodiments, gate stack 96 is recessed below the top surface of ILD 88. In some embodiments, gate stack 96 is recessed to a depth between approximately 10 nm and approximately 100 nm. In some embodiments, gate stack 96 is recessed using one or more etching processes. The one or more etching processes may include one or more dry etching processes, one or more wet etching processes, combinations thereof, or the like. The one or more etching processes may include an anisotropic etching process. In some embodiments, the one or more etching processes may be performed using an etchant such as Cl2, HCl, F2, HF, CF4, SiCl4, CHxFy, Ar, N2, O2, BCl3, NF3, combinations thereof, or the like.

[0045] Once the gate stack 96 has been recessed, a gate contact layer 99 can be formed from tungsten, such as fluorine-free tungsten (FFW), which can be deposited using a selective deposition process, such as a selective CVD process. The gate contact layer 99 can be considered part of the gate stack 96. However, the gate contact layer 99 can include other conductive materials, such as ruthenium, cobalt, copper, molybdenum, nickel, combinations thereof, or the like, and can be deposited using a suitable deposition process (e.g., ALD, CVD, PVD, or the like). As illustrated, the gate contact layer 99 can extend primarily or substantially between the gate seal spacer 80 and some or all of the surfaces of the gate dielectric layer 92 and the interface layer 91 (if exposed). The FFW can have a thickness of 8 nm to 10 nm, such as 8.5 nm.

[0046] According to some embodiments, in FIG. 16A and FIG. 16B , a metal dielectric liner 100 is optionally deposited in the recess 98 and above the recessed gate stack 96 (e.g., along the gate contact layer 99 ). The metal dielectric liner 100 provides a self-alignment advantage during the subsequent formation of the gate contact plug. In some embodiments, the metal dielectric liner 100 comprises a metal oxide or silicate, wherein the metal may be hafnium, aluminum, zirconium, or the like. For example, the metal dielectric liner 100 may be hafnium oxide, aluminum oxide, or zirconium silicate. The metal dielectric liner 100 may be formed using ALD, MBD, PECVD, or any other suitable method, and may have a thickness ranging from 1 nm to 4 nm, such as from 1 nm to 2 nm or from 2 nm to 4 nm.

[0047] In Figures 17A and 17B, a dielectric layer 102 is formed in recess 98 (see Figures 15A and 15B) and over ILD 88 and metal dielectric liner 100 (if present). In some embodiments, dielectric layer 102 overfills recess 98. In some embodiments, dielectric layer 102 comprises a material that does not contain oxygen. In some embodiments, dielectric layer 102 comprises silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), combinations thereof, or the like, and may be formed using ALD, CVD, combinations thereof, or the like. According to some embodiments discussed herein, the dielectric layer comprises silicon nitride and may be referred to as a gate mask or a nitride mask.

[0048] In Figures 18A and 18B, a planarization process is performed on dielectric layer 102 and metal dielectric liner 100 (if present) to expose the top surface of ILD 88. After the planarization process, within the process variation of the planarization process, the top surfaces of dielectric layer 102, metal dielectric liner 100, and ILD 88 are substantially flush or coplanar. In some embodiments, the planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After the planarization process, dielectric layer 102 has a thickness between approximately 10 nm and approximately 100 nm. In some embodiments (not specifically described), dielectric layer 102 may be a multilayer dielectric including nitride and oxide. In such embodiments, after the planarization process, the topmost layer is silicon nitride.

[0049] FIG19A and FIG19B illustrate a patterning process for forming ILD 88 and CESL 87 with openings 118. Openings 118 expose the top surface of corresponding epitaxial source / drain regions 82. In some embodiments, the patterning process may include one or more suitable etching processes while using a patterned mask stack as an etch mask. The one or more etching processes may include one or more dry etching processes or the like. The etching process may be anisotropic. In some embodiments, the one or more etching processes may be performed using an etchant such as CF4, CHF3, CH2F2, C4F6, C4F8, Ar, O2, N2, H2, combinations thereof, or the like.

[0050] In some embodiments, after forming the opening 118, the remaining portion of the patterned mask stack is removed using, for example, a suitable etching process that is selective to the remaining material of the patterned mask stack. In some embodiments, the etching process includes a dry etching process, a wet etching process, a combination thereof, or the like. In some embodiments, the suitable etching process can be performed using an etchant such as HCl, H2O2, a combination thereof, or the like.

[0051] In FIG. 20A and FIG. 20B , after forming opening 118, a silicide layer 120 is formed through opening 118 above epitaxial source / drain region 82. In some embodiments, a metal material is deposited in opening 118. The metal material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, combinations thereof, or the like, and may be formed using PVD, sputtering, combinations thereof, or the like. Subsequently, an annealing process is performed to form silicide layer 120. In some embodiments where epitaxial source / drain region 82 includes silicon, the annealing process causes the metal material to react with the silicon to form a silicide of the metal material at the interface between the metal material and epitaxial source / drain region 82. After forming silicide layer 120, unreacted portions of the metal material may be removed, if appropriate, using a suitable removal process, such as a suitable etching process.

[0052] After forming the silicide layer 120, conductive features 122 are formed in the openings 118. The conductive features 122 provide electrical connections to the corresponding epitaxial source / drain regions 82. In some embodiments, the conductive features 122 are formed by first forming a barrier layer (not separately shown) in the openings 118. The barrier layer may extend along the bottom and sidewalls of the openings 118. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, multilayers thereof, or the like, and may be formed using ALD, CVD, PVD, sputtering, combinations thereof, or the like. Subsequently, an adhesion layer (not specifically shown) is formed over the barrier layer within the openings 118. The adhesion layer may include cobalt, ruthenium, alloys thereof, combinations thereof, multilayers thereof, or the like, and may be formed using ALD, CVD, PVD, sputtering, combinations thereof, or the like. After forming the adhesion layer, a seed layer (not separately shown) is formed over the adhesion layer within the openings 118. The seed layer may include copper, titanium, nickel, gold, manganese, combinations thereof, multiple layers thereof, or the like, and may be formed using ALD, CVD, PVD, sputtering, combinations thereof, or the like. Subsequently, a conductive fill material (not separately shown) is formed over the seed layer within opening 118. In some embodiments, the conductive fill material overfills opening 118. The conductive fill material may include copper, aluminum, tungsten, ruthenium, cobalt, combinations thereof, alloys thereof, multiple layers thereof, or the like, and may be formed using, for example, electroplating, ALD, CVD, PVD, or other suitable methods.

[0053] Still referring to FIG. 20A and FIG. 20B , after forming the conductive fill material, a planarization process is performed to remove the barrier layer, adhesion layer, seed layer, and the portion of the conductive fill material that overfills opening 118 and is disposed above dielectric layer 102. The remaining portions of the barrier layer, adhesion layer, seed layer, and conductive fill material form conductive features 122 in opening 118. The planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After the planarization process is performed, within the process variation range of the planarization process, the top surface of conductive feature 122 and the top surface of dielectric layer 102 are substantially flush or coplanar.

[0054] In FIG. 21A and FIG. 21B , dielectric layer 104 is formed over dielectric layer 102 and ILD 88. In some embodiments, dielectric layer 104 comprises a material that does not contain oxygen. For example, dielectric layer 104 can be formed using materials and methods similar to those used for dielectric layer 102. In some embodiments, dielectric layer 102 and dielectric layer 104 comprise different materials. For example, dielectric layer 102 (e.g., the topmost layer of dielectric layer 102 if multiple layers are present) can be silicon nitride, and dielectric layer 104 can be silicon carbonitride (SiCN). Furthermore, in some embodiments, dielectric layer 104 can contain oxygen. For example, dielectric layer 102 can be any of the materials described above, and dielectric layer 104 can be an oxide, carbonate, or carbide, such as silicon carbonate (SiCO) or silicon oxycarbide (SiOC). In various embodiments, the dielectric layer 104 has a high etch selectivity to various adjacent features, such as the dielectric layer 102, the CESL 87, the gate spacer 86, and the gate seal spacer 80. For example, the etch selectivity to silicon nitride material can be greater than or equal to 10 (e.g., 10 times).

[0055] In FIG. 22A and FIG. 22B , an ILD 106 is formed over dielectric layer 104. In some embodiments, ILD 106 can be formed using materials and methods similar to those of ILD 88 described above with reference to FIG. 11A and FIG. 11B , and the description thereof will not be repeated herein. In some embodiments, ILD 88 and ILD 106 comprise the same material. In other embodiments, ILD 88 and ILD 106 comprise different materials.

[0056] In Figures 23A and 23B, an opening 128 is formed to expose the gate stack 96. In subsequent steps, the opening 128 will be filled with a conductive material to form a gate contact plug. In some embodiments, the patterning process includes suitable photolithography and etching processes, and extreme ultraviolet (EUV) lithography may be used.

[0057] As illustrated, openings 128 extend through ILD 106, dielectric layer 104, and dielectric layer 102. Furthermore, a final etch process is used to extend openings 128 through metal-dielectric liner 100 to expose the corresponding gate stack 96 or gate contact layer 99 (if present). Thus, metal-dielectric liner 100 acts as an etch stop layer to prevent damage to gate contact layer 99 during the patterning process. In some embodiments, a final etch process is not performed to extend some of openings 128R. These particular openings 128R may be referred to as redundant openings 128R because they can accommodate redundant conductive features of gate stack 96 (e.g., redundant gate contact plugs, as discussed in more detail below).

[0058] As further explained, some of the openings 128 may be misaligned with corresponding portions of the gate stack 96. These particular openings 128M may be referred to as misaligned openings 128M because they may accommodate misaligned conductive features of the gate stack 96 (e.g., misaligned gate contact plugs, as discussed in more detail below). When patterning the misaligned openings 128M, the metal-dielectric liner 100 protects adjacent features (e.g., the gate seal spacer 80) from being etched.

[0059] In some embodiments, the patterning process is performed by first forming a mask stack (not specifically illustrated) over ILD 106. The mask can be a multi-layer mask, wherein the lower layer is a metal layer comprising a metal nitride (such as TiN, MoN, WN, or the like), a metal carbide (such as WC, WBC, or the like), a boron-containing material (such as BSi, BC, BN, BCN, or the like), combinations thereof, or the like, and can be formed using ALD, CVD, combinations thereof, or the like. The middle layer of the mask stack can be a dielectric layer and comprise SiOx, SiN, SiCN, SiOC, combinations thereof, or the like, and can be formed using ALD, CVD, combinations thereof, or the like. The upper layer of the mask stack can comprise amorphous silicon (a-Si), a boron-containing material (such as BSi, BC, BN, BCN, or the like), combinations thereof, or the like, and can be formed using ALD, CVD, combinations thereof, or the like. Subsequently, a mask stack is used to pattern the ILD 106, dielectric layer 104, and dielectric layer 102 to form openings 128 for subsequently formed conductive features that provide electrical connections to the gate stack 96. Suitable etching processes (including the final etching process) may include one or more dry etching processes. The etching process may be anisotropic. In some embodiments, the suitable etching process is performed using an etchant such as CF4, CHF3, CH2F2, C4F6, C4F8, Ar, O2, N2, H2, combinations thereof, or the like.

[0060] In Figures 24A and 24B, conductive features 132 are formed in openings 128. Conductive features 132 provide electrical connections to corresponding gate stacks 96. Therefore, conductive features 132 may also be referred to as gate contact plugs or gate plugs. In some embodiments, conductive features 132 may be formed using materials and methods similar to those described above for conductive features 122, and are not described again herein. In some embodiments, the conductive fill material of conductive features 132 is the same as the conductive fill material of conductive features 122. In other embodiments, the conductive fill material of conductive features 132 is different from the conductive fill material of conductive features 122, such as conductive features 132 comprising tungsten, which may or may not include first forming a barrier layer. For example, conductive features 132 may be formed of tungsten and deposited using CVD or any other suitable method.

[0061] After forming the conductive fill material of the conductive features 132, a planarization process is performed to remove the liner layer (e.g., barrier layer, adhesion layer, and seed layer, if present) and the portion of the conductive fill material that overfills the opening 128. The remaining portion of the liner layer and the conductive fill material forms the conductive features 132 in the opening 128. The planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After performing the planarization process, within the process variation of the planarization process, the top surface of the conductive features 132 and the top surface of the ILD 106 are substantially flush or coplanar.

[0062] As described above, the conductive features 132 formed in the misaligned openings 128M can be referred to as misaligned conductive features 132M (e.g., misaligned contact gate plugs). Furthermore, the conductive features 132 formed in the redundant openings 128R can be referred to as redundant conductive features 132R. As illustrated, the redundant conductive features 132R are separated from the gate stack 96 (e.g., gate contact layer 99) by the metal-dielectric liner 100. The redundant conductive features 132R may not be functional electrical components of the integrated circuit unless later activated after the semiconductor device is manufactured. For example, it may be determined later (e.g., based on wafer testing of the semiconductor device) that some of the redundant conductive features 132R are required as functional electrical components. To this end, a high voltage stress (e.g., through a process called eFuse writing) is applied through those redundant conductive features 132R to induce dielectric breakdown of the metal-dielectric liner 100 separating the redundant conductive features 132R from the corresponding gate stack 96 (e.g., gate contact layer 99).

[0063] In some embodiments, the mask stack can be patterned using appropriate etchants for the various layers. Furthermore, the pattern of the mask stack is subsequently transferred to the ILD 106 and can be stopped at the dielectric layer 104, which can serve as an etch stop layer. The etch process can be isotropic, anisotropic, or a combination thereof. For example, the topmost layer of the mask stack (e.g., amorphous silicon) can be dry etched in an anisotropic etch process, and the underlying layers of the mask stack (e.g., dielectric and metal layers) can be etched in an isotropic etch process to transfer the pattern. The pattern can then be transferred through the ILD 106 using an isotropic etch process. As illustrated, the dielectric layer 104 can be partially etched before the pattern is fully transferred to the ILD 106.

[0064] In Figures 25A through 25G, ILD 106 is patterned to form openings 126 therein. Openings 126 expose corresponding conductive features 122. In some embodiments, the patterning process includes suitable photolithography (e.g., utilizing EUV lithography) and an etching process, and may include forming a mask stack (not specifically illustrated) similar to that discussed above in connection with opening 128. Suitable etching processes may include one or more dry etching processes. The etching process may be anisotropic. In some embodiments, the suitable etching process is performed using an etchant such as CF4, CHF3, CH2F2, C4F6, C4F8, Ar, O2, N2, H2, combinations thereof, or the like. As described in more detail above, dielectric layers 102 and 104 are formed of different materials and have different etch selectivities. As such, the material of dielectric layer 104 is selected so that dielectric layer 104 acts as an etch stop layer when forming opening 126. Furthermore, the high etch selectivity ensures that when the etching process is performed to extend the opening 126 through the dielectric layer 104, the dielectric layer 102, the CESL 87, and any other exposed silicon nitride layers remain substantially unetched. This reduces leakage between conductive features subsequently formed in the opening 126 and the adjacent gate stack 96. In some embodiments, for the etching process used to form the opening 126, the ratio of the etch rate of the dielectric layer 104 (e.g., comprising SiN) to the etch rate of the dielectric layer 102 (e.g., comprising SiCN or SiCO) is approximately or greater than 10.

[0065] 25A through 25F illustrate various cross-sections as identified in the top-down schematic diagram (e.g., plan view) provided in FIG. 25G . It should be noted that the structures illustrated in the cross-sections of FIG. 24A and FIG. 24B are continued in FIG. 25E and FIG. 25F . However, any structures of FIG. 25A through FIG. 25F are intended to represent a continuation of the exemplary cross-sections of FIG. 24A and FIG. 24B in order to illustrate various exemplary conductive features that will be subsequently formed in opening 126 .

[0066] 25A , 25B , and 25G , openings 126A may have a rectangular shape and / or an oval shape (or a rounded rectangular shape) and may be formed directly above corresponding conductive features 122 (e.g., corresponding epitaxial source / drain regions 82 ). In some embodiments, openings 126A may be centered above conductive features 122, or, in the illustrated embodiment, some of openings 126A may be directly above underlying conductive features 122 but laterally shifted (e.g., misaligned) relative to the underlying conductive features 122 such that the central axis of opening 126A is laterally shifted relative to the central axis of the underlying conductive features 122. In some embodiments, due to the shifting, openings 126A may extend below the top surface of the underlying conductive features 122 and partially or completely through dielectric layer 104 (e.g., exposing dielectric layer 102). In some embodiments, due to dielectric layer 104 acting as an etch stop layer, openings 126A do not extend below the top surface of conductive features 122. Furthermore, when opening 126A has a rectangular shape, opening 126A may have the same or similar length and width (e.g., with respect to the upper portion of opening 126A), thereby forming a square shape. When opening 126A has an elliptical shape, opening 126A may have the same or similar major and minor axes, thereby forming a circular shape. For example, the length, width, and / or axis may range from 10 nm to 30 nm, including 15 nm to 25 nm, such as approximately 15 nm.

[0067] Referring to FIG. 25A , FIG. 25B , and FIG. 25G , openings 126B may have a slot shape (e.g., an elongated rectangular shape) and may be formed above corresponding conductive features 122 and above gate stack 96 . As illustrated, openings 126B extend beyond the lateral edges of the underlying conductive features 122 . Thus, openings 126B may extend below the top surface of the underlying conductive features 122 and partially or completely through dielectric layer 104 . Furthermore, because portions of openings 126B may be directly above adjacent gate stack 96 , openings 126B may expose dielectric layer 102 . In some embodiments, due to dielectric layer 104 acting as an etch stop layer, openings 126B do not extend below the top surface of conductive features 122 . Furthermore, the length of openings 126B may be greater than or equal to twice the width of openings 126B (e.g., relative to the upper portion of openings 126B). In some embodiments, the length of openings 126B may be up to three times the width of openings 126B. For example, the width of opening 126B may be the same as the width of opening 126A, such as in the range of 10 nm to 20 nm (eg, approximately 15 nm), and the length of opening 126B may be in the range of 30 nm to 60 nm (eg, approximately 45 nm).

[0068] Referring to Figures 25C, 25D, and 25G, opening 126C can have a slot shape (e.g., an elongated rectangular shape) and can be formed over multiple conductive features 122, such as over two conductive features 122. In some embodiments (not specifically illustrated), opening 126C can also be formed over gate stack 96, similar to that discussed with respect to opening 126B. As illustrated, opening 126C extends beyond the lateral edges of the underlying conductive feature 122. Thus, opening 126C can extend below the top surface of the underlying conductive feature 122 and partially or completely through dielectric layer 104. Furthermore, portions of opening 126C can expose dielectric layer 102. In some embodiments, due to dielectric layer 104 acting as an etch stop layer, opening 126C does not extend below the top surface of conductive feature 122. Furthermore, the length and width of opening 126C (e.g., relative to the upper portion of opening 126C) can have similar dimensions and proportions as described above with respect to opening 126B.

[0069] Referring to Figures 25E, 25F, and 25G, openings 126D may have a slot shape (e.g., an elongated rectangular shape) and may be formed above corresponding conductive features 122 to subsequently form docking contacts, as discussed in more detail below. As illustrated, openings 126D extend beyond the lateral edges of underlying conductive features 122. As such, openings 126D may extend below the top surface of underlying conductive features 122 and partially or completely through dielectric layer 104. Furthermore, portions of openings 126D may expose dielectric layer 102. In some embodiments, due to dielectric layer 104 acting as an etch stop layer, openings 126D do not extend below the top surface of conductive features 122. Furthermore, the length and width of openings 126D (e.g., relative to the upper portion of openings 126D) may have similar dimensions and proportions as described above with respect to openings 126B and 126C. As further explained, because some of the conductive features 132D are exposed during the process of forming the opening 126D, the patterning process may etch a portion of the conductive features 132D. As a result, the conductive features 132D may be recessed from the top surface of the ILD 106.

[0070] In Figures 26A through 26I , conductive features 130 are formed in openings 126. Conductive features 130 provide electrical connections to corresponding epitaxial source / drain regions 82 via conductive features 122 (and, in some cases, to some of gate stacks 96 via conductive features 132). Therefore, the combination of conductive features 130 and corresponding conductive features 122 may also be referred to as source / drain contact plugs or source / drain plugs. Furthermore, conductive feature 122 may be referred to as a lower plug, and conductive feature 130 may be referred to as an upper plug. As illustrated, conductive feature 130A is formed in opening 126A, conductive feature 130B is formed in opening 126B, conductive feature 130C is formed in opening 126C, and conductive feature 130D is formed in opening 126D.

[0071] In some embodiments, opening 126 is formed after conductive feature 132 is formed. In such embodiments, conductive feature 132 may be protected, for example, by a mask (e.g., similar to the mask stack described above in conjunction with FIG. 23A and FIG. 23B ) while opening 128 is formed. In other embodiments, opening 126 is formed before opening 128 is formed. In such embodiments, conductive feature 130 is protected, for example, by a mask while opening 126 is formed. Furthermore, in some embodiments (not specifically described), openings 126A, 126B, 126C and corresponding conductive features 130A, 130B, 130C are formed before opening 126D and conductive feature 130D. Furthermore, any of conductive features 130A, 130B, 130C may be formed separately and in any suitable order.

[0072] After forming the conductive fill material of the conductive features 130, a planarization process is performed to remove the liner layer (e.g., barrier layer, adhesion layer, and seed layer, if present) and the portion of the conductive fill material that overfills the opening 126. The remaining portion of the liner layer and the conductive fill material forms the conductive features 130 in the opening 126. The planarization process may include a CMP process, an etch-back process, a polishing process, a combination thereof, or the like. After performing the planarization process, within the process variation of the planarization process, the top surfaces of the conductive features 130 and the ILD 106 are substantially flush or coplanar.

[0073] In some embodiments, conductive features 130 and 132 can be formed using materials and methods similar to those described above for conductive feature 122, and are not further described herein. In some embodiments, the conductive fill material of conductive feature 130 is the same as the conductive fill material of conductive feature 132. In other embodiments, the conductive fill material of conductive feature 130 is different from the conductive fill material of conductive feature 132. In some embodiments, the conductive fill material of conductive feature 130 and the conductive fill material of conductive feature 132 are the same as the conductive fill material of conductive feature 122. In other embodiments, the conductive fill material of conductive feature 130 and the conductive fill material of conductive feature 132 are different from the conductive fill material of conductive feature 122. In some embodiments, the top surfaces of conductive features 130 and 132 and the top surface of ILD 106 are substantially flush or coplanar.

[0074] Referring to Figures 26A, 26B, and 26G, conductive feature 130A can have the same rectangular or oval shape as described above in conjunction with opening 126A. Furthermore, conductive feature 130A can be centered or laterally offset above conductive feature 122. Furthermore, conductive feature 130A can have the same dimensions and proportions as described above in conjunction with opening 126A. Figure 26H illustrates how the resistance between conductive feature 130 and conductive feature 122 can be affected by the interface area between their respective conductive fill materials. Furthermore, the liner layer of either conductive feature 130 or 122 can have a higher resistance than its counterpart. For example, the slot shape of conductive feature 130B reduces this resistance by preventing misalignment between conductive feature 130B and conductive feature 122. The resistance is further reduced by increasing the interface area between the respective conductive fill materials of conductive features 130B and 122. Thus, the interface of conductive features 130A, 122 may have a resistance between 125 ohms and 150 ohms, such as 140 ohms, while the interface of conductive features 130B, 122 may have a resistance between 40 ohms and 50 ohms, such as 50 ohms. In some embodiments, the interface of conductive features 130B, 122 may have a resistance that is approximately three times or more less than the resistance between conductive features 130A, 122.

[0075] Referring to Figures 26A to 26D, 26G, and 26I, conductive features 130B and 130C can have the same slot shape as described above in conjunction with corresponding openings 126B and 126C. Furthermore, conductive features 130B and 130C can extend laterally beyond corresponding conductive feature 122, as illustrated and discussed above. Furthermore, conductive features 130B and 130C can have the same dimensions and proportions as described above in conjunction with openings 126B and 126C. As discussed above, this slot shape allows for a larger interface area for low-resistance electrical connection between conductive features 130B and 130C and corresponding conductive feature 122. Specifically, the corresponding conductive fill material has a lower electrical resistance than the corresponding liner layer. As illustrated in Figure 26I, the slot shape increases the interface area between the conductive fill material of conductive features 130B and 130C and the conductive fill material of conductive feature 122. Thus, the interface of conductive features 130C and 122 can have a resistance that is approximately three times or more less than the resistance between conductive features 130A and 122. For example, the resistance between conductive features 130C and 122 can be between 40 ohms and 50 ohms, such as 46 ohms. An additional advantage of these embodiments (e.g., the groove shape of conductive features 130B and 130C) is that a ring oscillator voltage boost of up to approximately 1% can be achieved.

[0076] Referring to Figures 26E, 26F, and 26G, conductive feature 130D can have the same slot shape and docking contact configuration as described above in conjunction with opening 126D. Conductive feature 130D can therefore be referred to as a docking contact because conductive feature 130D can contact both the corresponding conductive feature 132D and the corresponding conductive feature 122. Furthermore, conductive feature 130D can extend laterally beyond the corresponding conductive feature 122, achieving the benefits discussed above in conjunction with the contact configuration that allows docking with conductive feature 132. Furthermore, conductive feature 130D can have the same dimensions and proportions as described above in conjunction with opening 126D. It should be further appreciated that the slot shape and docking contact configuration of conductive feature 130D provide similar resistance reduction as described above in conjunction with conductive features 130B and 130C. It should be appreciated that conductive feature 130D can be utilized with transistors formed in a static RAM (e.g., SRAM) layout.

[0077] In some embodiments (not specifically described), after forming conductive feature 130, additional conductive features may be formed through ILD 106, dielectric layer 104, dielectric layer 102, and metal-dielectric liner 100 to form electrical connections to one of gate stacks 96 and one of conductive features 122 (e.g., to the underlying epitaxial source / drain region 82). The process may be performed similarly to that described above in connection with conductive features 122, 130, and 132, including similar photolithography steps (e.g., utilizing EUV lithography). However, conductive feature 130D (e.g., a docking contact) has the added advantage of being a replacement for these additional conductive features. Thus, the formation of conductive feature 130D eliminates photolithography steps, thereby reducing costs and improving the efficiency and yield of the semiconductor device.

[0078] In Figures 27A through 27F , in some embodiments, an interconnect structure 134 is formed over conductive features 130 and 132 and ILD 106. In some embodiments, interconnect structure 134 includes a plurality of dielectric layers, such as an inter-metal dielectric (IMD) (not separately illustrated) and conductive features within the IMD (not separately illustrated). The IMD can be formed using materials and methods similar to those used for ILD 88 described above with reference to Figures 11A and 11B , and will not be repeated herein. The conductive features include conductive lines and conductive vias and can be formed using a single damascene method, a dual damascene method, a combination thereof, or the like. The conductive features of interconnect structure 134 are in electrical contact with conductive features 130 and 132.

[0079] As further illustrated, interconnect structure 134 may include metallization layer 136, which is the lowest metallization layer in physical contact with some of conductive features 130 and 132. In some embodiments, metallization layer 136 may include one or more power rails 136P that provide power to various underlying components. For example, some power rails of metallization layer 136 may extend longer than the underlying conductive features 130. Furthermore, as illustrated in FIG. 27D , some of the underlying conductive features 130 may extend the same length as power rails 136P. Furthermore, the respective widths of conductive features 130 and metallization layer 136 may be substantially the same. Thus, certain conductive features (e.g., conductive feature 130D) may be considered to be part of the overlying power rails 136P. However, in some embodiments, conductive features 130 may comprise tungsten, while power rails 136P comprise copper, or conductive features 130 and power rails 136P may comprise substantially the same material.

[0080] Embodiments can achieve advantages. In some embodiments, source / drain contact plugs can be formed in various configurations to reduce resistance between components, such as lower plugs (e.g., conductive feature 122) and upper plugs (e.g., conductive feature 130). Specifically, conductive feature 130 can have a groove shape to prevent misalignment and increase the surface area of ​​the interface between conductive feature 130 and the corresponding conductive fill material of conductive feature 122, thereby reducing resistance therebetween. Furthermore, conductive feature 130 can extend over other integrated circuit components, such as gate stack 96. Thus, to prevent leakage between conductive feature 130 and gate stack 96, the material of dielectric layer 104 is selected to have a high etch selectivity to the gate mask (e.g., dielectric layer 102). Furthermore, metal dielectric liner 100 reduces the risk of misalignment of conductive feature 132M with gate stack 96, while also or alternatively providing the versatility of redundant conductive feature 132R.

[0081] In one embodiment, a method for forming a semiconductor device includes: forming an epitaxial source / drain region in a substrate; forming a first interlayer dielectric (ILD) above the epitaxial source / drain region; forming a gate stack above the substrate and adjacent to the first ILD; forming a gate mask above the gate stack; forming a source / drain plug through the first ILD and electrically connected to the epitaxial source / drain region; depositing a dielectric layer over the gate mask and the first ILD, the dielectric layer having a different etch selectivity than the gate mask; forming a second ILD over the dielectric layer; etching an opening through the second ILD and the dielectric layer, the opening exposing the source / drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature electrically connected to the source / drain plug. In another embodiment, forming the gate mask includes: recessing the gate stack; depositing a metal dielectric liner over the gate stack; and depositing a nitride layer over the metal dielectric liner. In another embodiment, the method further includes: forming additional epitaxial source / drain regions in the substrate; and forming additional source / drain plugs through the first interlayer dielectric and electrically connected to the additional epitaxial source / drain regions, wherein the conductive feature is in physical contact with the source / drain plugs and the additional source / drain plugs. In another embodiment, the method further includes: forming a gate plug through the second interlayer dielectric and electrically connected to the gate stack, wherein forming the conductive feature includes forming the conductive feature as a contact to the gate plug and the source / drain plugs. In another embodiment, the method further includes: performing an etching process to etch through the second interlayer dielectric and the dielectric layer before forming the conductive feature, wherein the dielectric layer acts as an etch stop during the etching process. In another embodiment, after performing the etching process, the gate mask remains substantially unetched. In another embodiment, the dielectric layer and the gate mask may have an etch selectivity greater than or equal to 10. In another embodiment, the gate mask comprises silicon nitride, and the dielectric layer comprises silicon carbonate or silicon carbonitride.

[0082] In one embodiment, a method for forming a semiconductor device includes: forming a first epitaxial region and a second epitaxial region in a substrate; forming a first oxide layer over the first epitaxial region and the second epitaxial region; forming a first gate stack and a second gate stack over the substrate, with the first gate stack interposed between the first epitaxial region and the second epitaxial region; forming a nitride mask over the first gate stack; etching the first oxide layer to expose the first epitaxial region and the second epitaxial region; forming a first conductive feature over the first epitaxial region and a second conductive feature over the second epitaxial region; forming an etch stop layer over the nitride mask and the first oxide layer; forming a second oxide layer over the etch stop layer; forming a gate plug over the first gate stack and in physical contact with the first gate stack; and forming a third conductive feature through the second oxide layer and the etch stop layer, the third conductive feature in physical contact with the first conductive feature. In another embodiment, the etch stop layer has an etch selectivity of 10 or greater compared to the nitride mask. In another embodiment, in plan view, the third conductive feature has a rectangular shape, wherein the length of the rectangular shape is two to three times greater than the width of the rectangular shape. In another embodiment, the third conductive feature is directly above the first epitaxial region, the first gate stack, and the second gate stack. In another embodiment, the third conductive feature is directly above the first epitaxial region and the second epitaxial region. In another embodiment, the third conductive feature is in physical contact with the gate plug.

[0083] In one embodiment, a semiconductor device includes: a gate stack over a substrate; a metal-dielectric liner over the gate stack; a gate mask over the metal-dielectric liner; a first oxide layer over the substrate, the top surface of the first oxide layer being flush with the top surface of the gate mask; a dielectric layer over the gate mask and the first oxide layer, the dielectric layer being a different material than the gate mask; a second oxide layer over the dielectric layer; a first conductive feature extending through the first oxide layer, the top surface of the first conductive feature being flush with the top surface of the gate mask; and a second conductive feature extending through the second oxide layer and the dielectric layer, the second conductive feature being in physical contact with the first conductive feature. In another embodiment, the gate mask comprises silicon nitride, and the dielectric layer comprises silicon carbonitride. In another embodiment, the gate mask comprises silicon nitride, and the dielectric layer comprises silicon carbonate. In another embodiment, in plan view, the second conductive feature has a length that is two to three times greater than its width. In another embodiment, the semiconductor device further includes a third conductive feature extending through the gate shield and physically contacting the gate stack, wherein the second conductive feature and the third conductive feature form a docking contact. In another embodiment, the second conductive feature is directly above the first conductive feature and directly above the gate stack, and wherein the gate shield is electrically interposed between the second conductive feature and the gate stack.

[0084] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0085] 50: base material 50N, 50P, 89: Area 51: Divider 52: Fin 54: Insulation material 56: Isolation Zone 58: Channel area 60: Virtual dielectric layer 62: Virtual gate layer 64: Mask layer 72: Virtual Gate 74:Mask 80: Gate sealing spacer 82: Source / Drain Region 86: Gate spacer 87: Contact etch stop layer 88, 106:ILD 90, 118, 126, 126A, 126B, 126C, 126D, 128, 128M, 128R: Open 91: Interface layer 92: Gate dielectric layer 94: Gate electrode 94A: cushion layer 94B: Work function adjustment layer 94C: conductive filling layer 96: Gate stack 98: Groove 99: Gate contact layer 100:Metal dielectric liner 102, 104: dielectric layer 120: Silicide layer 122, 130, 130A, 130B, 130C, 130D, 132, 132D, 132M, 132R: Conductive characteristics 134: Interconnection structure 136: Metallization layer 136P: Power rail AA, BB, CC: cross section

[0086] Domestic storage information (please note the order of storage institution, date, and number) none Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A method for forming a semiconductor device, comprising the following steps: forming a first epitaxial source / drain region and a second epitaxial source / drain region in a substrate; forming a first oxide layer over the first epitaxial source / drain region and the second epitaxial source / drain region; forming a first gate stack and a second gate stack over the substrate, the first gate stack being inserted between the first epitaxial region and the second epitaxial region; forming a nitride mask over the first gate stack; etching the first oxide layer to expose the first epitaxial source / drain region and the second epitaxial source / drain region; forming a first conductive feature over the first epitaxial source / drain region and a second conductive feature over the second epitaxial source / drain region; forming an etch stop layer over the nitride mask and the first oxide layer, the etch stop layer having an etch selectivity different from that of the nitride mask; forming a second oxide layer over the etch stop layer; A third conductive feature is formed through the second oxide layer and the etch stop layer, the third conductive feature being in contact with the first conductive feature; and a gate plug is formed above the first gate stack and in contact with the first gate stack.

2. The method of forming a semiconductor device as claimed in claim 1, wherein the step of forming the nitride mask includes the following steps: recessing the gate stack; depositing a metal dielectric pad over the gate stack; and depositing a nitride layer over the metal dielectric pad.

3. The method of forming a semiconductor element as claimed in claim 1, wherein the third conductive feature is located directly above the first epitaxial region and the second epitaxial region.

4. A method of forming a semiconductor element as claimed in claim 1, wherein the third conductive feature is in contact with the gate plug entity.

5. A method for forming a semiconductor device, comprising the following steps: forming a first epitaxial region and a second epitaxial region in a substrate; forming a first oxide layer over the first epitaxial region and the second epitaxial region; forming a first gate stack and a second gate stack over the substrate, the first gate stack being inserted between the first epitaxial region and the second epitaxial region; forming a nitride mask over the first gate stack; etching the first oxide layer to expose the first epitaxial region and the second epitaxial region; forming a first conductive feature over the first epitaxial region and a second conductive feature over the second epitaxial region; forming an etch stop layer over the nitride mask and the first oxide layer; forming a second oxide layer over the etch stop layer; forming a gate plug over the first gate stack and in contact with the first gate stack; and forming a third conductive feature passing through the second oxide layer and the etch stop layer, the third conductive feature being in contact with the first conductive feature.

6. A method for forming a semiconductor element as claimed in claim 5, wherein in a plan view, the third conductive feature has a rectangular shape, and wherein a length of the rectangular shape is two to three times greater than a width of the rectangular shape.

7. A method of forming a semiconductor element as claimed in claim 6, wherein the third conductive feature is located directly above the first epitaxial region, the first gate stack, and the second gate stack.

8. A semiconductor element, comprising: The first epitaxial region is located within a substrate. A second epitaxial region is located within the substrate; A first gate stack is positioned above the substrate and inserted between the first epitaxial region and the second epitaxial region; a second gate stack is positioned above the substrate; a metal dielectric pad is positioned above the first gate stack; a nitride mask is positioned above the metal dielectric pad; a first oxide layer is positioned above the substrate and above both the first and second epitaxial regions, with a top surface of the first oxide layer flush with a top surface of the nitride mask, the first oxide layer having a first opening and a second opening, the first opening exposing the first epitaxial region and the second opening exposing the second epitaxial region; a first conductive feature is positioned in the first opening and above the first epitaxial region, with a top surface of the first conductive feature flush with the top surface of the nitride mask; a second conductive feature is positioned in the second opening and above the second epitaxial region. An etch stop layer is located above the nitride mask and the first oxide layer, and the dielectric layer is made of a different material than the nitride mask; a second oxide layer is located above the etch stop layer; a third conductive feature extends through the second oxide layer and the etch stop layer, and the third conductive feature is in contact with the first conductive feature; and a gate plug is located above the first gate stack and is in contact with the first gate stack.

9. The semiconductor element as claimed in claim 8, wherein in a plan view, the third conductive feature has a rectangular shape, and wherein a length of the rectangular shape is two to three times greater than a width of the rectangular shape.

10. The semiconductor device as claimed in claim 9, wherein the third conductive feature is located directly above the first epitaxial region, the first gate stack, and the second gate stack.

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