Electronic device

Abstract

This disclosure provides an electronic device comprising: a first electronic unit; a first transistor electrically connected to the first electronic unit and including a first polycrystalline silicon semiconductor; a first insulating layer disposed on the first polycrystalline silicon semiconductor; a metal oxide layer disposed on the first insulating layer; a second transistor electrically connected to the first electronic unit and the first transistor and including a first oxide semiconductor; and a second insulating layer disposed between the metal oxide layer and the first oxide semiconductor; wherein the metal oxide layer includes a first pattern overlapping the first polycrystalline silicon semiconductor and a second pattern overlapping the first oxide semiconductor, and the thickness of the second insulating layer between the second pattern and the first oxide semiconductor is greater than or equal to 1000 Å and less than or equal to 8000 Å.

Description

[Technical Field]

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device using an oxide transistor with high carrier mobility. [Previous Technology]

[0002] Conventional electronic devices using oxide transistors often suffer from insufficient carrier mobility, resulting in poor device performance. To improve this problem, some electronic devices replace oxide transistors with low-temperature polycrystalline silicon transistors, but this introduces leakage current issues.

[0003] In view of this, there is a need to develop a novel electronic device to improve the above problems. [Summary of the Invention]

[0004] This disclosure provides an electronic device, comprising: a substrate, a first electronic unit, a first transistor, a first insulating layer, a metal oxide layer, a second transistor, and a second insulating layer. The first electronic unit is disposed on the substrate. The first transistor is disposed on the substrate and is electrically connected to the first electronic unit, comprising a first polycrystalline silicon semiconductor. The first insulating layer is disposed on the first polycrystalline silicon semiconductor. The metal oxide layer is disposed on the first insulating layer. The second transistor is electrically connected to the first electronic unit and the first transistor and comprises a first oxide semiconductor. The second insulating layer is disposed between the metal oxide layer and the first oxide semiconductor. The metal oxide layer comprises a separated first pattern and a second pattern, the first pattern overlapping the first polycrystalline silicon semiconductor, the second pattern overlapping the first oxide semiconductor, and the thickness of the second insulating layer between the second pattern and the first oxide semiconductor is greater than or equal to 1000 Å and less than or equal to 8000 Å.

Implementation Method

[0006] The following describes the implementation of this disclosure through specific embodiments. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different embodiments, and various details in this specification can also be modified and changed for different viewpoints and applications without departing from the spirit of this invention.

[0007] The exemplary embodiments disclosed herein will now be described in detail with reference to the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0008] It should be noted that, unless otherwise specified herein, having an element “a” is not limited to having a single element, but may include one or more elements. Furthermore, the use of ordinal numbers such as “first” and “second” in the specification and claims to modify elements of a claim does not itself imply or represent any prior ordinal number for the claimed element, nor does it represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0009] Certain terms are used throughout this disclosure and in the appended claims to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same element. This document is not intended to distinguish between elements that have the same function but different names. In the following description and claims, words such as “comprising,” “containing,” and “having” are open-ended terms and should therefore be interpreted as “containing but not limited to…”. Therefore, when the terms “comprising,” “containing,” and / or “having” are used in the description of this disclosure, they specify the presence of the corresponding feature, area, step, operation, and / or component, but do not exclude the presence of one or more of the corresponding feature, area, step, operation, and / or component.

[0010] In this text, the terms "about," "approximately," "substantially," and "roughly" generally indicate within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," "substantially," or "roughly," the meaning of "about," "approximately," "substantially," or "roughly" may still be implied. Furthermore, the terms "range from the first value to the second value" or "range between the first value and the second value" indicate that the range includes the first value, the second value, and other values ​​in between.

[0011] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined herein.

[0012] Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device in the diagram is flipped so that it is upside down, the element described as being on the "below" side will become the element on the "above" side. When a corresponding component (e.g., a membrane or region) is referred to as "on another component," it can be directly on the other component, or there may be other components between them. On the other hand, when a component is referred to as "directly on another component," there are no components between them. Additionally, when a component is referred to as "on another component," there is a vertical relationship between them in the top view direction, and this component can be above or below the other component, depending on the orientation of the device.

[0013] In this disclosure, the measurement of distance, width, length, and thickness can be obtained using an optical microscope or from cross-sectional images in an electron microscope, but this disclosure is not limited to these methods. Furthermore, the same photograph or more than one photograph can be used to measure distance, width, length, and thickness. Additionally, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the first and second values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0014] Furthermore, in this disclosure, unless otherwise specified, the electrical connection between two components may include a direct connection or an indirect connection. In an indirect connection, one or more other components, such as resistors, capacitors, or inductors, may be present between the two components. An electrical connection is used to transmit one or more signals, such as direct current or alternating current or voltage, depending on the application.

[0015] The electronic device disclosed herein may include, for example, a display device, a sensing device, an antenna device, a touch device, a splicing device, or other suitable electronic devices, but is not limited thereto. The display device disclosed herein may be a non-self-emissive display device or a self-emissive display device, such as a liquid crystal display, a cholesteric liquid crystal display, an electrophoretic display, an organic light-emitting diode display, or a light-emitting diode display, but is not limited thereto. The display device may include light-emitting diodes, light conversion layers, or other suitable materials, or combinations thereof, but is not limited thereto. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs (including QLEDs and QDLEDs), but are not limited thereto. The light conversion layer may include wavelength conversion materials and / or filter materials. The light conversion layer may include, for example, fluorescence, phosphorescence, quantum dots (QD), other suitable materials, or combinations thereof, but is not limited thereto. The sensing device may include, for example, biosensors, touch sensors, fingerprint sensors, infrared sensors, temperature sensors, other suitable sensors, or combinations of the above types of sensors. The antenna device may be, for example, a liquid crystal antenna or other types of antennas, but is not limited thereto. The splicing device may include, for example, a splicing display device or a splicing antenna device, but is not limited thereto. The electronic device may include electronic components, which may include passive components, active components, or combinations thereof, such as capacitors, resistors, inductors, varactor diodes, variable capacitors, filters, diodes, transistors, sensors, microelectromechanical systems (MEMS) components, chips, etc., but is not limited thereto. It should be noted that the electronic device disclosed herein may be various combinations of the above devices, but is not limited thereto.

[0016] Furthermore, the electronic device may be rectangular, circular, polygonal, have curved edges, or other suitable shapes. The electronic device may have peripheral systems such as drive systems, control systems, light source systems, and shelving systems to support display devices, antenna devices, or splicing devices.

[0017] It should be understood that the features in the following embodiments can be replaced, reorganized, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0018] FIG1 is a schematic diagram of the basic driving circuit of an electronic device according to an embodiment of the present disclosure.

[0019] In one embodiment of this disclosure, the basic driving circuit of the electronic device 1 may include a driving transistor T1, a data writing transistor T2, a reset transistor T3, a transistor T4, a transistor T5, and a switching transistor T6, but is not limited thereto. At least one of the aforementioned driving transistor T1, data writing transistor T2, reset transistor T3, transistor T4, transistor T5, and switching transistor T6 may be electrically connected to the electronic unit E. The driving transistor T1 may include a first terminal a1, a second terminal b1, and a control terminal c1, wherein the first terminal a1 may be a drain or a source, the second terminal b1 may be a drain or a source, and the control terminal c1 may be a gate. The data writing transistor T2 may include a first terminal a2, a second terminal b2, and a control terminal c2, wherein the first terminal a2 may be a drain or a source, the second terminal b2 may be a drain or a source, and the control terminal c2 may be a gate. A reset transistor T3 may include a first terminal a3, a second terminal b3, and a control terminal c3, wherein the first terminal a3 may be a drain or a source, the second terminal b3 may be a drain or a source, and the control terminal c3 may be a gate. A transistor T4 may include a first terminal a4, a second terminal b4, and a control terminal c4, wherein the first terminal a4 may be a drain or a source, the second terminal b4 may be a drain or a source, and the control terminal c4 may be a gate. A transistor T5 may include a first terminal a5, a second terminal b5, and a control terminal c5, wherein the first terminal a5 may be a drain or a source, the second terminal b5 may be a drain or a source, and the control terminal c5 may be a gate. A switching transistor T6 may include a first terminal a6, a second terminal b6, and a control terminal c6, wherein the first terminal a6 may be a drain or a source, the second terminal b6 may be a drain or a source, and the control terminal c6 may be a gate.

[0020] In one embodiment, the semiconductor materials in the driving transistor T1, data writing transistor T2, transistor T4, and transistor T5 may include, for example, low-temperature polysilicon (LTPS), but are not limited thereto. In one embodiment, the semiconductor materials in the reset transistor T3 and the switching transistor T6 may comprise metal oxides, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), or combinations thereof, but are not limited thereto.

[0021] In one embodiment, the first terminal a1 of the driving transistor T1 can be electrically connected to the second terminal b2 of the data writing transistor T2 and the second terminal b4 of the transistor T4. The second terminal b1 of the driving transistor T1 can be electrically connected to the first terminal a5 of the transistor T5. The control terminal c1 of the driving transistor T1 can be electrically connected to the first terminal a6 of the switching transistor T6 and can be electrically connected to a capacitor C2. The first terminal a2 of the data writing transistor T2 can be electrically connected to a data line DL, and the control terminal c2 of the data writing transistor T2 can be electrically connected to a scan line S SN-2. The first terminal a3 of the reset transistor T3 can be electrically connected to the control terminal c1 of the driving transistor T1 and forms a capacitor C1 with a high potential Vdd. The second terminal b3 of the reset transistor T3 can be electrically connected to an initial potential Vini, and the control terminal c3 of the reset transistor T3 can be electrically connected to a scan line S SN-4. The first terminal a4 of transistor T4 is electrically connected to a high potential Vdd, and the control terminal c4 of transistor T4 is electrically connected to a scan line S SN-1. The second terminal b5 of transistor T5 is electrically connected to electronic unit E, and the control terminal c5 of transistor T5 is electrically connected to the control terminal c4 of transistor T4. The second terminal b6 of switching transistor T6 is electrically connected to the first terminal a5 of transistor T5, and the control terminal c6 of switching transistor T6 is electrically connected to a scan line S SN-3. In one embodiment, the high potential Vdd can be used to adjust electronic unit E. One end of electronic unit E is electrically connected to the second terminal b5 of transistor T5, and the other end of electronic unit E is electrically connected to a low potential Vss.

[0022] Next, the structure of some transistors of an electronic device according to an embodiment of the present disclosure will be described.

[0023] FIG2 is a top view of a portion of the active area of ​​an electronic device according to an embodiment of the present disclosure. FIG3 is a cross-sectional schematic diagram of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. In FIG3, the cross-sectional schematic diagram of the portion of the active area is a cross-sectional schematic diagram along the section line A-A' of FIG2. In addition, in FIG3, the dashed lines indicate that the two elements connected by the dashed lines are electrically connected to each other in other areas of the electronic elements.

[0024] In one embodiment, as shown in Figures 2 and 3, the electronic device 1 disclosed herein includes: a substrate 11; a first electronic unit (electronic unit E as shown in Figure 1 or green display unit G1 as shown in Figure 11) disposed on the substrate 11; a first transistor TA disposed on the substrate 11, wherein the first transistor TA is electrically connected to the first electronic unit (electronic unit E as shown in Figure 1 or green display unit G1 as shown in Figure 11) and includes a first polycrystalline silicon semiconductor 131; a first insulating layer 14 disposed on the first polycrystalline silicon semiconductor 131; and a metal oxide layer 171. A first insulating layer 14 is disposed on the first insulating layer 14; a second transistor TB is electrically connected to the first electronic unit E (electronic unit E as shown in FIG. 1 or green display unit G1 as shown in FIG. 11) and the first transistor TA and includes a first oxide semiconductor 191; and a second insulating layer 18 is disposed between the metal oxide layer 171 and the first oxide semiconductor 191; wherein the metal oxide layer 171 includes a separate first pattern 1711 and a second pattern 1712, the first pattern 1711 overlaps with the first polycrystalline silicon semiconductor 131, and the second pattern 1712 overlaps with the first oxide semiconductor 191.

[0025] More specifically, in this disclosure, as shown in FIG2, in the top view Z, at least a portion of the first pattern 1711 of the metal oxide layer 171 overlaps with at least a portion of the first polycrystalline silicon semiconductor 131; and as shown in FIG3, in the cross-sectional view, at least a portion of the first pattern 1711 of the metal oxide layer 171 overlaps with at least a portion of the first polycrystalline silicon semiconductor 131. Furthermore, as shown in FIG2, in the top view Z, at least a portion of the second pattern 1712 of the metal oxide layer 171 overlaps with at least a portion of the first oxide semiconductor 191; and as shown in FIG3, in the cross-sectional view, at least a portion of the second pattern 1712 of the metal oxide layer 171 overlaps with at least a portion of the first oxide semiconductor 191.

[0026] In this disclosure, by providing an oxide metal layer 171, and in particular by providing a second pattern 1712 of the oxide metal layer 171 overlapping with the first oxide semiconductor 191, the carrier mobility of the second transistor TB containing the first oxide semiconductor 191 can be improved, thereby improving the performance of the second transistor TB and thus improving the performance of the electronic device.

[0027] In this disclosure, as shown in FIG2, an oxide metal layer 171 is provided on all second metal layers 17. In other embodiments of this disclosure, although not shown in the figures, not all second metal layers 17 are provided with an oxide metal layer 171, but only those corresponding to the first oxide semiconductor 191 are provided with an oxide metal layer 171. For example, in other embodiments of this disclosure, although not shown in the figures, the oxide metal layer 171 of the electronic device 1 may not include the first pattern 1711, that is, a portion 17A of the second metal layer 17 (as shown in FIG3) may selectively not be provided with an oxide metal layer 171.

[0028] In this disclosure, as shown in FIG3, the electronic device 1 may include: a substrate 11; a buffer layer 12 disposed on the substrate 11; a polycrystalline silicon semiconductor layer 13 (including a first polycrystalline silicon semiconductor 131) disposed on the buffer layer 12; an insulating layer 141 disposed on the polycrystalline silicon semiconductor layer 13; a first metal layer 15 disposed on the insulating layer 141; an insulating layer 142 disposed on the first metal layer 15, wherein the insulating layer 141 and the insulating layer 142 form a first insulating layer 14; and a second metal layer 17 disposed on the first insulating layer 14. A metal oxide layer 171 is disposed on the second metal layer 17; a second insulating layer 18 is disposed on the metal oxide layer 171; an oxide semiconductor layer 19 (including a first oxide semiconductor 191) is disposed on the second insulating layer 18; a third insulating layer 20 is disposed on the oxide semiconductor layer 19; a third metal layer 21 is disposed on the third insulating layer 20; a fourth insulating layer 22 is disposed on the third metal layer 21; a fourth metal layer 23 is disposed on the fourth insulating layer 22; and a fifth insulating layer 24 is disposed on the fourth metal layer 23. The fourth metal layer 23 is electrically connected to the first polycrystalline silicon semiconductor 131 and the first oxide semiconductor 191 through a plurality of vias passing through the first insulating layer 14, the second insulating layer 18, the third insulating layer 20, and the fourth insulating layer 22.

[0029] In this disclosure, the first transistor TA may include a portion of the first polysilicon semiconductor 131, a portion 232 of the fourth metal layer 23, and a portion 151 of the first metal layer 15. The portion 151 of the first metal layer 15 may serve as a gate, and the portion 232 of the fourth metal layer 23 may serve as a source or drain and be electrically connected to the first polysilicon semiconductor 131. Although not shown in the figures, the fourth metal layer 23 may further include another portion serving as a source or drain and being electrically connected to the first polysilicon semiconductor 131.

[0030] In this disclosure, the second transistor TB may include a first oxide semiconductor 191, a portion 17B of a second metal layer 17, a portion 211 of a third metal layer 21, and portions 233 and 234 of a fourth metal layer 23. The portion 17B of the second metal layer 17 and the portion 21 of the third metal layer 21 may serve as the bottom gate and the top gate, respectively. One of the portions 233 and 234 of the fourth metal layer 23 may serve as the source and the other as the drain. The portions 233 and 234 of the fourth metal layer 23 are electrically connected to the first oxide semiconductor 191.

[0031] In this disclosure, the electronic device 1 may further include an oxide semiconductor layer 19 disposed on the substrate 11; and a third transistor TC electrically connected to the first transistor TA (as shown by the dashed line) and including a second oxide semiconductor 192; wherein, a portion of the oxide semiconductor layer 19 is the first oxide semiconductor 191, another portion of the oxide semiconductor layer 19 is the second oxide semiconductor 192, and the metal oxide layer 171 includes a third pattern 1713, the third pattern 1713 overlapping with the second oxide semiconductor 192 and separate from the second pattern 1712.

[0032] More specifically, in this disclosure, as shown in FIG2, in the top view Z, at least a portion of the third pattern 1713 of the metal oxide layer 171 overlaps with at least a portion of the second oxide semiconductor 192; and as shown in FIG3, in the cross-sectional view, at least a portion of the third pattern 1713 of the metal oxide layer 171 overlaps with at least a portion of the second oxide semiconductor 192.

[0033] In this disclosure, the third transistor TC may include a second oxide semiconductor 192, a portion 17C of the second metal layer 17, a portion 212 of the third metal layer 21, and portions 234 and 235 of the fourth metal layer 23. The portion 17C of the second metal layer 17 and the portion 212 of the third metal layer 21 may serve as the bottom gate and the top gate, respectively. One of the portions 234 and 235 of the fourth metal layer 23 may serve as the source and the other as the drain. The portions 234 and 235 of the fourth metal layer 23 are electrically connected to the second oxide semiconductor 192.

[0034] In this disclosure, as shown in FIG3, the metal oxide layer 171 in the second transistor TB and the third transistor TC of the electronic device 1 respectively includes a second pattern 1712 and a third pattern 1713. In other embodiments of this disclosure, although not shown in the figures, the metal oxide layer 171 in the second transistor TB of the electronic device 1 may not include the second pattern 1712, that is, the metal oxide layer 171 may not be provided on the portion 17B of the second metal layer 17. In other embodiments of this disclosure, although not shown in the figures, the metal oxide layer 171 in the third transistor TC of the electronic device 1 may not include the third pattern 1713, that is, the metal oxide layer 171 may not be provided on the portion 17C of the second metal layer 17.

[0035] In this disclosure, as shown in the top view of FIG2, the electronic device 1 may further include a wire 15A, and the wire 15A is disposed between the second pattern 1712 and the third pattern 1713.

[0036] In this disclosure, a portion 17A of the second metal layer 17 may overlap with a portion 151 of the first metal layer 15 to form a capacitor.

[0037] In this disclosure, as shown in FIG3, the electronic device 1 may further include: a polysilicon semiconductor layer 13 disposed on a substrate 11; and another transistor TD, including a second polysilicon semiconductor 132; wherein a portion of the polysilicon semiconductor layer 13 is a first polysilicon semiconductor 131, and another portion of the polysilicon semiconductor layer 13 is a second polysilicon semiconductor 132. The transistor TD may include the second polysilicon semiconductor 132, a portion 152 of a first metal layer 15, and a portion 236 of a fourth metal layer 23. The portion 152 of the first metal layer 15 may serve as a gate, and the portion 236 of the fourth metal layer 23 may serve as a source or drain and be electrically connected to the second polysilicon semiconductor 132. Although not shown in the figure, the fourth metal layer 23 may further include another portion serving as a source or drain and being electrically connected to the second polysilicon semiconductor 132.

[0038] In this embodiment, the first transistor TA may be, for example, a driving transistor, such as the driving transistor T1 shown in FIG1. ​​In this embodiment, the second transistor TB may be, for example, a switching transistor, such as the switching transistor T6 shown in FIG1. ​​In this embodiment, the third transistor TC may be, for example, a reset transistor, such as the reset transistor T3 shown in FIG1. ​​In this embodiment, the transistor TD may be, for example, a data writing transistor, such as the data writing transistor T2 shown in FIG1. ​​However, this disclosure is not limited thereto.

[0039] In this disclosure, the so-called "metal oxide layer," such as the metal oxide layer 171 of this embodiment and the metal oxide layer described in subsequent embodiments, can provide oxygen atoms to the oxide semiconductor and improve the reliability of the oxide semiconductor, enabling the threshold voltage (Vth) of the subsequent transistor containing the oxide semiconductor to be positively biased. The thickness of the metal oxide layer can be approximately 30% to approximately 50% of the thickness of the oxide semiconductor layer, which is a numerical range for adequately supplying oxygen atoms to the oxide semiconductor layer. If the thickness of the metal oxide layer is less than approximately 30% of the thickness of the oxide semiconductor layer, the metal oxide layer may not be able to adequately supply oxygen atoms to the oxide semiconductor layer, raising concerns about a negatively biased threshold voltage in the oxide semiconductor layer. If the thickness of the metal oxide layer exceeds approximately 50% of the thickness of the oxide semiconductor layer, an excessive amount of oxygen atoms may be supplied, potentially causing the threshold voltage of the transistor containing the oxide semiconductor layer to be too high.

[0040] In this disclosure, the so-called "oxide semiconductor", such as the oxide semiconductor layer 19, the first oxide semiconductor 191, the second oxide semiconductor 192 of this embodiment and the oxide semiconductor described in subsequent embodiments, may be a high mobility oxide (HMO), wherein the mobility may be greater than 15 cm 2 / V-sec, for example, the mobility may be between 36 cm 2 / V-sec and 80 cm 2 / V-sec.

[0041] In this disclosure, the metal oxide layer and the oxide semiconductor may each be a metal oxide comprising indium (In), zinc (Zn), gallium (Ga), tin (Sn), or aluminum (Al). For example, the materials of the metal oxide layer and the oxide semiconductor layer may be indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin gallium zinc oxide (ITGZO), or indium gallium oxide (IGO). In one embodiment of this disclosure, the metal oxide layer and the oxide semiconductor may comprise the same base material; in another embodiment of this disclosure, the metal oxide layer and the oxide semiconductor may comprise the same material; however, this disclosure is not limited thereto. In one embodiment of this disclosure, the oxide semiconductor comprises indium gallium zinc oxide (IGZO), but this disclosure is not limited thereto. Furthermore, in one embodiment of this disclosure, if necessary, the metal oxide layer and the oxide semiconductor may each comprise a doped carrier, such as an N-type carrier or a P-type carrier.

[0042] In this disclosure, as shown in FIG3, the thickness t1 of the second insulating layer 18 between the second pattern 1712 and the first oxide semiconductor 191 can be greater than or equal to 1000 Å and less than or equal to 8000 Å (1000 Å ≦ t1 ≦ 8000 Å), for example, greater than or equal to 1000 Å and less than or equal to 5000 Å (1000 Å ≦ t1 ≦ 5000 Å), or greater than or equal to 1000 Å and less than or equal to 4000 Å (1000 Å ≦ t1 ≦ 4000 Å). The second insulating layer 18 can comprise a single-layer or multi-layer structure, and its material can each comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, aluminum oxide, or combinations thereof, but this disclosure is not limited thereto. In one embodiment, the second insulating layer 18 includes at least one silicon oxide layer, and the thickness of the silicon oxide layer may be greater than or equal to 1000 Å and less than or equal to 4000 Å (1000 Å ≤ thickness ≤ 4000 Å). In another embodiment, in addition to including a silicon oxide layer (whose thickness may be greater than or equal to 1000 Å and less than or equal to 4000 Å), the second insulating layer 18 may also include other insulating material layers, but the layer in contact with the first oxide semiconductor 191 must be a silicon oxide layer. When the thickness t1 of the second insulating layer 18 or the silicon oxide layer of the second insulating layer 18 is within the aforementioned range, it is advantageous for the metal oxide layer 171 to provide oxygen atoms to the oxide semiconductor layer 19.

[0043] In this disclosure, as shown in FIG3, the thickness t2 of the first insulating layer 14 may be greater than or equal to 1000 Å and less than or equal to 5000 Å (1000 Å ≦ t2 ≦ 5000 Å), for example, greater than or equal to 1000 Å and less than or equal to 2000 Å (1000 Å ≦ t2 ≦ 2000 Å), or greater than or equal to 3000 Å and less than or equal to 5000 Å (3000 Å ≦ t2 ≦ 5000 Å). The first insulating layer 14 may comprise a single-layer or multi-layer structure, and its material may each comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, aluminum oxide, or combinations thereof, but this disclosure is not limited thereto. In one embodiment, the first insulating layer 14 includes at least a silicon nitride layer, and the thickness of the silicon nitride layer may be greater than or equal to 1000 Å and less than or equal to 2000 Å (1000 Å ≤ thickness ≤ 2000 Å). In one embodiment, as shown in FIG2, the first insulating layer 14 may include an insulating layer 141 and an insulating layer 142, wherein the insulating layer 141 may be a silicon oxide layer with a thickness greater than or equal to 1000 Å and less than or equal to 2000 Å (1000 Å ≤ thickness ≤ 2000 Å), and the insulating layer 142 may be a silicon nitride layer with a thickness greater than or equal to 1000 Å and less than or equal to 2000 Å (1000 Å ≤ thickness ≤ 2000 Å).

[0044] In this disclosure, as shown in FIG3, the electronic device 1 may further include a conductive structure (including a portion 231 of the fourth metal layer 23), wherein the first pattern 1711 has an opening 1711A, and the conductive structure (including a portion 231 of the fourth metal layer 23) is electrically connected through the opening 1711A of the first pattern 1711 to a first transistor TA (e.g., a portion 151 of the first metal layer 15 (i.e., the gate)) and a second transistor TB (e.g., a portion 234 of the fourth metal layer 23 (i.e., the source or drain)). More specifically, the portions 231 and 234 of the fourth metal layer 23 are electrically connected (as shown by the dashed line), so the conductive structure (including a portion 231 of the fourth metal layer 23) is electrically connected through the opening 1711A of the first pattern 1711 to the gate of the first transistor TA (i.e., a portion 151 of the first metal layer 15) and the source or drain of the second transistor TB (i.e., a portion 234 of the fourth metal layer 23).

[0045] In this disclosure, as shown in FIG3, the electronic device 1 may further include a conductive pattern (i.e., a portion 17A of the second metal layer 17) overlapping with the first pattern 1711 and having an opening 17A1, wherein the first transistor TA includes a gate (i.e., a portion 151 of the first metal layer 15), the conductive pattern (i.e., a portion 17A of the second metal layer 17) is disposed between the first pattern 1711 and the gate (i.e., a portion 151 of the first metal layer 15) of the first transistor TA, and the conductive structure (including a portion 231 of the fourth metal layer 23) is electrically connected to the first transistor TA through the opening 17A1 of the conductive pattern (i.e., a portion 17A of the second metal layer 17).

[0046] In this disclosure, as shown in the enlarged view of FIG3, the width W1 of the opening 1711A of the first pattern 1711 may be greater than the width W2 of the opening 17A1 of the conductive pattern (i.e., portion 17A of the second metal layer 17) (W1 > W2). In other embodiments, although not shown in the figures, the width W1 of the opening 1711A of the first pattern 1711 may be approximately equal to the width W2 of the opening 17A1 of the conductive pattern (i.e., portion 17A of the second metal layer 17).

[0047] In this disclosure, as shown in FIG3, in a cross-sectional view, the width of the second metal layer 17 is greater than the width of the oxide metal layer 171 above it; or, as shown in FIG2, in the top view Z, the projection of the oxide metal layer 171 on the substrate 11 is smaller than the projection of the second metal layer 17 on the substrate 11, or the projection of the oxide metal layer 171 on the substrate 11 falls within the projection of the second metal layer 17 on the substrate 11.

[0048] In other embodiments of this disclosure, although not shown in the figures, in a cross-sectional view, the width of the second metal layer 17 may be substantially equal to the width of the oxide metal layer 171 above it; or, in the top view Z, the projection of the oxide metal layer 171 onto the substrate 11 may be substantially equal to the projection of the second metal layer 17 onto the substrate 11, or the projection of the oxide metal layer 171 onto the substrate 11 overlaps with the projection of the second metal layer 17 onto the substrate 11.

[0049] In this disclosure, as shown in the enlarged view of FIG3, the width W3 of the first pattern 1711 may be less than the width W4 of the conductive pattern (i.e., portion 17A of the second metal layer 17) (W3 < W4). In other embodiments, although not shown, the width W3 of the first pattern 1711 may be approximately equal to the width W4 of the conductive pattern (i.e., portion 17A of the second metal layer 17).

[0050] In this disclosure, the widths W1, W2, W3, and W4 mentioned above are the maximum widths of the referred elements.

[0051] As shown in FIG3, in this disclosure, the electronic device 1 may include: an active region AA; and a peripheral region P adjacent to the active region AA. The aforementioned first transistor TA, second transistor TB, third transistor TC, and transistor TD are disposed in the active region AA. Furthermore, the electronic device 1 may include: a fourth transistor TE and a fifth transistor TF, disposed in the peripheral region P and serving as a gate drive circuit. The fourth transistor TE can be considered as the signal output transistor of the first gate drive circuit, and the fifth transistor TF is the signal output transistor of the second gate drive circuit.

[0052] In this disclosure, the term "active area" refers to the area where the main components of an electronic device operate or are operated by the user, such as the light-emitting unit or the location for transmitting and receiving electromagnetic waves, but this disclosure is not limited thereto. In this disclosure, the term "peripheral area" refers to the area outside the active area of ​​an electronic device.

[0053] In this disclosure, as shown in FIG3, the fourth transistor TE may include a portion of the polysilicon semiconductor layer 13, a portion of the first metal layer 15, and a portion of the fourth metal layer 23. The portion of the first metal layer 15 may serve as the gate, and the portion of the fourth metal layer 23 may serve as the source and drain, respectively. The portion of the fourth metal layer 23 is electrically connected to a portion 211 of the third metal layer 21 (the top gate of the second transistor TB) through a portion 213 of the third metal layer 21, as shown by the dashed line. Therefore, the fourth transistor TE in the peripheral region P can be electrically connected to the second transistor TB in the active region AA to drive the second transistor TB.

[0054] In this disclosure, as shown in FIG3, the fifth transistor TF may include a portion of a polysilicon semiconductor layer 13, a portion of a first metal layer 15, and a portion of a fourth metal layer 23. The portion of the first metal layer 15 may serve as a gate, and the portion of the fourth metal layer 23 may serve as a source and a drain, respectively. The portion of the fourth metal layer 23 is electrically connected to a portion 152 (the gate of transistor TD) of the first metal layer 15 through a portion 153 of the first metal layer 15, as shown by the dashed line. Therefore, the fifth transistor TF in the peripheral region P can be electrically connected to the transistor TD in the active region AA to drive the transistor TD.

[0055] In this disclosure, the substrate 11 may be a flexible substrate or a rigid substrate, and the material of the substrate 11 may be glass, quartz, sapphire, ceramic, plastic, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), other suitable materials or combinations of the above materials, but this disclosure is not limited thereto.

[0056] In this disclosure, the first metal layer 15, the second metal layer 17, the third metal layer 21 and the fourth metal layer 23 may each contain a metal material, a metal oxide material, an alloy thereof or a combination thereof, such as gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO) or aluminum zinc oxide (AZO), but this disclosure is not limited thereto.

[0057] In this disclosure, the buffer layer 12, the third insulating layer 20, the fourth insulating layer 22 and the fifth insulating layer 24 may each include a single layer or a multilayer structure, and their materials may each include silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, aluminum oxide or a combination thereof, but this disclosure is not limited thereto.

[0058] In this disclosure, the material of the polycrystalline silicon semiconductor layer 13 (including the first polycrystalline silicon semiconductor 131 and the second polycrystalline silicon semiconductor 132) may include polycrystalline silicon, such as low-temperature polycrystalline silicon (LTPS).

[0059] In this disclosure, the so-called "electronic unit", such as the first electronic unit E shown in FIG1 and the electronic units described in subsequent embodiments, may include a chip, a light-emitting diode, a variable capacitor, a variable resistor, a varactor diode, other suitable electronic components or combinations thereof, but is not limited thereto.

[0060] In this disclosure, the term "pattern", such as the first pattern 1711 and the second pattern 1712 shown in FIG2 and FIG3 and the pattern referred to in subsequent embodiments, refers to an independent piece, which may be block-shaped, line-shaped or other suitable shape, but is not limited thereto.

[0061] In this disclosure, the term "part" refers to a region of an independent block.

[0062] In this disclosure, the term "structure", such as the conductive structure shown in FIG3 (including portion 231 of the fourth metal layer 23) and the structure referred to in the following embodiments, is composed of elements of a specific layer and portions thereof that penetrate multiple layers of insulating layers.

[0063] FIG4 is a schematic cross-sectional view of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. In FIG4, the dashed lines indicate that the two elements connected by the dashed lines are electrically connected to each other in other areas of the electronic elements. The electronic device of FIG4 is similar to that of FIG3, except for the following differences.

[0064] As shown in FIG4 in this disclosure, the electronic device 1 may further include another metal oxide layer 21'. The material of the metal oxide layer 21' and the functions it achieves are similar to those of the aforementioned metal oxide layer 171, and will not be described again.

[0065] In this disclosure, as shown in FIG4, in the third transistor TC of the active region AA, the metal oxide layer 21' may include a fourth pattern 21'B overlapping with the second oxide semiconductor 192, wherein the third pattern 1713 of the metal oxide layer 171 and the fourth pattern 21'B of the metal oxide layer 21' are disposed on opposite sides of the second oxide semiconductor 192. In one embodiment, as shown in FIG4, in a cross-sectional view, at least a portion of the fourth pattern 21'B of the metal oxide layer 21' overlaps with at least a portion of the second oxide semiconductor 192; and although not shown in the figure, in the top view Z, at least a portion of the fourth pattern 21'B of the metal oxide layer 21' overlaps with at least a portion of the second oxide semiconductor 192. The fourth pattern 21'B of the metal oxide layer 21' is located below a portion 212 of the third metal layer 21 and is separated from the second oxide semiconductor 192 by a third insulating layer 20.

[0066] In this disclosure, as shown in FIG4, in the second transistor TB of the active region AA, the metal oxide layer 21' may include a fifth pattern 21'A overlapping with the first oxide semiconductor 191, wherein the fifth pattern 21'A of the metal oxide layer 21' and the second pattern 1712 of the metal oxide layer 171 are disposed on opposite sides of the first oxide semiconductor 191. In one embodiment, as shown in FIG4, in a cross-sectional view, at least a portion of the fifth pattern 21'A of the metal oxide layer 21' overlaps with at least a portion of the first oxide semiconductor 191; and although not shown in the figure, in the top view Z, at least a portion of the fifth pattern 21'A of the metal oxide layer 21' overlaps with at least a portion of the first oxide semiconductor 191. The fifth pattern 21'A of the metal oxide layer 21' is located below a portion 211 of the third metal layer 21 and is separated from the first oxide semiconductor 191 by a third insulating layer 20.

[0067] In this disclosure, as shown in FIG4, in the fourth transistor TE in the peripheral region P, the metal oxide layer 171 may further include a sixth pattern 1714 disposed on a portion 17D of the second metal layer 17, and the sixth pattern 1714 is electrically connected to the fourth transistor TE and the second transistor TB, as shown by the dashed line. More specifically, the fourth metal layer 23, which serves as the source or drain, can be electrically connected to a portion 17B (the bottom gate of the second transistor TB) of the second metal layer 17 through the portion 17D of the second metal layer 17 and the sixth pattern 1714 of the metal oxide layer 171, as shown by the dashed line. Therefore, the fourth transistor TE in the peripheral region P can be electrically connected to the second transistor TB in the active region AA, thereby driving the second transistor TB. Although not shown in the figure, in other embodiments disclosed herein, the sixth pattern 1714 of the oxide metal layer 171 may be selectively not provided on a portion 17D of the second metal layer 17, and the fourth metal layer 23 of the source or drain portion is electrically connected to a portion 17B of the second metal layer 17 (the bottom gate of the second transistor TB) through a portion 17D of the second metal layer 17.

[0068] As shown in Figure 4, the other components of the electronic device, their materials, their locations, and other features are as described above and will not be repeated here.

[0069] FIG5 is a schematic cross-sectional view of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. In FIG5, the dashed lines indicate that the two elements connected by the dashed lines are electrically connected to each other in other areas of the electronic components. The electronic device of FIG5 is similar to that of FIG3, except for the following differences.

[0070] In this disclosure, as shown in FIG5, in the peripheral region P, a sixth pattern 1714 of an oxide metal layer 171 may be provided on a portion 17D of the second metal layer 17. In this disclosure, the fourth metal layer 23 serving as the source or drain in the fourth transistor TE can be electrically connected to a portion 17B of the second metal layer 17 (the bottom gate of the second transistor TB) through a portion 17D of the second metal layer 17 and the sixth pattern 1714 of the oxide metal layer 171, as shown by the dashed line. Furthermore, in this disclosure, the fourth metal layer 23 serving as the source or drain can also be electrically connected to a portion 211 of the third metal layer 21 (the top gate of the second transistor TB) through a portion 213 of the third metal layer 21, as shown by the dashed line. Therefore, the fourth transistor TE in the peripheral region P can be electrically connected to the second transistor TB in the active region AA to drive the second transistor TB.

[0071] As shown in Figure 5, the other components of the electronic device, their materials, their locations, and other features are as described above and will not be repeated here.

[0072] FIG6 is a schematic cross-sectional view of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. In FIG6, the dashed lines indicate that the two elements connected by the dashed lines are electrically connected to each other in other areas of the electronic components. The electronic device of FIG6 is similar to that of FIG3, except for the following differences.

[0073] In this disclosure, as shown in FIG6, in the third transistor TC of the active region AA, the oxide metal layer 171 may not include the third pattern 1713 (as shown in FIG3), that is, the oxide metal layer 171 is not provided on the portion 17C of the second metal layer 17. In other embodiments of this disclosure, although not shown in the figures, the oxide metal layer 171 may be provided on the portion 17C of the second metal layer 17 as shown in FIG3.

[0074] In the electronic device shown in FIG3, the transistor TD in the active region AA is a transistor including a second polysilicon semiconductor 132. However, in the electronic device shown in FIG6, the transistor TD' in the active region AA is a transistor including a third oxide semiconductor 193.

[0075] More specifically, as shown in FIG6, the transistor TD' may include a third oxide semiconductor 193 of oxide semiconductor layer 19, a portion 17E of second metal layer 17, a portion 214 of third metal layer 21, and portions 237 and 238 of fourth metal layer 23, wherein the portion 17E of second metal layer 17 and the portion 214 of third metal layer 21 serve as bottom gate and top gate, respectively, and one of the portions 237 and 238 of fourth metal layer 23 can serve as source and the other as drain, and the portions 237 and 238 of fourth metal layer 23 are electrically connected to the third oxide semiconductor 193. In addition, a pattern 1715 of metal oxide layer 171 is further provided on the portion 17E of second metal layer 17, and a pattern 21'C of metal oxide layer 21' is further provided under the portion 214 of third metal layer 21, and the pattern 1715 of metal oxide layer 171 and the pattern 21'C of metal oxide layer 21' are disposed on opposite sides of third oxide semiconductor 193.

[0076] In other embodiments of this disclosure, although not shown in the figures, a pattern 21'C of the metal oxide layer 21' may not be provided under a portion 214 of the third metal layer 21 of the transistor TD'.

[0077] In this disclosure, as shown in FIG6, in the peripheral region P, the fourth metal layer 23 serving as the source or drain of the fifth transistor TF can be electrically connected to a portion 17E (the bottom gate of transistor TD') of the second metal layer 17 through a portion 17F of the second metal layer 17 and a pattern 1716 of the oxide metal layer 171, and the pattern 1716 of the oxide metal layer 171 is disposed on the portion 17F of the second metal layer 17. In addition, the fourth metal layer 23 serving as the source or drain of the fifth transistor TF can be electrically connected to a portion 214 (the top gate of transistor TD') of the third metal layer 21 through a portion 215 of the third metal layer 21, and a pattern 21'D of the oxide metal layer 21' can be disposed below the portion 215 of the third metal layer 21.

[0078] In other embodiments of this disclosure, although not shown in the figures, the pattern 1716 of the oxide metal layer 171 may not be provided on a portion 17F of the second metal layer 17. In other embodiments of this disclosure, although not shown in the figures, a pattern 21'D of the oxide metal layer 21' may not be provided below a portion 215 of the third metal layer 21.

[0079] In this disclosure, since at least one side of the third oxide semiconductor 193 in the transistor TD' is provided with an oxide metal layer (e.g., pattern 1715 of oxide metal layer 171 and / or pattern 21'C of oxide metal layer 21'), even if the transistor TD' is an oxide semiconductor transistor, its performance can be close to that of a polycrystalline silicon transistor (e.g., transistor TD as shown in FIG3), and it can be used as, for example, data writing transistor T2 as shown in FIG1.

[0080] As shown in Figure 6, the other components of the electronic device, their materials, their locations, and other features are as described above and will not be repeated here.

[0081] FIG7 is a schematic cross-sectional view of a portion of the active region of an electronic device according to an embodiment of the present disclosure. FIG7 shows a first transistor TA, a second transistor TB, and a transistor TD in the active region, which are similar to those in FIG4, except for the following differences.

[0082] In this disclosure, as shown in FIG7, the electronic device 1 may not include the second metal layer 17 and the third metal layer 21 shown in FIG4.

[0083] In this disclosure, as shown in FIG7, the second transistor TB may include a first oxide semiconductor 191 of oxide semiconductor layer 19, a second pattern 1712 of metal oxide layer 171, a fifth pattern 21'A of metal oxide layer 21', and portions 233 and 234 of fourth metal layer 23. The second pattern 1712 of metal oxide layer 171 and the fifth pattern 21'A of metal oxide layer 21' may serve as a bottom gate and a top gate, respectively. One of portions 233 and 234 of fourth metal layer 23 may serve as a source and the other as a drain. The portions 233 and 234 of fourth metal layer 23 are electrically connected to the first oxide semiconductor 191.

[0084] In this disclosure, as shown in FIG7, the conductive structure of the electronic device 1 (including portion 231 of the fourth metal layer 23) is electrically connected to portion 151 of the first metal layer 15 through opening 1711A of the first pattern 1711. Furthermore, the first pattern 1711 overlaps with portion 151 of the first metal layer 15 to form a capacitor, wherein the first pattern 1711 can serve as one electrode of the capacitor.

[0085] In other embodiments of this disclosure, although not shown in the figures, the third transistor TC shown in Figures 3 to 6 may also include the second transistor TB structure shown in Figure 7, which will not be described in detail here.

[0086] In other embodiments of this disclosure, although not shown in the figures, the electronic device 1 may include a portion 211 of the third metal layer 21 as shown in FIG4, disposed on the fifth pattern 21'A of the oxide metal layer 21'. In other embodiments of this disclosure, although not shown in the figures, the electronic device 1 may include a portion 21 of the third metal layer 21 as shown in FIG4, replacing the fifth pattern 21'A of the oxide metal layer 21' in FIG7.

[0087] In this disclosure, when the metal oxide layer (e.g., oxide semiconductor layer 19 and metal oxide layer 21') is used as an electrode, the doping elements and their doping amounts in the metal oxide layer material can be adjusted to improve the conductivity of the metal oxide layer.

[0088] As shown in Figure 7, the other components of the electronic device, their materials, their locations, and other features are as described above and will not be repeated here.

[0089] FIG8 is a schematic cross-sectional view of a portion of the active region of an electronic device according to an embodiment of the present disclosure. FIG8 shows a first transistor TA, a second transistor TB, and a transistor TD in the active region, which are similar to those in FIG3, except for the following differences.

[0090] In this disclosure, as shown in FIG8, the electronic device 1 does not include the first metal layer 15 as shown in FIG3.

[0091] In this disclosure, as shown in FIG8, the oxide semiconductor layer 19 of the electronic device 1 further includes a fourth oxide semiconductor 194, and the fourth oxide semiconductor 194 has an opening 1941. In this disclosure, the conductive structure of the electronic device 1 (including the portion 231 of the fourth metal layer 23) can be electrically connected to the portion 17A of the second metal layer 17 through the opening 1941 of the fourth oxide semiconductor 194 and the opening 1711A of the first pattern 1711. In this disclosure, the portion 17A of the second metal layer 17 overlaps with the fourth oxide semiconductor 194 to form a capacitor, wherein the fourth oxide semiconductor 194 can serve as one electrode of the capacitor.

[0092] In other embodiments of this disclosure, although not shown in the figures, the first pattern 1711 may not have an opening 1711A; therefore, the conductive structure of the electronic device 1 (including the portion 231 of the fourth metal layer 23) can be electrically connected to the first pattern 1711 and the portion 17A of the second metal layer 17 through the opening 1941 of the fourth oxide semiconductor 194.

[0093] In other embodiments of this disclosure, although not shown in the figures, the electronic device 1 may not include the second metal layer 17 as shown in FIG8; in this case, in the second transistor TB, the second pattern 1712 of the metal oxide layer 171 can serve as the bottom gate (as shown in FIG7). In addition, the first pattern 1711 may not have an opening 1711A, so the conductive structure of the electronic device 1 (including the portion 231 of the fourth metal layer 23) can be electrically connected to the first pattern 1711 through the opening 1941 of the tetroxide semiconductor 194; wherein, the tetroxide semiconductor 194 and the first pattern 1711 overlap to form a capacitor, and the tetroxide semiconductor 194 and the first pattern 1711 serve as the upper and lower electrodes of the capacitor, respectively.

[0094] As shown in Figure 8, the other components of the electronic device, their materials, their locations, and other features are as described above and will not be repeated here.

[0095] Next, the method for manufacturing the electronic device disclosed herein will be briefly described.

[0096] Figures 9A to 9E are cross-sectional schematic diagrams of the fabrication process of a portion of the active region of an electronic device according to an embodiment of the present disclosure. Here, the fabrication of the first transistor TA, the second transistor TB, and the transistor TD of the active region in Figure 3 is used as an example. The fabrication methods of other parts of the electronic device (e.g., other parts of the active region or peripheral regions) or electronic devices of other embodiments are similar to those described below, and will not be repeated here.

[0097] As shown in Figure 9A, firstly, a substrate 11 is provided, on which a buffer layer 12, a polycrystalline silicon semiconductor layer 13, an insulating layer 141, a first metal layer 15, and an insulating layer 142 are sequentially formed. Then, a metal layer 17' is formed on the insulating layer 142, and an unpatterned metal oxide layer 171' is formed on the metal layer 17'. Next, a photoresist layer is formed on the unpatterned metal oxide layer 171', and the photoresist layer is patterned using a photolithography process to form a photoresist pattern PR on the unpatterned metal oxide layer 171'. As shown in Figure 9B. The material of the photoresist layer can be selected as either a positive or negative photoresist as needed.

[0098] Next, a first etching process is performed to pattern the unpatterned metal oxide layer 171' to form a metal oxide layer 171, as shown in FIG9C. Then, a second etching process is performed to pattern the metal layer 17' to form a second metal layer 17, as shown in FIG9D.

[0099] As shown in FIG9E, after the second metal layer 17 is formed, a second insulating layer 18, an oxide semiconductor layer 19, a third insulating layer 20, a third metal layer 21, a fourth insulating layer 22, a fourth metal layer 23 and a fifth insulating layer 24 are sequentially formed on the metal oxide layer 171. In this way, the fabrication of the electronic device of this embodiment is completed.

[0100] In this embodiment, since the unpatterned oxide metal layer 171' and the metal layer 17' are patterned using two etching processes, the oxide metal layer 171 is recessed compared to the second metal layer 17. For example, in a top view, the area of ​​the oxide metal layer 171 may be smaller than the area of ​​the second metal layer 17, or the projection of the oxide metal layer 171 on the substrate 11 may completely fall within the projection of the second metal layer 17 on the substrate 11.

[0101] In other embodiments disclosed herein, although not shown in the figures, the unpatterned oxide metal layer 171' and metal layer 17' can be patterned in a single etching process. In this case, the oxide metal layer 171 does not shrink. For example, in a top view, the area of ​​the oxide metal layer 171 can be approximately equal to the area of ​​the second metal layer 17, or the projection of the oxide metal layer 171 on the substrate 11 can be approximately equal to the projection of the second metal layer 17 on the substrate 11 and completely fall within the projection of the second metal layer 17 on the substrate 11.

[0102] As described above, the other components, materials, and locations of the electronic device in Figures 9A to 9E will not be repeated here.

[0103] Next, an electronic device incorporating a sensing unit will be described.

[0104] Figure 10 is a top view of a portion of an electronic device according to an embodiment of the present disclosure.

[0105] In one embodiment, as shown in FIG10, the electronic device 1 may include a first region A1, a second region A2, and a third region A3, which are arranged adjacent to each other. Furthermore, the electronic device 1 may include scan lines 31 and 32, a wire 33, a data line 34, and a data readout line 35. The scan lines 31 and 32 may extend along a first direction X, and the wire 33, data line 34, and data readout line 35 may extend along a second direction Y, wherein the first direction X and the second direction Y are different. In one embodiment, the first direction X and the second direction Y may be substantially perpendicular, but this disclosure is not limited thereto. In one embodiment, the scan lines 31 and 32 and the data line 34 are used to provide transistor signals, the wire 33 is used to provide a high potential, and the data readout line 35 is used to transmit signals sensed by the sensing unit.

[0106] In one embodiment, the first region A1 may be a main display area, including a complex driving circuit CR1 that controls electronic units and a complex sensing driving circuit CR2 that controls sensing units; wherein, the driving circuit CR1 of the electronic units may correspond to the electronic units (including a red display unit R, a blue display unit B, and a green display unit G), and the sensing driving circuit CR2 may correspond to the sensing unit S. In one embodiment, the driving circuit CR1 of the electronic units may refer to the schematic diagram of the driving circuit shown in FIG1, but this disclosure is not limited thereto. In one embodiment, the electronic units in the first region A1 may include a red display unit R, a blue display unit B, a green display unit G, and a sensing unit S. In one embodiment, scan line 32 and data line 34 can be electrically connected to drive circuit CR1 to provide signals to drive circuit CR1 to drive red display unit R, blue display unit B and green display unit G respectively; wire 33 can be electrically connected to drive circuit CR1 to provide a high potential to red display unit R, blue display unit B and green display unit G respectively to adjust the brightness of red display unit R, blue display unit B and green display unit G; scan line 32 can be electrically connected to sensing drive circuit CR2 to provide signals to sensing drive circuit CR2 to drive sensing unit S, and data readout line 35 can be electrically connected to sensing drive circuit CR2 to transmit the signals sensed by sensing unit S.

[0107] In one embodiment, the second area A2 may be a buffer display area. The second area A2 is similar to the first area A1, the main difference being that the second area A2 includes electronic units (including a red display unit R, a blue display unit B, and a green display unit G), but does not include a sensing unit S; therefore, the second area A2 does not have a scan line 32, a data readout line 35, or a sensing drive circuit CR2. The other parts of the second area A2 (e.g., the red display unit R, the blue display unit B, and the green display unit G and their wiring connections) are similar to those of the first area A1 and will not be described further. Furthermore, the second area A2 may also include an auxiliary drive circuit CR1', which can be referred to in the schematic diagram of the drive circuit shown in FIG1, but this disclosure is not limited thereto. The scan line 32 and the data line 34 may be electrically connected to the auxiliary drive circuit CR1' to provide signals to the auxiliary drive circuit CR1', and the wire 33 may be electrically connected to the auxiliary drive circuit CR1' to provide a high potential (Vdd). The function and connection method of the auxiliary drive circuit CR1' will be explained in detail later.

[0108] In one embodiment, the third region A3 may be a sensing region, for example, a camera setting region or a sensing element setting region, but this disclosure is not limited thereto. In one embodiment, the electronic unit in the third region A3 may include a red display unit R, a blue display unit B, and a green display unit G, but does not include the aforementioned driving circuit CR1, auxiliary driving circuit CR1', sensing driving circuit CR2, scan lines 31, 32, wires 33, data lines 34, and data readout lines 35. The wiring connection method and driving method of the electronic unit in the third region A3 will be described in detail later.

[0109] In one embodiment, the aforementioned red display unit R, blue display unit B, and green display unit G may each be a light-emitting diode, such as an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED), or a quantum dot light-emitting diode (quantum dot LED, which may include QLED and QDLED), but are not limited thereto. In one embodiment, the aforementioned sensing unit S may be a biosensor, a touch sensor, a fingerprint sensor, an infrared sensor, a temperature sensor, other suitable sensors, or a combination of sensors of the above types. In one embodiment, the scan lines 31, 32, the wire 33, the data line 34, and the data readout line 35 may each comprise a metallic material, a metal oxide material, an alloy thereof, or a combination thereof, such as gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), or aluminum zinc oxide (AZO), but this disclosure is not limited thereto.

[0110] Figure 11 is a cross-sectional schematic diagram of a portion of the sensing area and non-sensing area of ​​an electronic device according to an embodiment of the present disclosure.

[0111] In one embodiment, as shown in Figures 10 and 11, the electronic device 1 may include: a sensing area (e.g., a third area A3); and a non-sensing area (e.g., a second area A2) adjacent to the sensing area (e.g., the third area A3); wherein a first electronic unit (e.g., a green display unit G1) is disposed in the sensing area (e.g., the third area A3), a second transistor TB is disposed in the non-sensing area (e.g., the second area A2), and the metal oxide layer 171 includes a seventh pattern 1717, and the seventh pattern 1717 is electrically connected between the first electronic unit (e.g., the green display unit G1) and the second transistor TB. In Figure 11, only a portion of the driving circuit CR1' shown in Figure 10 is shown in the second area A2 of the electronic device 1. The driving circuit CR1' of the second area A2 of the electronic device 1 disclosed herein can be referenced, for example, as shown in Figures 1 to 8, and will not be described again here.

[0112] In one embodiment, the electronic device 1 may include: a fifth metal layer 25 disposed on a fifth insulating layer 24; a sixth insulating layer 26 disposed on the fifth metal layer 25; a first electrode layer 41 disposed on the sixth insulating layer 26; a pixel defining layer 42 disposed on the first electrode layer 41; a light-emitting layer 43 disposed on the first electrode layer 41; and a second electrode layer 44 disposed on the light-emitting layer 43.

[0113] In one embodiment, the material of the fifth metal layer 25 may contain a metallic material, a metal oxide material, an alloy thereof, or a combination thereof, such as gold, silver, copper, palladium, platinum, ruthenium, aluminum, cobalt, nickel, titanium, molybdenum, manganese, indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), or aluminum zinc oxide (AZO), but this disclosure is not limited thereto. In one embodiment, the sixth insulating layer 26 may contain a single-layer or multi-layer structure, and its material may each contain silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, aluminum oxide, or a combination thereof, but this disclosure is not limited thereto. In one embodiment, the first electrode layer 41 may be a reflective electrode, and its material may include aluminum, silver, or a combination thereof, but this disclosure is not limited thereto. In one embodiment, the material of the pixel defining layer 42 may include resin, polymer, photoresist, or a combination thereof, but this disclosure is not limited thereto. In one embodiment, the light-emitting layer 43 may be an organic light-emitting layer, but this disclosure is not limited thereto. In one embodiment, the second electrode layer 44 may be a transparent electrode, and its material may include ITO, IZO, ITZO, or a combination thereof, but this disclosure is not limited thereto.

[0114] As shown in FIG11, in one embodiment, a portion 234 of the fourth metal layer 23 of the second transistor TB in the non-sensing area (e.g., the second area A2 of FIG10) is electrically connected to the seventh pattern 1717 of the metal oxide layer 171, and the first electrode layer 41 of the first electronic unit (e.g., the green display unit G1) is electrically connected to the seventh pattern 1717 of the metal oxide layer 171 through a portion of the fifth metal layer 25 and a portion of the fourth metal layer 23, thereby making the second transistor TB and the first electronic unit (e.g., the green display unit G1) electrically connected through the seventh pattern 1717 of the metal oxide layer 171.

[0115] In one embodiment, as shown in Figures 10 and 11, the electronic device 1 may include: a sensing area (e.g., a third area A3); a non-sensing area (e.g., a second area A2) adjacent to the sensing area (e.g., the third area A3); and a second electronic unit (e.g., a green display unit G2); wherein the first electronic unit (e.g., a green display unit G1) and the second electronic unit (e.g., a green display unit G2) are both disposed in the sensing area (e.g., the third area A3), and the metal oxide layer 171 includes an eighth pattern 1718, which is electrically connected between the first electronic unit (e.g., the green display unit G1) and the second electronic unit (e.g., the green display unit G2).

[0116] More specifically, as shown in Figures 10 and 11, in one embodiment, the first electrode layer 41 of the first electronic unit (e.g., the green display unit G1) is electrically connected to the eighth pattern 1718 of the oxide metal layer 171 through a portion of the fifth metal layer 25 and a portion of the fourth metal layer 23, and the first electrode layer 41 of the second electronic unit (e.g., the green display unit G2) is electrically connected to the eighth pattern 1718 of the oxide metal layer 171 through a portion of the fifth metal layer 25 and a portion of the fourth metal layer 23, thereby electrically connecting the first electronic unit (e.g., the green display unit G1) and the second electronic unit (e.g., the green display unit G2) to each other.

[0117] In one embodiment, as shown in Figures 10 and 11, the first electronic unit (e.g., green display unit G1) and the second electronic unit (e.g., green display unit G2) are electrically connected to the second transistor TB through the seventh pattern 1717 and the eighth pattern 1718 of the metal oxide layer 171. Therefore, even if the third region A3 is not provided with a driving circuit, the auxiliary driving circuit CR1' of the second region A3 is electrically connected through the metal oxide layer 171 to drive the first electronic unit (e.g., green display unit G1) and the second electronic unit (e.g., green display unit G2) provided in the third region A3.

[0118] In FIG11, a second metal layer 17 may be disposed below the seventh pattern 1717 and the eighth pattern 1718 of the oxide metal layer 171, respectively; wherein the patterns of the second metal layer 17 below the seventh pattern 1717 and the eighth pattern 1718 correspond to the light-emitting layer 43 of the first electronic unit (e.g., green display unit G1) and the second electronic unit (e.g., green display unit G2), respectively, to serve as the light-shielding layer of the first electronic unit (e.g., green display unit G1) and the second electronic unit (e.g., green display unit G2). However, in other embodiments disclosed herein, the second metal layer 17 may be selectively not disposed below the seventh pattern 1717 and the eighth pattern 1718 of the oxide metal layer 171.

[0119] However, in other embodiments of this disclosure, the electronic unit disposed in the third region A3 can be electrically connected to the auxiliary driving circuit CR1' of the second region A3 through the metal oxide layer, or through other metal layers or metal oxide layers.

[0120] In one embodiment, as shown in FIG10, the first electronic unit and the second electronic unit (e.g., green display units G3, G4) disposed in the third region A3 can be electrically connected, for example, directly to a portion 234 of the fourth metal layer 23 of the second transistor TB in the auxiliary driving circuit CR1' through, for example, the fifth metal layer 25 shown in FIG11, without being electrically connected to the portion 234 of the fourth metal layer 23 through the oxide metal layer 171; however, this disclosure is not limited thereto.

[0121] In one embodiment, as shown in FIG10, the first electronic unit (e.g., blue electronic unit B1 or red electronic unit R1) disposed in the third region A3 can be electrically connected through, for example, the fifth metal layer 25 shown in FIG11 to a portion 234 of the fourth metal layer 23 of the second transistor TB in the auxiliary driving circuit CR1', without being electrically connected through the oxide metal layer 171 to the portion 234 of the fourth metal layer 23; while the first electronic unit (e.g., blue electronic unit B1 or red electronic unit R1) and the second electronic unit (e.g., blue electronic unit B2 or red electronic unit R2) disposed in the third region A3 can be electrically connected to each other through the eighth pattern 1718 of the oxide metal layer 171; however, this disclosure is not limited thereto.

[0122] In one embodiment, although not shown in the figures, the first electronic unit (e.g., blue electronic unit B1 or red electronic unit R1) disposed in the third region A3 is permeable, for example, the seventh pattern 1717 of the oxide metal layer 171 shown in FIG. 11 is electrically connected to a portion 234 of the fourth metal layer 23 of the second transistor TB in the auxiliary driving circuit CR1'; while the first electronic unit (e.g., blue electronic unit B1 or red electronic unit R1) and the second electronic unit (e.g., blue electronic unit B2 or red electronic unit R2) disposed in the third region A3 are permeable, for example, the fifth metal layer 25 shown in FIG. 11 is electrically connected to each other; but this disclosure is not limited thereto.

[0123] In one embodiment, although not shown in the figure, the electronic unit disposed in the third region A3 can be electrically connected to the auxiliary driving circuit CR1' of the second region A3 as shown in FIG10 through a metal layer (for example, the fifth metal layer 25 shown in FIG11); however, this disclosure is not limited thereto.

[0124] In one embodiment, although not shown in the figure, the electronic unit disposed in the third region A3 can be electrically connected to the driving circuit (e.g., the auxiliary driving circuit CR1' of the second region A3 as shown in Figure 10) through, for example, the seventh pattern 1717 of the oxide metal layer 171 as shown in Figure 11; but this disclosure is not limited thereto.

[0125] In one embodiment, although not shown in the figures, the electronic device 1 may include another auxiliary driving circuit disposed in the peripheral area to drive the electronic unit of the third area A3; however, this disclosure is not limited thereto.

[0126] In one embodiment, although not shown in the figures, a portion of the auxiliary drive circuit CR1' shown in FIG10 can drive one electronic unit, while another portion of the auxiliary drive circuit CR1' can drive two electronic units; however, this disclosure is not limited thereto.

[0127] FIG12 is a schematic diagram of a partial wiring configuration of the electronic component driving circuit and the sensing driving circuit of an electronic device according to an embodiment of the present disclosure. Please refer to FIG1 to FIG6 and FIG10 at the same time. For clarity, FIG11 only shows the wiring configuration of the reset transistor in the electronic component driving circuit and the reset transistor in the sensing driving circuit. The wiring configuration of the other transistors can be referred to the foregoing.

[0128] In one embodiment, as shown in FIG12, the oxide semiconductor layer 19 may include a second oxide semiconductor 192 and a fifth oxide semiconductor 195, and the second oxide semiconductor 192 and the fifth oxide semiconductor 195 are connected together. Furthermore, the metal oxide layer 171 may include a third pattern 1713 and a pattern 1719, wherein the third pattern 1713 is correspondingly disposed with respect to the second oxide semiconductor 192, and the pattern 1719 is correspondingly disposed with respect to the fifth oxide semiconductor 195.

[0129] More specifically, as shown in FIG12, the reset transistor T3 located in the driving circuit CR1 of the electronic component may include a portion 17C of the second metal layer 17, a third pattern 1713 of the metal oxide layer 171, a second oxide semiconductor 192 of the oxide semiconductor layer 19, and a portion 212 of the third metal layer 21, wherein the portion 17C of the second metal layer 17 and the portion 212 of the third metal layer 21 may serve as the bottom gate and the top gate, respectively. Other structures of the reset transistor T3 can be referred to the third transistor TC shown in FIGS. 2 to 6, and will not be repeated here. Furthermore, as shown in FIG12, the reset transistor ST located in the sensing driving circuit CR2 may include a portion 17G of the second metal layer 17, a pattern 1719 of the metal oxide layer 171, a fifth oxide semiconductor 195 of the oxide semiconductor layer 19, and a portion 216 of the third metal layer 21, wherein the portion 17G of the second metal layer 17 and the portion 216 of the third metal layer 21 may serve as the bottom gate and the top gate, respectively.

[0130] In one embodiment, although not shown, the reset transistor T3 in the driving circuit CR1 of the electronic component may not include the third pattern 1713 of the metal oxide layer 171 (as shown in FIG. 12). In one embodiment, although not shown, the portion 212 of the third metal layer 21 of the reset transistor T3 in the driving circuit CR1 of the electronic component may further include another metal oxide layer at the second oxide semiconductor 192 corresponding to the oxide semiconductor layer 19. In one embodiment, although not shown, the portion 216 of the third metal layer 21 of the reset transistor ST in the sensing driving circuit CR2 may further include another metal oxide layer at the pattern 1719 corresponding to the metal oxide layer 171.

[0131] In one embodiment, as shown in FIG12, a portion 17C of the second metal layer 17 and a portion 17G of the second metal layer 17 can be electrically connected in a bridging manner through a metal layer 51, so that the scan signal from the scan line S SN-4 can be simultaneously input to the reset transistor T3 and the reset transistor ST.

[0132] In one embodiment, although not shown in the figure, the portion 17C of the second metal layer 17 and the portion 17G of the second metal layer 17 are not electrically connected to each other, and the reset transistor T3 in the driving circuit CR1 of the electronic component and the reset transistor ST in the sensing driving circuit CR2 are controlled by different scan lines and different scan signals.

[0133] In one embodiment, as shown in FIG12, portions 212 and 216 of the third metal layer 21 can also be electrically connected in a bridging manner through a metal layer 52, so the reset control signal S reset can also be input to the reset transistor T3 and the reset transistor ST.

[0134] In one embodiment, as shown in FIG12, reset transistor T3 and reset transistor ST can share the same end 19A, for example, they can share the same source; while the other end 19B (e.g., drain) of reset transistor T3 and the other end 19C (e.g., drain) of reset transistor ST are respectively disposed in the driving circuit CR1 and the sensing driving circuit CR2 of the electronic components.

[0135] In one embodiment, although not shown in the figures, the driving circuit CR1 and the sensing driving circuit CR2 of the electronic components may share the same oxide semiconductor. For example, as shown in FIG12, one of the second oxide semiconductor 192 or the fifth oxide semiconductor 195 of the oxide semiconductor layer 19 may be omitted.

[0136] For example, in one embodiment, only the second oxide semiconductor 192 of the oxide semiconductor layer 19 may be provided without the fifth oxide semiconductor 195 (as shown in FIG12), and the portion 17G of the second metal layer 17 (as shown in FIG12) and the portion 216 of the third metal layer 21 (as shown in FIG12) may also be omitted. In this case, the end 19A, which serves as a common source, may be located in the driving circuit CR1, the sensing driving circuit CR2, or between the driving circuit CR1 and the sensing driving circuit CR2; the end 19B (e.g., the drain) may be located in the driving circuit CR1 or between the driving circuit CR1 and the sensing driving circuit CR2; and the end 19C (e.g., the drain) may be located in the sensing driving circuit CR2.

[0137] FIG13A is a top view of a portion of an electronic device according to an embodiment of the present disclosure. FIG13B is a cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of the present disclosure. In FIG13B, the cross-sectional schematic diagram of the portion of the electronic device is a cross-sectional schematic diagram along the section line D-D' of FIG13A. Furthermore, other components of the electronic device 1 shown in FIG13A can be referred to FIG10, and other components of the electronic device 1 shown in FIG13B can be referred to FIG3 to 8 and FIG11, which will not be described again here.

[0138] In one embodiment, as shown in Figures 13A and 13B, the first area A1 of the electronic device 1, which serves as the main display area, may further include a trench 27. More specifically, for example, the first insulating layer 14, the second insulating layer 18, the third insulating layer 20, the fourth insulating layer 22, and the fifth insulating layer 24 may be selectively patterned or removed to form the trench 27. In this embodiment, the trench 27 penetrates through the first insulating layer 14, the second insulating layer 18, the third insulating layer 20, the fourth insulating layer 22, and the fifth insulating layer 24; however, this disclosure is not limited thereto. In other embodiments of this disclosure, although not shown in the figures, the trench 27 may be provided only in at least one of the first insulating layer 14, the second insulating layer 18, the third insulating layer 20, the fourth insulating layer 22, and the fifth insulating layer 24.

[0139] In one embodiment, as shown in FIG13B, the groove 27 may be filled with a filler material 28, which may be photoresist, polymer material or a combination thereof, but this disclosure is not limited thereto.

[0140] In one embodiment, as shown in Figures 13A and 13B, trenches 27 are provided between the driving circuits CR1 of each electronic component or between the driving circuits CR1 and the sensing driving circuits CR2 of each electronic component in the first region A1 of the electronic device 1. However, this disclosure is not limited to this. In other embodiments of this disclosure, although not shown in the figures, trenches 27 may be selectively provided between the driving circuits CR1 of adjacent electronic components or between the driving circuits CR1 and the sensing driving circuits CR2 of adjacent electronic components. In one embodiment, the driving circuits CR1 and adjacent sensing driving circuits CR2 of the electronic components may be selectively without trenches 27. For example, the driving circuit CR1 corresponding to the blue display unit B and the adjacent sensing driving circuit CR2 may not have trenches 27 provided, while the driving circuit CR1 corresponding to the red display unit R and the adjacent sensing driving circuit CR2 may have trenches 27 provided. When the driving circuit CR1 of the electronic component and the adjacent sensing driving circuit CR2 are selectively not provided with trench 27, in one embodiment, the driving circuit CR1 of the electronic component and the adjacent sensing driving circuit CR2 may include different oxide semiconductors (e.g., the second oxide semiconductor 192 and the fifth oxide semiconductor 195 as shown in FIG12); in another embodiment, the driving circuit CR1 of the electronic component and the adjacent sensing driving circuit CR2 may selectively include a common oxide semiconductor (e.g., the second oxide semiconductor 192 or the fifth oxide semiconductor 195 as shown in FIG12), and the reset transistor T3 of the driving circuit CR1 and the reset transistor ST of the sensing driving circuit CR may share a common terminal 19A (as shown in FIG12) as a common source.

[0141] In one embodiment, although not shown in the figures, the trench 27 may also be disposed in the second region A2 of the electronic device 1 (as shown in FIG10). More specifically, the trench 27 may be selectively disposed between the driving circuit CR1 and the auxiliary driving circuit CR1' in the second region A2.

[0142] In one embodiment, although not shown in the figures, the groove 27 may also be provided in the third region A3 of the electronic device 1 (as shown in FIG10). More specifically, the groove 27 may be selectively provided in areas where no electronic units (e.g., red display unit R, blue display unit B, and green display unit G) are provided.

[0143] The above specific embodiments should be interpreted as merely illustrative and not as limiting the remainder of this disclosure in any way. [Simplified Explanation of the Diagram]

[0005] Figure 1 is a schematic diagram of the basic driving circuit of an electronic device according to an embodiment of the present disclosure. Figure 2 is a top view of a portion of the active area of ​​an electronic device according to an embodiment of the present disclosure. Figure 3 is a cross-sectional schematic diagram of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. Figure 4 is a cross-sectional schematic diagram of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. Figure 5 is a cross-sectional schematic diagram of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. Figure 6 is a cross-sectional schematic diagram of a portion of the active area and a portion of the peripheral area of ​​an electronic device according to an embodiment of the present disclosure. Figure 7 is a cross-sectional schematic diagram of a portion of the active area of ​​an electronic device according to an embodiment of the present disclosure. Figure 8 is a cross-sectional schematic diagram of a portion of the active area of ​​an electronic device according to an embodiment of the present disclosure. Figures 9A to 9E are cross-sectional schematic diagrams of the fabrication process of a portion of the active area of ​​an electronic device according to an embodiment of the present disclosure. Figure 10 is a top view of a portion of an electronic device according to an embodiment of the present disclosure. Figure 11 is a cross-sectional schematic diagram of a portion of the sensing area and non-sensing area of ​​an electronic device according to an embodiment of the present disclosure. Figure 12 is a schematic diagram of a portion of the wiring configuration of the electronic component driving circuit and the sensing driving circuit of an electronic device according to an embodiment of the present disclosure. Figure 13A is a top view of a portion of an electronic device according to an embodiment of the present disclosure. Figure 13B is a cross-sectional schematic diagram of a portion of an electronic device according to an embodiment of this disclosure. [Biomaterial Storage]

[0145] None.

Claims

1. An electronic device comprising: One substrate; A first electronic unit is disposed on the substrate; A first transistor is disposed on the substrate, wherein the first transistor is electrically connected to the first electronic unit and includes a first polycrystalline silicon semiconductor; a first insulating layer is disposed on the first polycrystalline silicon semiconductor; a metal oxide layer is disposed on the first insulating layer and includes a separated first pattern and a second pattern, wherein the first pattern has an opening; a second transistor is electrically connected to the first electronic unit and the first transistor and includes a first oxide semiconductor; a second insulating layer is disposed between the metal oxide layer and the first oxide semiconductor; and a conductive structure is electrically connected between the first transistor and the second transistor through the opening of the first pattern; wherein the first pattern overlaps with the first polycrystalline silicon semiconductor, the second pattern overlaps with the first oxide semiconductor, and the thickness of the second insulating layer between the second pattern and the first oxide semiconductor is greater than or equal to 1000 Å and less than or equal to 8000 Å.

2. The electronic device as claimed in claim 1, wherein, It further includes a conductive pattern that overlaps with the first pattern and has an opening, wherein the first transistor includes a gate, the conductive pattern is disposed between the first pattern and the gate of the first transistor, and the conductive structure is electrically connected to the first transistor through the opening of the conductive pattern.

3. The electronic device as claimed in claim 2, wherein, The width of the opening in the first pattern is greater than the width of the opening in the conductive pattern.

4. The electronic device as claimed in claim 2, wherein, The width of the first pattern is smaller than the width of the conductive pattern.

5. The electronic device as claimed in claim 1, wherein, The thickness of the first insulating layer is greater than or equal to 1000 Å and less than or equal to 5000 Å.

6. The electronic device as claimed in claim 1, wherein, It further includes: an oxide semiconductor layer disposed on the substrate; and a third transistor electrically connected to the first transistor and including a second oxide semiconductor; wherein a portion of the oxide semiconductor layer is the first oxide semiconductor, another portion of the oxide semiconductor layer is the second oxide semiconductor, and the metal oxide layer includes a third pattern, the third pattern overlapping with the second oxide semiconductor and separate from the second pattern.

7. The electronic device as claimed in claim 6, wherein, It also includes a conductor, which, in a top view, is positioned between the second pattern and the third pattern.

8. The electronic device as claimed in claim 6, wherein, It further includes another metal oxide layer, including a fourth pattern overlapping the second oxide semiconductor, wherein the third pattern and the fourth pattern are disposed on opposite sides of the second oxide semiconductor.

9. The electronic device as claimed in claim 1, wherein, It further includes another metal oxide layer, including a fifth pattern overlapping the first oxide semiconductor, wherein the fifth pattern and the second pattern are disposed on opposite sides of the first oxide semiconductor.

10. The electronic device as claimed in claim 1, wherein, The electronic device includes: an active region; a peripheral region adjacent to the active region; and a fourth transistor disposed in the peripheral region; wherein the second transistor is disposed in the active region, and the metal oxide layer includes a sixth pattern, the sixth pattern being electrically connected to the fourth transistor and the second transistor.

11. The electronic device as claimed in claim 1, wherein, The electronic device includes: a sensing area; and a non-sensing area adjacent to the sensing area; wherein the first electronic unit is disposed in the sensing area, the second transistor is disposed in the non-sensing area, the metal oxide layer includes a seventh pattern, and the seventh pattern is electrically connected between the first electronic unit and the second transistor.

12. The electronic device as claimed in claim 1, wherein, The electronic device includes: a sensing area; a non-sensing area adjacent to the sensing area; and a second electronic unit; wherein the first electronic unit and the second electronic unit are both disposed in the sensing area, and the metal oxide layer includes an eighth pattern, the eighth pattern being electrically connected between the first electronic unit and the second electronic unit.

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