Semiconductor device and methods of formation

Abstract

Some implementations provide semiconductor fabrication techniques and related semiconductor structures for forming p-type metal-oxide-semiconductor (PMOS) nanostructure transistors and n-type metal-oxide-semiconductor (NMOS) nanostructure transistors in semiconductor devices. The techniques involve forming various types of gate metals for the PMOS nanostructure transistors while maintaining the intrinsic NMOS nanostructure transistors of the semiconductor device. A p-type gate metal can be formed around the nanostructure channels of the PMOS nanostructure transistor. A self-assembled monolayer can then be formed on the surface of the p-type gate metal layer. During the formation of the n-type gate metal around the nanostructure channels of the NMOS nanostructure transistor, the self-assembled monolayer on the p-type gate metal prevents the formation of the n-type gate metal on the p-type gate metal. This results in almost no n-type gate metal deposition on the p-type gate metal, which minimizes the effect of the p-type threshold voltage (PVt) on the PMOS nanostructure transistor.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for their fabrication. Prior Technology

[0002] As semiconductor device manufacturing advances and technology processing node sizes shrink, transistors can be affected by short-channel effects (SCE), such as hot carrier degradation, barrier reduction, and quantum confinement. Furthermore, as the gate length of transistors decreases for smaller technology nodes, source / drain (S / D) electron tunneling increases, which increases the transistor's cutoff current (the current flowing through the transistor's channels when the transistor is in a cutoff configuration). Silicon (Si) / silicon-germanium (SiG) nanostructure transistors (e.g., nanowires, nanosheets, and gate-all-around (GA–A) devices) are potential candidates for overcoming short-channel effects at smaller technology nodes. Compared to other types of transistors, nanostructure transistors are efficient structures that can potentially experience reduced SCE and enhanced carrier mobility. Summary of the Invention

[0003] This disclosure relates to a method comprising: forming a first plurality of nanostructured channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructured channel layers arranged along a direction substantially perpendicular to the semiconductor substrate; forming a first type of metal layer surrounding each of the first plurality of nanostructured channel layers; forming a self-assembled monolayer film on the first type of metal layer; and forming a second type of metal layer on the second plurality of nanostructured channel layers, wherein the self-assembled monolayer film inhibits the formation of the second type of metal layer on the first type of metal layer.

[0004] This disclosure also relates to a method comprising: forming a first plurality of nanostructure channel layers arranged in a direction substantially perpendicular to a semiconductor substrate of a semiconductor device; forming a second plurality of nanostructure channel layers arranged in a direction substantially perpendicular to the semiconductor substrate; forming a gate dielectric layer surrounding the first plurality of nanostructure channel layers and surrounding the second plurality of nanostructure channel layers; forming a self-assembled monolayer film on the gate dielectric layer surrounding the second plurality of nanostructure channel layers; forming a p-type metal layer of a first gate structure on the first plurality of nanostructure channel layers, wherein the material of the self-assembled monolayer film inhibits the p-type metal layer from adsorbing onto the gate dielectric layer surrounding the second plurality of nanostructure channel layers; and forming an n-type metal layer of a second gate structure on the second plurality of nanostructure channel layers after forming the p-type metal layer.

[0005] This disclosure also relates to a semiconductor device comprising: a first plurality of nanostructured channel layers arranged along a direction generally perpendicular to a semiconductor substrate of the semiconductor device; a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers and arranged along a direction generally perpendicular to the semiconductor substrate; a first gate structure surrounding the first plurality of nanostructured channel layers, the first gate structure comprising: a p-type metal layer; and a residue located on the p-type metal layer, the residue comprising a ligand of at least one of the following: sulfur (S), silicon (SI), or phosphorus (P); and a second gate structure surrounding each of the second plurality of nanostructured channel layers, the second gate structure comprising an n-type metal layer. Simple Explanation of the Diagram

[0006] A better understanding of the various features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for ease of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1C are illustrations of exemplary implementations of the fin definition process described in this disclosure.

[0008] Figure 2 is a diagram illustrating the fabrication process of the exemplary dummy gate structure described in this disclosure.

[0009] Figure 3 is an illustration of an exemplary implementation of the source / drain recess formation process described in this disclosure.

[0010] Figures 4A and 4B are illustrations of exemplary implementations of the internal spacer formation process described in this disclosure.

[0011] Figure 5 is an illustration of an exemplary implementation of the source / drain region formation process described in this disclosure.

[0012] Figure 6 is an illustration of an exemplary implementation of the interlayer dielectric formation process described in this disclosure.

[0013] Figures 7A to 7H are illustrations of exemplary implementations of the alternative gate process described in this disclosure.

[0014] Figure 8 is an illustration of an example of elemental concentration in the gate structure of the nanostructured transistor described in this disclosure.

[0015] Figure 9 is an illustration of an example of elemental concentration in the gate structure of the nanostructured transistor described in this disclosure.

[0016] Figures 10A to 10D are illustrations of exemplary implementations of the gate structure in the nanostructured transistors disclosed herein.

[0017] Figures 11A and 11B are illustrations of exemplary implementations of the work function metal layer of the gate structure for forming nanostructured transistors as described in this disclosure.

[0018] Figures 12 and 13 are flowcharts of exemplary fabrication processes associated with the formation of semiconductor devices as described in this disclosure.

[0019] Figures 14A to 14I are illustrations of exemplary implementations of the work function metal layer of the gate structure for forming nanostructured transistors as disclosed herein.

[0020] Figure 15 is a flowchart of an exemplary process associated with the formation of a semiconductor device as described in this disclosure. Implementation

[0021] The following disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, this disclosure may also use spatially relative terms, such as "below," "under," "down," "above," "up," and similar terms, to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations described in the figures, spatially relative terms also encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0023] Nanostructured transistors can include gate structures surrounding a plurality of nanostructured channels. Gate structures surrounding nanostructured channels increase the gate structure's control over the conductive paths within the nanostructured channels, increase the drive current of the nanostructured transistor, and / or reduce the short-channel effect (SCE) of the nanostructured transistor. In some cases, semiconductor devices can include p-type metal-oxide-semiconductor (PMOS) nanostructured transistors and n-type metal-oxide-semiconductor (NMOS) nanostructured transistors. Integrating PMOS and NMOS nanostructured transistors into the same semiconductor device enables the implementation of complementary metal-oxide-semiconductor (CMOS) integrated circuits within the semiconductor device. CMOS integrated circuits have numerous use cases in the semiconductor industry, including microprocessors (e.g., central processing units (CPUs)), graphics processing units (GPUs), memory devices, digital logic circuits, image sensors (e.g., CMOS image sensors), and / or radio frequency (RF) circuits.

[0024] The threshold voltage (Vt) of a nanostructure transistor is the gate voltage required to selectively turn the transistor on or off. If the threshold voltage is too low (meaning the gate voltage required to activate the transistor is too low), the transistor may experience significant current leakage when it is off. Conversely, if the threshold voltage is too high, the power efficiency may decrease because a higher gate voltage is required to operate the transistor. For both PMOS and NMOS transistors, the type of metal used in the gate structure directly affects the threshold voltage. A metal tuned to the work function (φm) of the gate structure for optimal performance in a PMOS transistor may result in a large bandgap between the work function and conduction band (EC) of the NMOS transistor, leading to a high threshold voltage (and low power efficiency). The metal used to tune the work function of the gate structure for optimal performance of NMOS nanostructure transistors may result in a large band gap between the work function of the gate structure and the valence band (EV) of PMOS nanostructure transistors, leading to high threshold voltage (and low power efficiency) of PMOS nanostructure transistors.

[0025] This disclosure provides semiconductor fabrication techniques and related semiconductor structures for forming PMOS and NMOS nanostructure transistors in semiconductor devices. The techniques described herein include forming various types of gate metals for PMOS nanostructure transistors while maintaining the intrinsic NMOS nanostructure transistor of the semiconductor device. A p-type gate metal can be formed around the nanostructure channels of the PMOS nanostructure transistor. A self-assembled monolayer can then be formed on the surface of the p-type gate metal layer. During the formation of the n-type gate metal around the nanostructure channels of the NMOS nanostructure transistor, the self-assembled monolayer on the p-type gate metal prevents the formation of the n-type gate metal on the p-type gate metal. This results in almost no n-type gate metal deposition on the p-type gate metal, which minimizes the effect of the p-type threshold voltage (PVt) on the PMOS nanostructure transistor. In this way, the technology described in this disclosure enables the work function of both NMOS and PMOS nanostructure transistors to be tuned to achieve the desired threshold voltage. This allows for low current leakage and high operating efficiency in both NMOS and PMOS nanostructure transistors.

[0026] Figures 1A to 1C are illustrations of an exemplary implementation 100 of the fin-defined process described in this disclosure. Exemplary implementation 100 includes examples of forming the fin structure and associated shallow trench isolation (STI) regions of the semiconductor device 105 described in this disclosure. The semiconductor device 105 may be fabricated to include one or more transistors. These one or more transistors may include (one or more) nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GA–A) transistors, multi-bridge channel transistors, nanocharged transistors, and / or other types of nanostructured transistors. Exemplary implementation 100 includes examples of forming the fin structure and associated STI regions of the transistors in the semiconductor device 105.

[0027] Figures 1A to 1C show perspective views of the semiconductor device 105 and cross-sectional views along line A–A in the perspective views, respectively. As shown in Figure 1A, processing of the semiconductor device 105 is performed in conjunction with a semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material (e.g., gallium arsenide (GA–As)) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate.

[0028] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged along a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). For example, the layer stack 115 includes alternating layers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 above the semiconductor substrate 110 in the vertical direction. The number of sacrificial nanostructure layers 120 and nanostructure channel layers 125 shown in FIG. 1A is an example, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of this disclosure.

[0029] The sacrificial nanostructure layer 120 enables the definition of the vertical distance between adjacent nanostructure channels formed from the nanostructure channel layer 125 and acts as a berthing layer for the subsequently formed gate structures of the transistors of the semiconductor device 105, which are formed around the nanostructure channels. The sacrificial nanostructure layer 120 includes a first material composition, while the nanostructure channel layer 125 includes a second material composition. In some implementations, the first and second material compositions are the same. In some implementations, the first and second material compositions are different. For example, the sacrificial nanostructure layer 120 may include silicon germanium (SiG), while the nanostructure channel layer 125 may include silicon (Si). This allows the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 to be selectively etched depending on the type of etchant used (e.g., allowing the sacrificial nanostructure layer 120 to be etched while the nanostructure channel layer 125 is not etched, or allowing the nanostructure channel layer 125 to be etched while the sacrificial nanostructure layer 120 is not etched).

[0030] One or more types of deposition tools can be used to deposit and / or grow alternating layers of layer stack 115 to include nanostructures (e.g., nanosheets) on semiconductor substrate 110. For example, deposition tools can be used to grow sacrificial nanostructure layer 120 and / or nanostructure channel layer 125 via epitaxial growth, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) processes, and / or another suitable epitaxial technique. Additionally and / or alternatively, sacrificial nanostructure layer 120 and / or nanostructure channel layer 125 can be deposited via chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0031] One or more photomask layers may be formed on the layer stack 115 (e.g., using one or more deposition tools). The photomask layers may include a hard mask (HM) layer 130, a cap layer 135, an oxide layer 140, and / or a nitride layer 145. The photomask layers may be used to perform fin patterning operations to form fin structures in the semiconductor substrate 110.

[0032] As shown in Figure 1B, the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and the semiconductor substrate 110. This results in the formation of a fin structure 150 extending over the semiconductor substrate 110. The fin structure 150 may extend along the y-direction in the semiconductor device 105 and may be arranged along the x-direction in the semiconductor device 105. The fin structure 150 includes portions 155 of the layer stack 115 located above and / or on the fin portions 160 above the semiconductor substrate 110. The fin structure 150 may be formed by patterning one or more mask layers and etching the semiconductor substrate 110 based on the pattern formed in the one or more mask layers. The one or more mask layers may be patterned using photolithography techniques, including dual-patterning or multi-patterning techniques. Etching tools may be used to etch the semiconductor substrate 110 based on the pattern using dry etching techniques (e.g., reactive ion etching), wet etching techniques, and / or combinations thereof.

[0033] As further shown in Figure 1B, some fin structures 150 can be formed with different widths to be used for different types of nanostructure transistors. As an example, the first subgroup of fin structures 150a can be formed for p-type nanostructure transistors (e.g., p-type metal-oxide-semiconductor (PMOS) nanostructure transistors), while the second subgroup of fin structures 150b can be formed for n-type nanostructure transistors (e.g., n-type metal-oxide-semiconductor (NMOS) nanostructure transistors). As another example, the first subgroup of fin structures 150a can be formed for nanostructure transistors configured to operate at lower voltages, while the second subgroup of fin structures 150b can be formed for nanostructure transistors configured to operate at higher voltages.

[0034] As shown in Figure 1C, a liner 165 and an STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. The liner 165 and the STI region 170 may each comprise a dielectric material, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluorinated silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material.

[0035] A deposition tool can be used (e.g., using ALD or other conformal deposition techniques) to conformally deposit the liner, and can (e.g., using CVD, PVD, ALD, and / or other suitable deposition techniques) deposit a dielectric layer on the liner 165 such that the dielectric layer completely fills the space between the fin structures 150 and extends above the top of the fin structures 150. A planarization tool can then be used to perform a planarization or polishing operation (e.g., a chemical mechanical planarization (CMP) operation) to planarize the dielectric layer such that the top surface of the dielectric layer is substantially coplanar with the top of the nitride layer 145. The nitride layer 145 serves as a CMP stop layer in the planarization operation. An etching tool can then be used to etch the dielectric layer to form the STI region 170 such that the top surface of the STI region 170 is substantially coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0036] As noted above, Figures 1A to 1C are provided as examples. Other examples may differ from those described with respect to Figures 1A to 1C.

[0037] Figure 2 is an illustration of an exemplary implementation 200 of the dummy gate formation process described in this disclosure. Exemplary implementation 200 includes an example of a dummy gate structure 205 forming a nanostructure transistor of a semiconductor device 105. In some implementations, the operations described in conjunction with exemplary implementation 700 are performed after the processes described in conjunction with Figures 1A to 1C.

[0038] Figure 2 shows a perspective view of a semiconductor device 105 on which a dummy gate structure 205 is formed. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed over portions of the fin structure 150 and portions of the STI region 170. The dummy gate structure 205 extends along the x-direction and is arranged along the y-direction such that it is substantially perpendicular to the fin structure 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by an alternative gate structure or an alternative gate stack in subsequent process stages of the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess in the fin structure 150, where the source / drain region of the nanostructure transistor is formed.

[0039] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 on and / or above the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 below the gate electrode layer 210. The gate electrode layer 210 comprises polysilicon (PO) or other materials. The hard mask layer 215 comprises one or more layers, such as an oxide layer (e.g., a pad oxide layer, which may include silicon dioxide (SiO₂) or another material) and a nitride layer formed on the oxide layer (e.g., a pad nitride layer, which may include silicon nitride (e.g., Si₃N₄) or another material). The spacer layer 220 comprises silicon carbide (SiOC), nitrogen-free SiOC, or other suitable materials. The gate dielectric layer 225 may include silicon oxide (e.g., SiO x such as SiO 2), silicon nitride (e.g., Si xN y such as Si 3N 4), a high dielectric constant (high k) dielectric material (e.g., a dielectric material having a dielectric constant greater than about 3.9) and / or another suitable material.

[0040] Various semiconductor processing techniques that define the dummy gate structure 205 (such as techniques for depositing layers of the dummy gate structure 205, techniques for patterning layers of the dummy gate structure 205) and / or other semiconductor processing techniques can be used to form the layers of the dummy gate structure 205.

[0041] Figure 2 also shows the reference cross sections used in the following figures described in this disclosure. Cross section A–A lies in the xz plane (referred to as the y-cut) spanning the fin structure 150 in the source / drain region of semiconductor device 105. Cross section B–B lies in the yz plane (referred to as the x-cut) perpendicular to cross section A–A and spanning the dummy gate structure 205 and along the fin structure 150 below. Cross section C–C lies in the xz plane parallel to cross section A–A and perpendicular to cross section B–B, and along the dummy gate structure 205. For clarity, the following figures refer to these reference cross sections. In some figures, for ease of depiction, some reference numerals for components or features shown may be omitted to avoid obscuring other components or features.

[0042] As noted above, Figure 2 is provided as an example. Other examples may differ from those described with respect to Figure 2.

[0043] Figure 3 is an illustration of an exemplary implementation 300 of the source / drain recess formation process described in this disclosure. Exemplary implementation 300 includes an example of a source / drain recess 305 forming the source / drain region of a nanostructured transistor in a semiconductor device 105. Figure 3 shows several perspective views as shown in Figure 2, including a perspective view along cross-sectional plane A–A, a perspective view along cross-sectional plane B–B, and a perspective view along cross-sectional plane C–C in Figure 2. In some implementations, the operations described in conjunction with exemplary implementation 300 are performed after the processes described in conjunction with Figures 1A to 2.

[0044] As shown in cross-sectional planes A–A and B–B of Figure 3, during the etching operation, the source / drain recess 305 is formed as portions 155 extending through the fin structure 150. The source / drain recess 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some implementations, the etching operation includes the use of plasma etching, wet chemical etching, and / or another type of etching technique.

[0045] The source / drain recesses 305 also extend into a portion of the fin portion 160 of the fin structure 150. This results in the formation of a plateau region 310 in the fin structure 150. The sidewalls of those portions of each source / drain recess 305 below the layer stack 115 correspond to the sidewalls of the plateau region 310. The plateau region 310 (also referred to as the base) refers to the region of the fin portion 160 of the fin structure 150 in which nanostructure channels are defined from the nanostructure channel layer 125. The nanostructure channels 315 extend between adjacent source / drain recesses 305.

[0046] The nanostructure channel 315 includes a silicon-based nanostructure (e.g., a nanosheet or nanowire), which serves as a semiconductor channel for the nanostructure transistor of the semiconductor device 105. In some implementations, the nanostructure channel 315 may include silicon germanium (Silicon germanium) or another silicon-based material. The nanostructure channel 315 is arranged along a direction generally perpendicular to the semiconductor substrate 110 (e.g., the z-direction). In other words, the nanostructure channel 315 is arranged or stacked above the semiconductor substrate 110 in a vertical direction.

[0047] As noted above, Figure 3 is provided as an example. Other examples may differ from those described with respect to Figure 3.

[0048] Figures 4A and 4B are illustrations of an exemplary implementation 400 of the internal spacer formation process described in this disclosure. Exemplary implementation 400 includes an example of forming an internal spacer between the exposed ends of a nanostructure channel 315 in a source / drain recess 305. Figures 4A and 4B each show multiple perspective views as shown in Figure 2, including perspective views of cross-sectional planes A–A, B–B, and C–C in Figure 2. In some implementations, the operations described in conjunction with exemplary implementation 400 are performed after the processes described in conjunction with Figures 1A through 3.

[0049] As shown in the cross-sectional plane B–B of Figure 4A, during the etching operation, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain recesses 305 are etched laterally (e.g., along the x-direction generally parallel to the length of the sacrificial nanostructure layer 120), thereby forming a cavity 405 between the ends of the nanostructure channel 315 exposed in the source / drain recesses 305. Specifically, the etching tool can be used to laterally etch the ends of the sacrificial nanostructure layer 120 below the dummy gate structure 205 through the source / drain recesses 305 to form the cavity 405 between the ends of the nanostructure channel 315. The cavity 405 can be formed in an approximately curved shape, an approximately concave shape, an approximately triangular shape, an approximately square shape, or other shapes.

[0050] As shown in cross-sectional planes A–A and B–B of Figure 4B, internal spacers (InSP) 410 are formed in cavities 405 between the ends of adjacent nanostructure channels 315 in the source / drain recesses 305 in the vertical direction. The internal spacers 410 are included to reduce parasitic capacitance in the nanostructure transistors and protect the source / drain regions (which are subsequently formed in the source / drain recesses 305) from etching during the nanosheet release operation that removes the sacrificial nanostructure layer 120 between the nanostructure channels 315. The internal spacers 410 include silicon nitride (SixNy), silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and / or another dielectric material.

[0051] To form the internal spacer 410, a deposition tool can be used to deposit a dielectric material layer along the sidewalls and bottom surface of the source / drain recess in the cavity 405. CVD, PVD, ALD, and / or another deposition technique can be used to deposit the dielectric material layer. An etching tool is used to subsequently remove excess material from the source / drain recess, such that the remaining portion corresponds to the internal spacer 410 in the cavity 405. In some implementations, the etching operation may cause the surface of the internal spacer 410 facing the source / drain recess 305 to bend or recess. In some implementations, the surface of the internal spacer 410 facing the source / drain recess 305 is approximately flat, such that the surface of the internal spacer 410 and the surface of the end of the nanostructure channel 315 are approximately flat and flush.

[0052] As noted above, Figures 4A and 4B are provided as examples. Other examples may differ from those described with respect to Figures 4A and 4B.

[0053] Figure 5 is an illustration of an exemplary implementation 500 of the source / drain region formation process described in this disclosure. Exemplary implementation 500 includes an example of forming the source / drain regions of a nanostructured transistor for a semiconductor device 105. Figure 5 shows several perspective views as shown in Figure 2, including a perspective view along cross-sectional plane A–A, a perspective view along cross-sectional plane B–B, and a perspective view along cross-sectional plane C–C in Figure 2. In some implementations, the operations described in conjunction with exemplary implementation 500 are performed after the processes described in conjunction with Figures 1A to 4B.

[0054] As shown in cross-sectional planes A–A and B–B in Figure 5, the source / drain recess 305 is filled with one or more layers to form a source / drain region within the source / drain recess 305. For example, a deposition tool can be used to deposit a buffer region 505 at the bottom of the source / drain recess 305, and the deposition tool can deposit a source / drain region 510 on the buffer region 505 in the source / drain recess 305. In some implementations, the deposition tool is used to deposit a capping layer 515 on the source / drain region 510 in the source / drain recess 305.

[0055] Buffer region 505 may include silicon (Si), silicon (SiB) doped with boron or another dopant, and / or another material. Buffer region 505 may be incorporated between source / drain region 510 and adjacent plateau region 310 to reduce, minimize, and / or prevent dopant migration from source / drain region 510 to adjacent plateau region 310 and / or current leakage from source / drain region 510 to adjacent plateau region 310, which could otherwise cause short-channel effects in semiconductor device 105. Accordingly, buffer region 505 may increase the performance of semiconductor device 105 and / or increase the yield of semiconductor device 105.

[0056] The source / drain region 510 may refer individually or collectively as source or drain, depending on the context. The source / drain region 510 may be incorporated on the opposite side of the dummy gate structure 205 such that the nanostructure channel 315 beneath the dummy gate structure 205 extends between and is electrically coupled to the source / drain region 510. Each of the source / drain regions 510 comprises silicon (Si) with one or more dopants, such as p-type materials (e.g., boron (B) or germanium (Ge), n-type materials (e.g., phosphorus (P) or arsenic (As), etc.) and / or another type of dopant. Accordingly, the semiconductor device 105 may include a p-type metal-oxide-semiconductor (PMOS) nanostructure transistor (which includes p-type source / drain regions 510), an n-type metal-oxide-semiconductor (NMOS) nanostructure transistor (which includes n-type source / drain regions 510), and / or other types of nanostructure transistors.

[0057] One or more source / drain regions 510 can be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or formed using one or more other deposition techniques. For example, a deposition tool can epitaxially grow a first source / drain region 510 (referred to as L1) over an associated buffer region 505 (which may be referred to as L0), and a second source / drain region 510 (referred to as L2, L2-1, and / or L2-2) can be epitaxially grown over the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or another dopant) and may be included as a shielding layer to reduce short-channel effects in the semiconductor device 105 and reduce dopant extrusion or migration into the nanostructure channel 315. The second layer may include highly doped silicon or highly doped silicon-germanium. The second layer may be incorporated to provide compressive stress in the source / drain region 510 to reduce boron loss.

[0058] The capping layer 515 may include silicon, silicon-germanium, doped silicon, doped silicon-germanium, and / or other materials. The capping layer 515 may be included to reduce dopant diffusion during semiconductor processing operations of the semiconductor device 105 prior to contact formation and to protect the underlying source / drain regions 510. Furthermore, the capping layer 515 may facilitate the formation of a metal-semiconductor (e.g., silicate) alloy.

[0059] As noted above, Figure 5 is provided as an example. Other examples may differ from those described with respect to Figure 5.

[0060] Figure 6 is an illustration of an exemplary implementation 600 of the interlayer dielectric (ILD) formation process described in this disclosure. Figure 6 shows several perspective views as shown in Figure 2, including perspective views of cross-sectional plane A–A, cross-sectional plane B–B, and cross-sectional plane C–C in Figure 2. In some implementations, the operations described in conjunction with exemplary implementation 500 are performed after the processes described in conjunction with Figures 1A to 5.

[0061] As shown in cross-sectional planes A–A and B–B in Figure 6, a dielectric layer 605 is formed over the source / drain region 510. The dielectric layer 605 (which may be referred to as an ILD layer) fills the region between the dummy gate structures 205. The dielectric layer 605 is formed to reduce the likelihood of damage to the source / drain region 510 during the replacement gate process used to replace the dummy gate structures 205 and / or to prevent damage to the source / drain region 510. The dielectric layer 605 may be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0062] In some implementations, a contact etch stop layer (CESL) is conformally deposited over the source / drain region 510 (e.g., through a deposition tool) prior to the formation of the dielectric layer 605. Alternatively, a capping layer 515 may be a CESL. The dielectric layer 605 is then formed on the CESL. The CESL provides a mechanism to stop the etching process when forming contacts or vias in the source / drain region 510. The CESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or parts. The CESL may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the CESL may include or may be silicon nitride (SixNiy), silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or combinations thereof. The CESL may be deposited using deposition processes (e.g., ALD, CVD, or other deposition techniques).

[0063] As noted above, Figure 6 is provided as an example. Other examples may differ from those described with respect to Figure 6.

[0064] Figures 7A to 7H are illustrations of an exemplary implementation 700 of the alternative gate (RPG) process described herein. Exemplary implementation 700 includes an example of an alternative gate process for replacing the dummy gate structure 205 with a high-k / metal gate structure (e.g., an alternative gate structure) of the nanostructured transistor of semiconductor element 105. Figures 7A to 7H each show one or more perspective views shown in Figure 2, such as perspective views of cross-sectional plane B–B and / or cross-sectional plane C–C in Figure 2. In some implementations, the operations described in conjunction with exemplary implementation 700 are performed after the operations described in conjunction with Figures 1A to 6.

[0065] As shown in cross-sectional planes B–B and C–C of Figure 7A, the alternative gate process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. Removal of the dummy gate structure 205 leaves an opening (or recess) between the dielectric layers 605 and provides a path to the underlying sacrificial nanostructure layer 120. The dummy gate structure 205 can be removed in one or more etching operations. Such etching operations can include plasma etching, wet chemical etching, and / or another type of etching technique.

[0066] Removing the dummy gate structure 205 exposes the platform region 310a and the stacked nanostructure channels 315a arranged along the z-direction above the platform region 310a in the semiconductor device 105. Removing the dummy gate structure 205 also exposes the platform region 310b and the stacked nanostructure channels 315b arranged along the z-direction above the platform region 310b in the semiconductor device 105. The nanostructure channels 315a and 315b extend along the y-direction in the semiconductor device 105. The nanostructure channels 315a and 315b can be arranged along the x-direction in the semiconductor device 105 such that they are side-by-side or laterally adjacent.

[0067] Platform region 310a and nanostructure channel 315a can be exposed to prepare for forming an n-type gate structure of an NMOS nanostructure transistor for semiconductor device 105 around nanostructure channel 315a. Platform region 310b and nanostructure channel 315b can be exposed to prepare for forming a p-type gate structure of a PMOS nanostructure transistor for semiconductor device 105 around nanostructure channel 315b.

[0068] In some implementations, the z-direction thickness of the nanostructure channel 315a ranges from about 3 nanometers to about 10 nanometers. However, other values ​​and ranges of the z-direction thickness of the nanostructure channel 315a are within the scope of this disclosure. In some implementations, the z-direction thickness of the nanostructure channel 315b ranges from about 3 nanometers to about 10 nanometers. However, other values ​​and ranges of the z-direction thickness of the nanostructure channel 315b are within the scope of this disclosure.

[0069] In some implementations, the z-direction distance (e.g., channel-to-channel spacing) between adjacent vertically oriented nanostructure channels 315a is within the range of about 3 nanometers to about 10 nanometers. However, other values ​​and ranges of the z-direction spacing between nanostructure channels 315a are within the scope of this disclosure. In some implementations, the z-direction distance (e.g., channel-to-channel spacing) between adjacent vertically oriented nanostructure channels 315b is within the range of about 3 nanometers to about 10 nanometers. However, other values ​​and ranges of the z-direction spacing between nanostructure channels 315b are within the scope of this disclosure.

[0070] As further shown in Figure 7A, the alternative gate process includes a nanostructure release operation (e.g., a silicon-germanium release operation). A nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon-germanium layer). This results in the formation of openings 705 between nanostructure channels 315a (e.g., regions surrounding nanostructure channels 315a) and between nanostructure channels 315b (e.g., regions surrounding nanostructure channels 315b). The sacrificial nanostructure layer 120 can be removed through the space previously occupied by the dummy gate structure 205. The nanostructure release operation may include performing an etching operation using an etching tool to remove the sacrificial nanostructure layer 120 based on differences in etch selectivity between the materials of the sacrificial nanostructure layer 120 and the materials of the nanostructure channels 315a and 315b, and between the materials of the sacrificial nanostructure layer 120 and the internal spacer 410. The internal spacer 410 may be used as an etch stop layer in the etching operation to protect the source / drain regions 510 from etching.

[0071] As shown in Figure 7B, an interface layer 715 can be formed around nanostructure channels 315a and 315b. The interface layer 715 can be conformally deposited (e.g., using ALD, CVD, and / or another suitable conformal deposition technique) such that the interface layer 715 is deposited as a conformal thin film. The interface layer 715 may include silicon dioxide (SiO2) and / or another suitable dielectric material that can be used to tune the interface between the gate dielectric layer 720 and the nanostructure channels 315a and 315b. In some implementations, the interface layer 715 may have a thickness ranging from about 5 angstroms to about 25 angstroms. However, other values ​​and ranges of the thickness of the interface layer 715 are within the scope of this disclosure.

[0072] As further shown in Figure 7B, a gate dielectric layer 720 is formed around nanostructure channels 315a and 315b. The gate dielectric layer 720 can be conformally deposited (e.g., using ALD, CVD, and / or another suitable conformal deposition technique) such that the gate dielectric layer 720 is deposited as a conformal thin film.

[0073] The gate dielectric layer 720 may include one or more high-k materials (e.g., dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO₂, dielectric constant about 3.9)). Examples of such high-k materials include lanthanum oxide (La₂xO₂y, e.g., La₂O₃), hafnium oxide (HfO₂x, e.g., HfO₂), zirconium oxide (ZrO₂x, e.g., ZrO₂), and / or aluminum oxide (Al₂xO₂y, e.g., Al₂O₃), as well as other examples of high-k dielectric materials. Additionally and / or alternatively, silicon dioxide (SiO₂) and / or another dielectric material may be used instead of a high-k dielectric material.

[0074] In some implementations, the gate dielectric layer 720 is formed as a multilayer thin film comprising two or more layers of high-k dielectric material. For example, the gate dielectric layer 720 may include a first layer and a second layer on top of the first layer, the first layer comprising hafnium oxide (HfO x, e.g., HfO 2) and the second layer comprising zirconium oxide (ZrO x, e.g., ZrO 2). Other combinations of high-k dielectric layers of the gate dielectric layer 720 are within the scope of this disclosure.

[0075] In some implementations, the gate dielectric layer 720 may have a thickness ranging from about 5 angstroms to about 30 angstroms. However, other values ​​and ranges of the thickness of the gate dielectric layer 720 are within the scope of this disclosure.

[0076] As further shown in Figure 7B, a p-type metal layer 725 is formed on the gate dielectric layer 720. In some implementations, an adhesion liner is first formed on the gate dielectric layer 720, and the p-type metal layer 725 is formed on the adhesion liner. The p-type metal layer 725 is formed on the exposed portions of the plateau regions 310a and 310b, as well as on the nanostructure channels 315a and 315b, such that the p-type metal layer 725 surrounds the nanostructure channels 315a and 315b.

[0077] In some embodiments, the p-type metal layer 725 surrounds the nanostructure channels 315a and 315b, such that the p-type metal layer 725 is merged between pairs of adjacent nanostructure channels 315a in the vertical direction, while it is not merged between pairs of adjacent nanostructure channels 315b in the vertical direction. In some embodiments, the p-type metal layer 725 surrounds the nanostructure channels 315a and 315b, and the p-type metal layer 725 is not merged between pairs of adjacent nanostructure channels 315a in the vertical direction, and / or it is not merged between pairs of adjacent nanostructure channels 315b in the vertical direction. In these implementations, seams may appear in the portion of the p-type metal layer 725 between pairs of adjacent nanostructure channels 315a in the vertical direction and / or in the portion of the p-type metal layer 725 between pairs of adjacent nanostructures in the vertical direction.

[0078] Because the p-gate structure 710b includes a metal gate structure, the work function of the p-gate structure 710b can be tuned by including one or more work function tuning metals within it. This differs from polycrystalline silicon gate structures, where the work function is tuned by doping the polycrystalline silicon material with p-type and / or n-type dopants. A p-type metal layer 725 can be incorporated as a p-type work function metal in the p-gate structure 710b to tune its work function. The p-type metal layer 725 can include one or more p-type metals, such as tungsten (W), cobalt (Co), titanium nitride (TiN), tungsten nitride (WN), and / or another metal having a work function greater than approximately 4.7 electron volts (eV). The p-type metal layer 725 can be incorporated to tune the work function of the PMOS nanostructure transistor, such that the work function is adjusted to be close to the valence band of the material in the nanostructure channel 315b. This enables relatively low threshold voltages for PMOS nanostructure transistors, while also enabling relatively low current leakage for PMOS nanostructure transistors.

[0079] Deposition tools can be used to deposit a p-type metal layer 725 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The p-type metal layer 725 can be deposited in one or more deposition operations. In some implementations, the p-type metal layer 725 is formed to have a thickness ranging from about 0.1 angstroms to about 50 angstroms. However, other values ​​and ranges for the thickness of the p-type metal layer 725 are within the scope of this disclosure.

[0080] As noted above, the p-type metal layer 725 is formed around the nanostructure channels 315a and 315b. This is because the p-type metal layer 725 is formed without using a masking layer around the nanostructure channel 315a. If the p-type metal layer 725 were to surround the nanostructure channel 315a, it could cause the work function of the n-type gate structure 710a to be too far from the conduction band of the material of the nanostructure channel 315a. Therefore, as shown in Figures 7C and 7D, the p-type metal layer 725 is removed from the nanostructure channel 315a after its formation.

[0081] As shown in Figure 7C, a photoresist layer 730 can be formed on the semiconductor device 105. The photoresist layer 730 can be formed on a p-type metal layer 725 on platform regions 310a, platform regions 310b, nanostructure channels 315a and 315b. Deposition tools can be used to deposit the photoresist layer 730 using spin coating and / or another deposition technique.

[0082] As further shown in Figure 7C, a pattern is formed in the photoresist layer 730. The n-type gate structure 710a is exposed through the pattern in the photoresist layer 730. This allows the photoresist layer 730 to be used to remove the p-type metal layer 725 from the plateau region 310a and the nanostructure channel 315a, without removing the p-type metal layer 725 from the plateau region 310b and the nanostructure channel 315b. An exposure tool can be used to expose the photoresist layer 730 to a radiation source to pattern the photoresist layer 730. A development tool can be used to develop and remove portions of the photoresist layer 730 in the plateau region 310a and the nanostructure channel 315a.

[0083] As shown in Figure 7D, the portions of the p-type metal layer 725 exposed by the pattern in the photoresist layer 730 are removed from the platform region 310a and from the nanostructure channel 315a. The photoresist layer 730 over the p-type gate structure 710b protects these portions of the p-type metal layer 725 from removal from the platform region 310b and the nanostructure channel 315b. An etching tool can be used to etch the p-type metal layer 725 based on the pattern in the photoresist layer 730 to remove those portions of the p-type metal layer 725 from the platform region 310a and from the nanostructure channel 315a. In some implementations, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation.

[0084] Subsequently, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer 730. Chemical strippers, plasma ashing, and / or another technique can be used to remove the remaining portion of the photoresist layer 730. Removing the remaining portion of the photoresist layer 730 exposes the p-type metal layer 725 on the platform region 310b and the nanostructure channel 315b.

[0085] As shown in Figure 7E, a self-assembled monolayer 735 is formed on the p-type metal layer 725 of the p-type gate structure 710b. In other words, the self-assembled monolayer 735 is formed on the p-type metal layer 725 surrounding the nanostructure channel 315b and included in the platform region 310b.

[0086] The self-assembled monolayer film 735 includes a "monolayer" film because it can have a single-molecule thickness (e.g., the thickness of a single-molecule thick layer of material corresponding to the self-assembled monolayer film 735). The self-assembled monolayer film 735 is formed on the p-type metal layer 725 to block or suppress the formation of an n-type metal layer on the p-type metal layer 725. Subsequently, an n-type metal layer is formed on the nanostructure channel 315a of the n-type gate structure 710a to tune the work function of the n-type gate structure 710a. The self-assembled monolayer film 735 minimizes or reduces the influence of the n-type metal layer on the work function of the p-type gate structure 710b.

[0087] The self-assembled monolayer 735 comprises one or more materials that enable selective deposition of the self-assembled monolayer 735 on the p-type metal layer 725, with little or no deposition on the gate dielectric layer 720 of the n-type gate structure 710a. For example, the self-assembled monolayer 735 may be formed of a material including an anchoring base 740 that promotes adsorption of the material of the self-assembled monolayer 735 onto the p-type metal layer 725 and prevents adsorption onto the high-k dielectric material of the gate dielectric layer 720. In some implementations, the adsorption selectivity of the anchoring base 740 of the self-assembled monolayer 735 may include a range from 20:1 (e.g., adsorption on the p-type metal layer 725 relative to adsorption on the high-k dielectric material of the gate dielectric layer 720) to approximately 70:1 to achieve sufficient deposition selectivity for the self-assembled monolayer 735. Examples of such materials include those with an anchoring group 740, which includes amino (-NH₂), thiol (-SH), carboxyl (-COOH), carbonyl (-COH), trichlorosilane (-SiCl₃), and / or phosphonate (-P), etc. In some implementations, the anchoring group 740 includes nitrogen ligands (N-ligands), sulfur ligands (S-ligands), silicon ligands (Si-ligands), phosphorus ligands (P-ligands), and / or another type of ligand.

[0088] The self-assembled monolayer 735 includes one or more materials capable of blocking or inhibiting the adsorption of the precursor of the n-type metal layer of the n-type gate structure 710a onto the p-type metal layer 725 of the p-type gate structure 710b. For example, the self-assembled monolayer 735 may be formed of a material including a side chain group 745, which includes a hydrocarbon group such as an aryl hydrocarbon chain.

[0089] In some implementations, the self-assembled monolayer 735 is formed by depositing a solution of material containing the self-assembled monolayer 735 onto the surface of the p-type metal layer 725 using a spin coating technique. In some implementations, a pre-cleaning operation uses isopropanol (IPA) or another cleaning agent to pre-clean the p-type metal layer 725 before the deposition solution.

[0090] The solution may include the material of the self-assembled monolayer 735 dissolved in a solvent, which allows the material of the self-assembled monolayer 735 to be distributed on the p-type metal layer 725. The solvent may include γ-butyrolactone (GBL) solvent, diethylmethylamine (DEF) solvent, propylene glycol methyl ether acetate (PGMEA) solvent, propylene glycol methyl ether (PGME) solvent and / or another suitable solvent.

[0091] Once the p-type metal layer 725 is coated with a solvent, a spin-drying operation can be performed to solidify the solution by evaporating the solvent, leaving the material of the self-assembled monolayer film 735 on the p-type metal layer 725. The molecules of the material spontaneously self-assemble into a monolayer, thereby forming the self-assembled monolayer film 735. In some implementations, an additional cleaning operation is performed prior to the spin-drying operation (e.g., using IPA or another cleaning agent). In some implementations, the spin-drying operation is performed in the range of approximately 200 rpm to approximately 1000 rpm. However, other values ​​and ranges for the spin-drying operation are within the scope of this disclosure.

[0092] In some implementations, the self-assembled monolayer 735 is formed with a thickness ranging from about 0.1 angstroms to about 10 angstroms. If the thickness of the self-assembled monolayer 735 is less than about 0.1 angstroms, the self-assembled monolayer 735 may be insufficient to block or inhibit the formation of an n-type metal layer on the p-type metal layer 725, resulting in degradation of the work function of the p-type gate structure 710b. If the thickness of the self-assembled monolayer 735 is greater than about 10 angstroms, the self-assembled monolayer 735 may be too thick to be sufficiently removed from the p-type gate structure 710b. If the thickness of the self-assembled monolayer 735 is within the range of about 0.1 angstroms to about 10 angstroms, the self-assembled monolayer 735 can sufficiently block or inhibit the formation of an n-type metal layer on the p-type metal layer 725 and can be sufficiently removed from the p-type gate structure 710b. However, other values ​​for the thickness of the self-assembled monolayer 735, as well as ranges beyond about 0.1 angstroms to about 10 angstroms, are also within the scope of this disclosure.

[0093] As shown in Figure 7F, after forming a self-assembled monolayer 735 on the p-type metal layer 725 of the p-type gate structure 710b, an n-type metal layer 750 is formed on the n-type gate structure 710a. The n-type metal layer 750 is formed such that it surrounds each nanostructure channel 220a. The n-type metal layer 750 is also formed on the exposed portion of the platform region 310a below the nanostructure channel 315a. Deposition tools can be used to deposit the n-type metal layer 750 using CVD, PVD, ALD, and / or another suitable deposition technique. The n-type metal layer 750 can be deposited in one or more deposition operations.

[0094] In some embodiments, the n-type metal layer 750 surrounds the nanostructure channel 315a, and is merged between pairs of adjacent nanostructure channels 315a in the vertical direction. In some embodiments, the n-type metal layer 750 surrounds the nanostructure channel 315a, and is not merged between vertically adjacent pairs of adjacent nanostructure channels 315a in the vertical direction. In these implementations, seams may appear in the portion of the n-type metal layer 750 between pairs of adjacent nanostructure channels 315a in the vertical direction.

[0095] The n-type metal layer 750 includes one or more metallic materials that tune or adjust the work function of the n-type gate structure 710a near the conduction band of the material of the nanostructure channel 220a. In some implementations, the n-type metal layer 750 includes titanium aluminum (TiAl). In some implementations, the n-type metal layer 750 includes titanium aluminum carbon (TiAlC). In some implementations, the n-type metal layer 750 includes another aluminum-containing metal. In some implementations, another n-type metallic material is included in the n-type metal layer 750.

[0096] The n-type metal layer 750 is formed without using an additional photomask layer covering the p-type metal layer 725 of the p-type gate structure 710b. Alternatively, a self-assembled monolayer 735 on the p-type metal layer 725 blocks or inhibits the formation of the n-type metal layer 750 on the p-type metal layer 725. Thus, the self-assembled monolayer 735 allows the n-type metal layer 750 to be selectively deposited on the gate dielectric layer 720 on the nanostructure channel 315a. In particular, the side chain groups 745 of the material of the self-assembled monolayer 735 inhibit the adsorption of the precursor of the n-type metal layer 750 on the p-type metal layer 725.

[0097] As shown in Figure 7G, after the n-type metal layer 750 is formed, the self-assembled monolayer 735 can then be removed. Various techniques can be used to remove the self-assembled monolayer 735 from the p-type metal layer 725 of the p-type gate structure 710b. Alternatively, the removal of the self-assembled monolayer 735 can be omitted, leaving the self-assembled monolayer 735 on the p-type metal layer 725.

[0098] In some implementations, a thermal decomposition operation can be performed to remove the self-assembled monolayer 735 from the p-type metal layer 725 of the p-type gate structure 710b. The thermal decomposition operation may include heating the self-assembled monolayer 735 to a temperature ranging from about 300 degrees Celsius to about 500 degrees Celsius to decompose the hydrocarbon chains in the self-assembled monolayer 735. Decomposition of the side chain groups 745 (e.g., hydrocarbon chains) in the self-assembled monolayer 735 results in the desorption of the self-assembled monolayer 735 from the p-type metal layer 725.

[0099] In some implementations, a plasma treatment operation may be performed on the self-assembled monolayer 735 to remove the self-assembled monolayer 735 from the p-type metal layer 725. The plasma treatment operation may include cleaning the surface of the p-type metal layer 725 using a plasma (e.g., oxygen-based plasma, nitrogen-based plasma). This results in the self-assembled monolayer 735 being peeled off from the surface of the p-type metal layer 725.

[0100] In some implementations, the self-assembled monolayer 735 is completely removed from the p-type metal layer 725. In some implementations, as shown in FIG7G, the removal of the self-assembled monolayer 735 may leave a self-assembled monolayer residue 755 on the p-type metal layer 725. The self-assembled monolayer residue 755 may include residual anchoring bases 740 of the self-assembled monolayer 735, which are adsorbed on the surface of the p-type metal layer 725. The residual anchoring base 740 may include ligands of one or more elements of the residual anchoring base 740, such as sulfur (S) ligands (e.g., in an implementation where the anchoring base 740 of the self-assembled monolayer 735 includes a thiol group), silicon (Si) ligands (e.g., in an implementation where the anchoring base 740 of the self-assembled monolayer 735 includes trichlorosilane (SiCl 3)) and / or phosphorus (P) ligands (e.g., in an implementation where the anchoring base 740 of the self-assembled monolayer 735 includes a phosphonate ester), etc.

[0101] In some implementations, the material of the n-type metal layer 750 is completely blocked from deposition on the p-type metal layer 725 by the self-assembled monolayer film 735. In some implementations (e.g., in implementations where at least a portion of the self-assembled monolayer film 735 on the p-type metal layer 725 is discontinuous and / or porous), the self-assembled monolayer film residue 755 also includes n-type metal layer residue. The n-type metal layer residue may include aluminum (Al) residue retained on the p-type metal layer 725 of the p-type gate structure 710b after the formation of the n-type metal layer 750 on the n-type gate structure 710a. However, the thickness of the self-assembled monolayer residue 755 (including aluminum residue) on the p-type gate structure 710b (denoted as dimension D1 in FIG. 7G) is smaller than the thickness of the n-type metal layer 750 on the n-type gate structure 710a (denoted as dimension D2 in FIG. 7G) because the self-assembled monolayer 735 serves to block or inhibit the deposition of material of the n-type metal layer 750 on the p-type gate structure 710b. For example, the thickness (dimension D2) of the n-type metal layer 750 on the n-type gate structure 710a can include the range of about 5 angstroms to about 50 angstroms, while the thickness (dimension D1) of the self-assembled monolayer residue 755 (including aluminum residue) on the p-type gate structure 710b can be less than about 5 angstroms and as thin as about 0.1 angstroms. Due to the minimal thickness of the self-assembled monolayer residue 755, the self-assembled monolayer residue 755 can be a discontinuous film (e.g., a porous film) retained on the p-type metal layer 725. However, other values ​​and ranges for the thickness of the self-assembled monolayer film residue 755 and the thickness of the n-type metal layer 750 are within the scope of this disclosure.

[0102] The smaller thickness (size D1) of the self-assembled monolayer residue 755 (including aluminum residue) on the p-type gate structure 710b results in a reduced or minimized effect of the n-type metal layer 750 on the work function of the p-type gate structure 710b. Specifically, compared to the case where the self-assembled monolayer 735 is used to block the formation of the n-type metal layer 750 on the p-type gate structure 710b, the smaller thickness (size D1) of the self-assembled monolayer residue 755 (including aluminum residue) on the p-type gate structure 710b results in a work function of the p-type gate structure 710b that is closer to the valence band of the nanostructure channel 315b material. Therefore, using a self-assembled monolayer film 735 to block the formation of the n-type metal layer 750 on the p-type gate structure 710b allows the work function of the p-type gate structure 710b to be tuned to achieve the p-type threshold voltage (PVt) of the PMOS nanostructure transistor. This p-type threshold voltage (PVt) enables the PMOS nanostructure transistor to operate efficiently and has low current leakage.

[0103] As shown in Figure 7H, a gate electrode layer 760 of an n-type gate structure 710a is formed on an n-type metal layer 750, and a gate electrode layer 760 of a p-type gate structure 710b is formed on a p-type metal layer 725. In some implementations, when the self-assembled monolayer film residue 755 remains on the p-type metal layer 725, the gate electrode layer 760 is formed on the self-assembled monolayer film residue 755. In some implementations, separate gate electrode layers 760 are formed for the n-type gate structure 710a and the p-type gate structure 710b, respectively. In some implementations, a shared gate electrode layer 760 is formed for the n-type gate structure 710a and the p-type gate structure 710b. In some implementations, an adhesive layer is first formed on the n-type metal layer 750 and / or the p-type metal layer 725, and the gate electrode layer 760 is formed on the adhesive layer. The adhesive layer may include titanium nitride (TiN) and / or another material that promotes the adhesion of the gate electrode layer 760 to the n-type metal layer 750 and / or the p-type metal layer 725.

[0104] The gate electrode layer 760 comprises one or more metallic materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo). Deposition tools can be used to deposit the gate electrode layer 760 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The gate electrode layer 760 can be deposited in one or more deposition operations. In some implementations, a seed layer is first deposited, and the gate electrode layer 760 is deposited on the seed layer. In some implementations, planarization tools can be used to perform a CMP operation or another type of planarization operation to planarize the gate electrode layer 760 after deposition.

[0105] In this manner, the semiconductor substrate 105 may include a plurality of nanostructure channels 315a and a plurality of nanostructure channels 315b arranged along a z-direction generally perpendicular to the z-direction of the semiconductor substrate 110 of the semiconductor device 105. The nanostructure channels 315a and 315b may be adjacent to each other in the semiconductor element 105. The semiconductor element 105 may include an n-type gate structure 710a surrounding the nanostructure channels 315a and a p-type gate structure 710b surrounding the nanostructure channels 315b. The p-type gate structure 710b may include a p-type metal layer 725 and a self-assembled monolayer film residue 755 on the p-type metal layer 725. The n-type gate structure 710a may include an n-type metal layer 750. The self-assembled monolayer residue 755 may include one or more ligands of the anchoring base of the self-assembled monolayer 735, which is used to block or inhibit the deposition of the n-type metal layer 750 on the p-type metal layer 725, and / or the self-assembled monolayer residue 755 may include residual material of the n-type metal layer 750.

[0106] As noted above, Figures 7A through 7H are provided as examples. Other examples may differ from those described with respect to Figures 7A through 7H.

[0107] Figure 8 is an illustration of an example 800 of the elemental concentration in the gate structure of the nanostructured transistor described in this disclosure. In particular, example 800 includes an aluminum concentration of 805 in the n-type gate structure 710a and an aluminum concentration of 810 in the p-type gate structure 710b of the nanostructured transistor, which is formed by using a self-assembled monolayer film 735 to block or suppress the deposition of an n-type metal layer 750 on the p-type gate structure 710b, as described in conjunction with Figures 7A to 7H.

[0108] As shown in Figure 8, aluminum concentrations 805 and 810 are shown as functions of intensity 815 and depth 820 in the n-type gate structure 710a and p-type gate structure 710b, respectively. The intensity 815 of aluminum concentration 805 is highest in the n-type metal layer 750 of the n-type gate structure 710a because the n-type metal layer 750 is composed of an aluminum-containing n-type work function metal (e.g., titanium aluminum (TiAl) or titanium aluminum carbide (TiAlC)). The intensity 815 of aluminum concentration 810 in the p-type gate structure 710b is highest in the self-assembled monolayer film residue 755 because the self-assembled monolayer film residue 755 may include a small amount of aluminum residue on the p-type metal layer 725. However, the strength 815 of aluminum in the self-assembled monolayer residue 755 is less than the strength 815 of aluminum in the n-type metal layer 750 because the self-assembled monolayer 735 is used to block or inhibit the deposition of the n-type metal layer 750 on the p-type gate structure 710b.

[0109] As noted above, Figure 8 is provided as an example. Other examples may differ from those described with respect to Figure 8.

[0110] Figure 9 is an illustration of an example 900 of the elemental composition of the gate structure of the nanostructured transistor described in this disclosure. In particular, example 900 includes the elemental composition 905 of the p-type gate structure 710b of the nanostructured transistor, which is formed by using a self-assembled monolayer film 735 to block or inhibit the deposition of an n-type metal layer 750 on the p-type gate structure 710b, as described in conjunction with Figures 7A to 7H.

[0111] As shown in Figure 9, the elemental composition 905 is displayed as a function of the concentration 910 and depth 915 in the p-type gate structure 710b. Elemental composition 905 includes a self-assembled monolayer residue component 920 and an n-type metal layer residue component 925. The self-assembled monolayer residue component 920 corresponds to the self-assembled monolayer residue 755 that can remain on the p-type metal layer 725 of the p-type gate structure 710b after the removal of the self-assembled monolayer 735.

[0112] The self-assembled monolayer residue component 920 may include ligands of one or more elements of the anchoring base 740 of the self-assembled monolayer 735 adsorbed on the surface of the p-type metal layer 725 after the removal of the self-assembled monolayer 735. The ligands may include, for example, sulfur (S) ligands (e.g., in an implementation where the anchoring base 740 of the self-assembled monolayer 735 comprises a thiol group), silicon (Si) ligands (e.g., in an implementation where the anchoring base 740 of the self-assembled monolayer 735 comprises trichlorosilane (SiCl3)), and / or phosphorus (P) ligands (e.g., in an implementation where the anchoring base 740 of the self-assembled monolayer 735 comprises a phosphonate ester), etc.

[0113] The n-type metal layer residue composition 925 may include aluminum (Al) residues retained on the p-type metal layer 725 of the p-type gate structure 710b after the formation of the n-type metal layer 750 on the n-type gate structure 710a. As shown in Figure 8, the concentration of aluminum residues on the p-type gate structure 710b is lower than the concentration of aluminum on the n-type gate structure 710a because the self-assembled monolayer film 735 is used to block or inhibit the deposition of material of the n-type metal layer 750 on the p-type gate structure 710b.

[0114] As noted above, Figure 9 is provided as an example. Other examples may differ from those described with respect to Figure 9.

[0115] Figures 10A to 10D are illustrations of exemplary implementations of the gate structure in the nanostructured transistors disclosed herein. In particular, Figures 10A to 10D show various exemplary implementations of the p-type metal layer 725 (e.g., a p-type work function metal layer) of the p-type gate structure 710b of the nanostructured transistor included in the semiconductor device 105 and / or various exemplary implementations of the n-type metal layer 750 (e.g., an n-type work function metal layer) of the n-type gate structure 710a.

[0116] Figure 10A illustrates an exemplary implementation 1000, in which a seam 1005 appears in the p-type metal layer 725 of the p-type gate structure 710b. The seam 1005 may appear between portions of the p-type metal layer 725 located between pairs of adjacent nanostructure channels 315b in the vertical direction. In some implementations, a small amount of self-assembled monolayer film 735 as described herein may be deposited in the seam 1005.

[0117] Figure 10B illustrates an exemplary implementation 1010, in which the p-type metal layer 725 of the p-type gate structure 710b is not merged between pairs of adjacent nanostructure channels 315b in the vertical direction. In some implementations, the space between portions of the p-type metal layer 725 on the pairs of adjacent nanostructure channels 315b in the vertical direction is filled with another p-type metal layer. In some implementations, the space between portions of the p-type metal layer 725 on the pairs of adjacent nanostructure channels 315b in the vertical direction is filled with a gate electrode layer 760. In some implementations, a small amount of the self-assembled monolayer film 735 described herein may be deposited in the space between portions of the p-type metal layer 725 on the pairs of adjacent nanostructure channels 315b in the vertical direction.

[0118] Figure 10C illustrates an exemplary implementation 1015, in which the p-type metal layer 725 of the p-type gate structure 710b is completely merged in the space between pairs of adjacent nanostructure channels 315b in the vertical direction.

[0119] Figure 10D illustrates an exemplary implementation 1020, in which an adhesive layer 1025 may be included on the n-type metal layer 750 of the n-type gate structure 710a and the p-type metal layer 725 of the p-type gate structure 710b (included on the self-assembled monolayer film residue 755). The adhesive layer 1025 may include titanium nitride (TiN) and / or another suitable material to facilitate adhesion between the n-type metal layer 750 and the gate electrode layer 760, and / or to facilitate adhesion between the p-type metal layer 725 and the gate electrode layer 760.

[0120] As further shown in the exemplary implementation 1020 of Figure 10D, the n-type metal layer 750 of the n-type gate structure 710a is not merged between pairs of adjacent nanostructure channels 315a in the vertical direction. In some implementations, the adhesive layer 1025 fills the gaps between portions of the n-type metal layer 750 between pairs of adjacent nanostructure channels 315b in the vertical direction.

[0121] As noted above, Figures 10A to 10D are provided as examples. Other examples may differ from those described with respect to Figures 10A to 10D.

[0122] Figures 11A and 11B are illustrations of an exemplary implementation 1100 of the work function metal layer for forming the gate structure of the nanostructured transistor as described in this disclosure. As shown in Figure 11A, the exemplary implementation 1100 includes forming a self-assembled monolayer 1105, similar to that described in conjunction with Figure 7E. However, in the exemplary implementation 1100, the self-assembled monolayer 1105 is formed on the gate dielectric layer 720 of the n-type gate structure 710a, as shown in Figure 11A, rather than on the p-type metal layer 725 of the p-type gate structure 710b, as shown in Figure 7E. Therefore, in the exemplary implementation 1100, the self-assembled monolayer 1105 includes one or more materials that promote the selective deposition of the self-assembled monolayer 1105 on the gate dielectric layer 720 and prevent or inhibit the deposition of the self-assembled monolayer 1105 on the p-type metal layer 725 of the p-type gate structure 710b. In some implementations, the self-assembled monolayer 1105 is formed with a thickness ranging from greater than 0 angstroms to less than or approximately equal to 2 angstroms. However, other values ​​and ranges of the thickness of the self-assembled monolayer 1105 are within the scope of this disclosure.

[0123] As shown in Figure 11B, a self-assembled monolayer 1105 is formed on the gate dielectric layer 720 of the n-type gate structure 710a, enabling the deposition of an additional layer on the p-type gate structure 710b. Simultaneously, the self-assembled monolayer 1105 blocks or inhibits the deposition of the additional layer on the n-type gate structure 710a. In this manner, the self-assembled monolayer 1105 promotes the selective formation of the additional layer on the p-type gate structure 710b. In some implementations, the additional layer includes an additional p-type work function layer. For example, the self-assembled monolayer 1105 blocks or inhibits the deposition of another p-type metal layer 1110 on the n-type gate structure 710a, allowing the p-type metal layer 1110 to be selectively formed on the p-type metal layer 725 of the p-type gate structure 710b.

[0124] In some implementations, the self-assembled monolayer 1105 is then removed, and the operations described in conjunction with Figures 7E to 7H are performed to selectively form an n-type metal layer 750 on the n-type gate structure 710a using another self-assembled monolayer 735, while the self-assembled monolayer 735 blocks or inhibits the deposition of the n-type metal layer 750 on the p-type metal layer 1110 of the p-type gate structure 710b.

[0125] As noted above, Figures 11A and 11B are provided as examples. Other examples may differ from those described with respect to Figures 11A and 11B.

[0126] Figure 12 is a flowchart of an exemplary process 1200 associated with the formation of a semiconductor device as described in this disclosure. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / wafer transfer tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 12.

[0127] As shown in FIG12, process 1200 may include forming a first plurality of nanostructure channel layers (block 1210) arranged in a direction generally perpendicular to the semiconductor substrate of the semiconductor device. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a first plurality of nanostructure channel layers (e.g., nanostructure channel 315b) arranged in a direction (e.g., z-direction) generally perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0128] As further shown in FIG12, process 1200 may include forming a second plurality of nanostructure channel layers (block 1220) arranged in a direction substantially perpendicular to the semiconductor substrate. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form the second plurality of nanostructure channel layers (e.g., nanostructure channel 315a) arranged in a direction substantially perpendicular to the semiconductor substrate.

[0129] As further shown in Figure 12, process 1200 may include forming a metal layer of a certain type surrounding each of the first plurality of nanostructure channel layers (block 1230). For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a first type of metal layer (e.g., p-type metal layer 725) surrounding each of the first plurality of nanostructure channel layers.

[0130] As further shown in Figure 12, process 1200 may include forming a self-assembled monolayer film on a first type of metal layer (block 1240). For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a self-assembled monolayer film on the first type of metal layer (e.g., self-assembled monolayer film 735).

[0131] As further shown in Figure 12, process 1200 may include forming a second type of metal layer (block 1250) on the second plurality of nanostructure channel layers. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form the second type of metal layer (e.g., n-type metal layer 750) on the second plurality of nanostructure channel layers. In some implementations, a self-assembled monolayer film suppresses the formation of the second type of metal layer on the first type of metal layer.

[0132] Process 1200 may include additional implementations, such as those described below and / or in combination with any single implementation or any combination of one or more other processes described elsewhere in this disclosure.

[0133] In the first implementation, forming a self-assembled monolayer includes: depositing a solution of material containing the self-assembled monolayer through spin coating, and performing a spin drying operation to solidify the solution to form the self-assembled monolayer.

[0134] In the second implementation, either alone or in combination with the first implementation, process 1200 includes: removing the self-assembled monolayer film after forming the second type of metal layer.

[0135] In the third implementation, either alone or in combination with one or more of the first and second implementations, after the self-assembled monolayer is removed, the residue of the self-assembled monolayer (e.g., self-assembled monolayer residue 755) remains on the first type of metal layer.

[0136] In the fourth implementation, removing the self-assembled monolayer membrane, either alone or in combination with one or more of the first to third implementations, includes performing a thermal decomposition operation on the self-assembled monolayer membrane to decompose the hydrocarbon chain of the self-assembled monolayer membrane.

[0137] In the fifth implementation, performing the thermal decomposition operation, either alone or in combination with one or more of the first to fourth implementations, includes heating the self-assembled monolayer film to a temperature ranging from about 300 degrees Celsius to about 500 degrees Celsius.

[0138] In the sixth implementation, removing the self-assembled monolayer membrane, either alone or in combination with one or more of the first to fifth implementations, includes performing a plasma treatment operation on the self-assembled monolayer membrane to remove it.

[0139] In the seventh implementation, forming a self-assembled monolayer membrane, either alone or in combination with one or more of the first to sixth implementations, includes forming the self-assembled monolayer membrane as a discontinuous thin film.

[0140] Although Figure 12 shows an example block for process 1200, in some implementations, process 1200 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently compared to those depicted in Figure 12. Alternatively, two or more blocks of process 1200 may be executed in parallel.

[0141] Figure 13 is a flowchart of an exemplary process 1300 associated with the formation of a semiconductor device as described in this disclosure. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / wafer transport tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 13.

[0142] As shown in FIG13, process 1300 may include forming a first plurality of nanostructure channel layers (block 1310) arranged in a direction generally perpendicular to the semiconductor substrate of the semiconductor device. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a first plurality of nanostructure channel layers (e.g., nanostructure channel 315b) arranged in a direction (z direction) generally perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0143] As further shown in FIG13, process 1300 may include forming a second plurality of nanostructure channel layers (block 1320) arranged in a direction substantially perpendicular to the semiconductor substrate. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form the second plurality of nanostructure channel layers (e.g., nanostructure channel 315a) arranged in a direction substantially perpendicular to the semiconductor substrate.

[0144] As further shown in Figure 13, process 1300 may include forming a p-type metal layer (block 1330) of a first gate structure on the first plurality of nanostructure channel layers. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a p-type metal layer (e.g., p-type metal layer 725) of a first gate structure (e.g., p-type gate structure 710b) on the first plurality of nanostructure channel layers.

[0145] As further shown in Figure 13, process 1300 may include depositing a solution onto a p-type metal layer (block 1340). For example, as described in this disclosure, one or more semiconductor processing tools may be used to deposit the solution onto the p-type metal layer. In some implementations, the solution comprises a material dissolved in a solvent.

[0146] As further shown in Figure 13, process 1300 may include: curing the solution to form a self-assembled monolayer containing the material on a p-type metal layer (block 1350). For example, as described in this disclosure, one or more semiconductor processing tools may be used to cure the solution to form a self-assembled monolayer containing the material on a p-type metal layer (e.g., self-assembled monolayer 735).

[0147] As further shown in Figure 13, process 1300 may include forming an n-type metal layer (block 1360) of a second gate structure on the second plurality of nanostructure channel layers. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form an n-type metal layer (e.g., n-type gate structure 710a) of a second gate structure (e.g., n-type gate structure 710a) on the second plurality of nanostructure channel layers. In some implementations, the material of the self-assembled monolayer includes side chain groups that suppress the adsorption of the n-type metal layer on the p-type metal layer (e.g., side chain group 745).

[0148] Process 1300 may include additional implementations, such as those described below and / or in combination with any single implementation or any combination of one or more other processes described elsewhere in this disclosure.

[0149] In the first implementation, the material of the self-assembled monolayer includes an anchoring base (e.g., anchoring base 740) that promotes the adsorption of the material of the self-assembled monolayer onto the p-type metal layer.

[0150] In the second implementation, alone or in combination with the first implementation, the anchoring group includes at least one of amino, thiol, carboxyl, carbonyl, trichlorosilane (SiCl3), or phosphonate.

[0151] In the third implementation, either alone or in combination with one or more of the first and second implementations, the side chain group comprises an aryl hydrocarbon chain.

[0152] In the fourth implementation, either alone or in combination with one or more of the first to third implementations, process 1300 includes: removing the self-assembled monolayer after forming the n-type metal layer, wherein, after removing the self-assembled monolayer, a self-assembled monolayer residue (e.g., self-assembled monolayer residue 755) remains on the p-type metal layer.

[0153] In the fifth implementation, either alone or in combination with one or more of the first to fourth implementations, the self-assembled monolayer membrane residue includes at least one of a sulfur (S) ligand, a silicon (Si) ligand, or a phosphorus (P) ligand.

[0154] In the sixth implementation, either alone or in combination with one or more of the first to fifth implementations, the thickness (e.g., dimension D1) of the self-assembled monolayer film residue is less than the thickness (e.g., dimension D2) of the n-type metal layer on the second plurality of nanostructured channel layers.

[0155] In the seventh implementation, the solvent, either alone or in combination with one or more of the first to sixth implementations, includes at least one of γ-butyrolactone (GBL), diethylmethylamine (DEF), propylene glycol methyl ether acetate (PGMEA), or propylene glycol methyl ether (PGME).

[0156] While Figure 13 shows an example block for process 1300, in some implementations, process 1300 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently compared to those depicted in Figure 13. Alternatively, two or more blocks of process 1300 may be executed in parallel.

[0157] Figures 14A to 14I are illustrations of an exemplary implementation 1400 of the work function metal layer for forming the gate structure of the nanostructured transistor as disclosed herein. Exemplary implementation 1400 includes examples of using different self-assembled monolayer films of an n-type gate structure 710a and a p-type gate structure 710b to suppress the growth of opposite metal layer types. For example, as described in conjunction with Figures 14A to 14I, a first self-assembled monolayer film can be formed on the n-type gate structure 710a to suppress the growth of a p-type metal layer 725 on the n-type gate structure 710a, and a second (different) self-assembled monolayer film can be formed on the p-type gate structure 710b to suppress the growth of an n-type metal layer 750 on the p-type gate structure 710b.

[0158] As shown in Figure 14A, the exemplary implementation 1400 includes forming a self-assembled monolayer film 1400 on the gate dielectric layer 720 of the n-type gate structure 710a and the gate dielectric layer 720 of the p-type gate structure 710b, as shown in Figure 14A. Therefore, in the exemplary implementation 1400, the self-assembled monolayer film 1405 includes one or more materials that promote the selective deposition of the self-assembled monolayer film 1405 on the gate dielectric layer 720. For example, the self-assembled monolayer film 1405 may include an anchoring base that promotes material adsorption to the gate dielectric layer 720.

[0159] In some implementations, the material of the self-assembled monolayer 1405 is resistant to the adsorption of precursors for the p-type metal layer 725 to be formed for the p-type gate structure 710b. For example, the material of the self-assembled monolayer 1405 may include side chain groups resistant to the adsorption of titanium nitride (TiN) precursors (e.g., titanium tetrachloride (TiCl₄) and / or ammonia (NH₃)). In this way, the self-assembled monolayer 1405 can be used to suppress the growth of the p-type metal layer 725 on the n-type metal gate structure 710a.

[0160] As shown in Figure 14B, a photomask layer 1410 is formed on the n-type gate structure 710a. The photomask layer 140 may include a photoresist layer formed using a deposition tool (e.g., a spin coating technique). Alternatively, the photomask layer 1410 may include another type of photomask layer and may be formed using another deposition technique.

[0161] As shown in Figure 14C, the self-assembled monolayer 1405 is removed from the p-type gate structure 710b, while the masking layer 1410 protects the self-assembled monolayer 1405 on the n-type gate structure 710a. In other words, the self-assembled monolayer 1405 is selectively removed from the p-type gate structure 710b, leaving the self-assembled monolayer 1405 on the n-type gate structure 710a. One or more techniques described in conjunction with Figure 7G can be used to remove the self-assembled monolayer 1405. In some implementations, another technique can be used to remove the self-assembled monolayer 1405.

[0162] As further shown in Figure 14D, the p-type metal layer 725 is selectively formed on the gate dielectric layer 720 of the nanostructure channel 315b, but not on the nanostructure channel 315, because the self-assembled monolayer 1405 blocks or inhibits the growth of the p-type metal layer 725 on the nanostructure channel 315a (e.g., on which the n-type metal layer 750 is formed).

[0163] Using a self-assembled monolayer film 1405 to form a p-type metal layer 725 on the nanostructure channel 315b instead of on the nanostructure channel 315 allows the p-type metal layer 725 to be selectively formed on the nanostructure channel 315b without the need for subsequent patterning and etching steps to remove the p-type metal layer 725 from the nanostructure channel 315a, which would otherwise require forming a mask layer over the p-type metal layer 725 on the nanostructure channel 315b and etching the p-type metal layer 725 on the nanostructure channel 315a. This prevents residual material of the p-type metal layer 725 from remaining on the nanostructure channel 315a. Otherwise, residual material of the p-type metal layer 725 might remain on the nanostructure channel 315a because the p-type metal layer 725 was not completely removed from the nanostructure channel 315b.

[0164] The self-assembled monolayer 1405 allows the p-type metal layer 725 to be selectively formed on the nanostructure channel 315b because the material of the self-assembled monolayer 1405 and the monolayer structure inhibit the adsorption of precursors of the p-type metal layer 725 onto the surface of the gate dielectric layer 720 on the nanostructure channel 315a. For example, the material of the self-assembled monolayer 1405 inhibits the adsorption of precursors such as titanium tetrachloride (TiCl₄) and / or ammonia (NH₃), which can adsorb onto the surface of the gate dielectric layer 720 on the nanostructure channel 315b and react to form titanium nitride (TiN) of the p-type metal layer 725. In particular, the chemical incompatibility between the side chain groups of the material of the self-assembled monolayer 1405 and the precursors of the p-type metal layer 725, alone or in combination with the surface barrier provided by the dense molecular monolayer structure of the self-assembled monolayer 1405, can inhibit the adsorption of precursors of the p-type metal layer 725.

[0165] As shown in Figure 14E, after forming a p-type metal layer 725 on the gate dielectric layer 720 of the p-type gate structure 710b, the self-assembled monolayer 1405 is removed from the n-type gate structure 710a. One or more techniques described in conjunction with Figure 7G can be used to remove the self-assembled monolayer 1405. In some implementations, another technique can be used to remove the self-assembled monolayer 1405.

[0166] As shown in Figure 14F, a self-assembled monolayer 735 is formed on the p-type metal layer 725 of the p-type gate structure 710b. The self-assembled monolayer 735 may comprise a material different from that of the self-assembled monolayer 1405. This allows the self-assembled monolayer 735 to be selectively deposited on the p-type metal layer 725, while little or no self-assembled monolayer 735 is deposited on the gate dielectric layer 720 of the n-type gate structure 710a. Furthermore, the material of the self-assembled monolayer 735 can be resistant to the adsorption of precursors for the n-type metal layer 750 to be formed for the n-type gate structure 710a. For example, the material of the self-assembled monolayer 735 can be resistant to the adsorption of titanium aluminum carbon (TiAlC) precursors (e.g., titanium tetrachloride (TiCl₄) and / or triethylaluminum (Al₂(C₂H₅)₆ or TEA), one or more of the materials depicted in Figure 7E.

[0167] As shown in Figure 14G, after a self-assembled monolayer 735 is formed on the p-type metal layer 725 of the p-type gate structure 710b, an n-type metal layer 750 is formed on the n-type gate structure 710a. The self-assembled monolayer 735 on the p-type metal layer 725 blocks or inhibits the formation of the n-type metal layer 750 on the p-type metal layer 725. Therefore, the self-assembled monolayer 735 allows the n-type metal layer 750 to be selectively deposited on the gate dielectric layer 720 on the nanostructure channel 315a. The n-type metal layer 750 can be formed as described in conjunction with Figure 7F.

[0168] As shown in Figure 14H, after the formation of the n-type metal layer 750, the self-assembled monolayer 735 can then be removed. For example, one or more techniques described in conjunction with Figure 7G can be used to completely or partially remove the self-assembled monolayer 735.

[0169] As shown in Figure 14I, a gate electrode layer 760 of an n-type gate structure 710a is formed on an n-type metal layer 750, and a gate electrode layer 760 of a p-type gate structure 710b is formed on a p-type metal layer 725. The gate electrode layer 760 can be formed in a similar manner to that described above in conjunction with Figure 7H.

[0170] As noted above, Figures 14A to 14I are provided as examples. Other examples may differ from those described with respect to Figures 14A to 14I.

[0171] Figure 15 is a flowchart of an exemplary process 1500 associated with the formation of a semiconductor device as described in this disclosure. In some implementations, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / wafer transfer tools, and / or another type of semiconductor processing tool) are used to perform one or more process blocks of Figure 15.

[0172] As shown in Figure 15, process 1500 may include forming a first plurality of nanostructure channel layers (block 1510) arranged in a direction generally perpendicular to the semiconductor substrate of the semiconductor device. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a first plurality of nanostructure channel layers (e.g., nanostructure channel 315b) arranged in a direction (z-direction) generally perpendicular to the semiconductor substrate (e.g., semiconductor substrate 110) of the semiconductor device (e.g., semiconductor device 105).

[0173] As further shown in FIG15, process 1500 may include forming a second plurality of nanostructure channel layers (block 1520) arranged in a direction substantially perpendicular to the semiconductor substrate. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form the second plurality of nanostructure channel layers (e.g., nanostructure channel 315a) arranged in a direction substantially perpendicular to the semiconductor substrate.

[0174] As further shown in Figure 15, process 1500 may include forming a gate dielectric layer (block 1530) surrounding the first plurality of nanostructure channel layers and the second plurality of nanostructure channel layers. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a gate dielectric layer (e.g., gate dielectric layer 720) surrounding the first plurality of nanostructure channel layers and the second plurality of nanostructure channel layers.

[0175] As further shown in Figure 15, process 1500 may include forming a self-assembled monolayer film (block 1540) on the gate dielectric layer surrounding the second plurality of nanostructure channel layers. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a self-assembled monolayer film (e.g., self-assembled monolayer film 1405) on the gate dielectric layer surrounding the second plurality of nanostructure channel layers.

[0176] As further shown in Figure 15, process 1500 may include forming a p-type metal layer (block 1550) of a first gate structure on the first plurality of nanostructure channel layers. For example, as described in this disclosure, one or more semiconductor processing tools may be used to form a p-type metal layer (e.g., p-type metal layer 725) of a first gate structure (e.g., p-type gate structure 710b) on the first plurality of nanostructure channel layers. In some implementations, the material of the self-assembled monolayer film inhibits the p-type metal layer from adsorbing onto the gate dielectric layer surrounding the second plurality of nanostructure channel layers.

[0177] As further shown in Figure 15, process 1500 may include: after forming a p-type metal layer, forming an n-type metal layer with a second gate structure on the second plurality of nanostructure channel layers (block 1560). For example, as described in this disclosure, one or more semiconductor processing tools may be used to form an n-type metal layer (e.g., n-type gate structure 710a) with a second gate structure (e.g., n-type metal layer 750) on the second plurality of nanostructure channel layers after forming a p-type metal layer.

[0178] Process 1500 may include additional implementations, such as those described below and / or in combination with any single implementation or any combination of one or more other processes described elsewhere in this disclosure.

[0179] In the first implementation, the self-assembled monolayer is a first self-assembled monolayer, and process 1500 includes: depositing a solution onto a p-type metal layer on a first plurality of nanostructure channels before forming an n-type metal layer, wherein the solution includes a material dissolved in a solvent, and curing the solution to form a second self-assembled monolayer containing the material on the p-type metal layer (e.g., self-assembled monolayer 735), wherein the material of the second self-assembled monolayer includes side chain groups that inhibit the adsorption of the n-type metal layer onto the p-type metal layer (e.g., side chain group 745).

[0180] In the second implementation, alone or in combination with the first implementation, the material of the self-assembled monolayer includes an anchoring group (e.g., anchoring group 740) that promotes the adsorption of the material of the self-assembled monolayer onto the p-type metal layer, wherein the anchoring group includes at least one of amino, thiol, carboxyl, carbonyl, trichlorosilane (SiCl3) or phosphonate.

[0181] In the third implementation, either alone or in combination with one or more of the first and second implementations, process 1500 includes: removing the second self-assembled monolayer after forming the n-type metal layer, wherein, after removing the second self-assembled monolayer, a self-assembled monolayer residue (e.g., self-assembled monolayer residue 755) is retained on the p-type metal layer, wherein the second self-assembled monolayer residue includes at least one of a sulfur (S) ligand, a silicon (Si) ligand, or a phosphorus (P) ligand.

[0182] In the fourth implementation, the solvent, alone or in combination with one or more of the first to third implementations, includes at least one of γ-butyrolactone (GBL), diethylmethylamine (DEF), propylene glycol methyl ether acetate (PGMEA), or propylene glycol methyl ether (PGME).

[0183] In the fifth implementation, either alone or in combination with one or more of the first to fourth implementations, process 1500 includes: removing a self-assembled monolayer film from the gate dielectric layer surrounding the second plurality of nanostructured channel layers before forming an n-type gate electrode structure on the second plurality of nanostructured channel layers.

[0184] In the sixth implementation, either alone or in combination with one or more of the first to fifth implementations, the self-assembled monolayer includes a material that promotes the adsorption of the self-assembled monolayer onto the gate dielectric layer and inhibits the adsorption of the precursor of the p-type metal layer onto the gate dielectric layer.

[0185] In the seventh implementation, forming a self-assembled monolayer film on the gate dielectric layer surrounding the second plurality of nanostructure channel layers, either alone or in combination with one or more of the first to sixth implementations, includes: forming a self-assembled monolayer film on the gate dielectric layer surrounding the second plurality of nanostructure channel layers and surrounding the first plurality of nanostructure channel layers; forming a mask layer (e.g., photomask 1410) over the second plurality of nanostructure channel layers; and removing the self-assembled monolayer film from the first plurality of nanostructure channel layers while the mask layer prevents the self-assembled monolayer film from being removed from the second plurality of nanostructure channel layers.

[0186] While Figure 15 shows an example block for process 1500, in some implementations, process 1500 includes additional blocks, fewer blocks, different blocks, or blocks arranged differently compared to those depicted in Figure 15. Alternatively, two or more blocks of process 1500 may be executed in parallel.

[0187] In this manner, the technique described in this disclosure includes forming various types of gate metals for PMOS nanostructure transistors while maintaining the intrinsic NMOS nanostructure transistor of the semiconductor device. A p-type gate metal can be formed around the nanostructure channels of the PMOS nanostructure transistor. A self-assembled monolayer can then be formed on the surface of the p-type gate metal layer. During the formation of the n-type gate metal around the nanostructure channels of the NMOS nanostructure transistor, the self-assembled monolayer on the p-type gate metal prevents the formation of the n-type gate metal on the p-type gate metal. This results in almost no n-type gate metal deposition on the p-type gate metal, minimizing the impact of the p-type threshold voltage (PVt) on the PMOS nanostructure transistor. In this manner, the technique described in this disclosure allows the work function of both the NMOS and PMOS nanostructure transistors to be tuned to achieve the desired threshold voltage of both. This enables low current leakage for both NMOS and PMOS nanostructure transistors, and also enables high operating efficiency for both NMOS and PMOS nanostructure transistors.

[0188] As described in more detail above, some implementations of this disclosure provide a method. This method includes: forming a first plurality of nanostructure channel layers arranged along a direction substantially perpendicular to a semiconductor substrate of a semiconductor device. This method includes: forming a second plurality of nanostructure channel layers arranged along the direction substantially perpendicular to the semiconductor substrate. This method includes: forming a metal layer of each type surrounding the first plurality of nanostructure channel layers; this method includes: forming a self-assembled monolayer film on the first type of metal layer. This method includes: forming a second type of metal layer on the second plurality of nanostructure channel layers, wherein the self-assembled monolayer film inhibits the formation of the second type of metal layer on the first type of metal layer.

[0189] As described in more detail above, some implementations of this disclosure provide a method. This method includes: forming a first plurality of nanostructured channel layers arranged along a direction generally perpendicular to a semiconductor substrate of a semiconductor device. This method includes: forming a second plurality of nanostructured channel layers arranged along a direction generally perpendicular to the semiconductor substrate. This method includes: forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers. This method includes: depositing a solution onto the p-type metal layer, wherein the solution includes a material dissolved in a solvent. This method includes: curing the solution to form a self-assembled monolayer film comprising the material on the p-type metal layer. This method includes: forming an n-type metal layer of a second gate structure on the second plurality of nanostructured channel layers, wherein the material of the self-assembled monolayer film includes side chain groups that inhibit adsorption of the n-type metal layer onto the p-type metal layer.

[0190] As described in more detail above, some implementations of this disclosure provide a method. This method includes: forming a first plurality of nanostructured channel layers arranged along a direction generally perpendicular to a semiconductor substrate of a semiconductor device. This method includes: forming a second plurality of nanostructured channel layers arranged along a direction generally perpendicular to the semiconductor substrate. This method includes: forming a gate dielectric layer around the first plurality of nanostructured channel layers and the second plurality of nanostructured channel layers. This method includes: forming a self-assembled monolayer film on the gate dielectric layer surrounding the second plurality of nanostructured channel layers. This method includes: forming a p-type metal layer of a first gate structure on the first plurality of nanostructured channel layers, wherein the material of the self-assembled monolayer film inhibits the p-type metal layer from adsorbing onto the gate dielectric layer surrounding the second plurality of nanostructured channel layers. This method includes: after forming the p-type metal layer, forming an n-type metal layer of a second gate structure on the second plurality of nanostructured channel layers.

[0191] As described in more detail above, some implementations described in this disclosure provide a semiconductor device. This semiconductor device includes a first plurality of nanostructured channel layers arranged along a direction generally perpendicular to a semiconductor substrate. This semiconductor device includes a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers, arranged along the direction generally perpendicular to the semiconductor substrate. This semiconductor device includes a first gate structure surrounding the first plurality of nanostructured channel layers and including: a p-type metal layer; and a residue located on the p-type metal layer, the residue including at least one ligand selected from sulfur (S), silicon (Si), or phosphorus (P). This semiconductor device includes a second gate structure surrounding each of the second plurality of nanostructured channel layers and including an n-type metal layer.

[0192] The terms "about" and "substantially" can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not intended to be limiting. It should be understood that, according to this disclosure, the terms "about" and "substantially" can refer to a percentage of the value of a given quantity.

[0193] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described in this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and they can make various changes, substitutions, and modifications to this disclosure without departing from its spirit and scope.

[0194] 100: Example Implementation 105: Semiconductor Devices 110: Semiconductor substrate 115: Layer stacking 120: Sacrificial Nanostructure Layer 125: Nanostructured Channel Layer 130: Mask layer 135: Cap layer 140: Oxide layer 145: Nitride layer 150: Fin Structure 150a: Fin structure of the first subgroup 150b: Fin structure of the second subgroup 155: Part 160: Fin section 165: Lining 170: STI region 200: Example Implementation 205: Virtual gate structure 210: Gate electrode layer 215: Hard mask layer 220: Spacer layer 225: Gate dielectric layer 300: Example Implementation 305: Source / Drain recess 310: Platform Area 310a: Platform Area 310b: Platform Area 315: Nanostructured Channel 315a: Nanostructured Channel 315b: Nanostructured Channel 400: Example Implementation 405: Cavity 410: Internal spacers 500: Example Implementation 505: Buffer Area 510: Source / Drain Region 515: Cap Layer 600: Example Implementation 605: Dielectric layer 700: Example Implementation 705: Opening 710a:n-type gate structure 710b: P-type gate structure 715: Interface Layer 720: Gate dielectric layer 725: p-type metal layer 730: Photoresist layer 735: Self-assembled monolayer membrane 740: Anchoring base 745: Side chain group 750: n-type metal layer 755: Self-assembled monolayer membrane residue 760: Gate electrode layer 800: Example 805: Aluminum Concentration 810: Aluminum concentration 815: Strength 820: Depth 900: Example 905: Elemental Composition 910: Concentration 915: In-depth 920: Residual components of self-assembled monolayer membranes 925: n-type metal layer residue composition 1000: Example Implementation 1005: Seam 1010: Example Implementation 1015: Example Implementation 1020: Example Implementation 1025: Adhesive layer 1100: Example Implementation 1105: Self-assembled monolayer membrane 1110: p-type metal layer 1200: Exemplary Manufacturing Process 1210: Square 1220: Square 1230: Square 1240: Square 1250: Square 1300: Process 1310: Square 1320: Square 1330: Square 1340: Square 1350: Square 1360: Square 1400: Example Implementation 1405: Self-assembled monolayer membrane 1410: Photomask layer 1500: Process 1510: Square 1520: Square 1530: Square 1540: Square 1550: Square 1560: Square

Claims

1. A method of forming a semiconductor device, comprising: forming a first plurality of nanostructure channel layers arranged along a direction perpendicular to a semiconductor substrate of the semiconductor device; forming a second plurality of nanostructure channel layers arranged along the direction perpendicular to the semiconductor substrate; forming a first type metal layer surrounding each of the first plurality of nanostructure channel layers; forming a self-assembled monolayer film on the first type metal layer; and forming a second type metal layer on the second plurality of nanostructure channel layers, wherein the self-assembled monolayer film inhibits the formation of the second type metal layer on the first type metal layer.

2. The method of claim 1, wherein forming the self-assembled monolayer comprises: depositing a solution of a material comprising the self-assembled monolayer by spin coating; and performing a spin drying operation to cure the solution to form the self-assembled monolayer.

3. The method of claim 1, further comprising: removing the self-assembled monolayer after forming the second type of metal layer.

4. The method as described in claim 3, wherein after the self-assembled monolayer is removed, a residue of the self-assembled monolayer remains on the first type of metal layer.

5. The method as claimed in claim 3, wherein removing the self-assembled monolayer comprises: performing a thermal decomposition operation on the self-assembled monolayer to decompose the hydrocarbon chains of the self-assembled monolayer.

6. The method as claimed in claim 5, wherein performing the thermal decomposition operation comprises: heating the self-assembled monolayer film to a temperature ranging from about 300 degrees Celsius to about 500 degrees Celsius.

7. The method as described in request item 3, wherein, Removing the self-assembled monolayer membrane includes performing a plasma treatment operation on the self-assembled monolayer membrane to remove it.

8. The method of claim 1, wherein forming the self-assembled monolayer comprises: forming the self-assembled monolayer as a discontinuous thin film.

9. A method for forming a semiconductor device, comprising: Forming a first plurality of nanostructured channel layers arranged along a direction perpendicular to a semiconductor substrate of a semiconductor device; A second plurality of nanostructure channel layers are formed along a direction perpendicular to the semiconductor substrate; a gate dielectric layer is formed surrounding the first plurality of nanostructure channel layers and the second plurality of nanostructure channel layers; a self-assembled monolayer film is formed on the gate dielectric layer surrounding the second plurality of nanostructure channel layers; a p-type metal layer with a first gate structure is formed on the first plurality of nanostructure channel layers, wherein the material of the self-assembled monolayer film inhibits the p-type metal layer from adsorbing onto the gate dielectric layer surrounding the second plurality of nanostructure channel layers; and after forming the p-type metal layer, an n-type metal layer with a second gate structure is formed on the second plurality of nanostructure channel layers.

10. A semiconductor device comprising: a first plurality of nanostructured channel layers arranged along a direction perpendicular to a semiconductor substrate of the semiconductor device; a second plurality of nanostructured channel layers adjacent to the first plurality of nanostructured channel layers and arranged along the direction perpendicular to the semiconductor substrate; a first gate structure surrounding the first plurality of nanostructured channel layers, the first gate structure comprising: a p-type metal layer; and a self-assembled monolayer film residue located on the p-type metal layer, the self-assembled monolayer film residue comprising a ligand of at least one of the following: sulfur (S), silicon (SI), or phosphorus (P); and a second gate structure surrounding each of the second plurality of nanostructured channel layers, the second gate structure comprising an n-type metal layer.

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