Non-volatile memory including a depletion layer with nanocrystals

Abstract

A memory element may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent to the first well having a second conductivity type and defining a depletion layer therebetween with respect to the first well, and a plurality of nanocrystals within the depletion layer, each nanocrystal comprising a semiconductor material and carbon. The memory element may further include a spaced source region and a drain region adjacent to the second well, defining a channel between them, and a gate covering the channel.

Description

Non-volatile memory containing a vacancy layer with nanocrystals This disclosure generally relates to semiconductor devices, and more specifically to semiconductor memory devices and related methods. Numerous structures and techniques have been proposed to improve the performance of semiconductor devices by enhancing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon, which also include impurity-free zones that would otherwise degrade performance in other ways. The biaxial strain created by these strained material layers in the upper silicon layer alters carrier mobility, thereby enabling the fabrication of higher-speed and / or lower-power devices. U.S. Patent Application Publication No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter based on a similar strained silicon technique. U.S. Patent No. 6,472,685 B2, granted to Takagi, discloses a semiconductor device comprising a silicon and carbon layer sandwiched between silicon layers, such that the conduction and valence bands of the second silicon layer are subjected to tensile strain. In this way, electrons with a smaller effective mass, induced by the electric field applied to the gate, are confined within the second silicon layer, thus indicating that its N-channel MOSFET has high mobility. U.S. Patent No. 4,937,204, granted to Ishibashi et al., discloses a superlattice comprising a plurality of layers, fewer than eight monolayers, each containing a fractional or binary semiconductor layer or a binary compound semiconductor layer, wherein the plurality of layers are alternately grown epitaxially. The main current direction is perpendicular to each layer of the superlattice. U.S. Patent No. 5,357,119 to Wang et al. discloses a silicon-germanium short-period superlattice that achieves higher mobility by reducing alloy scattering in the superlattice. Based on a similar principle, U.S. Patent No. 5,683,934 to Candelaria discloses a MOSFET with improved mobility comprising a channel layer comprising an alloy of silicon and a second material, wherein the second material is present in a percentage of the silicon lattice to subject the channel layer to tensile stress. U.S. Patent No. 5,216,262, granted to Tsu, discloses a quantum well structure comprising two barrier regions and an epitaxially grown semiconductor thin layer sandwiched between them. Each barrier region consists of approximately two to six alternating SiO2 / Si monolayers with a thickness ranging from one to the other. The barrier regions are further sandwiched by a much thicker silicon segment. In an article titled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in *Applied Physics and Materials Science & Processing* (pp. 391–402), Tsu revealed a silicon / oxygen semiconductor-atomic superlattice (SAS). This silicon / oxygen superlattice structure was shown to be useful for silicon quantum and light-emitting devices. Specifically, it revealed how to fabricate and test a green electroluminescence diode structure. The current flow direction in this diode structure is vertical, that is, perpendicular to the SAS layers. The SAS revealed in this article can comprise semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. The silicon grown outside the adsorbed oxygen monolayer is described as an epitaxial layer with a relatively low defect density. One of the SAS structures comprises a 1.1 nm thick silicon portion, approximately eight atomic layers thick, while the silicon portion of another structure is twice that thickness. In a paper titled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002), Luo et al. further discussed Tsu's luminescent SAS structure. U.S. Patent No. 7,105,895 to Wang et al. discloses a thin silicon barrier structure with oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, which can reduce the current flowing perpendicularly through the lattice by more than four orders of magnitude. Its insulating / barrier layer allows low-defect epitaxial silicon to be deposited adjacent to the insulating layer. British Patent Application No. 2,347,520 by Mears et al., which has been published, discloses that aperiodic photonic bandgap (APBG) structures can be applied to electronic bandgap engineering. Specifically, the application reveals that material parameters, such as the location of band minimums and effective mass, can be adjusted to obtain new aperiodic materials with the desired bandgap structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric or magnetic permeability, are also disclosed as potentially being designed into the material. In addition, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for fabricating an insulating or barrier layer for semiconductor devices, comprising depositing a layer of silicon and at least one other element on a silicon substrate such that the deposited layer is substantially defect-free, thereby allowing substantially defect-free epitaxial silicon to be deposited on the deposited layer. Alternatively, a monolayer may consist of one or more elements, preferably including oxygen, which is absorbed on the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon form a barrier complex. Despite the existence of the aforementioned methods, we hope to further enhance the use of advanced semiconductor materials and processing technologies in order to improve the performance of semiconductor devices. A memory element may include a semiconductor substrate and an array of memory cells on the semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent to the first well having a second conductivity type and defining a depletion layer therebetween with respect to the first well, and a plurality of nanocrystals within the depletion layer, each nanocrystal comprising a semiconductor material and carbon. The memory element may further include a spaced source region and a drain region adjacent to the second well, defining a channel between them, and a gate covering the channel. In one example embodiment, the plurality of nanocrystals may be confined within a lattice of one of adjacent semiconductor portions. Also in an example embodiment, the plurality of nanocrystals may be laterally spaced and arranged in vertically spaced rows. Each memory cell also includes a body contact region coupled to the first well. As an example, each nanocrystal may include silicon and carbon. In one example, the memory cells may include non-volatile memory cells. The memory element may further include a corresponding shallow trench isolation (STI) region adjacent to the source region and the drain region and extending into the first well. In one example embodiment, the first conductivity type may include n-type, and the second conductivity type may include p-type. The memory cell may also include a plurality of word lines and bit lines connecting the array of memory cells. A method for manufacturing a memory element may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well in the semiconductor substrate having a first conductivity type, a second well adjacent to the first well having a second conductivity type and defining a depletion layer therebetween with respect to the first well, and a plurality of nanocrystals within the depletion layer, each nanocrystal comprising a semiconductor material and carbon. The memory element may further include a spaced source region and a drain region adjacent to the second well, defining a channel between them, and a gate covering the channel. In one example embodiment, the plurality of nanocrystals may be confined within a lattice of one of adjacent semiconductor portions. Also in an example embodiment, the plurality of nanocrystals may be laterally spaced and arranged in vertically spaced rows. The method further includes forming each memory cell and also includes forming a corresponding substrate contact region coupled to a first well of each memory cell. As an example, each nanocrystal may include silicon and carbon. In one example, the memory cells may include non-volatile memory cells. The method may further include forming a corresponding shallow trench isolation (STI) region adjacent to the source region and the drain region and extending into the first well. In an example embodiment, the first conductivity type may include n-type, and the second conductivity type may include p-type. The method may also include forming a plurality of word lines and bit lines connecting the memory cell array. The exemplary embodiments are described in detail with reference to the accompanying drawings, which are exemplary embodiments. However, embodiments may be implemented in many different forms and should not be construed as limited to the specific examples provided in this specification. Rather, these embodiments are provided only to make the invention disclosed herein more complete and exhaustive. Throughout this specification and the drawings, the same reference numerals refer to the same elements, and apostrophes (') are used to identify similar elements in different embodiments. Generally speaking, this disclosure relates to semiconductor devices that incorporate an enhanced semiconductor superlattice to provide better performance. In this disclosure, the enhanced semiconductor superlattice may also be referred to as an MST layer or "MST technology". In detail, MST technology involves advanced semiconductor materials, such as the superlattice 25, which will be further described below. In previous literature, the applicant has argued that the superlattice structure described in this specification can reduce the effective mass of charge carriers, thereby increasing charge carrier mobility. For example, please refer to U.S. Patent No. 6,897,472, the entire contents of which are incorporated herein by reference. The applicant's further development has confirmed that the presence of the MST layer can advantageously improve the mobility of free carriers in semiconductor materials, such as silicon and insulators (e.g., SiO2). 2 or HfO 2) The interface between them. The applicant's theory (but the applicant does not wish to be bound by this theory) suggests that this may occur through various mechanisms. One mechanism is to reduce the concentration of charged impurities near the interface, thereby reducing the diffusion of these impurities and / or trapping them to prevent them from reaching the vicinity of the interface. Charged impurities cause Coulomb scattering, which in turn reduces mobility. Another mechanism is to improve interface quality. For example, oxygen released from the MST film can flow into Si-SiO. The interface provides oxygen, thereby reducing substoichiometric SiO₂. x The presence of [something]. Alternatively, the trapping of interstitials by the MST layer can reduce the Si-SiO [something]. The interstitial silicon concentration near the interface is reduced, thereby decreasing the formation of substoichiometric SiO₂. x The trend. It is known in Si-SiO Secondary stoichiometry of SiO2 at the interface x Relative to stoichiometry SiO 2 exhibits poor insulation properties. Reducing the secondary stoichiometry at the interface (SiO2) x The amount of [material] can more effectively confine free carriers (electrons or holes) within silicon, thereby increasing the mobility of these carriers under the influence of an electric field parallel to the interface. This is the standard practice in field-effect transistor (FET) structures. Scattering caused by the direct influence of the interface is called "surface-roughness scattering," which can be advantageously reduced by the presence of adjacent MST layers after tempering or during thermal oxidation. In addition to their superior mobility, these MST structures are also designed to provide piezoelectric, pyroelectric, and / or ferroelectric properties that are beneficial for various types of components, which will be discussed further below. Referring to Figures 1 and 2, the material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 comprises a plurality of stacked layer groups 45a-45n, as shown in the schematic cross-sectional view of Figure 1. As shown in the figure, each layer group 45a-45n of the superlattice 25 comprises a plurality of stacked substrate semiconductor monolayers 46 (which define individual substrate semiconductor portions 46a-46n) and a non-semiconductor monolayer 50 thereon. For clarity, the non-semiconductor monolayer 50 is represented by speckles in Figure 1. As shown in the figure, the non-semiconductor monolayer 50 comprises a non-semiconductor monolayer confined within a lattice of an adjacent substrate semiconductor portion. The phrase "confined within a lattice of an adjacent substrate semiconductor portion" refers to at least some semiconductor atoms from the opposing substrate semiconductor portions 46a-46n being chemically bonded together through the non-semiconductor monolayer 50 between these opposing substrate semiconductor portions, as shown in Figure 2. Generally, this configuration can be made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n using atomic layer deposition (ALD) technology. This ensures that the available semiconductor bonding sites are not completely (i.e., not fully or less than 100%) occupied by bonds to non-semiconductor atoms, as will be discussed further below. Therefore, when more semiconductor material monolayer 46 is deposited on or above a non-semiconductor monolayer 50, the newly deposited semiconductor atoms can fill the remaining unoccupied semiconductor atom bonding sites below the non-semiconductor monolayer. In other embodiments, it is possible to use more than one such non-semiconductor monolayer. It should be noted that when this specification refers to a non-semiconductor monolayer or a semiconductor monolayer, it means that the material used in the monolayer, if formed in a bulk form, would be either non-semiconductor or semiconductor. That is, the properties exhibited by a single monolayer of a material (e.g., silicon) are not necessarily the same as those exhibited when formed in a bulk form or a relatively thick layer, as will be understood by those skilled in the art. The applicant's theory (but not to be bound by it) suggests that the non-semiconductor monolayer 50 and the adjacent substrate semiconductor portions 46a-46n enable the superlattice 25 to possess an effective mass with appropriately low charge carrier conductivity in the direction parallel to the layers. In other words, this parallel direction is orthogonal to the stacking direction. The non-semiconductor monolayer 50 also enables the superlattice 25 to have a general band structure, while advantageously functioning as an insulator between multiple layers or regions vertically above and below the superlattice. Furthermore, this superlattice structure can also advantageously act as a barrier against the diffusion of dopants and / or materials between multiple layers vertically above and below the superlattice 25. Therefore, these characteristics advantageously allow the superlattice 25 to provide an interface for high-k dielectrics, which not only reduces the diffusion of high-k materials into the channel region but also advantageously reduces unwanted scattering effects and improves device mobility, as will be understood by those skilled in the art to which this invention pertains. The theory of this invention also holds that semiconductor devices incorporating superlattice 25 can enjoy higher charge carrier mobility due to their lower effective conductivity mass. In some embodiments, due to the band engineering achieved by these embodiments, the superlattice 25 can further have a substantially direct band gap, which is particularly advantageous for devices such as optoelectronic devices. As shown in the figure, the superlattice 25 may also include a capping layer 52 above an upper layer group 45n. The capping layer 52 may include a plurality of substrate semiconductor monolayers 46. The capping layer 52 may include 2 to 100 monolayers of substrate semiconductors, preferably 10 to 50 monolayers. Each substrate semiconductor portion 46a-46n may include one selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, group IV semiconductors also include group IV-IV semiconductors, as will be understood by those skilled in the art. More specifically, the substrate semiconductor may include, for example, at least one of silicon and germanium. Each non-semiconductor monolayer 50 may comprise one non-semiconductor selected from, for example, the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor preferably also possesses the property of remaining thermally stable during the deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art. More specifically, the substrate semiconductor may comprise, for example, at least one of silicon and germanium. It should be noted that the term "monolayer" here refers to a single atomic layer or a single molecular layer. It should also be noted that the non-semiconductor monolayer 50 provided by a single monolayer should also include monolayers where all possible positions are not fully occupied (i.e., incomplete or less than 100% coverage). For example, referring to the atomic diagram of Figure 2, which presents a 4 / 1 repeating structure with silicon as the substrate semiconductor material and oxygen as one of the bandgap modifiers, only half of the possible positions for oxygen atoms are occupied. In other embodiments and / or when using different materials, the occupancy is not necessarily half-full, as those skilled in the art will understand. In fact, those skilled in atomic deposition will understand that, even in this schematic diagram, it can be seen that in a given monolayer, individual oxygen atoms are not precisely aligned along a flat plane. For example, a preferred occupancy is one-eighth to one-half of the possible oxygen positions being filled, but other occupancy ranges may be used in certain embodiments. Since silicon and oxygen are currently widely used in general semiconductor manufacturing processes, manufacturers will be able to immediately apply the materials described in this specification. Atomic deposition or monolayer deposition are also widely used techniques. Therefore, semiconductor devices incorporating the superlattice 25 of the embodiments described herein can be readily adopted and implemented, as will be understood by those skilled in the art to which this invention pertains. Another embodiment of the superlattice 25' with different properties according to the present invention will be described with reference to FIG. 3. In this embodiment, the repeating pattern is 3 / 1 / 5 / 1. More specifically, the bottommost substrate semiconductor portion 46a' has three monolayers, and the second bottom substrate semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. Each non-semiconductor monolayer 50' may contain a single monolayer. For this silicon / oxygen superlattice 25', the increase in charge carrier mobility is independent of the orientation of the planes of these layers. Other elements in FIG. 3 not mentioned here are similar to those discussed above with reference to FIG. 1, and will not be discussed again. In some implementations, each substrate semiconductor portion of the superlattice may have the same number of monolayers of thickness. In other implementations, at least some substrate semiconductor portions of the superlattice may have different numbers of monolayers of thickness. In still other implementations, each substrate semiconductor portion of the superlattice may have different numbers of monolayers of thickness. Referring now to Figures 4 and 5A, an exemplary nonvolatile random access memory (NVRAM) cell 100 and associated NVRAM element 101 are first described. Generally, in memory cell 100, NWELL / PWELL are encapsulated and isolated within PWELL / NWELL, with a depletion layer at the junction between the two wells, which utilizes an MST film for charge trapping. More specifically, in memory element 101, a plurality of memory cells 100 are formed on a semiconductor substrate 102 and electrically coupled to word lines 103 and bit lines 104 in an array. Each memory cell 100, as shown, includes a first well 105 located on the semiconductor substrate 102, having a first conductivity type, n-type in the example of Figure 4, which defines an NWELL (but may be a PWELL in other embodiments). The second well 106 is adjacent to the first well 105 (here above the first well) and has a second conductivity type (here p-type, defining a PWELL, but in other embodiments it could be an NWELL). More specifically, in the illustrated configuration, the second well 106 is surrounded by the first well 105. Furthermore, the second well 106 and the first well 105 define a depletion layer 107. The superlattice 125 described above is located within the depletion layer 107. More specifically, trap source atoms (e.g., fluorine, sulfur, or selenium) are also located within the stacked group of superlattice 125. Each memory cell 100 further includes, as shown, spaced source and drain regions 108, 109 adjacent to (here within) the second well 106, defining a channel 110 between them. A gate 111 (which may include a gate dielectric and gate electrode not shown) covers the channel 110 on the PWELL 106. The memory element 100 also includes, as shown, a substrate contact region 112 coupled to a first well 105, and a shallow trench isolation (STI) region 113 adjacent to the source region, drain region and substrate regions 108, 109, 112 and extending into the first well below the superlattice 125. The MST superlattice thin film 125 provides a technical advantage by allowing buried traps in the depletion layer 107 to capture electrons / holes for easier read and clear operations. The depletion layer 107 is designed to be located above the bottom of the STI region 113, which provides a further technical advantage by preventing write and clear interference to other memory cells 100 during programming and clear operations. The programming of a given memory cell within memory element 101 is now described with reference to Figures 5B-5D. The programmed cell 100 is shown in Figure 5B, an unprogrammed cell in the same column as the programmed cell is shown in Figure 5C, and an unprogrammed cell in a different column is shown in Figure 5D. Each corresponding voltage level applied to the contacts of source 108, drain 109, gate 111, and base 112 to perform these operations is illustrated in Figures 5A-5D. Generally, the contacts of source 108, drain 109, and gate 111 are coupled to ground (GND), and the contacts of base 112 are coupled to a write voltage (+V). WRITE A high reverse body bias is applied. This causes an avalanche breakdown in the depletion region 107 (i.e., the PWELL / NWELL junction), as shown in Figure 5B. More specifically, this causes buried traps in the depletion layer 107 to capture the generated electrons, thereby programming the given cell 100. To avoid interfering with the programming of other cells 100 in the same or different columns, an offset voltage (+V) is applied to the contacts of the source 108 and drain 109 of other cells. OS1 The gate 111 and base 112 contacts of other memory cells 100 are coupled to ground GND, but the base contact in the same column as the programmed cell is also coupled to the write voltage V. WRITE Please also refer to curve 120 in Figure 6. WRITE and V OS1 It can be determined by the group IV characteristics of the diode, and can be set, for example, V WRITE =5V and V OS1 =0.5V, but other suitable values ​​can be used in different implementations. Figures 7A-7D illustrate the clearing of the same given memory cell. Clearing is achieved by injecting holes into the depletion region 107 (capture layer) through the application of a forward body bias, by applying a V... ERASE This is achieved at substrate junction 112, as shown in Figure 7B. The injected holes recombine with trap electrons to clear the previous programmed state. To avoid interfering with the programmed values ​​in other cells 100, a Vt is applied to substrate junction 112. ERASE(See Figure 7C) When applying an appropriate offset voltage (V) to the source 108 and drain 109 contacts of the cell in the same column, an appropriate offset voltage (V) can be applied. OS2 ), and apply V to the junctions of the source 108, drain 109, and substrate 112 of the cells in other columns. OS2 Please also refer to Figure 8, curve 130, V. ERASE and V OS2 It can also be determined by the group IV characteristic curve of the diode, and can be set, for example, V ERASE =1V and V OS2 =0.8V, but other suitable values ​​can be used in different implementations. Figure 9 illustrates an exemplary read operation of one of the memory cells 100. Due to the body effect, the trapped electrons increase the MOSFET V. T The current programming state can be read through conventional MOSFET operation, i.e., by applying gate and drain bias voltages to the cell transistor, as shown in the figure. In this example, the source 108 contact is connected to ground (GND), and the gate 111 contact is connected to the read voltage V. READ The 109-pin drain electrode is connected to V. DD Furthermore, the base contact 112 is also connected to ground GND. Figures 10A-10C illustrate one exemplary method for fabricating memory cell 100. In this example, an MST-O (Si / O) thin film 125 is formed on a substrate 102 (e.g., a silicon substrate). In this embodiment, the MST-O layer 125 is deposited across the entire substrate 102 via carpet epitaxial growth prior to STI module formation. A relatively thick capping layer 152 can be epitaxially formed on the MST-O film 125, followed by STI module formation to define STI region 113. NWELL, trap source atoms (fluorine in this example), and PWELL dopants can then be sequentially introduced to confine atomic fluorine within depletion region 107 (Figure 10C). For example, ion implantation can be used to implant fluorine. A similar process for fabricating memory cell 100 is depicted in Figures 11A-11C, but here the MST-O film 125 is fabricated via selective epitaxial growth in a silicon trench after STI module formation, as shown. Implantation of NWELL, fluoride, and PWELL can be performed in the same manner as described above (Figure 11C). Please refer to plots 160-163 in Figures 12A-12D for further details. Exemplary well doping process design considerations for a 180 nm baseline are now described. This embodiment uses the following exemplary well fabrication sequence: MST silicon cap 300nm (as-grown) STI module Phosphorus 400keV 3E13 / cm² Fluorine 140keV 2E14 / cm² 1050C 5s RTA Boron 35keV 7E12 / cm² Boron 60keV 1.6E13 / cm² 1050C 5s RTA Phosphorus 19keV 2E15 / cm² 1050C 5s RTA Plot 160 shows the doping distribution below channel 110, and plot 161 shows the doping distribution below source / drain regions 108 and 109. Graphs 160 and 161 illustrate how the MST-O thin film advantageously confines / concentrates fluorine atoms at desired locations within the well, namely in the depletion layer 107. Furthermore, graph 162 depicts exemplary drain leakage characteristics, while the drain breakdown voltage (BV) versus NWELL and PWELL doses is shown in graph 163. Figure 13 provides a TEM image 164 of the memory cell 100 with exemplary dimensions, but other dimensions may be used in different embodiments. As described above, the memory cell 100 includes an MST-O layer 125 in a PWELL / NWELL depletion region 107, wherein atomic fluorine (or other trap source dopants) is confined within the MST-O layer. Now, referring to Figures 14A-14D, another method for providing electron / hole trapping is described using an MST layer 225 (see Figure 16) to fabricate nanocrystals within the NWELL / PWELL depletion region 207. More specifically, this method utilizes an MST film 225 process to form SiC nanocrystals 228 within the PWELL / NWELL depletion layer 207. The method begins with the formation of an MST-C (Si / C) film 225 on a substrate 202, followed by the formation of a thick epitaxial capping layer 252, similar to that described above with reference to Figure 10A. However, a relatively high-temperature rapid thermal annealing (RTA) is then performed, for example at 1100ºC, which results in the formation of SiC nanocrystals 228 to replace the MST film 225 (Figure 14A). Subsequent steps, such as the fabrication of an NFET in a shallow PWELL surrounded by an NWELL (or vice versa), can then be performed. More specifically, an STI module can be formed to create an STI region 213 (Figure 14B), followed by the implantation of NWELL 205, fluorine, and PWELL 206 (Figure 14C). A gate 211, source 208, drain 209, substrate 212, and associated contacts (not shown) can then be formed to complete the non-volatile memory cell 200 (Figure 14D). Figure 15, plotted as graph 260, illustrates exemplary carbon dosing times and concentrations that can be used to form MST-C thin film structures of SiC nanocrystals. Increasing the dosing time from 1 second to 3 seconds increases the carbon incorporation to 2.15E15 at / cm². 2 This would also increase the carbon content value to 0.005% (measured by X-rays), which is approximately twice the content at the same carbon level at a dose of 725°C for 1 second (measured by SIMS). Figures 16 and 17, TEM images 265 and 270, illustrate the exemplary MST-C method for forming SiC nanocrystals by annealing at 1100ºC for two minutes, and the resulting SiC nanocrystals 228. However, it should be noted that other annealing times and temperatures can also be used in different embodiments. For example, in different embodiments, the annealing time is typically in the range of about 2 to 5 minutes, and the temperature is in the range of about 945ºC to 1100ºC. Generally, as the annealing temperature increases, 800 cm⁻¹… -1 The nearby lateral optical SiC peaks become more pronounced. Since the initial superlattice 225 is a stacked layer structure (Fig. 16), the resulting nanocrystal 228 is also confined within the lattice of adjacent semiconductor portions, just like the original superlattice discussed above. Furthermore, due to the formation of atomic layers of carbon atoms, the nanocrystals tend to form vertical rows that are laterally spaced from each other, as shown in Fig. 17. In summary, the programming and clearing of the aforementioned NVRAM cells 100 and 200 can be advantageously controlled by injecting electrons and holes via NWELL substrate bias. More specifically, a write operation can be achieved by applying a positive reverse bias to the NWELL junction to induce a sudden collapse at the PWELL / NWELL junction. The electrons or holes generated by the collapse are captured by electron or hole traps in the depletion layers 107 or 207. The clearing operation can be achieved by injecting holes or electrons by applying a negative forward bias to the substrate contacts 112 and 212 to neutralize the captured electrons or holes. The read operation can be achieved by applying bias voltages to the gates 111 and 211 and the drains 109 and 209 of the cell transistor. Those skilled in the art to which this invention pertains will benefit from the disclosure and accompanying drawings, thereby conceiving various modifications and other embodiments. Therefore, it should be understood that the disclosure is not limited to the specific embodiments described in this specification, and related modifications and embodiments also fall within the scope of the appended claims. 21, 21': Substrate; 25, 25', 225: Superlattice / MST layer; 45a~45n, 45a'~45n-1', 45n': Layer group; 46, 46': Substrate semiconductor monolayer; 46a~46n, 46a'~46n-1', 46n': Substrate semiconductor portion; 50, 50': Band modification layer / non-semiconductor monolayer; 52, 52', 152, 252: Capping layer; 100, 200: Non-volatile memory cell; 101: Memory element; 102, 202: Semiconductor substrate; 103: Word line; 104: Bit line; 105: First well; 106: Second well; 107, 207: Depletion layer / Depletion region; 108, 208: Source region; 109, 209: Drain region; 110: Channel; 111, 211: Gate; 112: Substrate contact region; 113, 213: STI region; 125: Superlattice / MST superlattice thin film / MST-O layer; 205: NWELL; 206: PWELL; 212: Substrate; 228: SiC nanocrystal. Figure 1 is an enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an example embodiment. Figure 2 is a perspective atomic diagram of a portion of the superlattice shown in Figure 1. Figure 3 is an enlarged schematic cross-sectional view of a superlattice according to another example embodiment. Figure 4 is a schematic cross-sectional view of an example embodiment of a non-volatile memory cell containing a superlattice capable of trapping charges. Figure 5A is a top view of the non-volatile memory element integrating the memory cell of Figure 4 during programming. Figures 5B-5D are schematic cross-sectional views of different memory cells within the memory element of Figure 5A during programming of the memory cell of Figure 5B. Figure 6 is a diagram showing the current and voltage relationship during an exemplary programming operation of the memory cell in Figure 5B. Figure 7A is a top view of the non-volatile memory element in Figure 5A during the erasing process, and Figures 7B-7D are schematic cross-sectional views of different memory cells within the memory element in Figure 5A during the erasure of the memory cell in Figure 5B. Figure 8 is a diagram showing the current and voltage relationship during an exemplary clear operation of the memory cell in Figure 5B. Figure 9 shows a schematic cross-sectional view of the memory cell in Figure 5B during a read operation in an example embodiment. Figures 10A-10C are a series of schematic cross-sectional views illustrating a method for manufacturing the memory cell of Figure 4 according to an example embodiment. Figures 11A-11C are a series of schematic cross-sectional views illustrating a method for manufacturing the memory cell of Figure 4 according to another example embodiment. Figure 12A is an exemplary doping profile diagram illustrating the channel beneath the memory cell in Figure 4. Figure 12B is an exemplary doping distribution diagram illustrating the source / drain regions below the memory cell in Figure 4. Figure 12C depicts the drain leakage characteristics of the memory cell in Figure 4 in an example embodiment. Figure 12D depicts the relationship between the drain collapse voltage and NWEL and PWELL dosage of the memory cell in Figure 4 in an example embodiment. Figure 13 is a transmission electron microscope (TEM) image of an example embodiment of the depletion layer of the memory cell in Figure 4, which is of a representative size. Figures 14A-14D are a series of schematic cross-sectional views illustrating another memory cell in an example embodiment, including a depletion layer with traps, and related manufacturing steps. Figure 15 shows the relationship between atomic concentration and depth for the MST-C superlattice that can be used to fabricate the memory cells of Figure 14D. Figure 16 is a TEM image of the MST-C superlattice that can be used to fabricate the memory cell of Figure 14D. Figure 17 is a TEM image of the silicon carbide superlattice in Figure 16 forming nanocrystals after annealing. 200: Non-volatile memory unit 202: Semiconductor substrate 205:NWELL 207: Depletion Layer / Depletion Region 208: Source Region 209: Duji Zone 211: Gate 212: Matrix 213: STI Zone 228: SiC nanocrystal

Claims

1. A memory element comprising: A semiconductor substrate; The memory cell array on the semiconductor substrate includes each memory cell comprising a first well in the semiconductor substrate having a first conductivity type; a second well adjacent to the first well having a second conductivity type and defining a depletion layer therebetween with respect to the first well; a plurality of nanocrystals inside the depletion layer, wherein the plurality of nanocrystals are arranged in vertically spaced rows, each nanocrystal comprising a semiconductor material and carbon; a separated source region and a drain region adjacent to the second well, defining a channel between them; and a gate covering the channel.

2. The memory element of claim 1, wherein the plurality of nanocrystalline systems are confined within a lattice of one of adjacent semiconductor portions.

3. The memory element of claim 1, wherein the plurality of nanocrystals are laterally spaced from each other.

4. The memory element of claim 1, wherein each memory cell further includes a substrate contact region coupled to the first well.

5. The memory element as claimed in claim 1, wherein each nanocrystal comprises silicon and carbon.

6. The memory element as claimed in claim 1, wherein the memory cells include non-volatile memory cells.

7. The memory element of claim 1, comprising a corresponding shallow trench isolation (STI) region adjacent to the source region and the drain region and extending into the first well.

8. The memory element of claim 1, wherein the first conductivity type includes n-type and the second conductivity type includes p-type.

9. The memory element of claim 1 includes a plurality of word lines and bit lines connecting the memory cell array.

10. A method for manufacturing a memory element, comprising: An array of memory cells is formed on a semiconductor substrate. Each memory cell includes a first well in the semiconductor substrate having a first conductivity type; a second well adjacent to the first well having a second conductivity type and defining a depletion layer therebetween with respect to the first well; a plurality of nanocrystals inside the depletion layer, wherein the plurality of nanocrystals are arranged in vertically spaced rows, and each nanocrystal includes a semiconductor material and carbon; a separated source region and a drain region adjacent to the second well, defining a channel between them; and a gate covering the channel.

11. The method of claim 10, wherein the plurality of nanocrystalline systems are confined within a lattice of one of adjacent semiconductor portions.

12. The method of claim 10, wherein the plurality of nanocrystals are laterally spaced from each other.

13. The method of claim 10 further includes forming a corresponding substrate contact region coupled to the first well of each memory cell.

14. The method of claim 10, wherein each nanocrystal comprises silicon and carbon.

15. The method of claim 10, wherein the memory cells include non-volatile memory cells.

16. The method of claim 10, comprising forming a source region and a drain region adjacent to each memory cell and extending into a corresponding shallow trench isolation (STI) region within the first well.

17. The method of claim 10, wherein the first conductivity type includes n-type and the second conductivity type includes p-type.

18. The method of claim 10, comprising forming a plurality of word lines and bit lines connecting the memory cell array.

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