Radio-frequency power detector with common mode leakage cancellation

Abstract

A wireless circuit system may include: a radio frequency amplifier; a mixer configured to receive a local oscillator (LO) signal; and a power detector having an input port coupled to the radio frequency amplifier and a separate common-mode cancellation input port configured to receive a common-mode leakage signal associated with the LO signal. The wireless circuit system may further include a transformer coupled between the radio frequency amplifier and the mixer. The input port of the power detector may be coupled to a first coil of the transformer. The common-mode cancellation input port of the power detector may be coupled to either the first coil or a second coil of the transformer. One or more capacitors may be coupled between the transformer and the common-mode cancellation input port of the power detector. Eliminating the common-mode leakage signal in this manner improves the dynamic range of the power detector.

Description

RF Power Detector with Common-Mode Leakage Cancellation The present invention relates generally to electronic devices, and more particularly, to electronic devices having wireless communication circuitry. An electronic device may have wireless communication capabilities. An electronic device with wireless communication capabilities includes a wireless communication circuit system including one or more antennas. The wireless transceiver circuit system in the wireless communication circuit system uses the antenna to transmit and receive radio frequency signals. The RF signal transmitted by the antenna can be fed through a power amplifier, which is configured to amplify the low-power analog signal into a higher-power signal more suitable for long-distance transmission through the air. The RF signal received at the antenna can be fed through a low-noise amplifier, which is configured to amplify the low-power analog signal into a higher-power signal for processing at the receiver. A power detector can be used to measure the power level of the power amplifier or low-noise amplifier. Designing a satisfactory power detector can be challenging. An electronic device may include wireless communication circuitry. The wireless communication circuitry may include: one or more processors or signal processing blocks for generating baseband signals; a transceiver for up-converting (modulating) the baseband signals to radio frequency (RF) and down-converting (demodulating) the RF signals to baseband signals; a radio frequency power amplifier for amplifying the RF signals before transmission at one or more antennas; and a radio frequency low-noise amplifier for amplifying the RF signals received at one or more antennas in the electronic device. One aspect of the present disclosure provides a wireless circuit system comprising: a radio frequency (RF) amplifier; a mixer coupled to the RF amplifier and configured to receive an oscillating signal; and a power detection circuit having an input port coupled to the RF amplifier and a common-mode cancellation input port, different from the input port, configured to receive a common-mode leakage signal associated with the oscillating signal. The wireless circuit system may further comprise: a transformer having a first coil coupled to the RF amplifier and a second coil coupled to the mixer. The input port of the power detection circuit may be coupled to an output or input port of the RF amplifier via a pair of coupling capacitors. The common-mode cancellation input port of the power detection circuit may be coupled to the input port of the power detection circuit or the second coil of the transformer via one or more adjustable capacitors or resistors. The one or more adjustable capacitors or resistors may be fine-tuned to fully or only partially cancel a common-mode leakage signal received at the input port of the power detection circuit. One aspect of the present disclosure provides a circuit system comprising: an RF amplifier; and a power detection circuit coupled to an output or input port of the RF amplifier. The power detection circuit may include: a first input transistor coupled to the output or input port of the RF amplifier; a second input transistor coupled to the output or input port of the RF amplifier; and a replica input transistor coupled to a common-mode cancellation input port of the power detection circuit. The circuit system may further include: a mixer coupled to the RF amplifier and configured to receive a local oscillator (LO) signal, wherein the common-mode cancellation input port is configured to receive a common-mode leakage signal associated with the LO signal. The circuit system may further include: a transformer coupled to the output or input port of the RF amplifier; and one or more passive components coupled between the transformer and the common-mode cancellation input port of the power detection circuit. The one or more passive components may include an adjustable capacitor or an adjustable resistor that is trimmed to fully cancel or only partially cancel a common-mode leakage signal received at the first input transistor and the second input transistor. One aspect of the present disclosure provides a circuit system comprising: a passive circuit; a transformer having a first coil coupled to the passive circuit and a second coil; and a power detector having a differential input port coupled to the first coil of the transformer and a common-mode cancellation input port, the common-mode cancellation input port being separate from the differential input port and coupled to a center tap of the first coil of the transformer. The power detector may include: a first input transistor having a gate terminal coupled to the differential input port of the power detector; a second input transistor having a gate terminal coupled to the differential input port of the power detector; and a third input transistor having a gate terminal coupled to the common-mode cancellation input port of the power detector. This application claims priority to U.S. patent application No. 18 / 649,395, filed on April 29, 2024, which claims priority to U.S. provisional patent application No. 63 / 583,544, filed on September 18, 2023, which are hereby incorporated by reference in their entirety. An electronic device (such as device 10 in FIG. 1 ) may include wireless circuitry. The wireless circuitry may include radio frequency (RF) amplifiers, such as power amplifiers and low-noise amplifiers. The power amplifier may be used to amplify RF signals in a transmit path, while the low-noise amplifier may be used to amplify RF signals in a receive path. Power detection circuits (sometimes referred to as power detectors) may be coupled to the outputs of these RF amplifiers. The power detector coupled to the output of the RF power amplifier may be configured to execute an adaptive power control algorithm to adjust the power level of the power amplifier, while the power detector coupled to the output of the RF low-noise amplifier may be configured to execute an automatic gain control algorithm to adjust the power level of the low-noise amplifier. Other circuits, such as mixers, can be coupled to the output of the radio frequency (RF) amplifier. The mixers can receive high-frequency local oscillator (LO) signals, which can generate common-mode signals and / or other spikes that can leak into the power detector's input. If not carefully controlled, this common-mode leakage can reduce the power detector's dynamic range. To help counteract this common-mode leakage, the power detector can tap into the common-mode signal at various points along the signal path. In one embodiment, the power detector can tap the common-mode signal at the power detector's differential input ports. In another embodiment, the power detector can tap the common-mode signal across opposite terminals of a transformer secondary at the mixer's input. In yet another embodiment, the power detector can tap the common-mode signal at the center tap terminal of the transformer secondary at the mixer's input. The common-mode signal can be coupled to a replica input transistor within the power detector via an optional adjustable coupling component. Configuring and operating the power detector in this manner is technically advantageous and helps improve the dynamic range of the power detector while also improving the detector's accuracy over process, voltage, and temperature variations (eg, improving the signal-to-noise ratio). The electronic device 10 of Figure 1 can be a computing device (such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a mobile phone, a media player, or other handheld or portable electronic device), a smaller device (such as a wristwatch device, a pendant device, a headphone or earphone device, a device embedded in glasses or other equipment worn on the user's head, or other wearable or pocket-sized device), a television, a computer monitor without an embedded computer, a gaming device, a navigation device, an embedded system (such as a system with electronic equipment having a display installed in an information station or car), a wireless voice-controlled speaker connected to the Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that implements the functions of two or more of these devices, or other electronic equipment. As shown in the functional block diagram of Figure 1, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12, sometimes referred to as a casing, may be formed from plastic, glass, ceramic, fiber composites, metal (such as stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations thereof. In some embodiments, part or all of housing 12 may be formed from a dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12 or at least some of the structures comprising housing 12 may be formed from metallic elements. Device 10 may include control circuitry 14. Control circuitry 14 may include storage, such as storage circuitry 16. Storage circuitry 16 may include hard drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. Storage circuitry 16 may include memory integrated within device 10 and / or removable storage media. Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), and the like. Control circuitry 14 may be configured to use hardware (e.g., dedicated hardware or circuitry), firmware, and / or software to perform operations in device 10. Software code used to perform operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). Software code may sometimes be referred to as program instructions, software, data, commands, or program code. The software code stored on storage circuitry 16 may be executed by processing circuitry 18. The control circuit system 14 can be used to execute software on the device 10, such as a satellite navigation application, an Internet browsing application, a voice-over-internet-protocol (VOIP) phone call application, an email application, a media playback application, operating system functions, etc. To support interaction with external devices, the control circuit system 14 can be used to implement communication protocols. Communication protocols that can be implemented using the control circuit system 14 include Internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols - sometimes called Wi-Fi) ® ), protocols for other short-range wireless communication links (such as Bluetooth ® protocols or other wireless personal area network (WPAN) protocols), IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular telephone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based space ranging protocols (e.g., radio detection and ranging (RADAR) protocols or other desired range detection protocols for signals transmitted at millimeter wave and centimeter wave frequencies, or any other desired communication protocols. Each communication protocol may be associated with a corresponding radio access technology (RAT) that specifies the physical connection method used in implementing the protocol. Device 10 may include input / output circuitry 20. Input / output circuitry 20 may include input / output devices 22. Input / output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input / output devices 22 may include user interface devices, data port devices, and other input / output components. For example, input / output devices 22 may include touch sensors, displays (e.g., touch-sensitive and / or force-sensitive displays), light-emitting components (such as displays without touch sensor capabilities), buttons (mechanical, capacitive, optical, etc.), scroll wheels, trackpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), and the like. In some configurations, wired or wireless connections may be used to couple keyboards, headphones, displays, pointing devices (such as touchpads, mice, and joysticks), and other input / output devices to device 10 (e.g., some of the input / output devices 22 may be peripheral devices coupled to the main processing unit or other parts of device 10 via wired or wireless links). I / O circuitry 20 may include wireless circuitry 24 to support wireless communications. Wireless circuitry 24 (sometimes referred to herein as wireless communications circuitry 24) may include one or more antennas. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, and / or any other circuitry for transmitting and / or receiving RF signals using the antenna(s). The wireless circuit system 24 may transmit and / or receive radio frequency signals within a corresponding frequency band (sometimes referred to herein as a communication frequency band or simply a "frequency band"). The frequency bands handled by the wireless circuit system 24 may include: wireless local area network (WLAN) frequency bands (e.g., Wi-Fi ® (IEEE 802.11) or other WLAN communication bands), such as the 2.4 GHz WLAN band (e.g., from 2400 to 2480 MHz), the 5 GHz WLAN band (e.g., from 5180 to 5825 MHz), Wi-Fi ® Band 6E (e.g., from 5925 to 7125 MHz) and / or other Wi-Fi ® Frequency bands (e.g., from 1875 to 5160 MHz); Wireless Personal Area Network (WPAN) bands, such as 2.4 GHz Bluetooth ®frequency bands or other WPAN communication bands; cellular telephone bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G new radio frequency range 1 (FR1) bands below 10 GHz, 5G new radio frequency range 2 (FR2) bands between 20 and 60 GHz, etc.); cellular sidebands; 6G bands between 100 and 1000 GHz (e.g., sub-THz, THz, or very high frequency bands, etc.); other centimeter or millimeter wave bands between 10 and 300 GHz; near field communication bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS band from 1565 to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); IEEE Ultra-wideband (UWB) frequency bands operating under the 802.15.4 protocol and / or other ultra-wideband (UWB) communication protocols; communication frequency bands according to the 3GPP wireless communication standard series; communication frequency bands according to the IEEE 802.XX standard series; and / or any other desired frequency bands of interest. FIG2 is a diagram showing illustrative components within wireless circuitry 24. As shown in FIG2 , wireless circuitry 24 may include a processor (such as processor 26), radio frequency (RF) transceiver circuitry (such as RF transceiver 28), RF front-end circuitry (such as RF front-end module (FEM) 40), and antenna 42. Processor 26 may be a baseband processor, an application processor, a general-purpose processor, a microprocessor, a microcontroller, a digital signal processor, a host processor, application-specific signal processing hardware, or another type of processor. Processor 26 may be coupled to transceiver 28 via path 34. Transceiver 28 may be coupled to antenna 42 via RF transmission line path 36. RF front-end module 40 may be disposed on RF transmission line path 36 between transceiver 28 and antenna 42. In the example of FIG2 , for clarity, wireless circuitry 24 is illustrated as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. In general, wireless circuitry 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a respective path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a respective RF transmission line path 36. Each RF transmission line path 36 may have a respective front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmission line path 36. If desired, one or more of the RF transmission line paths 36 in the wireless circuit system 24 may be implemented without any front-end modules disposed thereon. RF transmission line path 36 can be coupled to an antenna feed on antenna 42. The antenna feed can, for example, include a positive antenna feed terminal and a ground antenna feed terminal. RF transmission line path 36 can have a positive transmission line signal path coupled to the positive antenna feed terminal on antenna 42. RF transmission line path 36 can have a ground transmission line signal path coupled to a ground antenna feed terminal on antenna 42. This example is merely illustrative, and in general, any desired antenna feed scheme can be used to feed antenna 42. If desired, antenna 42 can have multiple antenna feeds coupled to one or more RF transmission line paths 36. RF transmission line path 36 may include a transmission line used to route RF antenna signals within device 10 ( FIG. 1 ). The transmission line in device 10 may include a coaxial cable, a microstrip transmission line, a stripline transmission line, an edge-coupled microstrip transmission line, an edge-coupled stripline transmission line, a combination of these types of transmission lines, or the like. Transmission lines in device 10, such as those in RF transmission line path 36, may be integrated into rigid and / or flexible printed circuit boards. When performing wireless transmissions, processor 26 may provide a transmission signal (e.g., a digital or baseband signal) to transceiver 28 via path 34. Transceiver 28 may further include circuitry for converting the transmission (baseband) signal received from processor 26. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the transmission (baseband) signal to a radio frequency before transmission via antenna 42. The example of FIG. 2 in which processor 26 communicates with transceiver 28 is illustrative only. In general, transceiver 28 may communicate with a baseband processor, an application processor, a general-purpose processor, a microcontroller, a microprocessor, or one or more processors within circuitry 18. Transceiver circuitry 28 may also include digital-to-analog converter (DAC) and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. The transceiver 28 may use a transmitter (TX) 30 to transmit RF signals via an RF transmission line path 36 and a front-end module 40 through an antenna 42. The antenna 42 may transmit the RF signals to an external wireless device by radiating the RF signals into free space. When performing wireless reception, antenna 42 can receive RF signals from an external wireless device. The received RF signals can be transmitted to transceiver 28 via RF transmission line path 36 and front-end module 40. Transceiver 28 may include circuitry, such as receiver (RX) 32, for receiving signals from front-end module 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to a baseband frequency before transmitting the received signals to processor 26 via path 34. The front-end module (FEM) 40 may include RF front-end circuitry that operates on RF signals delivered (transmitted and / or received) via the RF transmission line path 36 . The FEM 40 may, for example, include front-end module (FEM) components such as RF filter circuitry 44 (e.g., a low-pass filter, a high-pass filter, a notch filter, a band-pass filter, multiplexer circuitry, duplexer circuitry, diplexer circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more RF switches), RF amplifier circuitry 48 (e.g., one or more power amplifier circuits 50 and / or one or more low-noise amplifier circuits 52), a signal attenuator, impedance matching circuitry (e.g., circuitry that helps match the impedance of the antenna 42 to the impedance of the RF transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjusts the frequency response of the antenna 42), RF coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on RF signals transmitted and / or received by the antenna 42. The front-end module components can be mounted to a common substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip. If desired, amplifier circuitry 48 and / or other components in front-end 40 (such as filter circuitry 44) can also be implemented as part of transceiver circuitry 28. Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to adjust the frequency response and wireless performance of antenna 42 over time. Transceiver 28 may be separate from front-end module 40. For example, transceiver 28 may be formed on another substrate, such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of front-end module 40. For clarity, in the example of FIG. 1 , control circuitry 14 is shown as separate from wireless circuitry 24. However, wireless circuitry 24 may include processing circuitry that forms part of processing circuitry 18 and / or storage circuitry that forms part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, processor 26 and / or portions of transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., a portion of control circuitry 14 formed on processor 26, a portion of control circuitry 14 formed on transceiver 28, and / or a portion of control circuitry 14 separate from wireless circuitry 24) may provide control signals that control the operation of front-end module 40 (e.g., via one or more control paths in device 10). The transceiver circuitry 28 may include a wireless local area network transceiver circuitry that handles WLAN communication bands (e.g., Wi-Fi ® (IEEE 802.11) or other WLAN communication bands), such as the 2.4 GHz WLAN band (e.g., from 2400 to 2480 MHz), the 5 GHz WLAN band (e.g., from 5180 to 5825 MHz), Wi-Fi ® Band 6E (e.g., from 5925 to 7125 MHz), and / or other Wi-Fi ® frequency band (e.g., from 1875 to 5160 MHz); wireless personal area network transceiver circuitry that handles 2.4 GHz Bluetooth ®frequency band or other WPAN communication band; cellular telephone transceiver circuit system that handles cellular telephone frequency bands (e.g., frequency bands from about 600 MHz to about 5 GHz, 3G frequency bands, 4G LTE frequency bands, 5G new radio frequency range 1 (FR1) bands below 10 GHz, 5G new radio frequency range 2 (FR2) bands between 20 and 60 GHz, etc.); near field communication (NFC) transceiver circuit system that handles near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuit system that handles satellite navigation frequency bands (e.g., GPS frequency bands from 1565 to 1610 MHz, Global Navigation Satellite System (GLONASS) frequency bands, BeiDou Navigation Satellite System (BDS) frequency bands, etc.); ultra-wideband (UWB) transceiver circuit system that uses IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; radio transceiver circuitry that handles unlicensed radio frequency bands reserved for industrial, scientific, and medical (ISM) purposes; and / or any other desired radio frequency transceiver circuitry for covering any other desired communications band of interest. Wireless circuitry 24 may include one or more antennas (such as antenna 42). Antenna 42 may be formed using any desired antenna structure. For example, antenna 42 may be an antenna having a resonant element formed from a loop antenna structure, a patch antenna structure, an inverted-F antenna structure, a slot antenna structure, a planar inverted-F antenna structure, a helical antenna structure, a monopole antenna, a dipole antenna, a hybrid of these designs, or the like. Two or more antennas 42 may be configured as one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may have a conductive cavity with an antenna resonant element of antenna 42 attached (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna). The RF amplifier can be coupled to a power detector for power level monitoring purposes. FIG3 is a diagram showing an illustrative power detector coupled to the output of the RF amplifier. As shown in FIG3 , the wireless circuitry 24 can have one or more antennas 42 coupled to a transmit path and a receive path via an RF duplexing circuit, such as a bidirectional transmitter 60. The bidirectional transmitter 60 can have a first port coupled to the common antenna 42, a second port coupled to the transmit path (e.g., a second port configured to receive the amplified RF signal to be radiated by the antenna 42), and a third port coupled to the receive path (e.g., a third port to which the RF signal received by the antenna 42 is transmitted). The receive path may include low-noise amplifier (LNA) circuitry 52, down-conversion mixing circuitry such as mixer 68, and a data converter such as analog-to-digital converter (ADC) 66. LNA circuitry 52 may include one or more amplifiers coupled in series and / or parallel. Mixer 68 may use a local oscillator signal to down-convert (or demodulate) the RF signal to a baseband (or intermediate) frequency. Analog-to-digital converter (ADC) circuitry 66 may then convert the demodulated signal from the analog domain to the digital domain to produce a corresponding digital baseband signal. Mixer 68 and ADC circuitry 66 are sometimes considered part of receiver circuitry 32. The digital baseband signal may then be received by one or more processors 26. Processor 26 may represent one or more processors, such as a baseband processor, an application processor, a digital signal processor, a microcontroller, a microprocessor, a central processing unit (CPU), a programmable device, a combination of these, and / or one or more processors within circuit system 18 (see FIG. 1 ). The circuitry described above for processing signals received by antenna 42 is sometimes collectively referred to as wireless receive circuitry. If desired, one or more additional front-end module components (such as RF filter circuitry 44 of FIG. 2 (e.g., a low-pass filter, a high-pass filter, a notch filter, a band-pass filter, an attenuator, multiplexer circuitry, bidirectional circuitry, duplexer circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more RF switches), impedance matching circuitry, antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjusts the frequency response of antenna 42), RF coupler circuitry, charge pump circuitry, power management circuitry, and / or any other desired front-end module circuitry) may optionally be coupled to the input and / or output of LNA circuitry 52 along the RF receive line path. On the other hand, the transmit path may include power amplifier (PA) circuitry 50, up-converting mixing circuitry (such as mixer 64), and a data converter (such as digital-to-analog converter (DAC) 62). Processor 26 may generate a digital baseband signal (sometimes referred to as a digital signal) for transmission. DAC circuitry 62 may convert the digital baseband signal from the digital domain to the analog domain to generate a corresponding analog baseband signal. Mixer 64 may use a local oscillator signal to up-convert (or modulate) the RF signal to a RF (or intermediate frequency). DAC circuitry 62 and mixer 64 are sometimes considered part of transmitter circuitry 30. The up-converted RF signal may then be fed to amplifier circuitry 50. PA circuitry 52 may include one or more amplifiers coupled in series and / or parallel, configured to amplify the signal for transmission by antenna 42. The circuitry described above for preparing signals for transmission by antenna 42 is sometimes collectively referred to as wireless transmission circuitry. If desired, one or more additional front-end module components (such as RF filter circuitry 44 of FIG. 2 (e.g., a low-pass filter, a high-pass filter, a notch filter, a band-pass filter, an attenuator, multiplexer circuitry, bidirectional circuitry, duplexer circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more RF switches), impedance matching circuitry, antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjusts the frequency response of antenna 42), RF coupler circuitry, charge pump circuitry, power management circuitry, and / or any other desired front-end module circuitry) may optionally be coupled to the input and / or output of amplifier circuitry 50 along the RF transmission line path. The power (transmit) amplifier 50 and the low-noise (receive) amplifier 52 may be collectively referred to as RF amplifiers. Power detection circuitry may be coupled to the outputs of the RF amplifiers to implement power monitoring operations. Still referring to FIG3 , a first power detection circuit (such as power detector 70-TX) may be coupled to the output of the transmit amplifier circuitry 50, while a second power detection circuit (such as power detector 70-RX) may be coupled to the output of the receive amplifier circuitry 52. ​​Power detector 70-TX may be used to detect or measure the output power level of the RF signal generated at the output of amplifier circuitry 50. The detected output power level may then be used by an automatic power control (APC) algorithm to dynamically adjust the gain of the power amplifier circuitry 50 to ensure that the transmit path outputs the signal at the desired power level. The APC algorithm, which may be executed on the processor 26 or other control circuitry in device 10, may compare the measured output power level with a reference power level. If the output power level is too high, the APC algorithm may reduce the gain of the amplifier 50. If the output power level is too low, the APC algorithm may increase the gain of the amplifier 50. Power detector 70-RX can be used to detect or measure the output power level of the RF signal generated at the output of receive amplifier circuitry 52. ​​The detected output power level can then be used by an automatic gain control (AGC) algorithm to dynamically adjust the gain of LNA circuitry 52 to ensure that the receive path outputs a signal at a desired power level, regardless of the strength of the signal reaching the input of circuitry 52. ​​The AGC algorithm, which may be executed on processor 26 or other control circuitry in device 10, can be used to ensure that the signal output from circuitry 52 is at a constant output power level. If the input signal is weak, the AGC algorithm can increase the gain of amplifier 52 to maintain a constant output level. If the input signal is strong, the AGC algorithm can decrease the gain of amplifier 52 to prevent the output level from becoming too high. The example of FIG3 is illustrative, in which power detectors 70-TX and 70-RX are coupled at the output of the RF amplifier. If desired, one or more power detectors may be coupled at the output of DAC 62, at the output of mixer 64, and / or at any other point(s) along the transmit signal path, at the output of mixer 68, at the output of ADC 66, and / or at any other point(s) along the receive signal path. FIG4 is a diagram of wireless circuitry 24 having an RF amplifier 53 with an output port coupled to a mixer 68 via a transformer 80. RF amplifier 53 may represent a variable gain amplifier (VGA), the low-noise amplifier 52 of FIG3 , or other amplifier circuitry along the receive signal path. Transformer 80 may be coupled between the output port of RF amplifier 53 and the input port of mixer 68. RF amplifier 53 may be a differential amplifier with a differential output port. Similarly, mixer 68 may be a differential mixing circuit with a differential input port. Transformer 80 may include a primary coil (winding) 82p and a secondary coil (winding) 82s. Primary coil 82p may have opposite (remote) terminals coupled across the differential output port of RF amplifier 53 and a center tap terminal coupled to voltage line 84. Voltage line 84 may be supplied with a fixed bias voltage, a supply voltage, or other fixed or adjustable voltage. The secondary winding 82s may have opposite (far) terminals coupled across the differential input ports of the mixer 68 and a center tap terminal configured to receive the bias current Ibias. The differential output port of RF amplifier 53 can be coupled to a power detector (such as power detector 70). Power detector 70 coupled to receive amplifier 53 in FIG4 may correspond to power detector 70-RX in FIG3 (as an example). Specifically, power detector 70 may have a differential input port coupled to the differential output port of RF amplifier 53 via coupling capacitors 86 and 88. Capacitor 86 may have a first terminal coupled to the first terminal of primary coil 82p and a second terminal coupled to the first input of power detector 70. Capacitor 88 may have a first terminal coupled to the second terminal of primary coil 82p and a second terminal coupled to the second input of power detector 70. One of the first and second inputs of power detector 70 may serve together as the differential input port of power detector 70. The power detector 70 may include a signal squaring component (unit) with a signal squaring function. A squarer-based power detector exhibits similar gain for differential-mode and common-mode signals at its input terminals (i.e., the squaring unit can detect both differential-mode and common-mode signals). Mixer 68 further receives a high-frequency local oscillator (LO) signal, sometimes referred to as an oscillator signal. If care is not taken, the LO signal received at mixer 68 may leak into the input port of the power detector 70, as shown by leakage path 190. For example, the second harmonic LO (2LO) component may leak into the power detector input as a common-mode signal. Common-mode signals in the signal path (such as LO leakage, 2LO leakage, and / or other glitches at the power detector input) can cause spurious voltages at the output of the power detector 70, which can reduce the dynamic range of the power detector 70. In some cases, 2LO leakage can dominate the detected signal strength response and significantly reduce the dynamic range of the power detector 70. (Multiple) such common-mode signals, which degrade the dynamic range of the power detector 70 and are sometimes referred to and defined herein as "common-mode leakage," may arise due to non-ideal conductive and / or magnetic coupling and may cause the power / gain control algorithm associated with the amplifier 53 to operate incorrectly, thereby degrading the signal-to-noise ratio (SNR) of the overall system. According to some embodiments, power detector 70 can tap common-mode signals from various points in the signal path between amplifier 53 and mixer 68. In the example of FIG4 , common-mode signals (or leakage) can be tapped from the differential input port of power detector 70. As shown in FIG4 , a first common-mode tap capacitor 90 and a second common-mode tap capacitor 92 can be coupled between the differential input port of power detector 70 and a common-mode cancellation input port 99 of power detector 70. First common-mode tap capacitor 90 can have a first terminal coupled to the first input port of power detector 70 and a second terminal coupled to common-mode cancellation input port 99. Second common-mode tap capacitor 92 can have a first terminal coupled to the second input port of power detector 70 and a second terminal also coupled to common-mode cancellation input port 99. Configured in this manner, common-mode leakage, including the second harmonic LO voltage V_2LO and other undesirable common-mode spurious signals, can be coupled from mixer 68 to input port 99. The common-mode signal fed into input port 99 of power detector 70 can be used to cancel any undesirable common-mode leakage at the output port of power detector 70. Configuring and operating in this manner optimizes the dynamic range of power detector 70. Capacitors 90 and 92 can optionally be implemented as adjustable or trimmable capacitors that are tuned to completely cancel common-mode leakage or limit it to a target voltage level based on the desired dynamic range or accuracy of power detector 70. The embodiment of FIG. 4 , in which additional common-mode tap capacitors 90 and 92 are connected to the differential input ports of power detector 70 , is exemplary and may introduce additional loading on the primary signal. FIG. 5 shows another embodiment in which the common mode is tapped across transformer secondary winding 82 s. As shown in FIG. 5 , a first common-mode tap capacitor 94 and a second common-mode tap capacitor 96 may be coupled between secondary winding 82 s and a common-mode cancellation input port 99 of power detector 70 . The first common-mode tap capacitor 94 may have a first terminal coupled to the first terminal of secondary winding 82 s (the upper terminal in FIG. 5 ) and a second terminal coupled to common-mode cancellation input port 99 . The second common-mode tap capacitor 96 may have a first terminal coupled to the second terminal of secondary winding 82 s (the lower terminal in FIG. 5 ) and a second terminal coupled to common-mode cancellation input port 99 . Configured in this manner, common-mode leakage, including the second harmonic LO voltage V_2LO and other undesirable common-mode parasitic signals, can be coupled from mixer 68 to input port 99. The common-mode signal fed into input port 99 of power detector 70 can be used to cancel any undesirable common-mode leakage at the output port of power detector 70. Configuring and operating in this manner, the dynamic range of power detector 70 can be optimized. Capacitors 94 and 96 can optionally be implemented as adjustable or trimmable capacitors that are fine-tuned to completely cancel common-mode leakage or limit it to a target voltage level based on the desired dynamic range or accuracy of power detector 70. The embodiment of FIG. 5 is exemplary (in which additional common-mode tap capacitors 94 and 96 are connected across opposing terminals of secondary winding 82s in transformer 80) and can sense larger common-mode signals compared to the embodiment of FIG. 4 , but may still introduce additional loading on the primary signal. FIG. 6 shows another embodiment in which the common-mode signal is tapped at the center tap terminal of transformer secondary winding 82s. As shown in FIG. 6 , common-mode tap capacitor 98 can be coupled between secondary winding 82s and common-mode cancellation input port 99 of power detector 70. Common-mode tap capacitor 98 can have a first terminal coupled to the center tap terminal of secondary winding 82s and a second terminal coupled to common-mode cancellation input port 99. Configured in this manner, common-mode leakage, including the second harmonic LO voltage V_2LO and other undesirable common-mode parasitic signals, can be coupled from mixer 68 to input port 99. The common mode signal fed into the input port 99 of the power detector 70 can be used to cancel any undesirable common mode leakage at the output port of the power detector 70. Configuring and operating in this manner, the dynamic range of the power detector 70 can be optimized. Compared to the examples of Figures 4 and 5 , the embodiment of Figure 6 has no impact on RF performance because the center tap of secondary coil 82s behaves like an AC ground node for differential-mode operation. This can result in better common-mode leakage cancellation within power detector 70. Capacitor 98 can have an adjustable or trimmable capacitance. In some cases, capacitor 98 can be trimmed to completely (totally) cancel common-mode leakage. In other cases, capacitor 98 can be trimmed so that the common-mode leakage is tuned to a target voltage level at the power detector output (e.g., capacitor 98 is trimmed to only partially cancel common-mode leakage). The amount or degree of trimming can be determined based on the desired dynamic range or accuracy of power detector 70. 6 is illustrative, in which an adjustable capacitor 98 is coupled between the center tap of the secondary winding 82s and the common-mode cancellation input port 99. In other embodiments, an adjustable or trimmable resistor may be coupled between the center tap of the secondary winding 82s and the common-mode cancellation input port 99. Based on the desired dynamic range or accuracy of the power detector 70, such a resistor may be similarly trimmed to completely cancel common-mode leakage or to limit common-mode leakage to a target voltage level. The embodiment of FIG6 is illustrative, in which a trimmable capacitor 98 is coupled to the center tap of secondary winding 82s. FIG8 shows yet another embodiment, in which the common-mode signal is tapped at the center tap terminal of transformer primary winding 82p. This common-mode tap point can be used when primary winding 82p of transformer 80 is coupled to a passive circuit, such as passive circuit 55. Passive circuit 55 can be an attenuator, phase shifter, or other passive circuit along the receive or transmit path. As shown in FIG8, common-mode tap capacitor 98 can be coupled between primary winding 82p and common-mode cancellation input port 99 of power detector 70. Common-mode tap capacitor 98 can have a first terminal coupled to the center tap terminal of primary winding 82p and a second terminal coupled to common-mode cancellation input port 99. Configured in this manner, common-mode leakage, including the second harmonic LO voltage V_2LO and other undesirable common-mode spurious signals, can be coupled from mixer 68 to input port 99. The common mode signal fed into the input port 99 of the power detector 70 can be used to cancel any undesirable common mode leakage at the output port of the power detector 70. Configuring and operating in this manner, the dynamic range of the power detector 70 can be optimized. Similar to the embodiment of FIG. 6 , the embodiment of FIG. 8 has no impact on RF performance because the center tap of primary coil 82p behaves like an AC ground node for differential-mode operation. This can result in better common-mode leakage cancellation within power detector 70 . Capacitor 98 can have an adjustable or trimmable capacitance. In some cases, capacitor 98 can be trimmed to completely (totally) cancel common-mode leakage. In other cases, capacitor 98 can be trimmed so that common-mode leakage is tuned to a target voltage level at the power detector output (e.g., capacitor 98 can be trimmed to only partially cancel common-mode leakage). The amount or degree of trimming can be determined based on the desired dynamic range or accuracy of power detector 70 . The example of FIG. 8 is illustrative, in which adjustable capacitor 98 is coupled between the center tap of primary coil 82p and common-mode cancellation input port 99 . In other embodiments, an adjustable or trimmable resistor can be coupled between the center tap of primary coil 82p and common-mode cancellation input port 99 . Based on the desired dynamic range or accuracy of the power detector 70, such resistors can be similarly trimmed to completely cancel common-mode leakage or limit common-mode leakage to a target voltage level. FIG7 is a circuit diagram of a power detector 70 of the type described in conjunction with FIG3 through FIG6 and FIG8 . As shown in FIG7 , power detection circuit 70 may include input transistors (such as first input transistor 110-1 and second input transistor 110-2), a replica input transistor (such as replica input transistor 114), and load transistors (such as first load transistor 122 and second load transistor 124). First input transistor 110-1 may have the same size as second input transistor 110-2. Replica input transistor 114 may refer to and is defined herein as a transistor having similar connection and bias conditions as input transistors 110-1 and 110-2 and having a size equal to the combined size of input transistors 110-1 and 110-2. Because there are two input transistors 110-1 and 110-2 of the same size, replica input transistor 114 may have a size equal to twice that of input transistor 110-1. In an embodiment where the power detector 70 has only a single input transistor 110 , the replica input transistor 114 may have the same size as the single input transistor 110 . Transistors 110-1, 110-2, and 114 may be n-type metal oxide semiconductor (NMOS) transistors, while load transistors 122 and 124 may be p-type metal oxide semiconductor (PMOS) transistors. First input transistor 110-1 may have a gate terminal coupled to a first input terminal configured to receive a first (positive) RF signal Vrfp via an AC coupling capacitor 102-1; a source terminal coupled to a ground line 104 (e.g., a ground supply line at which a ground voltage Vss is provided); and a drain terminal coupled to a first power detector output terminal at which a first (positive) power detector output voltage Voutp is provided. Second input transistor 110-2 may have a gate terminal coupled to a second input terminal configured to receive a second (minus / negative) RF signal Vrfm via second AC coupling capacitor 102-2; a source terminal coupled to ground 104; and a drain terminal also coupled to the first power detector output terminal. First input transistor 110-1 and second input transistor 110-2 may be coupled in parallel. The first and second input terminals, receiving differential voltages Vrfp and Vrfm, may serve together as differential input ports of power detector 70 (which may be connected to differential output ports of amplifier 53, as shown in Figures 4 through 6). The first and second power detector output terminals, generating differential voltages Voutp and Voutm, may serve together as differential output ports of power detector 70. The terms "source" and "drain" are sometimes used interchangeably when referring to the current-conducting terminals of a metal-oxide-semiconductor transistor. Thus, the source and drain terminals are sometimes referred to as "source-drain" terminals (e.g., a transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal). Replica input transistor 114 may have a source terminal coupled to ground; a gate terminal configured to receive a bias voltage Vbias via a series resistor 192; and a drain terminal coupled to a second power detector output terminal at which a second (minus / negative) power detector output voltage Voutm is provided. Resistor 192 is optional. Configured in this manner, input transistors 110-1 and 110-2 and replica input transistor 114 may be operable to perform AC voltage to DC current conversion and are sometimes referred to as AC to DC converters or squaring subcircuits or cells (e.g., configured to convert an input signal to a DC current). Perform the square function on x x 2 The circuit, where x is equal to the differential signal Vrfp minus Vrfm). 7 is illustrative, wherein the drain terminals of input transistors 110-1 and 110-2 are directly connected to the first power detector output terminal, and wherein the drain terminal of replica input transistor 114 is directly connected to the second power detector output terminal. If desired, the first stacked transistor may alternatively be coupled in series between input transistor 110-1 and the first power detector output terminal, and the second stacked transistor may alternatively be coupled in series between replica input transistor 114 and the second power detector output terminal. Load transistor 122 may have a drain terminal coupled to the first power detector output terminal; a gate terminal coupled to its own drain terminal via resistor 130; and a source terminal coupled to power supply line 106 (e.g., a positive power supply line on which power supply voltage Vdd is provided) via first source resistor 126. Thus, load transistor 122 is coupled in series with first input transistor 110-1 and second input transistor 110-2. Similarly, load transistor 124 may have a drain terminal coupled to the second power detector output terminal; a gate terminal coupled to its own drain terminal via resistor 132; and a source terminal coupled to power supply line 106 via second source resistor 126. Thus, load transistor 124 is coupled in series with replica input transistor 114. Source resistor 126 is optional. Input transistors 110-1 and 110-2 can also be configured to receive the same bias voltage Vbias as replica input transistor 114. The gate terminal of second input transistor 110-2 can be configured to receive bias voltage Vbias via series resistor 163. Resistor 163 is optional. Similarly, the gate terminal of first input transistor 110-1 can be configured to receive bias voltage Vbias via series resistor 162. Resistor 162 is also optional. Bias voltage Vbias can be generated using an associated bias voltage generation circuit including current source 168 and bias transistor 158. Bias transistor 158 can be an NMOS transistor (as an example). Bias transistor 158 may have a drain terminal coupled in series with current source 168, a source terminal coupled to ground supply line 104, and a gate terminal shorted to its own drain terminal. Current source 168 may alternatively be implemented using a current mirror circuit (as an example). Bias transistor 158, with its gate and drain terminals shorted together, may be referred to and defined herein as a "diode-connected" transistor. Configured in this manner, diode-connected bias transistor 158 can provide bias voltage Vbias to the gate terminals of input transistors 110-1 and 110-2, as well as to the gate terminals of replica input transistor 114. In general, other types of bias voltage generating circuits may be employed. The example of FIG. 7 is illustrative, in which transistors 110-1, 110-2, and 114 all receive the same bias voltage Vbias. As another example, replica input transistor 114 may optionally be configured to receive a different bias voltage than input transistors 110-1 and 110-2. As another example, transistors 110-1, 110-2, and 114 may each be configured to receive a different respective bias voltage. As shown in FIG7 , the gate terminal of replica input transistor 114 can serve as common-mode cancellation input port 99 of power detector 70. Configured in this manner, the second harmonic LO voltage V_2LO and other undesirable common-mode leakage / parasitic signals can be coupled from mixer 68 to the gate terminal of replica input transistor 114. In the embodiment of FIG4 , the gate terminal of replica input transistor 114 is shorted to the second terminals of common-mode tap capacitors 90 and 92. In the embodiment of FIG5 , the gate terminal of replica input transistor 114 is shorted to the second (lower) terminals of common-mode tap capacitors 94 and 96. In the embodiment of FIG6 , the gate terminal of replica input transistor 114 is shorted to the second (lower) terminal of capacitor 98. As described above at least in conjunction with FIG. 4 , a common-mode leakage signal (such as 2LO) can leak into the differential input ports of power detector 70, into the gate terminals of input transistors 110-1 and 110-2 (see, for example, leakage path 190). Here, simultaneously feeding the tapped common-mode leakage signal to the gate terminals of replica input transistor 114 results in the generation of identical common-mode leakage signals at the first and second power detector output terminals. Because power detector 70 operates in differential mode, the common-mode leakage signal can be canceled across the differential output ports of power detector 70. This common-mode cancellation scheme is technically advantageous and helps improve the dynamic range and accuracy of power detector 70 across a wide range of process, voltage, and temperature (PVT) variations, which can also improve system calibration accuracy and signal-to-noise ratio. The embodiments of Figures 4-6 are illustrative, in which power detector 70 is coupled to the output port of a receive amplifier. If desired, the common-mode cancellation techniques described herein can also be extended to power detectors having input ports coupled along the transmit path (see, for example, Figure 9 ). As shown in Figure 9 , the transmit components in wireless circuitry 24 may include a mixer 64, an RF amplifier 53, and a transformer 80 coupled between mixer 64 and amplifier 53. RF amplifier 53 may represent a variable gain amplifier (VGA), power amplifier 50 in Figure 3 , or other amplification circuitry along the transmit signal path. Transformer 80 may be coupled between the output port of mixer 64 and the input port of amplifier 53. RF amplifier 53 may be a differential amplifier having differential input ports. Similarly, mixer 64 may be a differential mixing circuit having differential output ports. Transformer 80 may include a primary coil (winding) 82p and a secondary coil (winding) 82s. The primary coil 82p may have opposite (remote) terminals coupled across the differential output ports of the mixer 64. The secondary coil 82s may have opposite (remote) terminals coupled across the differential input ports of the RF amplifier 53. Power detector 70 may have differential inputs coupled to the differential inputs of amplifier 53 via respective coupling capacitors 86 and 88. According to some embodiments, power detector 70 may have separate common-mode cancellation inputs coupled to the differential inputs of detector 70, primary coil 82p (e.g., the common-mode cancellation inputs may be coupled across opposite terminals of primary coil 82p or to the center tap terminal of primary coil 82p), or optionally to secondary coil 82s via one or more adjustable capacitors or resistors. Configured in this manner, common-mode leakage, including the second harmonic LO voltage V_2LO and other undesirable common-mode parasitic signals, can be coupled from mixer 64 to input port 99. The common-mode signal fed into input port 99 of power detector 70 can be used to cancel any undesirable common-mode leakage at the output of power detector 70. Configuring and operating in this manner optimizes the dynamic range of power detector 70. The methods and operations described above in conjunction with Figures 1-9 may be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code used to perform these operations may be stored on non-transitory computer-readable storage media (e.g., tangible computer-readable storage media) stored on one or more components of device 10 (e.g., storage circuitry 16 and / or wireless communication circuitry 24 of Figure 1). Software code may sometimes be referred to as software, data, instructions, program instructions, or program code. Non-transitory computer-readable storage media may include a disk drive, non-volatile memory (such as non-volatile random access memory (NVRAM)), a removable flash drive or other removable media, other types of random access memory, and the like. The software stored on the non-transitory computer-readable storage medium may be executed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless circuitry 24, processing circuitry 18 in FIG. 1 , etc.). The processing circuitry may include a microprocessor, an application processor, a digital signal processor, a central processing unit (CPU), an application-specific integrated circuit (ASIC) having processing circuitry, or other processing circuitry. According to one embodiment, a wireless circuit system is provided, comprising: a radio frequency amplifier; a mixer coupled to the radio frequency amplifier and configured to receive an oscillation signal; and a power detection circuit having an input port coupled to the radio frequency amplifier and a common-mode cancellation input port different from the input port, the common-mode cancellation input port being configured to receive a common-mode leakage signal associated with the oscillation signal. According to another embodiment, the wireless circuit system includes a transformer having a first coil coupled to the radio frequency amplifier and a second coil coupled to the mixer. According to another embodiment, the wireless circuit system includes: a first capacitor coupled between a first output or input terminal of the RF amplifier and the input port of the power detection circuit; and a second capacitor coupled between a second output or input terminal of the RF amplifier and the input port of the power detection circuit. According to another embodiment, the wireless circuit system includes: a third capacitor coupled between the first capacitor and the common-mode cancellation input port of the power detection circuit; and a fourth capacitor coupled between the second capacitor and the common-mode cancellation input port of the power detection circuit. According to another embodiment, the wireless circuit system includes: a third capacitor coupled between a first terminal of the second coil and the common-mode cancellation input port of the power detection circuit; and a fourth capacitor coupled between a second terminal of the second coil and the common-mode cancellation input port of the power detection circuit. According to another embodiment, the wireless circuit system includes a third capacitor coupled between a center tap of the second coil and the common-mode cancellation input port of the power detection circuit. According to another embodiment, the third capacitor has an adjustable capacitance that is fine-tuned to cancel a common-mode leakage signal received at the input port of the power detection circuit. According to another embodiment, the third capacitor has an adjustable capacitance that is fine-tuned to only partially cancel a common-mode leakage signal received at the input port of the power detection circuit. According to another embodiment, the wireless circuit system includes: a resistor coupled between a center tap of the second coil and the common-mode cancellation input port of the power detection circuit, the resistor having an adjustable resistance that is fine-tuned to fully cancel or only partially cancel a common-mode leakage signal received at the input port of the power detection circuit. According to another embodiment, the power detection circuit includes: a first input transistor having a gate terminal coupled to the input port of the power detection circuit; a second input transistor having a gate terminal coupled to the input port of the power detection circuit; a replica input transistor; a first load transistor coupled in series with the first input transistor and the second input transistor; and a second load transistor coupled in series with the replica input transistor. According to another embodiment, the replica input transistor has a gate terminal coupled to the common-mode cancellation input port of the power detection circuit. According to another embodiment, the first input transistor has a first transistor size, the second input transistor has a second transistor size equal to the first transistor size, and the replica input transistor has a third transistor size greater than the first transistor size. According to one embodiment, a circuit system is provided, comprising: a radio frequency amplifier; and a power detection circuit coupled to an output or input port of the radio frequency amplifier, wherein the power detection circuit comprises: a first input transistor coupled to the output or input port of the radio frequency amplifier; a second input transistor coupled to the output or input port of the radio frequency amplifier; and a replica input transistor coupled to a common-mode cancellation input port of the power detection circuit. According to another embodiment, the circuit system includes a mixer coupled to the RF amplifier and configured to receive a local oscillator (LO) signal, the common-mode cancellation input port configured to receive a common-mode leakage signal associated with the LO signal. According to another embodiment, the power detection circuit includes: a first load transistor coupled in series with the first input transistor and the second input transistor; and a second load transistor coupled in series with the replica input transistor. According to another embodiment, the circuit system includes: a transformer coupled to the output or input port of the RF amplifier; and one or more capacitors coupled between the transformer and the common-mode cancellation input port of the power detection circuit. According to another embodiment, the one or more capacitors include an adjustable capacitor or an adjustable resistor that is trimmed to fully cancel or only partially cancel a common-mode leakage signal received at the first input transistor and the second input transistor. According to another embodiment, the transformer includes a primary coil and a secondary coil, and the adjustable capacitor is coupled to a center tap terminal of the secondary coil in the transformer. According to one embodiment, a circuit system is provided, comprising: a passive circuit; a transformer having a first coil coupled to the passive circuit and a second coil; and a power detector having a differential input port coupled to the first coil of the transformer and a common-mode cancellation input port, the common-mode cancellation input port being separate from the differential input port and coupled to a center tap of the first coil of the transformer. According to another embodiment, the power detector includes: a first input transistor having a gate terminal coupled to the differential input port of the power detector; a second input transistor having a gate terminal coupled to the differential input port of the power detector; and a third input transistor having a gate terminal coupled to the common-mode cancellation input port of the power detector. The foregoing is merely illustrative and various modifications may be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination. 10: Electronic device; Device 12: Housing 14: Control circuit system 16: Storage circuit system 18: Processing circuit system; Circuit system 20: Input / output circuit system 22: Input / output device 24: Wireless circuit system; Wireless communication circuit system 26: Processor 28: Radio frequency transceiver; Transceiver; Transceiver circuit system 30: Transmitter circuit; Transmitter circuit system; Transmitter (TX) 32: Receiver circuit; Receiver circuit system; Receiver (RX) 34: Path 36: RF transmission line path; RF transmission line 40: RF front-end module; front-end module (FEM); front end 42: antenna 44: RF filter circuit system; filter circuit system 46: switching circuit system 48: RF amplifier circuit system; amplifier circuit system 50: power amplifier circuit; power amplifier (PA) circuit system; amplifier circuit system; power (transmit) amplifier; amplifier 52: low-noise amplifier circuit; low-noise amplifier (LNA) circuit system; PA circuit system; low-noise (receive) amplifier; receive amplifier circuit system; circuit system; amplifier 53: RF amplifier; receive amplifier; amplifier 55: passive circuit 60: bidirectional 62: digital-to-analog converter (DAC); DAC circuit 64: mixer 66: analog-to-digital converter (ADC); ADC circuit 68: mixer 70: power detector 70-RX: power detector 70-TX: power detector 80: transformer 82p: primary coil (winding) 82s: Secondary coil (winding); 84: Voltage line; 86: Coupling capacitor; Capacitor 88: Coupling capacitor; Capacitor 90: First common-mode tap capacitor; Capacitor 92: Second common-mode tap capacitor; Capacitor 94: First common-mode tap capacitor; Capacitor 96: Second common-mode tap capacitor; Capacitor 98: Common-mode tap capacitor; Capacitor; Adjustable capacitor; 99: Common-mode cancellation input port; Input port; 102-1: AC coupling capacitor; 102-2: Second AC coupling capacitor; 104: Ground line; Ground power line; 106: Power line; 110: Input transistor; 110-1: First input transistor. Transistor 110-2: second input transistor; Transistor 114: replica input transistor; Transistor 122: first load transistor; Load transistor 124: second load transistor; Load transistor 126: source resistor; Resistor 130: Resistor 132: Resistor 158: bias transistor 162: Resistor 163: Resistor 168: current source 190: leakage path; Resistor 192: Ibias: bias current; V_2LO: second harmonic LO voltage; Vbias: bias voltage; Vdd: supply voltage; Voutm: second (minus / negative) power detector output voltage;Differential voltage Voutp: first (positive) power detector output voltage Vrfm: differential voltage Vrfp: first (positive) RF signal; differential voltage Vss: ground voltage; FIG1 is a diagram of an illustrative electronic device having wireless circuitry according to some embodiments. FIG2 is a diagram of an illustrative wireless circuitry having a radio frequency amplifier according to some embodiments. FIG3 is a diagram showing an illustrative power detector coupled to the output of the radio frequency amplifier according to some embodiments. FIG4 is a diagram of an illustrative power detector with a common mode signal tapped at the input port of the power detector according to some embodiments. FIG5 is a diagram of an illustrative power detector with a common mode signal tapped across the terminals of a secondary transformer winding according to some embodiments. FIG6 is a diagram of an illustrative power detector with a common mode signal tapped at the center tap terminal of the secondary transformer winding according to some embodiments. FIG7 is a circuit diagram of an illustrative power detector with a replica input transistor configured to receive a common mode leakage signal according to some embodiments. FIG8 is a diagram of an illustrative power detector with a common mode signal tapped at the center tap terminal of the primary transformer winding according to some embodiments. [ FIG. 9 ] is a diagram of an illustrative power detector coupled to an input port of an RF amplifier according to some embodiments. 24: Wireless circuit system; wireless communication circuit system 26: Processor 30: transmitter circuit; transmitter circuit system; transmitter (TX) 32: Receiver circuit; Receiver circuit system; Receiver (RX) 42: Antenna 50: power amplifier circuit; power amplifier (PA) circuit system; amplifier circuit system 52: Low-noise amplifier circuit; low-noise amplifier (LNA) circuit system 60: Bidirectional 62: Digital to Analog Converter (DAC) 64: Mixer 66: Analog-to-digital converter (ADC) 68: Mixer 70-RX: Power Detector 70-TX: Power Detector

Claims

1. A wireless circuit system comprising: a radio frequency amplifier; a mixer coupled to the radio frequency amplifier and configured to receive an oscillation signal; a transformer coupled to the radio frequency amplifier and the mixer; and a power detection circuit having an input port coupled to the radio frequency amplifier and having a common-mode cancellation input port different from the input port, the common-mode cancellation input port being coupled to the transformer and configured to receive a common-mode leakage signal associated with the oscillation signal.

2. The wireless circuit system of claim 1, wherein the transformer has a first coil coupled to the radio frequency amplifier and a second coil coupled to the mixer.

3. The wireless circuit system of claim 2 further comprises: a first capacitor coupled between a first output or input terminal of the RF amplifier and the input port of the power detection circuit; and a second capacitor coupled between a second output or input terminal of the RF amplifier and the input port of the power detection circuit.

4. The wireless circuit system of claim 3, further comprising: a third capacitor coupled between the first capacitor and the common-mode cancellation input port of the power detection circuit; and a fourth capacitor coupled between the second capacitor and the common-mode cancellation input port of the power detection circuit.

5. The wireless circuit system of claim 3, further comprising: a third capacitor coupled between a first terminal of the second coil and the common-mode cancellation input of the power detection circuit; and a fourth capacitor coupled between a second terminal of the second coil and the common-mode cancellation input of the power detection circuit.

6. The wireless circuit system of claim 3 further includes: a third capacitor coupled between a center tap of the second coil and the common-mode cancellation input port of the power detection circuit.

7. The wireless circuit system of claim 6, wherein the third capacitor has an adjustable capacitor that is finely adjusted to cancel a common-mode leakage signal received at the input port of the power detection circuit.

8. The wireless circuit system of claim 6, wherein the third capacitor has an adjustable capacitance that is finely adjusted to partially cancel a common-mode leakage signal received at the input port of the power detection circuit.

9. The wireless circuit system of claim 3, further comprising: a resistor coupled between a center tap of the second coil and the common-mode cancellation input of the power detection circuit, wherein the resistor has an adjustable resistance that is finely adjusted to completely or only partially cancel a common-mode leakage signal received at the input of the power detection circuit.

10. The wireless circuit system of claim 1, wherein the power detection circuit comprises: a first input transistor having a gate terminal coupled to the input port of the power detection circuit; a second input transistor having a gate terminal coupled to the input port of the power detection circuit; a replica input transistor; a first load transistor coupled in series with the first input transistor and the second input transistor; and a second load transistor coupled in series with the replica input transistor.

11. The wireless circuit system of claim 10, wherein the replica input transistor has a gate terminal coupled to the common-mode cancellation input port of the power detection circuit.

12. The wireless circuit system of claim 11, wherein the first input transistor has a first transistor size, wherein the second input transistor has a second transistor size equal to the first transistor size, and wherein the copy input transistor has a third transistor size greater than the first transistor size.

13. A circuit system comprising: a radio frequency amplifier; and a power detection circuit coupled to an output or input port of the radio frequency amplifier, wherein the power detection circuit includes: A first input transistor coupled to the output or input port of the RF amplifier; a second input transistor coupled to the output or input port of the RF amplifier; a duplicate input transistor coupled to a common-mode cancellation input port of the power detection circuit; a transformer coupled to the output or input port of the RF amplifier; and one or more capacitors coupled between the transformer and the common-mode cancellation input port of the power detection circuit.

14. The circuit system of claim 13 further includes: a mixer coupled to the RF amplifier and configured to receive a local oscillator (LO) signal, wherein the common-mode cancellation input port is configured to receive a common-mode leakage signal associated with the LO signal.

15. The circuit system of claim 13, wherein the power detection circuit further comprises: a first load transistor coupled in series with the first input transistor and the second input transistor; and a second load transistor coupled in series with the replica input transistor.

16. The circuit system of claim 13, wherein the one or more capacitors include an adjustable capacitor or an adjustable resistor, the adjustable capacitor or the adjustable resistor being finely adjusted to completely or only partially cancel a common-mode leakage signal received at the first input transistor and the second input transistor.

17. The circuit system of claim 16, wherein the transformer includes a primary coil and a secondary coil, and wherein the adjustable capacitor is coupled to a center tap terminal of the secondary coil in the transformer.

18. A circuit system comprising: a passive circuit; a transformer having a first coil coupled to the passive circuit and having a second coil; and a power detector having a differential input port coupled to the first coil of the transformer and a common-mode cancellation input port, the common-mode cancellation input port being decoupled from the differential input port and coupled to a center tap of the first coil of the transformer.

19. The circuit system of claim 18, wherein the power detector comprises: a first input transistor having a gate terminal coupled to the differential input port of the power detector; a second input transistor having a gate terminal coupled to the differential input port of the power detector; and a third input transistor having a gate terminal coupled to the common-mode cancellation input port of the power detector.

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