Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure including a substrate, a bit line structure disposed above the substrate, a spacer structure disposed on and extending along the sidewall of the bit line structure, and a bit line contact disposed in each active region and contacting the bottom of the first spacer. The spacer structure includes a first spacer surrounding the sidewall of the bit line structure and a second spacer surrounding the lower portion of the sidewall of the first spacer. The top surface of the first spacer is higher than the top surface of the second spacer. Furthermore, this invention also discloses a method for manufacturing a semiconductor structure.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor structure and its manufacturing method. [Previous Technology]

[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memory (DRAM) are becoming more highly integrated. Furthermore, DRAM performance is improved by reducing the pitch between semiconductor structures within the DRAM. However, the shrinking size of semiconductor structures not only increases the difficulty of the manufacturing process, but also makes the components within the semiconductor structure prone to leakage due to excessively close spacing.

[0003] Therefore, in the semiconductor manufacturing process, how to reduce leakage current in order to improve the process yield of semiconductor structure has become an important issue. [Summary of the Invention]

[0004] Embodiments of this disclosure provide a method for manufacturing a semiconductor structure, comprising the following steps: A substrate is provided, the substrate including a plurality of active regions and a plurality of insulating regions, wherein each insulating region is located between adjacent active regions. Each of a plurality of bit line contacts is formed in each active region, and each of a plurality of bit line structures is formed in each bit line contact. A first oxide layer covering the bit line structures is deposited. A second oxide layer is deposited on the first oxide layer. A photoresist layer is formed to completely cover the second oxide layer. The upper portion of the second oxide layer is removed to expose the upper portion of the first oxide layer.

[0005] In some embodiments, removing the upper portion of the second oxide layer includes the following steps: After forming the photoresist layer, a planarization process is performed on the photoresist layer until the top surface of the second oxide layer is exposed. The upper portion of the second oxide layer is etched to expose the upper portion of the first oxide layer.

[0006] In some embodiments, the method further includes the following steps: After depositing the first oxide layer, two contact spacers are formed, wherein each of the two contact spacers is located on the opposite side of each bit line contact and is surrounded by the first oxide layer.

[0007] In some embodiments, the method further includes the following steps: Removing the photoresist layer; Etching the top of the first oxide layer on each bit line structure until each of the two contact spacers is exposed; After etching the top of the first oxide layer, each bit line structure is shortened in height.

[0008] In some embodiments, after etching the top of the first oxide layer, the top of the first oxide layer and each bit line structure are rounded.

[0009] In some embodiments, after etching the top of the first oxide layer, the stepped profile of the top of the second oxide layer located on the exposed upper portion of the first oxide layer is changed to a smooth tapered profile of the top of the second oxide layer located on the exposed upper portion of the first oxide layer.

[0010] In some embodiments, the method further includes the following steps: After removing the photoresist layer, a first dielectric layer is conformally deposited on each bit line structure, the exposed two-contact spacer, a portion of the active region, and a portion of the insulating region. A sacrificial layer is deposited on the first dielectric layer to completely cover each bit line structure. The top of each bit line structure, the top of the first oxide layer, the top of the first dielectric layer, and the top of the sacrificial layer are removed.

[0011] In some embodiments, after removing the top of each bit line structure, the top surface of each bit line structure, the top surface of the first oxide layer, and the top surface of the first dielectric layer are coplanar.

[0012] In some embodiments, the method further includes the following steps: After removing the top of each bitline structure, the sacrificial layer is removed. A plurality of unit contacts are formed, each unit contact being located between two adjacent bitline structures. The bottom of each unit contact is contacted with each active region.

[0013] In some embodiments, the method further includes the following steps: During the formation of the cell contact, the upper portion of the first dielectric layer, the upper portion of the first oxide layer, and the upper portion of each bit line structure are partially removed. The top of the first dielectric layer, the top of the second oxide layer, the top of the first oxide layer, and the top of each bit line structure collectively form a rocket shape.

[0014] In some embodiments, the method further includes the following steps: forming a plurality of landing pads on each unit contact; forming a second dielectric layer on each bitline structure to separate each landing pad from one another.

[0015] Further embodiments of this disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a bit line structure disposed above the substrate, a spacer structure disposed on and extending along the sidewall of the bit line structure, and a bit line contact disposed in each active region and contacting the bottom of a second spacer. The substrate includes a plurality of active regions and a plurality of insulating regions adjacent to the active regions. The spacer structure includes a first spacer surrounding the sidewall of the bit line structure and a second spacer surrounding the lower portion of the sidewall of the first spacer.

[0016] In some embodiments, the semiconductor structure further includes two contact spacers disposed on opposite sides of the bit line contacts.

[0017] In some embodiments, the first spacer surrounds each of the two contact spacers.

[0018] In some embodiments, the spacer structure further includes a third spacer surrounding the upper portion of the sidewall of the first spacer, the sidewall of the second spacer, and the upper portion of each of the two-contact spacers.

[0019] In some embodiments, the top of the third spacer, the top of the second spacer, the top of the first spacer, and the top of the bit line structure together form a slope.

[0020] In some embodiments, the semiconductor structure further includes a landing pad disposed on top of the bit line structure and covering the slope.

[0021] In some embodiments, the bit line structure includes a bottom cover layer disposed on the bit line contact, a conductive layer disposed on the bottom cover layer, and a top cover layer disposed on the conductive layer. A first spacer surrounds the upper part of the top cover layer, and the first spacer and the second spacer surround the lower part of the top cover layer.

[0022] In some embodiments, the height of the lower part of the top cover layer is greater than the height of the upper part of the top cover layer.

[0023] In some embodiments, the semiconductor structure further includes two-unit contacts disposed on opposite sides of the bit line contacts. Each of the two-unit contacts partially contacts the active region.

Implementation Method

[0025] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0026] Furthermore, for ease of description, spatially related terms such as "above," "over," "below," and "between" may be used in this disclosure to describe the relationship or function of one element or feature to another as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptors used in this disclosure can be interpreted accordingly.

[0027] The terms “including,” “having,” and “containing” used in this disclosure are open-ended terms, meaning including but not limited to.

[0028] It should be noted that when the following figures (e.g., Figures 1 to 11) are illustrated and described as a series of operations or steps, the order in which these operations or steps are described should not be limited. For example, some operations or steps may be performed in a different order than those in this disclosure, or some operations or steps may occur simultaneously, or some operations may be omitted, and / or some operations or steps may be repeated. Furthermore, actual operations or steps in the process stage may be performed before, during, or after the formation of the semiconductor structure (e.g., semiconductor structure 100 in Figure 11) to form the semiconductor structure 100. Therefore, this disclosure may only briefly describe a portion of these additional operations or steps. Moreover, unless otherwise stated, the same interpretations discussed for the following figures (e.g., Figures 1 to 11) can be directly applied to the other figures.

[0029] In the prior art, gaps or seams exist between the cell contacts and the bit line structure, resulting in storage-bit-line leakage (SBLEK). Furthermore, SBLEK worsens with subsequent manufacturing processes. Therefore, embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same to solve the leakage problem caused by gaps or seams between the cell contacts and the bit line structure.

[0030] Please refer to Figures 1 through 3. Figures 1 through 3 are views of a method of fabricating a semiconductor structure according to some embodiments of the present disclosure during the formation of a photoresist layer. In Figure 1, substrate 110 includes a plurality of active regions 112 and a plurality of insulating regions 114. Each insulating region 114 is located between adjacent active regions 112 to isolate the plurality of active regions 112 from each other. In some embodiments, substrate 110 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. Substrate 110 may include elemental semiconductors, such as germanium. In some embodiments, substrate 110 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, indium gallium phosphide, or other suitable materials. In some embodiments, substrate 110 may include compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, in some embodiments, the substrate 110 may optionally have a semiconductor-on-insulator (SOI) structure.

[0031] Next, each of the plurality of bit line contacts BC is formed in each active region 112. Then, each of the plurality of bit line structures BL is formed on each of the plurality of bit line contacts BC. Furthermore, each bit line structure BL includes a bottom cover layer 132 on each bit line contact BC, a conductive layer 134 on the bottom cover layer 132, and a top cover layer 136 on the conductive layer 134.

[0032] Furthermore, two recesses (not shown) are formed on opposite sides of each bitline contact BC. In some embodiments, each of the two recesses exposes the sidewall of each bitline contact BC. A first oxide layer 122 is deposited over the substrate 110 and in the two recesses, covering each bitline structure BL. In some embodiments, the first oxide layer 122 comprises a low-k dielectric material, and the low-k dielectric material has, for example, a low dielectric constant (3.5). In some embodiments, the first oxide layer 122 comprises SiCO. In some embodiments, an insulating layer 120 is formed between the first oxide layer 122 and the substrate 110. In some embodiments, a spacer material layer 124A is formed on the first oxide layer 122 in each of the two recesses. In some embodiments, the spacer material layer 124A comprises SiN. Subsequently, a second oxide layer 142 is deposited on the top surface of the first oxide layer 122 and each of the two spacer material layers 124A. By forming a first oxide layer 122 embedded in the substrate 110 and surrounding each of the two spacer material layers 124A, gaps or gaps between each bit line structure and the subsequently formed cell contacts can be avoided.

[0033] In Figure 2, a photoresist layer 150 is formed to completely cover the second oxide layer 142. Subsequently, in Figure 3, a planarization process is performed to remove the top of the photoresist layer 150 until the top surface TP of the second oxide layer 142 is exposed.

[0034] Please refer to Figures 4 through 6. Figures 4 through 6 are views of a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure during etching of the upper portion of the second oxide layer. In Figure 4, the upper portion of the photoresist layer 150 is removed to expose the upper portion of the second oxide layer 142. In some embodiments, the upper portion of the photoresist layer 150 is removed by an etch-back process.

[0035] In Figure 5, the upper portion of the second oxide layer 142 is removed to expose the upper portion of the first oxide layer 122 on each bit line structure BL. In some embodiments, the upper portion of the second oxide layer 142 on each bit line structure BL is removed by a wet etching process. In some embodiments, the wet etching process is performed using a dilute hydrofluoric acid (DHF) etchant. In some embodiments, as shown in the enlarged view 500 of the dashed box in Figure 5, after removing the upper portion of the second oxide layer 142, a stepped profile SW is formed at the exposed upper portion of the first oxide layer 122.

[0036] In Figure 6, the photoresist layer 150 is removed (as shown in Figure 5). Next, the upper portion of the first oxide layer 122 located on each bit line structure BL is removed until a portion of each of the two spacer material layers 124A is exposed to form two contact spacers 124, and the top of the first oxide layer 122 and each bit line structure BL are rounded. Therefore, after removing the photoresist layer 150, each bit line structure BL is shortened by a height SH1 (as shown in Figure 5). In some embodiments, the top of the first oxide layer 122 is removed by an etching process, such as a dry etching process or a wet etching process, and the top cover layer 136 is substantially not damaged during the removal of the top of the first oxide layer 122. Therefore, the height SH1 is substantially equal to the thickness of the top of the first oxide layer 122. In some embodiments, as shown in the enlarged view 600 of the dashed box in Figure 6, after etching the top of the first oxide layer 122, the stepped profile SW at the top of the second oxide layer 142 on the exposed upper portion of the first oxide layer 122 (as shown in Figure 5) becomes a smooth tapered profile ST at the top of the second oxide layer 142 on the exposed upper portion of the first oxide layer 122. In some embodiments, the height H1 measured from the top surface of the top cover layer 136 to the top surface of the conductive layer 134 is about 120 nanometers (nm). In some embodiments, the height H2 measured from the top of the second oxide layer 142 (after removing the top of the first oxide layer 122) to the top surface of the conductive layer 134 is about 45 nm. In some embodiments, the thickness of the first oxide layer 122 on the sidewall of each bit line structure BL is about between 3 nm and 4 nm, and preferably, the thickness T1 of the first oxide layer 122 on the sidewall of each bit line structure BL is 3.5 nm.

[0037] Please refer to Figures 7 through 9. Figures 7 through 9 are views of a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure during the formation of spacer structures on the sidewalls of each bit line structure. In Figure 7, after the top of the first oxide layer 122 is removed, a first dielectric layer 160 is conformally deposited on each bit line structure BL, each of the two exposed contact spacers 124, a portion of a plurality of active regions 112, and a portion of each insulating region 114. In some embodiments, the first dielectric layer 160 comprises a nitride. The first dielectric layer 160 is configured to protect the first oxide layer 122 and the second oxide layer 142. Specifically, the first dielectric layer 160 is configured such that no gaps or seams are created between each bit line structure BL and each of the two unit contacts, such that the thickness of the first dielectric layer 160 covering each of the two contact spacers 124 is sufficient to avoid damage to the first oxide layer 122 during subsequent etching configured to form the unit contacts (described later). In some embodiments, the thickness T2 of the first dielectric layer 160 on each bit line structure BL is between about 5 nm and 8 nm. In some embodiments, the thickness T3 of the first dielectric layer 160 covering each of the two contact spacers 124 is about 5 nm.

[0038] In Figure 8, a sacrificial layer 170 is deposited on the first dielectric layer 160 to completely cover each bit line structure BL (not shown). In some embodiments, the sacrificial layer 170 comprises a nitride. Then, the top of each bit line structure BL, the top of the first oxide layer 122, the top of the first dielectric layer 160, and the top of the sacrificial layer 170 are removed. In some embodiments, the top of each bit line structure BL, the top of the first oxide layer 122, the top of the first dielectric layer 160, and the top of the sacrificial layer 170 are removed by an etching process (e.g., an etch-back process). Therefore, after the etching process, each bit line structure BL is shortened by a height SH2 (as shown in Figure 7). In some embodiments, the height SH2 is approximately 20 nm. Therefore, after the etching process, the height H1' measured from the top surface of the top capping layer 136 to the top surface of the conductive layer 134 is approximately 100 nm. Furthermore, after the etching process, the top surface of each bit line structure BL, the top surface of the first oxide layer 122, the top surface of the first dielectric layer 160, and the top surface of the sacrificial layer 170 are coplanar. Through the sacrificial layer 170 and the etching process, the first oxide layer 122 on the sidewalls of each bit line structure BL is not lost during the shortening of each bit line structure BL.

[0039] In Figure 9, the sacrificial layer 170 is removed to expose the first dielectric layer 160. In some embodiments, the sacrificial layer 170 is removed by an etching process (e.g., a dry etching process or a wet etching process). Furthermore, after removing the sacrificial layer 170, the top of the first dielectric layer 160 on each bit line structure BL is lost.

[0040] Please refer to Figures 10 and 11. Figures 10 and 11 are views of a method of manufacturing a semiconductor structure according to some embodiments of the present disclosure during the formation of a plurality of unit contacts and a plurality of landing pads. In Figure 10, a plurality of openings (not shown) are formed on opposite sides of each bit line contact BC in substrate 110 to expose the sides of each of the two contact spacers 124, respectively. In some embodiments, the openings are formed by an etching process (e.g., a dry etching process or a wet etching process). Subsequently, a conductive material is formed in each opening to completely cover each bit line structure BL. Then, the top portion of the conductive material is removed by an etch-back process (e.g., a RIE process) to form a plurality of unit contacts CC, each unit contact CC being adjacent to each of the two contact spacers 124. Specifically, each unit contact CC is formed on opposite sides of the conductive layer 134 of each bit line structure BL. In addition, during the removal of the upper part of the conductive material, the top of each bit line structure BL is removed at a height of SH3 (as shown in Figure 9).

[0041] Additionally, during the formation of the unit contact CC, the upper portion of the first dielectric layer 160, the upper portion of the first oxide layer 122, and the upper portion of each bit line structure BL are partially removed. In some embodiments, after the partial removal of the upper portion of the first dielectric layer 160, the upper portion of the first oxide layer 122, and the upper portion of each bit line structure BL during the formation of the unit contact CC, the top of the first dielectric layer 160, the top of the second oxide layer 142, the top of the first oxide layer 122, and the top of each bit line structure BL collectively form a rocket shape. In some embodiments, after the formation of the unit contact CC, the top of the first dielectric layer 160, the top of the second oxide layer 142, the top of the first oxide layer 122, and the top of each bit line structure BL collectively form a slope SL. Furthermore, after removing the sacrificial layer 170, a spacer structure SP including the first oxide layer 122, the second oxide layer 142, and the first dielectric layer 160 is formed. In this way, by removing the top of the conductive material and the top of each bit line structure BL, damage to the top of the first oxide layer 122 on each bit line structure BL can be avoided when removing the sacrificial layer.

[0042] In Figure 11, a landing pad material is formed on each unit contact CC, with the top surface of the landing pad material higher than the top surface of each bitline structure BL. Subsequently, the landing pad material is etched to form a plurality of openings (not shown), and a plurality of landing pads LP are formed on top of each bitline structure BL, covering the slope SL. In some embodiments, during the formation of the openings, a portion of each bitline structure BL and each spacer structure SP may be removed. Then, a second dielectric layer 180 is formed in each opening to separate each landing pad LP from each other.

[0043] As shown in Figure 11, the embodiments disclosed herein also provide a semiconductor structure 100. The semiconductor structure 100 includes a substrate 110, a bit line structure BL disposed above the substrate 110, and a spacer structure SP disposed on and extending along the sidewalls of the bit line structure BL. The substrate 110 includes a plurality of active regions 112 and a plurality of insulating regions 114, each insulating region 114 being located between adjacent active regions 112 to separate the active regions 112 from each other. The spacer structure SP includes a first spacer 122 surrounding the sidewalls of the bit line structure BL and a second spacer 142 surrounding the lower portion of the sidewalls of the first spacer 122. Additionally, the semiconductor structure 100 includes bit line contacts BC disposed in each active region 112 and contacting the bottom of the second spacer 142. Furthermore, the top surface of the first spacer 122 is higher than the top surface of the second spacer 142.

[0044] In some embodiments, the semiconductor structure 100 further includes two contact spacers 124 disposed on opposite sides of the bit line contact BC. In some embodiments, a first spacer 122 surrounds each contact spacer 124. In some embodiments, the spacer structure SP further includes a third spacer 160 surrounding the upper portion of the sidewall of the first spacer 122, the sidewall of the second spacer 142, and the upper portion of each of the two contact spacers 124. In some embodiments, the top of the third spacer 160, the top of the second spacer 142, the top of the first spacer 122, and the top of the bit line structure BL collectively form a slope SL. In other words, the slope SL refers to a curved surface formed on the common top surface of each bit line structure BL, the first oxide layer 122, and the first dielectric layer 160. In some embodiments, the semiconductor structure 100 further includes a landing pad LP disposed on the top of the bit line structure BL and covering the slope SL.

[0045] Furthermore, the bit line structure BL includes a bottom cover layer 132 disposed on the bit line contact BC, a conductive layer 134 disposed on the bottom cover layer 132, and a top cover layer 136 disposed on the conductive layer 134. A first spacer 122 surrounds the upper portion of the top cover layer 136, and a first spacer 122 and a second spacer 142 surround the lower portion of the top cover layer 136. In some embodiments, the height H3 of the lower portion of the top cover layer 136 (as shown in Figure 10) is greater than the height H4 of the upper portion of the top cover layer 136 (as shown in Figure 10). In some embodiments, the semiconductor structure 100 further includes two unit contacts CC disposed on opposite sides of the bit line contact BC, and each of the two unit contacts CC partially contacts each active region 112.

[0046] In summary, through the embodiments disclosed herein, gaps or slits can be prevented between each bit line structure and each of the two unit contacts, thereby improving the leakage current problem of the semiconductor structure. Furthermore, damage to the top of each bit line structure during manufacturing can be avoided, thus preventing damage to the semiconductor structure.

[0047] Although some embodiments of this disclosure have been described in considerable detail, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

[0048] The foregoing has provided a brief overview of the features of several embodiments in this disclosure, enabling those skilled in the art to more readily understand this disclosure. Anyone skilled in the art should understand that this disclosure can easily serve as a basis for changes or designs to other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments disclosed herein. Anyone skilled in the art will also understand that equivalent structures as described above do not depart from the spirit and scope of this disclosure, and that modifications, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0024] The following embodiments are read in conjunction with the accompanying drawings for a clear understanding of the viewpoints of this disclosure. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for clear discussion. Figures 1 to 3 are views of the method of manufacturing a semiconductor structure according to some embodiments of this disclosure during the formation of a photoresist layer; Figures 4 to 6 are views of the method of manufacturing a semiconductor structure according to some embodiments of this disclosure during the etching of the upper portion of the second oxide layer; Figures 7 to 9 are views of the method of manufacturing a semiconductor structure according to some embodiments of this disclosure during the formation of spacer structures on the sidewalls of each bit line structure; and Figures 10 and 11 are views of the method of manufacturing a semiconductor structure according to some embodiments of this disclosure during the formation of a plurality of unit contacts and a plurality of landing pads. [Biomaterial Storage]

[0050] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, the substrate including a plurality of active regions and a plurality of insulating regions, wherein each insulating region is located between adjacent active regions; each of the plurality of bit line contacts is formed in each of the active regions, and each of the plurality of bit line structures is formed in each of the bit line contacts; a first oxide layer is deposited covering the bit line structures; a second oxide layer is deposited on the first oxide layer, wherein each bit line structure includes: a bottom capping layer disposed on the bit line contact; a conductive layer disposed on the bottom capping layer; and a top capping layer disposed on the conductive layer, wherein the first oxide layer surrounds an upper portion of the top capping layer, and the first oxide layer and the second oxide layer surround a lower portion of the top capping layer; a photoresist layer is formed to completely cover the second oxide layer; and an upper portion of the second oxide layer is removed to expose an upper portion of the first oxide layer.

2. The method as described in claim 1, wherein removing the upper portion of the second oxide layer comprises: After the photoresist layer is formed, a planarization process is performed on the photoresist layer until a top surface of the second oxide layer is exposed. And etching the upper part of the second oxide layer to expose the upper part of the first oxide layer.

3. The method as described in claim 1, further comprising: After the first oxide layer is deposited, two contact spacers are formed, wherein each contact spacer is located on the opposite side of each bit line contact and is surrounded by the first oxide layer.

4. The method as described in claim 3, further comprising: Remove the photoresist layer; And etching a top of the first oxide layer on each of the bit line structures until each of the contact spacers is exposed, wherein after etching the top of the first oxide layer, each of the bit line structures is shortened by a height.

5. The method as described in claim 4, wherein after etching the top of the first oxide layer, the top of the first oxide layer and each of the bit line structures are rounded.

6. The method as described in claim 4, wherein after etching the top of the first oxide layer, a stepped profile of the top of the second oxide layer located on the exposed upper portion of the first oxide layer is transformed into a smooth tapered profile of the top of the second oxide layer located on the exposed upper portion of the first oxide layer.

7. The method as described in claim 4, further comprising: After removing the photoresist layer, a first dielectric layer is conformally deposited on each bit line structure, the exposed contact spacers, a portion of the active regions, and a portion of the insulating regions; a sacrificial layer is deposited on the first dielectric layer to completely cover each bit line structure; and a top of each bit line structure, a top of the first oxide layer, a top of the first dielectric layer, and a top of the sacrificial layer are removed.

8. The method as described in claim 7, wherein after removing the top of each bit line structure, a top surface of each bit line structure, a top surface of the first oxide layer, and a top surface of the first dielectric layer are coplanar.

9. The method as described in claim 7, further comprising: After removing the top of each bit line structure, remove the sacrificial layer; And forming a plurality of unit contacts, each of which is located between two adjacent units of the bit line structure, wherein a bottom of each unit contact is in contact with the active region.

10. The method as described in claim 9, further comprising: During the formation of these unit contacts, a portion of the upper part of the first dielectric layer, the upper part of the first oxide layer, and the upper part of each of the bit line structures are partially removed, wherein the top of the first dielectric layer, a top of the second oxide layer, the top of the first oxide layer, and the top of each of the bit line structures together form a rocket shape.

11. The method as described in claim 10, further comprising: Multiple landing pads are formed on each of the unit contacts; And a second dielectric layer is formed on each of the bit line structures to separate each of the landing pads from each other.

12. A semiconductor structure, comprising: A substrate includes a plurality of active regions and a plurality of insulating regions adjacent to the active regions; a bit line structure is disposed above the substrate; A spacer structure is disposed on one sidewall of a bitline structure and extends along the sidewall of the bitline structure, wherein the spacer structure includes: a first spacer surrounding the sidewall of the bitline structure; and a second spacer surrounding a lower portion of the sidewall of the first spacer, wherein a top surface of the first spacer is higher than a top surface of the second spacer; and a bitline contact disposed in each of the active regions and contacting a bottom of the first spacer, wherein the bitline structure includes: a bottom cover layer disposed on the bitline contact; a conductive layer disposed on the bottom cover layer; and a top cover layer disposed on the conductive layer, wherein the first spacer surrounds an upper portion of the top cover layer, and the first spacer and the second spacer surround a lower portion of the top cover layer.

13. The semiconductor structure as described in claim 12, further comprising: Two contact spacers are disposed on the opposite side of the bit line contact.

14. The semiconductor structure as described in claim 13, wherein the first spacer surrounds each of the contact spacers.

15. The semiconductor structure as described in claim 13, wherein the spacer structure further comprises: A third spacer surrounds an upper portion of the sidewall of the first spacer, a sidewall of the second spacer, and an upper portion of each of the contact spacers.

16. The semiconductor structure as claimed in claim 15, wherein a top of the third spacer, a top of the second spacer, a top of the first spacer, and a top of the bit line structure together form a slope.

17. The semiconductor structure as described in claim 16, further comprising: A landing pad is placed on top of the bit line structure and covers the slope.

18. The semiconductor structure as claimed in claim 12, wherein the height of the lower portion of the top cover layer is greater than the height of the upper portion of the top cover layer.

19. The semiconductor structure as described in claim 12, further comprising: Two unit contacts are provided on the opposite side of the bit line contact, wherein each unit contact partially contacts the respective active area.

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