Semiconductor device and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor device includes: providing a substrate having a doped region; forming a first trench in the doped region of the substrate; conformally forming a first dielectric layer in the first trench; conformally forming a first barrier layer in the first trench and on the first dielectric layer; filling a first conductive structure in the first trench and on the first barrier layer; partially removing the first conductive structure to form a second trench; forming a second barrier layer on the first conductive structure and in the second trench; conformally forming a second dielectric layer in the second trench and on the second barrier layer; and filling a second conductive structure in the second trench and on the second dielectric layer.

Description

Semiconductor Device and Method for Manufacturing the Same The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a transistor and a method for manufacturing the same. Dynamic random access memory (DRAM) is a volatile memory. Due to the architecture and design of the components, there are various leakage mechanisms, resulting in the loss of potential within the memory cell. In a transistor, gate-induced drain leakage (GIDL) has a great impact on the reliability of the semiconductor device and will have a negative impact on the dynamic random access memory, thereby resulting in poor quality of the dynamic random access memory. Therefore, how to replace the traditional semiconductor device and its manufacturing method, and thereby solve the problem of gate-induced drain leakage, has become one of the important issues. In view of this, an object of the present invention is to provide a method for manufacturing a semiconductor device, which includes: providing a substrate, wherein the substrate has a doped region; forming a first groove in the doped region of the substrate; conformally forming a first dielectric layer in the first groove; conformally forming a first barrier layer in the first groove and on the first dielectric layer; filling a first conductive structure in the first groove and on the first barrier layer; partially removing the first conductive structure to form a second groove; forming a second barrier layer on the first conductive structure and in the second groove; conformally forming a second dielectric layer in the second groove and on the second barrier layer; and filling a second conductive structure in the second groove and on the second dielectric layer. In some embodiments of the present invention, the work function of the second conductive structure is less than the work function of the first conductive structure. In some embodiments of the present invention, the first dielectric layer surrounds the second dielectric layer, and the first dielectric layer is laterally in contact with the second dielectric layer. In some embodiments of the present invention, the manufacturing method further includes: partially removing the second conductive structure to form a third groove; and filling an insulating capping in the third groove. In some embodiments of the present invention, the manufacturing method further includes: partially removing the second conductive structure to form a third groove; conformally forming a third dielectric layer in the third groove; and filling an insulating capping in the third groove and on the third dielectric layer. In some embodiments of the present invention, the second dielectric layer is laterally in contact with the third dielectric layer. In some embodiments of the present invention, the first dielectric layer and the second dielectric layer form a gate dielectric structure with an increasing thickness upwards. In some embodiments of the present invention, the thickness of a portion of the gate dielectric structure above the second barrier layer is greater than the thickness of the portion of the gate dielectric structure below the second barrier layer. In some embodiments of the present invention, forming the second barrier layer on the first conductive structure further includes: conformally forming a barrier structure in the second groove; and laterally removing an upper sidewall portion of the barrier structure to form the second barrier layer. In some embodiments of the present invention, forming the second barrier layer on the first conductive structure further includes: conformally forming a barrier structure in the second groove; laterally removing an upper sidewall portion of the barrier structure to form the second barrier layer; and laterally thinning an upper sidewall portion of the first dielectric layer. In some embodiments of the present invention, the first dielectric layer includes a bottom and an upper sidewall portion, the upper sidewall portion is located above the bottom, and the thickness of the upper sidewall portion of the first dielectric layer is less than the thickness of the bottom of the first dielectric layer. Another object of the present invention is to provide a semiconductor device, which includes a substrate, a first conductive structure, a second conductive structure, a gate dielectric structure, a first barrier layer, and a second barrier layer. The substrate includes a source region and a drain region, and the first conductive structure is located between the source region and the drain region. The second conductive structure is located on the first conductive structure. The gate dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer surrounds the first conductive structure and the second conductive structure, the second dielectric layer is partially located between the first conductive structure and the second conductive structure, and the second dielectric layer surrounds the second conductive structure, wherein the first dielectric layer is in lateral contact with the second dielectric layer. The first barrier layer is located between the first conductive structure and the first dielectric layer. The second barrier layer is located between the first conductive structure and the second dielectric layer. In some embodiments of the present invention, the work function of the second conductive structure is less than the work function of the first conductive structure. In some embodiments of the present invention, the semiconductor device further includes a third dielectric layer, wherein the third dielectric layer is located on the second conductive structure. In some embodiments of the present invention, the semiconductor device further includes a third dielectric layer and an insulating capping layer. The third dielectric layer is located on the second conductive structure, the third dielectric layer is partially located between the second conductive structure and the insulating capping layer, and the third dielectric layer surrounds the insulating capping layer. In some embodiments of the present invention, the second dielectric layer is in lateral contact with the third dielectric layer. In some embodiments of the present invention, the third dielectric layer has a U-shaped cross-section. In some embodiments of the present invention, the inner wall of the first dielectric layer is trapezoidal. In some embodiments of the present invention, the thickness of a portion of the gate dielectric structure above the second barrier layer is greater than the thickness of the portion of the gate dielectric structure below the second barrier layer. In summary, the present invention provides a transistor device, whose gate structure is formed by stacking multiple dielectric layers, wherein the multiple dielectric layers are generally tubular, conical, cylindrical or test-tube shaped, so the gate structure has a gradually increasing thickness. When the transistor structure of the present invention is applied to a dynamic random access memory, it can effectively suppress gate-induced drain leakage current. In addition, a part of the thickness of the gate dielectric structure of the transistor of the present invention is relatively thin, so the channel current, standard threshold voltage can be increased, and the subthreshold swing can be improved, thereby enhancing the gate control ability. The gate metal of the transistor device of the present invention is protected by multiple barrier layers, so the negative impact of the diffusion mechanism induced in the semiconductor manufacturing process can be effectively suppressed, thereby improving the product quality. The above is only used to illustrate the problems to be solved by the present invention, the technical means for solving the problems, and the effects produced thereby, etc. The specific details of the present invention will be introduced in detail in the following embodiments and related drawings. The following will disclose multiple embodiments of the present invention in the drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings. Please refer to FIG. 1. FIG. 1 illustrates a manufacturing method 100 of a semiconductor device 200 (please refer to FIG. 11) in some embodiments of the present invention. The manufacturing method 100 starts from step 110, which includes providing a substrate having a doped region. Then, the manufacturing method 100 proceeds to step 120, which includes forming a first groove in the doped region of the substrate. Then, the manufacturing method 100 proceeds to step 130, where step 130 includes conformally forming a first dielectric layer in the first groove. Then, the manufacturing method 100 proceeds to step 140, which includes filling a first conductive structure in the first groove and on the first dielectric layer. Then, the manufacturing method 100 proceeds to step 150, which includes partially removing the first conductive structure to form a second groove. Then, the manufacturing method 100 proceeds to step 160, which includes conformally forming a second dielectric layer in the second groove. Then, the manufacturing method 100 proceeds to step 170, which includes filling a second conductive structure in the second groove and on the second dielectric layer, where the work function of the second conductive structure is less than that of the first conductive structure. Then, the manufacturing method 100 proceeds to step 180, which includes partially removing the second conductive structure and forming a third groove, and filling an insulating capping in the third groove. In this specification, conformally forming a certain layered structure (single-layer or multi-layer structure) means generating a layered structure with a uniform thickness along a specific shape, so the formed layered structure has a specific corresponding shape. Please refer to FIGS. 1 and 2, where FIG. 2 can be used to represent step 110 of the manufacturing method 100, and step 110 includes providing a substrate 210 having a doped region 211. The substrate 210 may include a semiconductor material (such as silicon) or a compound semiconductor material, and the compound semiconductor material includes silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide. The doped region 211 includes a p-type doped region 212 and an n-type doped region 213, where the n-type doped region 213 is located above the p-type doped region 212. In addition, the doped region 211 further includes an n-type lightly doped region 213a, where the n-type lightly doped region 213a is adjacent to and above the p-type doped region 212. Specifically, the p-type doped region 212 is doped with boron, gallium, indium, or other suitable dopants in Group III (III) of the periodic table, and the n-type doped region 213 is doped with arsenic, phosphorus, and other suitable dopants in Group V (V) of the periodic table. In addition, the dopant concentration of the n-type lightly doped region 213a is lower than that of other regions of the n-type doped region 213. Please refer to FIG. 1 and FIG. 3, where FIG. 3 can be used to represent steps 120, 130, and 140 of manufacturing method 100. In some embodiments of the present invention, step 120 includes forming a first groove 214 in the doped region 211 (please refer to FIG. 2) of the substrate 210, thereby forming a source region 215 and a drain region 216, where the source region 215 includes a p-type region 215a and an n-type region 215b, where the n-type region 215b is located above the p-type region 215a, and the n-type region 215b may further include an n-type lightly doped region 215c, and the n-type lightly doped region 215c is adjacent to the p-type region 215a. The first groove 214 may be formed by a dry etching process, such as reactive-ion etching (RIE) or other suitable dry etching processes, and the present invention is not limited thereto. In addition, the drain region 216 includes a p-type region 216a and an n-type region 216b, where the n-type region 216b is located above the p-type region 216a, and the n-type region 216b may further include an n-type lightly doped region 216c, and the n-type lightly doped region 216c is adjacent to the p-type region 216a. It should be noted that the dopant concentration of the n-type lightly doped region 215c is lower than the dopant concentration of the n-type region 215b, and the dopant concentration of the n-type lightly doped region 216c is lower than the dopant concentration of the n-type region 216b, where the settings of the n-type lightly doped region 215c and the n-type lightly doped region 216c help to improve the gate leakage current problem. In some embodiments of the present invention, step 130 of manufacturing method 100 includes conformally forming a first dielectric layer 221 in the first groove 214, where the first dielectric layer 221 may be formed by oxidizing a part of the substrate 210 (e.g., the inner wall of the first groove 214), and the first dielectric layer 221 is generally tubular, conical, cylindrical, or test-tube-shaped and has a single opening. Specifically, the first dielectric layer 221 is manufactured by an in-situ steam generation (ISSG) process, thereby obtaining a first dielectric layer 221 with excellent properties. However, the first dielectric layer 221 may also be manufactured by atomic layer deposition (ALD) or inductively coupled plasma-chemical vapor deposition (ICP-CVD), and the present invention is not limited thereto. In some embodiments, the first dielectric layer 221 may include silicon oxide (SiO 2 ), hafnium oxide (HfO 2 ), lanthanum oxide (La 2O 3 ) Zirconium oxide (ZrO 2 ), barium oxide (BaO), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), strontium oxide (SrO), yttrium oxide (Y2O 3 ), hafnium silicate (HfSiO 4 ), zirconium silicate (ZrSiO 4 ), aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO) or calcium oxide (CaO), and the present invention is not limited thereto. In some embodiments of the present invention, step 140 of manufacturing method 100 includes filling the first conductive structure 231 in the first groove 214 and on the first dielectric layer 221. Specifically, a chemical mechanical polishing (CMP) process can be performed on the substrate 210, the first dielectric layer 221, the first conductive structure 231, and the first barrier layer 241 such that the top surfaces of the first dielectric layer 221, the first conductive structure 231, the first barrier layer 241, and the substrate 210 are flush. In addition, the first conductive structure 231 can include ruthenium, palladium, platinum, tungsten, cobalt, nickel, hafnium, zirconium, titanium, tantalum, aluminum, and / or conductive metal oxides and conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide). In addition, the first conductive structure 231 can be formed by chemical vapor deposition (CVD), sputtering, or other suitable methods. In some embodiments, a first barrier layer 241 is conformally formed on the first dielectric layer 221 before forming the first conductive structure 231. In addition, the first barrier layer 241 can include titanium, titanium nitride (TiN, TiN 2 ), tantalum, or tantalum nitride, etc., and the first barrier layer 241 can be manufactured by processes such as physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition, etc. The setting of the first barrier layer 241 helps to prevent the first conductive structure 231 and the surrounding structures from being affected by the diffusion mechanism, thereby improving the product quality. Please refer to FIG. 1 and FIG. 4. In some embodiments of the present invention, step 150 of manufacturing method 100 includes partially removing the first conductive structure 231 and the first barrier layer 241 to form a second groove 217. Specifically, the second groove 217 may be formed by a dry etching process, such as reactive ion etching or other suitable dry etching processes, and the present invention is not limited thereto. Please refer to FIG. 1, FIGS. 5 to 7. In some embodiments of the present invention, step 160 of manufacturing method 100 includes conformally forming a second dielectric layer 223 in the second groove 217, wherein the first dielectric layer 221 surrounds the second dielectric layer 223, and the first dielectric layer 221 is laterally in contact with the second dielectric layer 223. In addition, in step 160, after forming the first conductive structure 231, a second barrier layer 243 is further formed on the first conductive structure 231. In some embodiments, forming the second barrier layer 243 on the first conductive structure 231 further includes: conformally forming a barrier structure 242 in the second groove 217; and laterally removing the upper sidewall portion 242a of the barrier structure 242 to form the second barrier layer 243. The barrier structure 242 and the second barrier layer 243 may include titanium, titanium nitride (TiN, TiN 2 )), tantalum, tantalum nitride, etc., and the barrier structure 242 may be manufactured by processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc., and the present invention is not limited thereto. Thereby, the first barrier layer 241 and the second barrier layer 243 jointly coat the first conductive structure 231, thus helping to avoid the first conductive structure 231 and the surrounding structures from being affected by the diffusion mechanism, and further improving the product quality. In addition, the cross-section of the barrier structure 242 is generally U-shaped and includes an upper sidewall portion 242a and a bottom portion 242b, wherein the upper sidewall portion 242a extends upward from the outer periphery of the bottom portion 242b. Specifically, laterally removing the upper sidewall portion 242a of the barrier structure 242 may include performing an etching process (e.g., a dry etching process, a wet etching process, or a gas etching process) on the barrier structure 242, and the bottom portion 242b of the barrier structure 242 may also be partially removed by the aforementioned etching process, and the remaining portion of the barrier structure 242 forms the second barrier layer 243. In addition, the etching process performed on the barrier structure 242 also thins and laterally partially removes the first dielectric layer 221, thereby forming an upper sidewall portion 221a of the first dielectric layer 221, wherein the thickness T1 of the upper sidewall portion 221a of the first dielectric layer 221 is less than the thickness T2 of other portions of the first dielectric layer 221. Specifically, the first dielectric layer 221 is generally tubular, conical, cylindrical, or test-tube-shaped and has a single opening, wherein the first dielectric layer 221 has a U-shaped cross-section. In addition, the first dielectric layer 221 further includes a bottom portion 221b, and the upper sidewall portion 221a is located above the bottom portion 221b, wherein the thickness T1 of the upper sidewall portion 221a is less than the thickness T2 of the bottom portion 221b of the first dielectric layer 221. In addition, the bottom portion 221b is generally tubular, conical, cylindrical, or test-tube-shaped and has a single opening, and the upper sidewall portion 221a extends upward along the outer periphery of the bottom portion 221b, so the inner wall of the first dielectric layer 221 presents a stepped shape. In addition, a chemical mechanical polishing process may be performed on the substrate 210, the first dielectric layer 221, and the barrier structure 242, such that the top surface of the first dielectric layer 221, the top surface of the barrier structure 242, and the top surface of the substrate 210 are flush. In FIG. 7, the second dielectric layer 223 is conformally formed in the second groove 217, wherein the second dielectric layer 223 is generally tubular, conical, cylindrical, or test-tube-shaped and has a single opening, and the second dielectric layer 223 has a U-shaped cross-section, wherein the first dielectric layer 221 surrounds the second dielectric layer 223, and the inner sidewall surface of the first dielectric layer 221 laterally contacts the outer sidewall surface of the second dielectric layer 223. The second dielectric layer 223 may also be manufactured by an in-situ vapor generation process, an atomic layer deposition process, or a high-density plasma chemical vapor deposition process, and the second dielectric layer 223 may include silicon oxide (SiO 2 ), hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), zirconium oxide (ZrO 2 ), barium oxide (BaO), titanium oxide (TiO 2 ) tantalum oxide (Ta 2 O 5 ), strontium oxide (SrO), yttrium oxide (Y2O 3 ), hafnium silicate (HfSiO 4 ), zirconium silicate (ZrSiO 4 ), aluminum oxide (Al 2 O 3 ), magnesium oxide (MgO) or calcium oxide (CaO), and the present invention is not limited thereto. Please refer to FIG. 1 and FIG. 8. FIG. 8 can be used to represent step 170 of manufacturing method 100. Step 170 includes filling a second conductive structure 233 in a second groove 217 and on a second dielectric layer 223, wherein the work function of the second conductive structure 233 is less than that of the first conductive structure 231. In addition, the second conductive structure 233 may include doped polysilicon, ruthenium, palladium, platinum, tungsten, cobalt, nickel, hafnium, zirconium, titanium, tantalum, aluminum, and / or conductive metal oxides and conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide). When the second conductive structure 233 is doped polysilicon, the second conductive structure 233 includes polysilicon and a dopant, and the dopant may be the aforementioned n-type dopant or p-type dopant, but the present invention is not limited thereto. In addition, a chemical mechanical polishing process may be performed on the substrate 210 and the second conductive structure 233 such that the top surfaces of the first dielectric layer 221, the barrier structure 242, and the substrate 210 are flush. Please refer to FIG. 1, FIGS. 9 to 11. FIGS. 9 to 11 can be used to illustrate step 180 of manufacturing method 100. In some embodiments of the present invention, step 180 includes: partially removing the second conductive structure 233 to form a third groove 219; and filling the third groove 219 with an insulating capping 251. In addition, the insulating capping 251 is located directly above the first conductive structure 231 and the second conductive structure 233 and protects the first conductive structure 231 and the second conductive structure 233. In some other embodiments of the present invention, step 180 of manufacturing method 100 may further include: conformally forming a third dielectric layer 225 in the third groove 219 before filling the insulating capping 251; and filling the insulating capping 251 in the third groove 219 and on the third dielectric layer 225, such that the third dielectric layer 225 is partially located between the second conductive structure 233 and the insulating capping 251, wherein the insulating capping 251 is located directly above the first conductive structure 231 and the second conductive structure 233 and protects the first conductive structure 231 and the second conductive structure 233. In addition, a chemical mechanical polishing process may be performed on the substrate 210 and the insulating capping 251, such that the top surface of the insulating capping 251 is flush with the top surface of the substrate 210. Please refer to FIG. 9. FIG. 9 can be used to illustrate partially removing the second conductive structure 233 to form a third groove 219. The third groove 219 may be formed by a dry etching process, such as reactive ion etching or other suitable dry etching processes, which is not limited in the present invention. Please refer to FIG. 10. FIG. 10 can be used to illustrate conformally forming a third dielectric layer 225 in the third groove 219. The third dielectric layer 225 is located on the second dielectric layer 223. The third dielectric layer 225 is generally tubular, conical, cylindrical or test tube-shaped and has a single opening. Therefore, the third dielectric layer 225 has a U-shaped cross section, wherein the inner surface of the second dielectric layer 223 laterally contacts the outer surface of the third dielectric layer 225, such that the second dielectric layer 223 surrounds the second conductive structure 233 and the third dielectric layer 225. The third dielectric layer 225 may also be made by atomic layer deposition or high density plasma chemical vapor deposition, and the third dielectric layer 225 may include silicon oxide (SiO 2 ), hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), zirconium oxide (ZrO 2 ), barium oxide (BaO), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ) Strontium oxide (SrO), yttrium oxide (Y2O 3 ) Hafnium silicate (HfSiO 4 ) Zirconium silicate (ZrSiO 4 ) Aluminum oxide (Al 2 O 3 ) Magnesium oxide (MgO) or calcium oxide (CaO), and the present invention is not limited thereto. In addition, a chemical mechanical polishing process may be performed on the substrate 210 and the third dielectric layer 225 such that the top surface of the third dielectric layer 225 is flush with the top surface of the substrate 210. Please refer to FIG. 11. FIG. 11 can be used to show that an insulating capping 251 is filled in the third groove 219. The insulating capping 251 may be manufactured by a chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a plasma enhanced chemical vapor deposition process, wherein the insulating capping 251 includes silicon nitride (Si 3 N 4 ) or silicon oxynitride (Si 2 ON 2 ), but the present invention is not limited thereto. Referring to FIG. 11, another object of the present invention is to provide a semiconductor device 200, which includes a substrate 210, a first conductive structure 231, a second conductive structure 233, a first dielectric layer 221, and a second dielectric layer 223. The substrate 210 includes a source region 215 and a drain region 216. The first conductive structure 231 is located between the source region 215 and the drain region 216. The second conductive structure 233 is located on the first conductive structure 231 and between the source region 215 and the drain region 216. In addition, the first dielectric layer 221 surrounds the first conductive structure 231 and the second conductive structure 233. The second dielectric layer 223 is partially located between the first conductive structure 231 and the second conductive structure 233, and the second dielectric layer 223 surrounds the second conductive structure 233 but does not surround the first conductive structure 231, wherein the inner sidewall of the first dielectric layer 221 is more laterally in contact with the outer sidewall of the second dielectric layer 223. In some embodiments, the work function of the second conductive structure 233 is less than the work function of the first conductive structure 231. Thus, the first conductive structure 231 and the second conductive structure 233 serve as gate conductors, and the first dielectric layer 221 and the second dielectric layer 223 form a gate dielectric structure with an increasing thickness upwards, thereby suppressing gate-induced drain leakage current. It can be seen that the semiconductor device 200 of the present invention can be a transistor device, which can be used in a dynamic random access memory and effectively reduce the problems caused by gate-induced drain leakage current. In addition, the thickness of the gate dielectric structure around the first conductive structure 231 is relatively thin, so the channel current, the standard voltage threshold (SVT), and the subthreshold swing can be improved, thereby enhancing the gate control ability. In some embodiments of the present invention, the first dielectric layer 221 and the second dielectric layer 223 are generally tubular, conical, cylindrical or test-tube shaped and have a single opening, and the first dielectric layer 221 and the second dielectric layer 223 have a U-shaped cross-section. In addition, the first dielectric layer 221 includes an upper sidewall portion 221a and a bottom 221b, and the upper sidewall portion 221a is located above the bottom 221b, wherein the thickness T1 of the upper sidewall portion 221a is less than the thickness T2 of the bottom 221b of the first dielectric layer 221, the thickness T1 of the upper sidewall portion 221a is less than 5 nm, and the thickness T2 of the bottom 221b is less than or equal to 5 nm. In some embodiments, the thickness T1 of the upper sidewall portion 221a is less than 4.5 nm, and the thickness T2 of the bottom 221b is less than or equal to 4.5 nm. Specifically, the bottom 221b is generally tubular, conical, cylindrical or test-tube shaped and has a single opening, and the upper sidewall portion 221a extends upwardly aligning with the outer periphery of the bottom 221b, so that the inner wall of the first dielectric layer 221 presents a stepped shape. The first dielectric layer 221 further surrounds the second dielectric layer 223, wherein the second dielectric layer 223 is generally tubular, conical, cylindrical or test-tube shaped and has a single opening, so that the inner sidewall surface of the first dielectric layer 221 laterally contacts the outer sidewall surface of the second dielectric layer 223. In addition, the first dielectric layer 221 and the second dielectric layer 223 may include the same dielectric material, but may also include different dielectric materials, but the present invention is not limited thereto. In some embodiments, the thickness T3 of the second dielectric layer 223 is less than or equal to 2 nm. In some embodiments, the thickness T3 of the second dielectric layer 223 is less than or equal to 1.5 nm. In some embodiments of the present invention, the semiconductor device 200 further includes a third dielectric layer 225 and an insulating capping 251. The third dielectric layer 225 is located on the second conductive structure 233, and the third dielectric layer 225 is partially located between the second conductive structure 233 and the insulating capping 251, and the third dielectric layer 225 surrounds the insulating capping 251, but the third dielectric layer 225 does not surround the first conductive structure 231 and the second conductive structure 233, wherein the second dielectric layer 223 further laterally contacts the third dielectric layer 225. In some embodiments, the thickness T4 of the third dielectric layer 225 is less than or equal to 1.5 nm. In some embodiments, the thickness T4 of the third dielectric layer 225 is less than or equal to 1.2 nm. Thereby, the first conductive structure 231 and the second conductive structure 233 serve as gate conductors, and the first dielectric layer 221, the second dielectric layer 223 and the third dielectric layer 225 form a gate dielectric structure with an increasing thickness upward, thereby suppressing gate-induced drain leakage current. In some other embodiments of the present invention, the semiconductor device 200 does not include the third dielectric layer 225, so that the insulating capping 251 directly contacts the second dielectric layer 223 and the second conductive structure 233, wherein the insulating capping 251 is located directly above the first conductive structure 231 and the second conductive structure 233 and protects the first conductive structure 231 and the second conductive structure 233. Specifically, the third dielectric layer 225 is generally tubular, conical, cylindrical, or test-tube shaped and has a single opening. The third dielectric layer 225 has a U-shaped cross-section. The second dielectric layer 223 surrounds the third dielectric layer 225 and the insulating cap 251, and the inner side wall of the second dielectric layer 223 laterally contacts the outer side wall of the third dielectric layer 225, so that the second dielectric layer 223 and the third dielectric layer 225 together serve as a gate dielectric structure and suppress gate-induced drain leakage current. In addition, the first dielectric layer 221, the second dielectric layer 223, and the third dielectric layer 225 may include the same dielectric material, but may also include different dielectric materials, and the present invention is not limited thereto. In some embodiments of the present invention, the semiconductor device 200 includes a first barrier layer 241 and a second barrier layer 243. The first barrier layer 241 surrounds the first conductive structure 231, and the first barrier layer 241 is generally tubular, conical, cylindrical, or test-tube shaped and has a single opening. The second barrier layer 243 is located above the first conductive structure 231 and closes the opening of the first barrier layer 241. Specifically, the first barrier layer 241 is located between the first conductive structure 231 and the first dielectric layer 221, and the second barrier layer 243 is located between the first conductive structure 231 and the second dielectric layer 223. Thereby, the first barrier layer 241 and the second barrier layer 243 together cover the first conductive structure 231, and the first barrier layer 241 and the second barrier layer 243 help to prevent the first conductive structure 231 and the surrounding structures from being affected by the diffusion mechanism, thereby improving the product quality. In summary, the present invention provides a transistor device, the gate structure of which is formed by stacking multiple dielectric layers, and the multiple dielectric layers are generally tubular, conical, cylindrical, or test-tube shaped, so the gate structure has a gradually increasing thickness. When the transistor structure of the present invention is applied to a dynamic random access memory, it can effectively suppress gate-induced drain leakage current. In addition, a part of the thickness of the gate dielectric structure of the transistor of the present invention is thinner, so the channel current, the standard threshold voltage can be increased, and the subthreshold swing can be improved, thereby enhancing the gate control ability. The gate metal of the transistor device of the present invention is protected by multiple barrier layers, so the negative impact of the diffusion mechanism induced in the semiconductor manufacturing process can be effectively suppressed, thereby improving the product quality. The different embodiments of the present invention have been described above. It should be understood that the different embodiments are presented only as examples and not as limitations. Without departing from the spirit and scope of the present invention, many modifications can be made to the embodiments disclosed herein according to the disclosure herein. Therefore, the breadth and scope of the present invention should not be limited by the embodiments described above. 100: Manufacturing method 110, 120, 130, 140, 150, 160, 170, 180: Steps 200: Semiconductor device 210: Substrate 211: Doped region 212: p-type doped region 213: n-type doped region 213a: n-type lightly doped region 214: First groove 215: Source region 215a: p-type region 215b: n-type region 215c: n-type lightly doped region 216: Drain region 216a: p-type region 216b: n-type region 216c: n-type lightly doped region 217: Second groove 219: Third groove 221: First dielectric layer 221a: Upper sidewall portion 221b: Bottom 223: Second dielectric layer 225: Third dielectric layer 231: First conductive structure 233: Second conductive structure 241: First barrier layer 242: Barrier structure 242a: Upper sidewall portion 242b: Bottom 243: Second barrier layer 251: Insulating capping T1, T2, T3, T4: Thickness To achieve the above advantages and features, the principles briefly described above will be more specifically explained with reference to the embodiments, and the specific embodiments are shown in the accompanying drawings. These drawings only illustratively describe the present invention and thus do not limit the scope of the invention. Through the drawings, the principles of the present invention will be clearly explained, and additional features and details will be completely described, where: FIG. 1 illustrates a flowchart of a manufacturing method of a semiconductor device in some embodiments of the present invention; and FIGS. 2 to 11 illustrate schematic diagrams of the respective steps of the manufacturing method in FIG. 1. Domestic deposit information (please note in the order of deposit institution, date, number) None Foreign deposit information (please note in the order of deposit country, institution, date, number) None 100: Manufacturing method 110, 120, 130, 140, 150, 160, 170, 180: Steps

Claims

1. A method for manufacturing a semiconductor device, comprising: A substrate is provided, wherein the substrate has doped regions; A first groove is formed in the doped region of the substrate; a first dielectric layer is conformally formed in the first groove; a first barrier layer is conformally formed in the first groove and on the first dielectric layer; a first conductive structure is filled in the first groove and on the first barrier layer; a portion of the first conductive structure is removed to form a second groove; a second barrier layer is formed on the first conductive structure and in the second groove; a second dielectric layer is conformally formed in the second groove and on the second barrier layer, wherein the first dielectric layer and the second dielectric layer form a gate dielectric structure with increasing thickness; and a second conductive structure is filled in the second groove and on the second dielectric layer.

2. The manufacturing method as described in claim 1, wherein the work function of the second conductive structure is less than the work function of the first conductive structure.

3. The manufacturing method as claimed in claim 1, wherein the first dielectric layer surrounds the second dielectric layer and the first dielectric layer is in lateral contact with the second dielectric layer.

4. The manufacturing method as described in claim 1, further comprising: The second conductive structure portion is removed to form the third groove; And fill the third groove with an insulating cap.

5. The manufacturing method as described in claim 1, further comprising: The second conductive structure portion is removed to form the third groove; A third dielectric layer is conventionally formed in the third groove; An insulating cap is filled in the third groove and on the third dielectric layer.

6. The manufacturing method as described in claim 5, wherein the second dielectric layer is in lateral contact with the third dielectric layer.

7. The manufacturing method as described in claim 1, wherein the first dielectric layer and the second dielectric layer form a gate dielectric structure with increasing thickness.

8. The manufacturing method as described in claim 7, wherein after the second barrier layer is formed, the inner wall of the first dielectric layer is stepped.

9. The manufacturing method as claimed in claim 1, wherein forming a second barrier layer on the first conductive structure further comprises: A barrier structure is conformally formed in the second groove; And the upper sidewall portion of the barrier structure is removed laterally to form the second barrier layer.

10. The manufacturing method as claimed in claim 1, wherein forming a second barrier layer on the first conductive structure further comprises: A barrier structure is conformally formed in the second groove; The upper sidewall of the barrier structure is removed laterally to form the second barrier layer; And the upper sidewall portion of the first dielectric layer is thinned laterally.

11. The manufacturing method as claimed in claim 1, wherein the first dielectric layer includes a bottom and an upper sidewall portion, the upper sidewall portion being located above the bottom, wherein the thickness of the upper sidewall portion of the first dielectric layer is less than the thickness of the bottom of the first dielectric layer.

12. The manufacturing method as claimed in claim 1, wherein the first dielectric layer is manufactured by a near-field vapor generation process and the second dielectric layer is manufactured by an atomic layer deposition process.

13. A semiconductor device, comprising: A substrate includes a source region and a drain region; a first conductive structure is located between the source region and the drain region; A second conductive structure is located on the first conductive structure; a gate dielectric structure includes: a first dielectric layer surrounding the first conductive structure and the second conductive structure; and a second dielectric layer partially located between the first conductive structure and the second conductive structure, and the second dielectric layer surrounding the second conductive structure, wherein the first dielectric layer is in lateral contact with the second dielectric layer, and the thickness of the gate dielectric structure increases upward; a first barrier layer located between the first conductive structure and the first dielectric layer; and a second barrier layer located between the first conductive structure and the second dielectric layer.

14. The semiconductor device of claim 13, wherein the work function of the second conductive structure is less than the work function of the first conductive structure.

15. The semiconductor device of claim 13 further includes a third dielectric layer, wherein the third dielectric layer is located on the second conductive structure.

16. The semiconductor device of claim 13 further includes: The third dielectric layer is located on the second conductive structure; And an insulating cap, wherein the third dielectric layer surrounds the insulating cap, and a portion of the third dielectric layer is located between the second conductive structure and the insulating cap.

17. The semiconductor device of claim 15 or 16, wherein the second dielectric layer is in more lateral contact with the third dielectric layer.

18. The semiconductor device of claim 15 or 16, wherein the third dielectric layer has a U-shaped cross-section.

19. The semiconductor device of claim 13, wherein the inner wall of the first dielectric layer is stepped.

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