Amplifier and operation method thereof

Abstract

An amplifier includes a signal input terminal, a signal output terminal, an amplification circuit, and at least one variable voltage generating circuit. The signal input terminal receives an input signal. The signal output terminal outputs an amplified signal. The transistor of the amplification circuit includes a first terminal, a second terminal, a control terminal, and a body terminal, wherein the control terminal is coupled to the signal input terminal, the second terminal is coupled to the signal output terminal, and the body terminal is in a floating state. The at least one variable voltage generating circuit is coupled to the transistor of the amplification circuit. During a transition state, a first voltage difference exists between the second terminal and the first terminal of the transistor, and a second voltage difference exists during a steady state. The first voltage difference is greater than the second voltage difference.

Description

Technical Field

[0001] This disclosure relates to an amplifier and its operation method, and more particularly to an amplifier and its operation method that can quickly transition from a transition state to a steady state. Prior Technology

[0002] Amplifiers are essential components in radio frequency (RF) transceiver circuits, used to amplify RF signals. For example, amplifiers can include power amplifiers (PAs) and low-noise amplifiers (LNAs). In communication systems, amplifiers are placed near the antenna to amplify the received signal. Amplifier performance can be evaluated by various parameters, such as gain, noise figure, linearity, power loss, and stability.

[0003] When designing amplifiers, for example, to achieve a good noise figure, floating-body transistors are used, where the body terminal of the transistor is floating. In practical applications, amplifiers may switch between many operating states. During the transition between operating states, the threshold voltage of a transistor with its body terminal in a floating state may be less likely to stabilize, thus making it harder for the transistor current (e.g., drain-source current) to stabilize, resulting in a slower transition response of the amplifier. Observations have shown that increasing the voltage difference between the transistor's drain and source can help the transistor stabilize more quickly, allowing the drain-source current to stabilize more rapidly, thereby improving the amplifier's transition response. Therefore, an amplifier architecture is needed that can quickly switch between different operating modes while maintaining performance parameters such as noise figure. Summary of the Invention

[0004] One embodiment provides an amplifier including a signal input terminal, a signal output terminal, an amplification circuit, and at least one variable voltage generating circuit. The signal input terminal is used to receive an input signal. The signal output terminal is used to output an amplified signal. The amplification circuit is coupled between the signal input terminal and the signal output terminal. The amplification circuit includes a first transistor, which includes a first terminal, a second terminal, a control terminal, and a body terminal. The first terminal is coupled to a first node, the second terminal is coupled to a second node, the control terminal is coupled to the signal input terminal, and the body terminal is in a floating state. The at least one variable voltage generating circuit is coupled to the amplification circuit. During a transition state, the at least one variable voltage generating circuit provides a first voltage difference between the second terminal and the first terminal of the first transistor. During a steady state, the at least one variable voltage generating circuit provides a second voltage difference between the second terminal and the first terminal of the first transistor. The first voltage difference is greater than the second voltage difference.

[0005] Another embodiment provides an operating method for an amplifier. The amplifier includes a signal input terminal, a signal output terminal, an amplification circuit, and at least one variable voltage generating circuit. The signal input terminal is used to receive an input signal. The signal output terminal is used to output an amplified signal. The amplification circuit is coupled between the signal input terminal and the signal output terminal. The amplification circuit includes a first transistor, which includes a first terminal, a second terminal, a control terminal, and a body terminal. The first terminal is coupled to a first node, the second terminal is coupled to a second node, the control terminal is coupled to the signal input terminal, and the body terminal is in a floating state. The at least one variable voltage generating circuit is coupled to the amplification circuit. The operating method includes, during a transition state, the at least one variable voltage generating circuit providing a first voltage difference between the second terminal and the first terminal of the first transistor; and during a steady state, the at least one variable voltage generating circuit providing a second voltage difference between the second terminal and the first terminal of the first transistor. The first voltage difference is greater than the second voltage difference. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic diagram of an amplifier according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of another amplifier according to an embodiment of the present disclosure. Figures 3 and 4 are schematic diagrams of the voltage levels of some nodes of an amplifier according to an embodiment of the present disclosure. Figure 5 is a schematic diagram of yet another amplifier according to an embodiment of the present disclosure. Figure 6 is a schematic diagram of yet another amplifier according to an embodiment of the present disclosure. Figure 7 is a schematic diagram of the voltage levels of some nodes of an amplifier according to an embodiment of the present disclosure. Figure 8 is a schematic diagram of yet another amplifier according to an embodiment of the present disclosure. Figure 9 is a schematic diagram of yet another amplifier according to an embodiment of the present disclosure. Figure 10 is a schematic diagram of the voltage levels of a portion of a node of an amplifier according to an embodiment of the present disclosure. Figure 11 is a schematic flowchart of an amplifier operation method according to an embodiment of the present disclosure. Implementation

[0007] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and to maintain the simplicity of the drawings, only a portion of the electronic device is depicted, and specific elements in the drawings are not drawn to scale. Furthermore, the number and dimensions of the elements in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention. Elements indicated by the same symbols in the drawings have the same or similar properties or functions in the preceding and following text.

[0008] In the following description and claims, the terms "comprising," "containing," and "having" are open-ended terms and should therefore be interpreted as "containing but not limited to...". Thus, when the terms "comprising," "containing," and / or "having" are used in the description of this invention, they specify the presence of the corresponding features, areas, steps, operations, and / or components, but do not exclude the presence of one or more of the corresponding features, areas, steps, operations, and / or components.

[0009] Figure 1 is a schematic diagram of an amplifier 100 according to an embodiment of the present disclosure. As shown, the amplifier 100 may include a signal input terminal NIN, a signal output terminal NOUT, and an amplification circuit 101 coupled thereto. For example, the signal input terminal NIN may be coupled to a pre-amplifier circuit (e.g., an antenna) to receive the signal SIN. The amplification circuit 101 may amplify the signal SIN, and the signal output terminal NOUT may be used to output the amplified signal SOUT to subsequent circuits for further processing of the amplified signal, etc.

[0010] In one embodiment, the amplifier circuit 101 may include a first transistor T1, which may include, for example, a MOSFET, a bipolar junction transistor (BJT), etc. The first transistor T1 may include a first terminal, a second terminal, and a control terminal. For example, in the case of an N-type MOSFET, the first terminal of the first transistor T1 may be one of the source and drain terminals, the second terminal may be the other, and the control terminal may be the gate; or in the case of a BJT, the first terminal of the first transistor T1 may be one of the emitter and collector terminals, the second terminal may be the other, and the control terminal may be the base. In some embodiments, the first terminal of the first transistor T1 may be coupled to a first node N1, and the second terminal may be coupled to a second node N2. Specifically, the first node N1 may be further coupled to a reference voltage terminal, such as ground, via other components (e.g., an inductor). The second node N2 may be further coupled to an operating voltage terminal VDD, such as a system voltage terminal or a battery voltage terminal. Furthermore, the second node N2 may be further coupled to a signal output terminal NOUT. The control terminal of the first transistor T1 can be coupled to the signal input terminal NIN to receive radio frequency signals.

[0011] In some embodiments, amplifier 100 may further include at least one variable voltage generating circuit 110 which may be coupled to amplifier circuit 101, as described further below.

[0012] Figure 2 is a schematic diagram of another amplifier 200 according to an embodiment of the present disclosure. Amplifier 200 may be similar to amplifier 100 in Figure 1; the similarities will not be repeated, only the main differences are described below. As shown, the amplification circuit 201 of amplifier 200 may further include a second transistor T2.

[0013] In some embodiments, similar to the first transistor T1, the second transistor T2 may include a MOSFET, a bipolar junction transistor (BJT), etc. The second transistor T2 may include a first terminal, a second terminal, and a control terminal. For example, the second transistor T2 may be an N-type MOSFET, with its first terminal being the source, its second terminal being the drain, and its control terminal being the gate. Alternatively, the second transistor T2 may be a P-type MOSFET, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate. However, this is merely illustrative and not intended to limit the invention. In other embodiments, the first transistor T1 and / or the second transistor T2 may be other suitable types of transistors and may be coupled in other suitable ways.

[0014] As shown in the figure, the first terminal of the second transistor T2 can be coupled to the second node N2, the second terminal can be coupled to the signal output terminal NOUT, and the control terminal can be coupled to the third node N3. In other words, the first transistor T1 and the second transistor T2 can be cascode-connected. Furthermore, the first transistor T1 and the second transistor T2 can be directly or indirectly cascaded. For example, in the case of direct cascading, the first terminal of the second transistor T2 can be directly coupled to the second terminal of the first transistor T1, without any other active or passive components in between. Furthermore, in the case of indirect cascading, an additional component, such as a third transistor (not shown), can be placed between the first terminal of the second transistor T2 and the second terminal of the first transistor T1.

[0015] In some embodiments, the first transistor T1 and / or the second transistor T2 may be fabricated using, for example, SOI (Silicon-On-Insulator) processes, GaAs-related processes, etc. For instance, in the manufacturing process of an IC device, a transistor may be formed on a substrate. Each single cell in the transistor may include, for example, a gate electrode. A gate dielectric may be disposed between the gate electrode and the substrate. Furthermore, examples of manufacturing processes may include, but are not limited to, implantation steps, wafer bonding and polishing steps, ion splitting steps, etc.

[0016] In a further embodiment, the first transistor T1 and / or the second transistor T2 may also include a body (or bulk) connection, which may be, for example, floating or contacted. For instance, a floating body connection means that the body does not have a predetermined voltage, which can achieve a better noise figure. However, because the body does not have a definite voltage level, the transistor's threshold voltage is less likely to stabilize, resulting in a slower current stabilization and a slower amplifier response. Furthermore, the body of the first transistor T1 is preferably in a floating state. Experiments have shown that providing a larger voltage difference (also known as the transverse voltage) VDS between the second and first terminals of the first transistor T1 during state transitions helps the threshold voltage of the first transistor T1 stabilize quickly, thereby allowing the current to stabilize more quickly and achieving a better transition response. A better transition response contributes to achieving a good noise figure for the amplifier. In some embodiments, after the first transistor T1 reaches a stable state, a normal or low voltage difference VDS can be provided between the second terminal and the first terminal to facilitate normal or power-saving operation of the circuit. In some embodiments, a body-contact connection can refer to the body terminal having a predetermined voltage. The body terminal of the second transistor T2 is preferably in a floating or contact state.

[0017] As shown in Figure 2, there is a voltage difference VDS(T1) between the second and first terminals of the first transistor T1. The first terminal of the first transistor T1 is coupled to the first node N1, and the second terminal is coupled to the second node N2. Therefore, the voltage difference VDS(T1) between the second and first terminals of the first transistor T1 can essentially depend on the difference between the voltage level V2 of the second node N2 and the voltage level V1 of the first node N1, and can be expressed, for example, as VDS = V2 - V1. For instance, in the case where the first transistor T1 is an N-type metal-oxide-semiconductor field-effect transistor, its voltage difference VDS can be the voltage difference between the drain and source terminals, also known as the drain-source voltage.

[0018] In some embodiments, during the transition period PT, the current flowing through the first transistor T1 (e.g., the drain current) is substantially unstable. During the steady-state period PS following the transition period PT, the current flowing through the first transistor T1 is substantially stable; for example, the variation in the current flowing through the first transistor T1 during the steady-state period PS is less than ±10%. Generally, the transition period PT can correspond to the short transient state at amplifier startup. In some embodiments, the duration of the transition period PT can be substantially between 360 nanoseconds and 440 nanoseconds.

[0019] In some embodiments, the first variable voltage generating circuit 210 may be coupled to a third node N3, thereby being coupled to the control terminal of the second transistor T2. The first variable voltage generating circuit 210 can be used to provide a pulse voltage signal VPS1 at the third node N3, which has a variable voltage level. The voltage level of the pulse voltage signal VPS1 can determine the voltage level of the control terminal of the second transistor T2, thereby determining the voltage level of the first terminal of the second transistor T2. In the embodiment of Figure 2, the second terminal of the first transistor T1 is coupled to the first terminal of the second transistor T2 via the second node N2, therefore, the voltage level of the second terminal of the first transistor T1 can be determined by the voltage level of the pulse voltage signal VPS1. Specifically, during the transition state PT, the pulse voltage signal VPS1 may have a first level L1, and the voltage level of the second terminal of the first transistor T1 can be determined by the first level L1. During the steady-state period PS following the transition period PT, the pulse voltage signal VPS1 may have a second bit L2, and the voltage bit at the second terminal of the first transistor T1 may be determined by the second bit L2. For example, the first bit L1 may be different from the second bit L2.

[0020] Figures 3 and 4 are schematic diagrams of the voltage levels of some nodes of an amplifier according to an embodiment of the present disclosure. Figure 3 shows the voltage level change waveforms of the pulse voltage signal VPS1 during the transition period PT and the steady-state period PS, and Figure 4 shows the voltage difference VDS(T1) between the second and first terminals of the first transistor T1 during the transition period PT and the steady-state period PS. In some embodiments, the voltage level of the first node N1 may be substantially the same during the transition period PT and the steady-state period PS (e.g., remain unchanged), for example, grounded. Therefore, the voltage level of the first terminal of the first transistor T1 may be substantially the same. In some embodiments, the first voltage level L1 may be higher than the second voltage level L2.

[0021] As shown in Figure 3, during the transition period PT, the pulse voltage signal VPS1 can have a higher first level L1, which can pull up the voltage level at the second terminal of the first transistor T1, thereby providing a larger voltage difference between the second and first terminals of the first transistor T1, such as a first voltage difference VDS1. During the steady-state period PS following the transition period PT, the pulse voltage signal VPS1 can have a lower second level L2, which can pull the voltage level at the second terminal of the first transistor T1 back to a normal or lower level, thereby providing a normal or smaller voltage difference between the second and first terminals of the first transistor T1, such as a second voltage difference VDS2. As shown in Figure 4, during the transition period PT, the voltage difference VDS(T1) between the second and first terminals of the first transistor T1 is the first voltage difference VDS1, and during the steady-state period PS it is the second voltage difference VDS2. Furthermore, the first voltage difference VDS1 can be greater than the second voltage difference VDS2. For example, the first voltage difference VDS1 can be 1.0 volts, and the second voltage difference VDS2 can be 0.6 volts.

[0022] In the above embodiments, during the transition period PT, there can be a large voltage difference VDS1 between the second terminal and the first terminal of the first transistor T1, for example, 1.0 volts. Therefore, the threshold voltage of the first transistor T1 can reach stability more quickly, allowing the current (e.g., drain current) of the first transistor T1 to reach stability quickly, thereby accelerating the transition response of amplifiers 100 and 200. During the steady-state period PS, there is a normal or low voltage difference VDS2 between the second terminal and the first terminal of the first transistor T1, for example, 0.6 volts. Therefore, the first transistor T1 can operate in normal or power-saving mode.

[0023] In some embodiments, a second terminal of the second transistor T2 may be coupled to an operating voltage terminal VDD. A voltage difference VDS(T2) exists between the second terminal and the first terminal of the second transistor T2. This voltage difference VDS(T2) may substantially depend on the difference between the operating voltage terminal VDD and the voltage level V2 of the second node N2. During the transition period PT, in response to a pulse voltage signal VPS1 having a higher threshold L1, the operating voltage terminal VDD provides a first operating voltage. During the steady-state period PS following the transition period PT, in response to a pulse voltage signal VPS1 having a normal or lower threshold L2, the operating voltage terminal VDD provides a second operating voltage, wherein the first operating voltage may be higher than the second operating voltage.

[0024] Furthermore, during the transition period PT, the voltage difference VDS1(T1) between the second and first terminals of the first transistor T1 can be relatively large (e.g., a large first voltage difference VDS1). In this case, a higher first operating voltage ensures that the voltage difference VDS(T2) between the second and first terminals of the second transistor T2 is an appropriate value, for example, it does not decrease due to the large first voltage difference VDS1. In a particular embodiment, the voltage difference VDS(T2) between the second and first terminals of the second transistor T2 remains substantially the same during the transition period PT and the steady-state period PS, thereby enabling the amplifier to operate normally during both the transition period PT and the steady-state period PS.

[0025] In the above embodiments, the position change waveform of the pulse voltage signal VPS1 is only an illustrative example and can be adjusted according to requirements and component characteristics. For example, in other embodiments, the pulse voltage signal VPS1 may present other change waveforms, such as when the second transistor T2 is a P-type transistor, the first position L1 may be lower than the second position L2.

[0026] Figure 5 is a schematic diagram of yet another amplifier 500 according to an embodiment of the present disclosure. Figure 6 is a schematic diagram of yet another amplifier 600 according to an embodiment of the present disclosure, further illustrating the internal structure of the variable voltage generation circuit 620. Figure 7 is a schematic diagram of the voltage levels of some nodes of an amplifier according to an embodiment of the present disclosure, showing the voltage change waveforms of the pulse voltage signal VPS2 during the transition period PT and the steady-state period PS.

[0027] As shown in Figure 5, amplifier 500 may include amplifier circuit 501, which may be similar to amplifier circuit 201 in Figure 2. The similarities will not be repeated, only the main differences are described below. Amplifier 500 may include a second variable voltage generating circuit 520, which may be an embodiment of variable voltage generating circuit 110 in Figure 1. The second variable voltage generating circuit 520 may be coupled to a second node N2, and thus further coupled to a second terminal of the first transistor T1. The second variable voltage generating circuit 520 may provide a pulse voltage signal VPS2 at the second node N2, which has a variable voltage level. The voltage level of the pulse voltage signal VPS2 can determine the voltage level of the second node N2, thereby determining the voltage level of the second terminal of the first transistor T1. In some embodiments, referring to Figure 7, during the transition period PT, the pulse voltage signal VPS2 may have a third level L3, and the voltage level of the second terminal of the first transistor T1 may be determined by this third level L3. During the steady-state period PS following the transition period PT, the pulse voltage signal VPS2 may have a fourth bit L4, and the voltage bit at the second terminal of the first transistor T1 may be determined by the fourth bit L4.

[0028] As shown in Figure 6, amplifier 600 may include amplifier circuit 601 and variable voltage generation circuit 620, which may be an embodiment of second variable voltage generation circuit 520. Variable voltage generation circuit 620 may include switch SW1. Switch SW1 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal may be coupled to a reference voltage terminal to receive a first reference voltage VREF1. The second terminal may be coupled to a second node N2. The control terminal of switch SW1 can be used to receive control signal VCTRL1.

[0029] As shown in Figure 7, regarding the voltage level of the pulse voltage signal VPS2, the third bit L3 during the transition period PT may differ from the fourth bit L4 during the steady-state period PS. In a specific embodiment, the third bit L3 may be higher than the fourth bit L4. Therefore, during the transition period PT, the first voltage difference VDS1 between the second and first terminals of the first transistor T1 may be greater than its second voltage difference VDS2 during the steady-state period PS. During the transition period PT, switch SW1 is turned on according to the control signal VCTRL1, so that the second node N2 receives the first reference voltage VREF1. In this case, the level of the first reference voltage VREF1 may correspond to the third bit L3. During the steady-state period PS, switch SW1 is turned off according to the control signal VCTRL1, so that the second node N2 does not receive the first reference voltage VREF1. In this case, the voltage level at the second node N2 may correspond to the fourth bit L4.

[0030] Figure 8 is a schematic diagram of yet another amplifier 800 according to an embodiment of the present disclosure. Figure 9 is a schematic diagram of yet another amplifier 900 according to an embodiment of the present disclosure, further illustrating the internal structure of the variable voltage generation circuit 930. Figure 10 is a schematic diagram of the voltage levels of some nodes of an amplifier according to an embodiment of the present disclosure, showing the voltage change waveforms of the pulse voltage signal VPS3 during the transition period PT and the steady-state period PS.

[0031] As shown in Figure 8, amplifier 800 may include amplifier circuit 801, which may be similar to amplifier circuit 201 in Figure 2. The similarities will not be repeated, only the main differences are described below. Amplifier 800 may include a third variable voltage generating circuit 830, which may be an embodiment of variable voltage generating circuit 110 in Figure 1. The third variable voltage generating circuit 830 may be coupled to the first node N1, and thus may be further coupled to the first terminal of the first transistor T1. The third variable voltage generating circuit 830 may provide a pulse voltage signal VPS3 at the first node N1, which has a variable voltage level. The voltage level of the pulse voltage signal VPS3 can determine the voltage level of the first node N1, thereby determining the voltage level of the first terminal of the first transistor T1. In some embodiments, referring to Figure 10, during the transition period PT, the pulse voltage signal VPS3 may have a fifth bit L5, and the voltage level of the first terminal of the first transistor T1 may be determined by the fifth bit L5. During the steady-state period PS following the transition period PT, the pulse voltage signal VPS3 may have a sixth bit L6, and the voltage bit at the first terminal of the first transistor T1 may be determined by the sixth bit L6.

[0032] As shown in Figure 9, amplifier 900 may include amplification circuit 901 and variable voltage generation circuit 930, which may be an embodiment of variable voltage generation circuit 830. Variable voltage generation circuit 930 may include switches SW2 and SW3. Switch SW2 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal may be coupled to a reference voltage terminal to receive a second reference voltage VREF2, the second terminal may be coupled to a first node N1, and the control terminal may be used to receive a control signal VCTRL2. Similarly, switch SW3 may include a first terminal, a second terminal, and a control terminal, wherein the first terminal may be coupled to a reference voltage terminal to receive a third reference voltage VREF3, the second terminal may be coupled to a first node N1, and the control terminal may be used to receive a control signal VCTRL3. In some embodiments, the voltage levels of the second reference voltage VREF2 and the third reference voltage VREF3 may be different or the same. For example, the second reference voltage VREF2 can be a negative voltage level, and the third reference voltage VREF3 can be a zero voltage level.

[0033] As shown in Figure 10, regarding the voltage level of the pulse voltage signal VPS3, the fifth bit L5 of PT during the transition period may differ from the sixth bit L6 of PS during the steady-state period. In a specific embodiment, the fifth bit L5 may be lower than the sixth bit L6. Further, during the transition period PT, switch SW2 is turned on according to control signal VCTRL2, and switch SW3 is turned off according to control signal VCTRL3, so that the first node N1 receives the second reference voltage VREF2. In this case, the level of the second reference voltage VREF2 may correspond to the fifth bit L5, for example, a negative voltage level. During the steady-state period PS, switch SW2 is turned off according to control signal VCTRL2, and switch SW3 is turned on according to control signal VCTRL3, so that the first node N1 receives the third reference voltage VREF3. In this case, the level of the third reference voltage VREF3 may correspond to the sixth bit L6, for example, a zero voltage level.

[0034] In this embodiment, the voltage potential of the second node N1 can be substantially the same (e.g., remain unchanged) during the transition period PT and the steady-state period PS. Therefore, the voltage potential of the second terminal of the first transistor T1 can be substantially the same. Since the voltage potential of the first node N1 is lower during the transition period PT (compared to the steady-state period PS), the voltage potential of the first terminal of the first transistor T1 is lower during the transition period PT. Therefore, during the transition period PT, the first voltage difference VDS1 between the second terminal and the first terminal of the first transistor T1 can be larger, which is relative to the second voltage difference VDS2 during the steady-state period PS.

[0035] Figure 11 is a schematic flowchart of an amplifier operation method 1100 according to an embodiment of the present disclosure. The amplifier operation method 1100 can be used to operate at least one of the aforementioned amplifiers. The amplifier operation method 1100 may include, for example, the following steps:

[0036] Step 1110: During the transition period PT, at least one variable voltage generating circuit provides a first voltage difference VDS1 between the second terminal and the first terminal of the first transistor T1; and

[0037] Step 1120: During the steady-state period PS following the transition period PT, at least one variable voltage generating circuit provides a second voltage difference VDS2 between the second terminal and the first terminal of the first transistor T1, wherein the first voltage difference VDS1 is greater than the second voltage difference VDS2.

[0038] In some embodiments, at least one variable voltage generating circuit may be coupled to at least one node of an amplifier circuit, the node being directly or indirectly coupled to a transistor of the amplifier circuit. For example, a variable voltage generating circuit may provide a pulsed voltage signal at a node, the pulsed voltage signal having different voltage levels during different states of the transistor (e.g., transition state, steady state), such that the voltage difference between the two ends of the transistor (e.g., between the second end and the first end) is different. For example, the voltage difference between the two ends of the transistor may be larger during the transition state and normal or smaller during the steady state.

[0039] In summary, during the transition period PT, due to the large voltage difference VDS1 between the second and first terminals of the transistor (e.g., drain and source terminals), the threshold voltage of the transistor can quickly reach stability, allowing the transistor current to stabilize rapidly and accelerating the amplifier's transition response. During the steady-state period PS following the transition period PT, a normal or low voltage difference can exist between the second and first terminals of the transistor, allowing the transistor to operate in normal or power-saving mode.

[0040] In at least one of the above embodiments, the voltage levels of, for example, the operating voltage terminal, at least one reference voltage terminal, and at least one pulse voltage signal (e.g., pulse voltage signals VPS1, VPS2, or VPS3) can be set according to usage requirements and semiconductor manufacturing processes. It should be understood that the features described in the embodiments can be replaced, recombined, or mixed in several different embodiments to complete other embodiments without departing from the spirit of the invention. Features between embodiments can be used individually or in combination as long as they do not violate the spirit of the invention or conflict with it, and they still fall within the scope of this disclosure. For example, according to one embodiment, at least two of the first variable voltage generating circuit, the second variable voltage generating circuit, and the third variable voltage generating circuit described herein can be used in combination.

[0041] In at least one embodiment, when one element is coupled to another element, it may be directly coupled or indirectly coupled through other elements. The reference voltage terminal described herein can provide a substantially stable reference voltage. The reference voltage terminal described herein may be, but is not limited to, ground. The plurality of reference voltage terminals described herein may be the same reference voltage terminal or different reference voltage terminals. The switch described herein can be turned on or off; when the switch is on, a signal can be transmitted through the switch, and when the switch is off, a signal can be blocked by the switch. The signal described herein may be a current signal and / or a voltage signal. The switch described herein may be composed of transistors or other suitable electronic components. For example, when the switch includes a field-effect transistor, the first terminal of the switch may be one of the drain and source terminals, the second terminal of the switch may be the other of the drain and source terminals, and the switch may be controlled through the gate terminal. For example, when the switch includes a bipolar transistor, the first terminal of the switch may be one of the collector and emitter terminals, the second terminal of the switch may be the other of the collector and emitter terminals, and the switch may be controlled through the base terminal. In this document, when a component is mentioned as selectively set or optionally set, it means that the component can be set or not set as needed, and all of these are within the scope of the embodiments. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0042] 100, 200, 500, 600, 800, 900: Amplifiers 110, 210, 520, 620, 830, 930: Variable voltage generation circuit 1100: Operating Instructions 1110, 1120: Steps L1, L2, L3, L4: Levels N1, N2, N3: Nodes NIN: Signal Input Terminal NOUT: Signal output terminal PS: During steady state PT: Transition Period SIN: Input signal SOUT: Amplify the signal SW1, SW2, SW3: Switches T1, T2: Transistors V1, V2: Voltage levels VCTRL1, VCTRL2, VCTRL3: Control signals VDD: Operating voltage terminal VDS, VDS1, VDS2: Voltage difference VPS1, VPS2, VPS3: Pulse voltage signal

Claims

1. An amplifier, comprising: a signal input terminal for receiving an input signal; a signal output terminal for outputting an amplified signal; an amplification circuit coupled between the signal input terminal and the signal output terminal, the amplification circuit comprising a first transistor, the first transistor comprising a first terminal, a second terminal, a control terminal, and a body terminal, wherein the first terminal is coupled to a first node, the second terminal is coupled to a second node, the control terminal is coupled to the signal input terminal, and a connection state of the body terminal is a floating state; and at least one variable voltage generating circuit coupled to the amplification circuit; wherein: During a transition state, the at least one variable voltage generating circuit provides a first voltage difference between the second terminal and the first terminal of the first transistor; during a steady state, the at least one variable voltage generating circuit provides a second voltage difference between the second terminal and the first terminal of the first transistor; and the first voltage difference is greater than the second voltage difference.

2. The amplifier as claimed in claim 1, wherein, The amplifier circuit further includes: a second transistor, including a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second node, the second terminal is coupled to the signal output terminal, and the control terminal is coupled to a third node.

3. The amplifier as described in claim 2, wherein: The at least one variable voltage generating circuit includes a first variable voltage generating circuit coupled to the third node and used to provide a first pulse voltage signal at the third node; during the transition state, the first pulse voltage signal has a first bit; and during the steady state, the first pulse voltage signal has a second bit.

4. The amplifier as described in claim 3, wherein: During the transition state, a voltage level at the second terminal of the first transistor is determined by the first bit of the first pulse voltage signal; during the steady state, the voltage level at the second terminal of the first transistor is determined by the second bit of the first pulse voltage signal; and during both the transition and steady states, a voltage level at the first terminal of the first transistor remains substantially unchanged.

5. The amplifier as claimed in claim 3, wherein the first bit is different from the second bit.

6. The amplifier as claimed in claim 2, wherein the second transistor further includes an integral terminal, and a connection state of the integral terminal of the second transistor is a floating state or an integral terminal contact state.

7. The amplifier as claimed in claim 2, wherein: The second terminal of the second transistor is also coupled to an operating voltage terminal; during the transition state, the operating voltage terminal provides a first operating voltage; During this steady state, the operating voltage terminal provides a second operating voltage; and the first operating voltage is higher than the second operating voltage.

8. The amplifier as claimed in claim 2, wherein: The at least one variable voltage generating circuit includes a second variable voltage generating circuit coupled to the second node and used to provide a second pulse voltage signal at the second node; during the transition state, the second pulse voltage signal has a third bit; and during the steady state, the second pulse voltage signal has a fourth bit.

9. The amplifier as claimed in claim 8, wherein the third bit is higher than the fourth bit.

10. The amplifier as claimed in claim 8, wherein: The second variable voltage generating circuit includes a first switch, which includes a first terminal, a second terminal, and a control terminal. The first terminal is coupled to a first reference voltage terminal, the second terminal is coupled to the second node, and the control terminal is used to receive a first control signal. During the transition state, the first switch is turned on according to the first control signal, so that the second node receives the first reference voltage. During the steady state, the first switch is turned off according to the first control signal.

11. The amplifier as claimed in claim 2, wherein: The at least one variable voltage generating circuit includes a third variable voltage generating circuit coupled to the first node and used to provide a third pulse voltage signal at the first node; during the transition state, the third pulse voltage signal has a fifth bit; and during the steady state, the third pulse voltage signal has a sixth bit.

12. The amplifier as claimed in claim 11, wherein the fifth bit is lower than the sixth bit.

13. The amplifier as claimed in claim 11, wherein: The third variable voltage generating circuit includes a second switch, which includes a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first node, the second terminal is coupled to a second reference voltage terminal, and the control terminal is used to receive a second control signal.

14. The amplifier as claimed in claim 13, wherein: The third variable voltage generating circuit includes a third switch, which includes a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first node, the second terminal is coupled to a third reference voltage terminal, and the control terminal is used to receive a third control signal. A voltage level at the second reference voltage terminal is lower than a voltage level at the third reference voltage terminal. During the transition state, the second switch is turned on according to the second control signal, and the third switch is turned off according to the third control signal, so that the first node receives a voltage at the second reference voltage terminal. During the steady state, the second switch is turned off according to the second control signal, and the third switch is turned on according to the third control signal, so that the first node receives a voltage at the third reference voltage terminal.

15. The amplifier as claimed in claim 1, wherein a duration during the transition period is substantially between 360 nanoseconds and 440 nanoseconds.

16. The amplifier as claimed in claim 1, wherein: During the transition state, the current flowing through the first transistor is substantially unstable; and during the steady state, the current flowing through the first transistor is substantially stable.

17. An operating method for an amplifier, wherein the amplifier comprises: A signal input terminal is used to receive an input signal; A signal output terminal for outputting an amplified signal; an amplifier circuit coupled between the signal input terminal and the signal output terminal, the amplifier circuit including a first transistor, the first transistor including a first terminal, a second terminal, a control terminal and a body terminal, wherein the first terminal is coupled to a first node, the second terminal is coupled to a second node, the control terminal is coupled to the signal input terminal, and the body terminal is in a floating connection state. and at least one variable voltage generating circuit coupled to the amplifier circuit; the operation method includes: during a transition state, the at least one variable voltage generating circuit provides a first voltage difference between the second terminal and the first terminal of the first transistor; During a steady state, the at least one variable voltage generating circuit provides a second voltage difference between the second terminal and the first terminal of the first transistor, and the first voltage difference is greater than the second voltage difference.

18. The operating method as described in claim 17, wherein: The amplifier circuit further includes: a second transistor, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the second node, the second terminal is coupled to the signal output terminal, and the control terminal is coupled to a third node; the at least one variable voltage generating circuit includes a first variable voltage generating circuit coupled to the third node; and the operation method further includes: the first variable voltage generating circuit providing a first pulse voltage signal at the third node; wherein: during the transition state, the first pulse voltage signal has a first bit; and during the steady state, the first pulse voltage signal has a second bit.

19. The operating method as described in claim 17, wherein: The at least one variable voltage generating circuit includes a second variable voltage generating circuit coupled to the second node; and the operation method further includes: the second variable voltage generating circuit providing a second pulse voltage signal at the second node; wherein: during the transition state, the second pulse voltage signal has a third bit; and during the steady state, the second pulse voltage signal has a fourth bit.

20. The operating method as described in claim 17, wherein: The at least one variable voltage generating circuit includes a third variable voltage generating circuit coupled to the first node; and the operation method further includes: the third variable voltage generating circuit providing a third pulse voltage signal at the first node; wherein: during the transition state, the third pulse voltage signal has a fifth bit; and during the steady state, the third pulse voltage signal has a sixth bit.

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