Method for encoding a backplane, method for identifying a backplane and server system

Abstract

A backplane encoding method is disclosed, applicable to a server system. The server system includes a motherboard and a backplane. The motherboard includes a first connector. The backplane includes a second connector and logic circuitry. The first connector is coupled to the second connector. The encoding method includes: encoding the backplane through multiple pins of the first connector to obtain an identification code corresponding to the backplane; storing the identification code in the firmware of the logic circuitry; and storing the identification code in the BIOS of the server system. This application further provides a backplane identification method and a server system.

Description

Technical Field

[0001] This case concerns backplane identification technology in server systems, specifically a method for encoding the backplane. Prior Technology

[0002] In existing technology, the LED control of SSDs is software-controlled, with related hardware including a backplane, motherboard, and connecting cables between the motherboard and backplane. The backplane is primarily used to connect SSDs, and the number of SSDs that can be installed depends on the backplane design. Some SSDs connect their LED control signal lines to a Complex Programmable Logic Device (CPLD) on the backplane. In server systems, the motherboard contains at least one Central Processing Unit (CPU), which provides sequential signals to control the LEDs.

[0003] When the server system starts up and detects the status of the SSDs mounted on the backplane, the CPU transmits a sequence of signals to the CPLD on the backplane to control the LEDs. The CPLD converts this sequence of signals into parallel signals and transmits them to the SSDs to control the LED display. Furthermore, each backplane requires its own independent CPLD firmware to operate.

[0004] As system complexity increases, such as with the number of backplanes or CPUs, the number of connecting cables also increases. This can make what seems like a simple operation potentially problematic, such as incorrect system component installation leading to incorrect indicator displays. To correctly identify the backplane configuration and the number of SSDs, the system typically restricts different backplane and SSD combinations to be installed in specific locations and slots, and the CPU needs to address each connected SSD for indicator control.

[0005] However, when encountering a backplane combination that does not conform to the system connection cable definition, the sequence signal provided by the CPU to control the LEDs may be incorrect, causing the system to fail to recognize it correctly, and thus preventing the system from correctly controlling the LEDs of the SSD. Summary of the Invention

[0006] In some embodiments, a backplane encoding method is applicable to a server system. The server system includes a motherboard and a backplane. The motherboard includes a first connector. The backplane includes a second connector and logic circuitry. The first connector is coupled to the second connector. The encoding method includes: encoding the backplane through a plurality of pins of the first connector to obtain an identification code corresponding to the backplane; storing the identification code in the firmware of the logic circuitry; and storing the identification code in the BIOS of the server system.

[0007] In some embodiments, multiple pins are redundant pins of the first connector.

[0008] In some embodiments, the number of pins is two. The identification code is two bits long.

[0009] In some embodiments, the logic circuit is a CPLD.

[0010] In some embodiments, the first connector and the second connector are MCIO connectors.

[0011] In some embodiments, a backplane encoding method is applicable to a server system. The server system includes a motherboard and multiple backplanes. The motherboard includes multiple first connectors. Each backplane includes a second connector and logic circuitry. Each first connector is coupled to each second connector. The encoding method includes: encoding each backplane through multiple pins of each first connector to obtain an identification code corresponding to each backplane; storing the identification code in the firmware of each logic circuit; and storing the identification code in the BIOS of the server system.

[0012] In some embodiments, the plurality of pins are redundant pins of each first connector.

[0013] In some embodiments, the firmware of each logic circuit stores the identification codes of all backplanes.

[0014] In some embodiments, each first connector has two pins, and the identification code is two bits long.

[0015] In some embodiments, each logic circuit is a CPLD.

[0016] In some embodiments, the plurality of first connectors and the plurality of second connectors are MCIO connectors.

[0017] In some embodiments, the plurality of first connectors includes a third connector and a fourth connector. The third connector is an MCIO connector. The fourth connector is a disk array card. The second connector coupled to the third connector is an MCIO connector, and the second connector coupled to the fourth connector is a SAS connector.

[0018] In some embodiments, a backplane identification method is applicable to a server system. The server system includes a motherboard and a backplane. The motherboard includes processing circuitry and a first connector. The processing circuitry is coupled to the first connector. The backplane includes a second connector, logic circuitry, multiple hard drive connectors, and multiple hard drives. The logic circuitry is coupled to the second connector, the multiple hard drive connectors are coupled to the logic circuitry, and each hard drive is coupled to its respective hard drive connector. The first connector is coupled to the second connector. The logic circuitry includes firmware. The identification method includes: the processing circuitry of the motherboard providing a first signal to the logic circuitry of the backplane; the logic circuitry of the backplane providing a second signal to the multiple hard drives based on the first signal and an identification code stored in the firmware; and each hard drive controlling its indicator light based on the second signal.

[0019] In some embodiments, the processing circuit provides a first signal to the logic circuit based on an identification code stored in the BIOS of the server system.

[0020] In some embodiments, the processing circuitry further includes a VPP port. The processing circuitry is coupled to the first connector via the VPP port.

[0021] In some embodiments, the VPP port is interconnected with the first connector, the first connector with the second connector, and the second connector with the logic circuit via SMBus.

[0022] In some embodiments, a backplane identification method is applicable to a server system. The server system includes a motherboard and multiple backplanes. The motherboard includes processing circuitry and multiple first connectors. The processing circuitry is coupled to the multiple first connectors. Each backplane includes a second connector, logic circuitry, multiple hard drive connectors, and multiple hard drives. The logic circuitry is coupled to the second connectors, the multiple hard drive connectors are coupled to the logic circuitry, and each hard drive is coupled to each hard drive connector. Each first connector is coupled to each second connector. The logic circuitry includes firmware. The identification method includes: the motherboard's processing circuitry providing a first signal to the logic circuitry of each backplane; the logic circuitry of each backplane providing a second signal to the multiple hard drives of each backplane based on the first signal and an identification code stored in the firmware of the logic circuitry of each backplane; and the multiple hard drives of each backplane controlling their indicator lights based on the second signal.

[0023] In some embodiments, the processing circuit provides a first signal to each logic circuit based on an identification code stored in the BIOS of the server system.

[0024] In some embodiments, the processing circuitry further includes a VPP port. The processing circuitry is coupled to a plurality of first connectors via the VPP port.

[0025] In some embodiments, the VPP port is interconnected with each of the first connectors, each of the first connectors is interconnected with each of the second connectors, and each of the second connectors is interconnected with each of the logic circuits via SMBus.

[0026] In some embodiments, a backplane identification method is applicable to a server system. The server system includes a motherboard and a backplane. The motherboard includes processing circuitry and a first connector. The processing circuitry is coupled to the first connector. The backplane includes a second connector, logic circuitry, multiple hard drive connectors, and multiple hard drives. The logic circuitry is coupled to the second connector, the multiple hard drive connectors are coupled to the logic circuitry, and each hard drive is coupled to its respective hard drive connector. The first connector is coupled to the second connector. The logic circuitry includes firmware. The identification method includes: encoding the backplane through multiple pins of the first connector to obtain an identification code corresponding to the backplane; storing the identification code in the firmware of the logic circuitry; storing the identification code in the BIOS of the server system; the processing circuitry of the motherboard providing a first signal to the logic circuitry of the backplane; the logic circuitry of the backplane providing a second signal to the multiple hard drives based on the first signal and the identification code stored in the firmware; and each hard drive controlling its indicator light based on the second signal.

[0027] In some embodiments, a backplane identification method is applicable to a server system. The server system includes a motherboard and multiple backplanes. The motherboard includes processing circuitry and multiple first connectors. The processing circuitry is coupled to the multiple first connectors. Each backplane includes a second connector, logic circuitry, multiple hard drive connectors, and multiple hard drives. The logic circuitry is coupled to the second connectors, the multiple hard drive connectors are coupled to the logic circuitry, and each hard drive is coupled to each hard drive connector. Each first connector is coupled to each second connector. The logic circuitry includes firmware. The identification method includes: encoding each backplane through multiple pins of each first connector to obtain an identification code corresponding to each backplane; storing the identification code in the firmware of each logic circuit; storing the identification code in the BIOS of the server system; the processing circuitry of the motherboard providing a first signal to the logic circuitry of each backplane; the logic circuitry of each backplane providing a second signal to the multiple hard drives of each backplane based on the first signal and the identification code stored in the firmware of the logic circuitry of each backplane; and the multiple hard drives of each backplane controlling their indicator lights based on the second signal.

[0028] In some embodiments, a server system includes a motherboard and a backplane. The motherboard includes processing circuitry and a first connector. The processing circuitry includes a VPP port. The processing circuitry provides a first signal. The first connector is coupled to the VPP port. The backplane includes a second connector, logic circuitry, a plurality of hard drive connectors, and a plurality of hard drives. The second connector is coupled to the first connector. The logic circuitry is coupled to the second connector. The logic circuitry includes firmware. The logic circuitry provides a second signal based on the first signal and an identification code stored in the firmware. The plurality of hard drive connectors are coupled to the logic circuitry. Each of the plurality of hard drives is individually coupled to a respective hard drive connector. Each hard drive controls its indicator lights based on the second signal.

[0029] In some embodiments, a server system includes a motherboard and multiple backplanes. The motherboard includes processing circuitry and multiple first connectors. The processing circuitry includes a VPP port. The processing circuitry provides a first signal. The multiple first connectors are coupled to the VPP port. Each of the multiple backplanes includes a second connector, logic circuitry, multiple hard drive connectors, and multiple hard drives. The second connectors are coupled to each of the first connectors. The logic circuitry is coupled to the second connectors. The logic circuitry includes firmware. The logic circuitry provides a second signal based on the first signal and an identification code stored in the firmware. The multiple hard drive connectors are coupled to the logic circuitry. Each of the multiple hard drives is coupled to each of the hard drive connectors. Each hard drive controls its indicator lights based on the second signal.

[0030] The following detailed description of the features and advantages of this invention is sufficient to enable anyone skilled in the art to understand the technical content of this invention and implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the relevant purpose and advantages of this invention. Simple Explanation of the Diagram

[0031] Figure 1 is a schematic diagram of one embodiment of a server system. Figure 2 is a flowchart of one embodiment of the encoding method for the backplane. Figure 3 is a schematic diagram of one embodiment of step S01. Figure 4 is a flowchart of one embodiment of the backplate identification method. Figure 5 is a schematic diagram of another embodiment of the server system. Figure 6 is a flowchart of another embodiment of the encoding method for the backplane. Figure 7 is a flowchart of another embodiment of the backplate identification method. Implementation

[0032] Figure 1 is a schematic diagram of one embodiment of server system 1. Referring to Figure 1, server system 1 includes a motherboard 10 and a backplane 11. The motherboard 10 includes processing circuitry 101 and a first connector 102. The processing circuitry 101 includes a VPP port 1011. The first connector 102 is coupled to the VPP port 1011. The backplane 11 includes a second connector 111, logic circuitry 112, multiple hard drive connectors 113, and multiple hard drives 114. The second connector 111 is coupled to the first connector 102. The logic circuitry 112 is coupled to the second connector 111. The multiple hard drive connectors 113 are coupled to the logic circuitry 112. Each of the multiple hard drives 114 is individually coupled to a hard drive connector 113.

[0033] In some embodiments, the processing circuit 101 may be, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a microcontroller (MCU), a complex programmable logic device (CPLD), an embedded processor, a network processor, a coprocessor, and other processing units suitable for server systems or electronic devices.

[0034] In some embodiments, the first connector 102 and the second connector 111 may be, but are not limited to, multichannel I / O connectors (MCIO), serial Attached SCSI connectors (SAS), RAID cards, serial advanced technology accessory connectors (SATA), small computer system interface connectors (SCSI), PCIe connectors, M.2 connectors, and other types of connectors suitable for server systems or electronic devices.

[0035] In some embodiments, the second connector 111 is a second connector 111 of a corresponding type to the first connector 102 to which it is connected. For example, if the first connector 102 to which the second connector 111 is connected is an MCIO connector, then the second connector 111 is an MCIO connector. As another example, if the first connector 102 to which the second connector 111 is connected is a SAS connector or a disk array card, then the hard drive connector 113 is a SAS connector.

[0036] In some embodiments, the logic circuit 112 may be, but is not limited to, combinational logic circuits, sequential logic circuits, programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), application-specific integrated circuits (ASICs), and other logic circuits suitable for server systems or electronic devices.

[0037] In some embodiments, hard drive 114 may be, but is not limited to, solid-state drive (SSD), hard disk drive (HDD), hybrid drive (SSHD), small computer system interface drive (SCSI HDD), serial advanced technology accessory drive (SATA HDD), serial attached SCSI drive (SAS HDD), non-volatile memory performance interface drive (NVMe SSD), Fibre Channel drive (FC HDD), and other storage devices suitable for server systems or electronic devices.

[0038] In some embodiments, the hard drive connector 113 corresponds to different types of hard drives 114 it connects to, and its backplane also corresponds to different identification codes, thus the data format transmitted by the hard drive connector 113 is also different. For example, if the hard drive 114 connected to the hard drive connector 113 is an NVMe SSD, then the hard drive connector 113 transmits data in a format corresponding to NVMe, such as the Inter-Integrated Circuit (I2C) communication protocol format. As another example, if the hard drive 114 connected to the hard drive connector 113 is a SAS HDD, then the hard drive connector 113 transmits data in a format corresponding to SAS, such as the Server General Purpose Input / output (SGPIO) format.

[0039] In some embodiments, VPP port 1011 and first connector 102, first connector 102 and second connector 111, and second connector 111 and logic circuit 112 may be interconnected via, but not limited to, system management bus (SMBus), serial peripheral bus (SPI), high-speed data transmission line, PCIe bus, I²C bus, SATA cable, SAS cable, multichannel I / O connection line (MCIO), disk array card connection line, and other transmission lines or buses suitable for server systems or electronic devices.

[0040] Figure 2 is a flowchart of one embodiment of the encoding method for the backplane 11. Please refer to Figures 1 and 2. First, the processing circuit 101 encodes the backplane 11 through multiple pins of the first connector 102 to obtain an identification code corresponding to the backplane 11 (step S01). Next, the processing circuit 101 transmits the identification code to the second connector 111 through the first connector 102. When the logic circuit 112 receives the identification code corresponding to the backplane 11 through the second connector 111, the logic circuit 112 stores the identification code in the firmware of the logic circuit 112 (step S02). After obtaining the identification code corresponding to the backplane 11, the processing circuit 101 stores the identification code in the BIOS of the server system 1 (step S03).

[0041] In some embodiments, during step S01, the processing circuit 101 obtains the identification code corresponding to the backplane 11 through the redundant pins 1021 of the first connector 102. Figure 3 is a schematic diagram of one embodiment of step S01. Please refer to Figure 3. In the embodiment of Figure 3, the first connector 102 is an MCIO connector, and the first connector 102 includes 74 pins (B1~B37 and A1~A37). In the embodiment of Figure 3, the first connector 102 obtains the identification code corresponding to the backplane 11 through pins A9 and A27. That is, pins A9 and A27 are redundant pins 1021 on the first connector 102 that do not have special functions. In this embodiment, pins A9 and A27 of the first connector 102 are electrically connected to two general purpose input / output pins (GPIO) of the processing circuit 101, respectively, to detect the identification code of the backplane electrically connected to the first connector 102.

[0042] In some embodiments, the number of pins of the first connector 102 used to encode the backplane 11 corresponds to the length of the identification code of the backplane 11. Taking FIG3 as an example, the number of pins of the first connector 102 used to encode the backplane 11 is two (A9 and A27), then the length of the identification code of the backplane 11 is two bits. In FIG3, the number of pins of the first connector 102 used to encode the backplane 11 is two, but this is not a limitation, and the number of pins of the first connector 102 used to encode the backplane 11 can be any positive integer.

[0043] In some embodiments, the identification code is represented in binary. Taking Figure 3 as an example, if the identification code of the backplane 11 is 2 bits long, then the identification code of the backplane 11 can be 00, 01, 10, or 11. As another example, if the identification code of the backplane 11 is 3 bits long, then the identification code of the backplane 11 can be 000, 001, 010, 011, 100, 101, 110, or 111.

[0044] In some embodiments, multiple pins of the first connector 102 are configured with pull-up or pull-down resistors via the second connector 111 of the backplane 11 to obtain an identification code corresponding to the backplane 11. The configuration of these pull-up or pull-down resistors is based on the type of hard drive 114 inserted on the backplane 11. Referring to Figure 3, pin A9 is electrically connected to a grounded pull-down resistor on the backplane 11. This pull-down resistor causes the processing circuit 101 of the motherboard 10 to obtain a code of 0 from the corresponding pin of the second connector 111 of the backplane 11 via pin A9. Pin A27 is electrically connected to a pull-up resistor connected to Vdd on the backplane 11. This pull-up resistor causes the processing circuit 101 of the motherboard 10 to obtain a code of 1 from the corresponding pin of the second connector 111 of the backplane 11 via pin A27. If the code corresponding to pin A9 on backplane 11 is the first bit of the identification code of backplane 11, and the code corresponding to pin A27 on backplane 11 is the second bit of the identification code of backplane 11, then the identification code of backplane 11 is 01.

[0045] In some embodiments, the processing circuit 101 of the motherboard 10 is electrically connected to pins A9 and A27 of the first connector via two GPIO pins, respectively. Similarly, the logic circuit 112 of the backplane 11 is also electrically connected to pins A9 and A27 of the first connector via two different GPIO pins through the second connector 111. Therefore, both the processing circuit 101 and the logic circuit 112 can directly obtain the identification code corresponding to the backplane 11 based on the influence of the pull-up resistors and / or pull-down resistors connected to the second connector 111 of the backplane 11 on the voltage levels of pins A9 and A27. In some embodiments, the processing circuit 101 transmits the identification code as a signal to the second connector 111 via the first connector 102. For example, please refer to FIG1. After the processing circuit 101 obtains the identification code corresponding to the backplane 11, the processing circuit 101 transmits the identification code to the second connector 111 through the first connector 102 in the form of signal S3. When the logic circuit 112 receives the signal S3 through the second connector 111, the logic circuit 112 stores the identification code in the firmware of the logic circuit 112.

[0046] In some embodiments, the identification code of the backplane 11 is directly assigned by the processing circuit 101 of the motherboard 10.

[0047] In some embodiments, the method for generating the identification code of the backplane 11 is as follows: the processing circuit 101 of the motherboard 10 transmits an indication signal to the unknown backplane 11 based on a plurality of known backplane 11 identification codes already stored in the BIOS of the server system 1. The unknown backplane 11 detects the hard drive types of the plurality of hard drives 114 contained therein and performs calculations based on the indication signal containing the information of the plurality of known backplane 11 identification codes transmitted by the processing circuit 101 of the motherboard 10 to generate another identification code. The logic circuit 112 of the unknown backplane 11 stores this other identification code in the firmware of the logic circuit 112 and sends this other identification code back to the processing circuit 101 of the motherboard 10. This other identification code is the identification code of the unknown backplane 11.

[0048] For example, suppose the motherboard 10 supports three types of hard drives: NVMe, SAS, and SATA. The logic circuit 112 defines the third bit of the identification code of the backplane 11 based on the type of the multiple hard drives 114 contained in the backplane 11. For instance, when the multiple hard drives 114 contained in the backplane 11 are type 1 hard drives, the third bit of the identification code of the backplane 11 is 1; when the multiple hard drives 114 contained in the backplane 11 are type 2 hard drives, the third bit of the identification code of the backplane 11 is 2; and when the hard drives contained in the backplane 11 are type 3 hard drives, the third bit of the identification code of the backplane 11 is 3. When the motherboard 10 receives a 301 (i.e., an indication signal) for an unknown backplane 11, it means that the motherboard 10 has obtained identification codes 300 and 301 for the multiple known backplanes 11. If the multiple hard drives 114 contained in the unknown backplane 11 are of type 3 hard drives, then the logic circuit 112 of the unknown backplane 11 will continue the encoding of 301 to generate an identification code with a value of 302 corresponding to the unknown backplane 11, store this identification code in the firmware of the logic circuit 112, and send this identification code back to the processing circuit 101 of the motherboard 10. In the above example, since the motherboard 10 has not yet obtained any identification code of the backplane 11 containing type 1 or type 2 hard drives, the transmitted indication signal does not contain the identification code of the backplane 11 corresponding to type 1 or type 2 hard drives. Therefore, if the multiple hard drives 114 contained in the unknown backplane 11 are type 1 or type 2 hard drives, then their corresponding identification code can be 100 or 200.

[0049] Figure 4 is a flowchart of one embodiment of the backplane 11 identification method. In some embodiments, the server system 1 executes the backplane 11 identification method as shown in Figure 4 only after the server system 1 has completed the encoding method of the backplane 11 as shown in Figure 2. Please refer to Figures 1 and 4. First, the processing circuit 101 of the motherboard 10 provides a first signal S1 to the logic circuit 112 of the backplane 11 (step S11). Next, the logic circuit 112 of the backplane 11 provides a second signal S2 to the plurality of hard drives 114 according to the first signal S1 and the identification code stored in the firmware (step S12). Finally, each hard drive 114 controls its indicator light according to the second signal S2 (step S13).

[0050] In step S11, specifically, the processing circuit 101 of the motherboard 10 first transmits the first signal S1 to the first connector 102 through the VPP port 1011, and the first signal S1 is then transmitted to the logic circuit 112 of the backplane 11 through the first connector 102 and the second connector 111.

[0051] In some embodiments, the processing circuit 101 provides a first signal S1 to the logic circuit 112 based on the identification code stored in the BIOS of the server system 1 after the server system 1 completes step S03.

[0052] In some embodiments, the first signal S1 is a sequential signal. In some embodiments, the second signal S2 is a parallel signal.

[0053] Figure 5 is a schematic diagram of another embodiment of server system 1. Referring to Figure 5, server system 1 includes a motherboard 20 and multiple backplanes 11. The motherboard 20 includes processing circuitry 101 and multiple first connectors 102. The processing circuitry 101 includes a VPP port 1011. The multiple first connectors 102 are coupled to the VPP port 1011. Each backplane 11 includes a second connector 111, logic circuitry 112, multiple hard disk connectors 113, and multiple hard disks 114. The second connectors 111 are coupled to each of the first connectors 102. The logic circuitry 112 is coupled to the second connectors 111. The multiple hard disk connectors 113 are coupled to the logic circuitry 112. The multiple hard disks 114 are each coupled to each hard disk connector 113.

[0054] In some embodiments, the number of the plurality of first connectors 102 included in the motherboard 20 corresponds to the number of the plurality of backplanes 11. For example, please refer to FIG5. The number of the plurality of first connectors 102 included in the motherboard 20 of the server system 1 shown in FIG5 corresponds to the number of the plurality of backplanes 11, both of which are 3. In FIG5, the number of the plurality of first connectors 102 included in the motherboard 20 and the number of the plurality of backplanes 11 are 3, but this is not a limitation thereof. The number of the plurality of first connectors 102 included in the motherboard 20 and the number of the plurality of backplanes 11 can be any positive integer.

[0055] In some embodiments, the plurality of first connectors 102 include third connectors 103 and fourth connectors 104. The third connectors 103 and fourth connectors 104 are different types of connectors. The second connectors 111 coupled to the third connectors 103 and the second connectors 111 coupled to the fourth connectors 104 are also therefore different types of connectors. For example, please refer to FIG5. The plurality of first connectors 102 shown in FIG5 includes two third connectors 103 and one fourth connector 104. The two third connectors 103 are MCIO connectors, while the one fourth connector 104 is a disk array card. In this case, the two second connectors 111 coupled to the two third connectors 103 are MCIO connectors, and the second connector 111 coupled to the fourth connector 104 is a SAS connector.

[0056] Figure 6 is a flowchart of another embodiment of the encoding method for the backplane 11. Please refer to Figures 5 and 6. First, the processing circuit 101 encodes each backplane 11 through multiple pins of each first connector 102 to obtain an identification code corresponding to each backplane 11 (step S21). Next, the processing circuit 101 transmits the identification code to each second connector 111 through each first connector 102. When each logic circuit 112 receives the identification code corresponding to each backplane 11 through each second connector 111, each logic circuit 112 stores the identification code in its firmware (step S22). After obtaining the identification code corresponding to each backplane 11, the processing circuit 101 stores the identification code in the BIOS of the server system 1 (step S23).

[0057] In some embodiments, during step S21, the processing circuit 101 encodes each backplane 11 through the redundant pins 1021 of each first connector 102 to obtain an identification code corresponding to each backplane 11.

[0058] In some embodiments, the firmware of each logic circuit 112 stores the identification codes of all backplanes 11. In other words, in some embodiments, the identification codes stored in the firmware of each logic circuit 112 are the same, that is, all logic circuits 112 of the backplanes 11 can use the same firmware.

[0059] In some embodiments, the processing circuit 101 transmits the identification code as a signal to each of the first connectors 102 and each of the second connectors 111. For example, please refer to FIG5. After the processing circuit 101 obtains the identification code corresponding to each backplane 11, the processing circuit 101 transmits the identification code as a signal S3 to each of the first connectors 102 and each of the second connectors 111. When each logic circuit 112 receives the signal S3 through each of the second connectors 111, each logic circuit 112 stores the identification code in the firmware of each logic circuit 112.

[0060] Figure 7 is a flowchart of another embodiment of the backplane 11 identification method. In some embodiments, the server system 1 executes the backplane 11 identification method as shown in Figure 7 only after the server system 1 has completed the encoding method of the backplane 11 as shown in Figure 6. Please refer to Figures 5 and 7. First, the processing circuit 101 of the motherboard 20 provides a first signal S1 to the logic circuit 112 of each backplane 11 (step S31). Next, the logic circuit 112 of each backplane 11 provides a second signal S2 to the plurality of hard drives 114 of each backplane 11 according to the first signal S1 and the identification code stored in the firmware of the logic circuit 112 of each backplane 11 (step S32). Finally, the plurality of hard drives 114 of each backplane 11 control their indicator lights according to the second signal S2 (step S33).

[0061] In step S31, specifically, the processing circuit 101 of the motherboard 20 first transmits the first signal S1 to each first connector 102 through the VPP port 1011. The first signal S1 is then transmitted to the logic circuit 112 of each backplane 11 through each first connector 102 and each second connector 111.

[0062] In some embodiments, the processing circuit 101 provides a first signal S1 to each logic circuit 112 based on the identification code stored in the BIOS of the server system 1 after the server system 1 completes step S23.

[0063] In summary, in some embodiments, by storing the identification code of each backplane 11 in the BIOS of the server system 1 and the firmware of the logic circuit 112 of each backplane 11, the problem of incorrect display of the hard drive 114 LEDs due to incorrect installation can be effectively avoided, further improving the reliability of the server system 1. Furthermore, all backplanes 11 in the server system 1 can use the same firmware, eliminating the need for individual firmware to support different backplanes 11, thereby simplifying the management of the server system 1. In addition, in some embodiments, by using the redundant pins 1021 of the first connector 102 to encode each backplane 11, the server system 1 can determine the combination of backplanes 11 without using additional connection cables, further improving the flexibility of the server system 1 and helping to reduce the complexity of after-sales service and maintenance of the server system 1.

[0064] Although the technical content of this case has been disclosed above with reference to preferred embodiments, it is not intended to limit this case. Any modifications and refinements made by those skilled in the art without departing from the spirit of this case should be included within the scope of this case. Therefore, the scope of protection of this case shall be determined by the appended claims.

[0065] 1: Server System 10,20: Motherboard 11: Back panel 101: Processing Circuit 102: First Connector 103: Third Connector 104: Fourth Connector 1011: VPP port 111: Second connector 112: Logic Circuits 113: Hard drive connector 114: Hard Drive S1: First Signal S2: Second signal S3: Signal 1021: Redundant pins S01~S03, S11~S13, S21~S23, S31~S33: Steps

Claims

1. A backplane encoding method, applicable to a server system, the server system including a motherboard and at least one backplane, the motherboard including at least one first connector, each of the at least one backplane including a second connector and a logic circuit, each of the at least one first connector being coupled to each of the at least one second connector, the encoding method comprising: encoding each of the at least one backplane through a plurality of pins of each of the at least one first connector to obtain an identification code corresponding to each of the at least one backplane, wherein, The pins of each of the at least one first connector obtain the identification code corresponding to each of the at least one backplane through a pull-up resistor and / or a pull-down resistor configured in the second connector of each of the at least one backplane, and the configuration of the pull-up resistor and / or the pull-down resistor is configured according to the type of multiple hard drives inserted in each of the at least one backplane; each of the at least one identification code is stored in firmware of each of the at least one logic circuit; each of the at least one identification code is stored in a BIOS of the server system; when one of the at least one unknown backplanes is connected to the motherboard, a processing circuit of the motherboard transmits an indication signal to the unknown backplane according to the identification codes of multiple known backplanes stored in the BIOS; The logic circuit of the unknown backplane detects the type of the hard drives inserted in the unknown backplane and calculates another identification code according to the indication signal; and the logic circuit of the unknown backplane stores the other identification code in the firmware and sends the other identification code back to the processing circuit of the motherboard, wherein the other identification code is the identification code of the unknown backplane; wherein the firmware of each of the at least one logic circuit stores the identification codes of all the at least one backplane.

2. The backplane encoding method as described in claim 1, wherein the pins are redundant pins of each of the at least one first connector.

3. The encoding method for the backplane as described in claim 1, wherein the number of pins is 2 and the length of the identification code is 2 bits.

4. The encoding method for the backplane as described in claim 1, wherein the at least one first connector and the at least one second connector are MCIO connectors.

5. The backplane encoding method as claimed in claim 1, wherein the at least one first connector includes a third connector and a fourth connector, the third connector being an MCIO connector, the fourth connector being a disk array card, the second connector coupled to the third connector being an MCIO connector, and the second connector coupled to the fourth connector being a SAS connector.

6. A backplane identification method, applicable to a server system, the server system including a motherboard and at least one backplane, the motherboard including a processing circuit and at least one first connector, the processing circuit being coupled to the at least one first connector, each of the at least one backplane including a second connector, a logic circuit, a plurality of hard drive connectors and a plurality of hard drives, the logic circuit being coupled to the second connector, the hard drive connectors being coupled to the logic circuit, each hard drive being coupled to each of the hard drive connectors, each of the at least one first connector being coupled to each of the at least one second connector, the logic circuit including firmware, the identification method comprising: encoding each of the at least one backplane through a plurality of pins of each of the at least one first connector to obtain an identification code corresponding to each of the at least one backplane, wherein... The pins of each of the at least one first connector obtain the identification code corresponding to each of the at least one backplane through a pull-up resistor and / or a pull-down resistor configured in the second connector of each of the at least one backplane, and the configuration of the pull-up resistor and / or the pull-down resistor is configured according to the type of hard disks inserted in each of the at least one backplane; each of the at least one identification code is stored in the firmware of each of the at least one logic circuit; the processing circuit of the motherboard provides a first signal to the logic circuit of each of the at least one backplane; the logic circuit of each of the at least one backplane provides a second signal to the hard disks of each of the at least one backplane according to the first signal and the identification code stored in the firmware of the logic circuit of each of the at least one backplane; and the hard disks of each of the at least one backplane control their indicator lights according to the second signal.

7. The backplane identification method as described in claim 6, wherein the processing circuit provides the first signal to each of the at least one logic circuit based on the identification code stored in a BIOS of the server system.

8. The backplane identification method as claimed in claim 6, wherein the processing circuitry further includes a VPP port, the processing circuitry being coupled to the at least one first connector via the VPP port.

9. A backplane identification method, applicable to a server system, the server system including a motherboard and at least one backplane, the motherboard including a processing circuit and at least one first connector, the processing circuit being coupled to the at least one first connector, each of the at least one backplane including a second connector, a logic circuit, a plurality of hard drive connectors and a plurality of hard drives, the logic circuit being coupled to the second connector, the hard drive connectors being coupled to the logic circuit, each hard drive being coupled to each of the hard drive connectors, each of the at least one first connector being coupled to each of the at least one second connector, the logic circuit including firmware, the identification method comprising: encoding each of the at least one backplane through a plurality of pins of each of the at least one first connector to obtain an identification code corresponding to each of the at least one backplane, wherein... The pins of each of the at least one first connector obtain the identification code corresponding to each of the at least one backplane through a pull-up resistor and / or a pull-down resistor configured in the second connector of each of the at least one backplane, and the configuration of the pull-up resistor and / or the pull-down resistor is configured according to the type of hard disks inserted in each of the at least one backplane; each of the at least one identification code is stored in the firmware of each of the at least one logic circuit; each of the at least one identification code is stored in a BIOS of the server system; the processing circuit of the motherboard provides a first signal to the logic circuit of each of the at least one backplane; the logic circuit of each of the at least one backplane provides a second signal to the hard disks of each of the at least one backplane according to the first signal and the identification code stored in the firmware of the logic circuit of each of the at least one backplane; the hard disks of each of the at least one backplane control their indicator lights according to the second signal; When one of the at least one unknown backplanes is connected to the motherboard, the processing circuit of the motherboard transmits an indication signal to the unknown backplane based on the identification codes of the multiple known backplanes stored in the BIOS; the logic circuit of the unknown backplane detects the type of the hard drives inserted in the unknown backplane and calculates another identification code based on the indication signal; and the logic circuit of the unknown backplane stores the other identification code in the firmware and sends the other identification code back to the processing circuit of the motherboard, wherein the other identification code is the identification code of the unknown backplane; wherein the firmware of each of the at least one logic circuit stores the identification codes of all the at least one backplane.

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