Package structures and methods for constructing package structures

Abstract

The present invention provides a packaging structure comprising a first interposer, a second interposer, and a quantum wafer. The first interposer includes a first alignment feature. The second interposer includes a second alignment feature. The quantum wafer is bonded to the first interposer, wherein an extension of the first quantum wafer extends beyond a first edge of the first interposer. The first and second interposers are configured such that the first alignment feature engages with the second alignment feature to cause alignment and coupling of one or more components on the extension of the first quantum wafer with one or more components on the second interposer.

Description

Technical Field

[0001] This disclosure is generally about superconducting quantum computing systems, and more specifically, about techniques for packaging multiple chips with qubits to construct modular quantum processors or quantum computers. Prior Technology

[0002] Quantum computing systems can be implemented using superconducting circuit quantum electrodynamics (cQED) architectures, which are constructed using quantum circuit components such as superconducting qubits and other types of superconducting quantum devices controlled by microwave and / or flux bias control signals. Generally, a superconducting qubit is an electronic circuit implemented using components such as superconducting tunneling junctions (e.g., Josephson junctions), superconducting quantum interference devices (SQUIDs), inductors, and / or capacitors, and behaves as a quantum mechanical anharmonic (nonlinear) oscillator with quantized states when cooled to low temperatures.

[0003] As quantum processors scale with increasing superconducting qubit counts and integration densities, modularization approaches have been implemented. This involves individually fabricating multiple smaller, high-yield wafers with qubits and packaging them together to form larger-scale quantum processors. Smaller wafers with qubits are easier to fabricate and defects can be screened before packaging. While modular architectures allow for the construction of larger superconducting quantum processors from smaller modules, packaging individual wafers with qubits together to provide a modular package structure with proper alignment is not straightforward. Summary of the Invention

[0004] The exemplary embodiments disclosed herein include packaging structures and techniques for constructing packaging structures by assembling modules (e.g., quantum computing modules) that include multiple quantum chips (with qubits) and packaging interlayers having alignment features to achieve module alignment.

[0005] For example, an exemplary embodiment includes a package structure comprising a first interposer, a second interposer, and a quantum wafer. The first interposer includes a first alignment feature. The second interposer includes a second alignment feature. The quantum wafer is bonded to the first interposer, wherein an extension of the first quantum wafer extends beyond a first edge of the first interposer. The first and second interposers are arranged such that the first and second alignment features engage to cause alignment and coupling of one or more components on the extension of the first quantum wafer with one or more components on the second interposer.

[0006] Advantageously, the alignment features of the interposer are configured to achieve accurate alignment of packaged components and modules with tight tolerances by physically adjaculating the first and second interposers to engage the corresponding first and second alignment features. For example, the alignment features of the interposer enable accurate alignment and coupling of a quantum chip (or a component thereof) on the first interposer to a chip-to-chip coupling component (e.g., a transmission line) on the second interposer, thereby achieving tight tolerance alignment and coupling of the quantum chip-to-chip coupling structure (e.g., alignment and coupling of qubits of the quantum chip on the first interposer to transmission lines on the second interposer).

[0007] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first alignment feature includes a first edge of the first interposer and the second alignment feature includes a second edge of the second interposer. The first edge and the second edge are adjacent to each other to cause alignment and coupling of one or more components on an extension of the quantum wafer with one or more components on the second interposer.

[0008] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first alignment feature is fitted within the second alignment feature to cause alignment and coupling of one or more components on an extension of the quantum wafer with one or more components on a second interposer layer.

[0009] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first alignment feature includes a first pattern of alignment features and the second alignment feature includes a second pattern of alignment features. The first pattern of alignment features and the second pattern of alignment features interlock to cause alignment and coupling of one or more components on an extension of the quantum wafer with one or more components on a second interposer layer.

[0010] Another exemplary embodiment includes a package structure comprising a first interposer, a second interposer, and a first quantum wafer. The first interposer includes a first edge. The second interposer includes a second edge. The first quantum wafer is bonded to the first interposer, wherein an extension of the first quantum wafer extends beyond the first edge of the first interposer. The first and second interposers are disposed in a plane, wherein the first edge and the second edge are adjacent to cause alignment and coupling of one or more components on the extension of the first quantum wafer with one or more components on the second interposer.

[0011] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first intermediary layer includes a first shape at least partially defined by a first edge, and the second intermediary layer includes a second shape at least partially defined by a second edge, wherein the first shape and the second shape are different shapes.

[0012] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first intermediary layer includes a first shape at least partially defined by a first edge, and the second intermediary layer includes a second shape at least partially defined by a second edge, wherein the first shape and the second shape are the same shape.

[0013] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the second interposer layer includes a second quantum chip, one or more components on the second interposer layer include transmission lines coupled to the second quantum chip, and one or more components on an extension of the first quantum chip include one or more qubits.

[0014] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the package structure further includes a third interposer layer, which includes a third edge. The first interposer layer includes a second edge, and the first quantum wafer is bonded to the first interposer layer, wherein a second extension of the first quantum wafer extends beyond the second edge of the first interposer layer. The third interposer layer is disposed on a plane having the first and second interposers layer. The second edge of the first interposer layer is adjacent to the third edge of the third interposer layer to cause alignment and coupling of one or more components on the second extension of the first quantum wafer with one or more components on the third interposer layer.

[0015] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first interposer layer includes a first shape at least partially defined by a first edge and a second edge of the first interposer layer, the second interposer layer includes a second shape at least partially defined by a second edge of the second interposer layer, and the third interposer layer includes a third shape at least partially defined by a third edge of the third interposer layer. The first shape, the second shape, and the third shape are identical.

[0016] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the first interposer layer includes a first shape at least partially defined by a first edge and a second edge of the first interposer layer, the second interposer layer includes a second shape at least partially defined by a second edge of the second interposer layer, and the third interposer layer includes a third shape at least partially defined by a third edge of the third interposer layer. The second and third shapes are the same shape, and the first shape is different from the second and third shapes.

[0017] In another exemplary embodiment, as can be combined with the foregoing paragraphs, the third interposer layer includes a third quantum chip. One or more components on the third interposer layer include transmission lines coupled to the third quantum chip, and one or more components on the second extension of the first quantum chip include one or more qubits.

[0018] Another exemplary embodiment includes a package structure comprising a first module and a second module. The first module includes: a first interposer layer having a first edge; and a first quantum chip bonded to the first interposer layer, wherein an extension of the first quantum chip extends beyond the first edge of the first interposer layer. The second module includes: a second interposer layer having a second edge; a second quantum chip bonded to the second interposer layer; and a transmission line disposed on the second interposer layer and coupled to the second quantum chip. The first and second interposers are disposed in a plane, wherein the first edge and the second edge are adjacent to cause alignment and coupling of one or more components on the extension of the first quantum chip to one or more of the transmission lines on the second interposer layer coupled to the second quantum chip.

[0019] Another exemplary embodiment includes a method comprising: forming an interposer on a substrate; and dicing the substrate to separate the interposer into at least a first interposer including a first edge and a second interposer including a second edge. The first edge and the second edge are configured to cause alignment of a structure on the first interposer with a structure on the second interposer when the first edge and the second edge are adjacent, wherein the first interposer and the second interposer are disposed in a plane.

[0020] Another exemplary embodiment includes a method comprising: constructing a first module including: a first interposer layer having a first edge; and a first quantum wafer bonded to the first interposer layer, wherein an extension of the first quantum wafer extends beyond the first edge of the first interposer layer; constructing a second module including: a second interposer layer having a second edge; a second quantum wafer bonded to the second interposer layer; and a transmission line disposed on the second interposer layer and coupled to the second quantum wafer; and assembling the first module and the second module, wherein the first interposer layer and the second interposer layer are disposed in a plane, wherein the first edge and the second edge are adjacent to cause alignment and coupling of one or more components on the extension of the first quantum wafer to one or more of the transmission lines on the second interposer layer coupled to the second quantum wafer.

[0021] Other embodiments will be described in the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0022] Figure 1 schematically illustrates a modular packaging structure according to an exemplary embodiment of the present disclosure.

[0023] Figures 2A, 2B and 2C schematically illustrate a method for constructing a modular packaging structure according to an exemplary embodiment of the present disclosure.

[0024] Figures 3A and 3B schematically illustrate a modular packaging structure according to another exemplary embodiment of the present disclosure.

[0025] Figure 4A schematically illustrates a modular packaging structure according to another exemplary embodiment of this disclosure.

[0026] Figures 4B, 4C and 4D schematically illustrate a method for constructing a modular packaging structure according to another exemplary embodiment of the present disclosure.

[0027] Figure 5A schematically illustrates a modular packaging structure according to another exemplary embodiment of this disclosure.

[0028] Figures 5B, 5C and 5D schematically illustrate a method for constructing a modular packaging structure according to another exemplary embodiment of the present disclosure.

[0029] Figures 6A and 6B schematically illustrate a method for constructing an intermediary layer for a modular packaging structure according to an exemplary embodiment of the present disclosure.

[0030] Figures 7A and 7B schematically illustrate a method for constructing an intermediary layer for a modular packaging structure according to another exemplary embodiment of this disclosure.

[0031] Figures 8A and 8B schematically illustrate a method for constructing an intermediary layer for a modular packaging structure according to another exemplary embodiment of this disclosure.

[0032] Figures 9A, 9B, and 9C schematically illustrate a method for constructing an intermediary layer for a modular packaging structure according to another exemplary embodiment of the present disclosure.

[0033] Figure 10 illustrates a flowchart of a method for constructing a modular packaging structure according to an exemplary embodiment of the present disclosure.

[0034] Figure 11 schematically illustrates a quantum computing system according to an exemplary embodiment of the present disclosure, the quantum computing system including a quantum processor including a modular packaging structure using multiple quantum modules. Implementation

[0035] The exemplary embodiments disclosed herein will now be described in further detail with respect to modular packaging structures and techniques for constructing modular packaging structures using quantum modules, wherein such quantum modules have packaging interposers designed to have alignment features. The alignment features are configured to achieve strict tolerance alignment of two or more interposers disposed on the same plane (e.g., the XY plane) by physically engaging the alignment features of the interposers to induce alignment between one or more structures on one interposer and one or more structures on another interposer, wherein this strict tolerance alignment is achieved in the first and second orthogonal lateral directions (e.g., the X and Y directions) of the plane (XY plane).

[0036] It should be understood that the various features shown in the accompanying drawings are schematic illustrations not drawn to scale. Furthermore, the same or similar element symbols are used throughout the drawings to indicate the same or similar features, elements, or structures, and therefore, detailed explanations of the same or similar features, elements, or structures will not be repeated for each item in the drawings. Additionally, the term "illustrative" as used herein means "serving as an example, example, or illustration." Any embodiment or design described herein as "illustrative" should not be construed as superior or more advantageous than other embodiments or designs.

[0037] Additionally, it should be understood that the phrase "configured to" used in conjunction with circuits, structures, elements, components or the like that perform one or more functions or otherwise provide some functionality is intended to cover circuits, structures, elements, components or the like that are implemented in hardware, software and / or a combination thereof and implemented in an implementation that includes hardware, wherein the hardware may include quantum circuit elements (e.g., qubits, tunable couplers, etc.), discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application-specific integrated circuit (ASIC) chips, field-programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing unit (CPU), graphics processing unit (GPU) etc.), one or more integrated circuits and / or combinations thereof. Therefore, by way of example only, when circuits, structures, elements, components, etc. are defined as being configured to provide a particular function, it is intended to cover, but not limited to, embodiments of circuits, structures, elements, components, etc., consisting of elements, processing devices, and / or integrated circuits that enable them to perform a particular function when in an operational state (e.g., connected or otherwise deployed in a system, powered, receiving input, and / or generating output), as well as embodiments when circuits, structures, elements, components, etc. are in a non-operational state (e.g., not connected or otherwise deployed in a system, not powered, not receiving input, and / or not generating output) or in a partially operational state.

[0038] To provide spatial context for the different structural orientations of the semiconductor structures shown in the figures, XYZ Cartesian coordinates are displayed in the figures. The terms "vertical," "vertical direction," or "vertical height" as used herein refer to the Z-direction of the Cartesian coordinates shown in the figures, and the terms "horizontal," "horizontal direction," "lateral," or "lateral direction" as used herein refer to the X-direction and / or Y-direction of the Cartesian coordinates shown in the figures.

[0039] Furthermore, the term "quantum chip" as used herein refers to a die (e.g., a semiconductor die) containing superconducting electronic integrated circuits, which include various superconducting components such as qubits, tunable couplers, ground planes, signal coplanar waveguides, and resonators. Multiple dies having the same and / or different configurations of superconducting electronic integrated circuits can be fabricated on a wafer (e.g., a semiconductor wafer), wherein individual dies can be diced (cut) from the wafer using a die monolithization process to provide monolithized dies that can be packaged together to construct a modular quantum processor architecture. The terms "quantum chip" and "quantum die" are synonymous and are used interchangeably herein. The terms "quantum computing module," "quantum module," or "module" as used herein are synonymous and refer to an assembly of interposers to which one or more quantum chips are bonded. Furthermore, the terms “non-current coupling” or “non-current connection” used in this article refer to non-direct electrical connections, such as connections achieved through capacitive coupling, inductive coupling, optical coupling, or combinations thereof.

[0040] Figure 1 schematically illustrates a modular packaging structure according to an exemplary embodiment of the present disclosure. More specifically, Figure 1 is a schematic top view of a modular packaging structure 100, which includes a plurality of quantum modules, including a first module 110, a second module 120, and a third module 130. The first module 110 includes a first interposer 111 and a quantum chip 112 bonded to the surface of the first interposer 111. The first interposer 111 includes a first edge 111-1 and a second edge 111-2. The second module 120 includes a second interposer 121 and a quantum chip 122 bonded to the surface of the second interposer 121. The second interposer 121 includes a first edge 121-1. The third module 130 includes a third interposer 131 and a quantum chip 132 bonded to the surface of the third interposer 131. The third interposer 131 includes a first edge 131-1.

[0041] As further shown in Figure 1, the quantum wafer 112 includes a first portion 112-1 (alternately referred to herein as a first extension) that extends beyond a first edge 111-1 of the first interposer 111 and partially overlaps with a portion of the second interposer 121. Additionally, the quantum wafer 112 includes a second portion 112-2 (alternately referred to herein as a second extension) that extends beyond a second edge 111-2 of the first interposer 111 and partially overlaps with a portion of the third interposer 131. The first extension 112-1 includes one or more components aligned and coupled to one or more components on the second interposer 121. The second extension 112-2 includes one or more components aligned and coupled to one or more components on the third interposer 131.

[0042] For example, in some embodiments, the first extension 112-1 includes one or more qubits aligned and capacitively coupled to one or more transmission lines on the second interposer 121. Similarly, in some embodiments, the second extension 112-2 includes one or more qubits aligned and capacitively coupled to one or more transmission lines on the third interposer 131. In some embodiments, the capacitive coupling of components (e.g., qubits) on the quantum chip 112 to components (e.g., transmission lines) on the second and third interposers 121 and 131 provides a non-current connection that allows coupling of the quantum chip to the second and third interposers 121 and 131 without additional bonding steps, thereby providing greater flexibility in assembling modular quantum processors comprising a plurality of individual quantum chips mounted on different interposers and operatively coupled together to implement a modular package structure with a large array of qubits.

[0043] Figure 1 illustrates an exemplary embodiment in which strict tolerance alignment between the first module 110 and the second module 120 is achieved by abutting the first edge 111-1 of the first interposer layer 111 with the first edge 121-1 of the second interposer layer 121. Alternatively, strict tolerance alignment between the first module 110 and the third module 130 is achieved by abutting the second edge 111-2 of the first interposer layer 111 with the first edge 131-1 of the third interposer layer 131. In the exemplary embodiment of Figure 1, the first interposer layer 111, the second interposer layer 121, and the third interposer layer 131 are disposed on the same plane (XY plane). In an exemplary package configuration, the first edge 111-1 of the first interposer 111 and the first edge 121-1 of the second interposer 121 include corresponding alignment features that engage (e.g., physically abut) to cause alignment of, for example, qubits on the first extension 112-1 of the quantum wafer 112 with transmission lines in the overlapping region of, for example, the second interposer 121 (e.g., tight tolerance alignment achieved in the X and Y (orthogonal) lateral directions of the XY plane), thereby achieving proper alignment of the quantum wafer 112 of the first module 110 to the second module 120. Similarly, the second edge 111-2 of the first interposer 111 and the first edge 131-1 of the third interposer 131 include corresponding alignment features that engage (e.g., physically abut) to cause alignment of, for example, qubits on the second extension 112-2 of the quantum wafer 112 with transmission lines in the overlapping region of, for example, the third interposer 131 (e.g., self-alignment achieved in the X and Y (orthogonal) lateral directions of the XY plane), thereby achieving proper alignment of the quantum wafer 112 of the first module 110 to the third module 130.

[0044] Figures 2A, 2B, and 2C schematically illustrate a method for constructing a modular package structure according to an exemplary embodiment of the present disclosure. Specifically, Figures 2A, 2B, and 2C schematically illustrate a method for manufacturing the exemplary modular package structure 100 of Figure 1. Figure 2A illustrates the initial stage 200 of the manufacturing process starting from a substrate 102, which is segmented (or delineated) into a first region 111a, a second region 121a, and a third region 131a based on a first dividing line 102-1 and a second dividing line 102-2. The first region 111a, the second region 121a, and the third region 131a correspond to the respective first interposer 111, the second interposer 121, and the third interposer 131.

[0045] The substrate 102 is formed of any suitable material used to form the quantum hardware chip, such as single-crystal silicon (Si), silicon-germanium (SiGe), sapphire, glass, etc. The lateral (XY) dimensions of the substrate 102 may depend on the size, number, and / or layout of the interposers required to construct a given package structure. For example, in an exemplary non-limiting embodiment, the substrate 102 may be a semiconductor wafer, such as a 300 mm diameter silicon wafer (12-inch diameter silicon wafer) having a thickness in the range of 10 micrometers to 1000 micrometers, or a panel, such as an 800 × 800 square millimeter panel having a thickness in the range of 10 micrometers to 1000 micrometers.

[0046] A metallization process is performed to form patterned metallized structures in different interposer regions 111a, 121a, and 131a on the surface of substrate 102, as required by a given package design. The metallization process involves depositing and patterning metal / metal materials to form planar transmission lines (for data and control signals), ground planes, wafer bonding pads, and other patterned metal elements formed for superconducting quantum computing applications. Metal / metal materials include superconducting metal / metal materials, including but not limited to niobium, aluminum, titanium, tungsten, molybdenum, their nitrides, combinations thereof, and / or similar materials. A superconducting material is any material that exhibits superconducting properties (e.g., no resistance, expelling a magnetic field in a superconducting state) at or below the superconducting critical temperature.

[0047] In some embodiments, the metallization formed on the surface of substrate 102 comprises a single-layer wiring network. In other embodiments, to support higher integration density, the metallization may be a multilayer wiring structure formed on the surface of substrate 102, wherein the multilayer wiring structure comprises multiple layers of patterned superconducting metallization, dielectric layers, and interlayer metal vias that can be fabricated using, for example, back-to-office (BEOL) processes, which are typically used to construct wiring network structures on the functional surface of a semiconductor wafer.

[0048] Furthermore, in some embodiments, holes may be drilled in areas of the substrate 102 to provide through-holes for mounting a plurality of connectors (e.g., clip-on connectors) to the surface of the substrate 102. For example, the through-holes in the substrate 102 may be formed using a precision-machined backplate placed on the surface of the substrate 102 and having various shaped openings corresponding to the shapes and openings to be cut into the substrate 102 to facilitate connector mounting and precise placement of the substrate 102 to the base plate.

[0049] Next, Figure 2B schematically illustrates the result of the dicing process 201, in which the substrate 102 is diced along the first dicing line 102-1 and the second dicing line 102-2 shown in Figure 2A to separate the first interposer region 111a, the second interposer region 121a, and the third interposer region 131a into individual first interposers 111, second interposers 121, and third interposers 131, each having associated metallization and cut shapes / openings for mounting connectors thereto. In some embodiments, the dicing process is performed using state-of-the-art waterjet guided laser processes or other suitable wafer dicing processes for precise dicing. The dicing along the first dicing line 102-1 monomerizes the second interposer 121 from the substrate 102, and the dicing along the second dicing line 102-2 monomerizes the first interposers 111 and the third interposers 131 from the substrate 102. In an exemplary embodiment, the total area of ​​the first interposer 111, the second interposer 121, and the third interposer 131 substantially includes the entire area of ​​the original substrate 102.

[0050] As schematically illustrated in Figure 2B, the cutting along the first dividing line 102-1 results in the formation of a first edge 111-1 of the first intermediary layer 111 and a first edge 121-1 of the second intermediary layer 121. These edges 111-1 and 121-1 include corresponding alignment features (e.g., alignment edges) formed simultaneously as a result of the division. These alignment features achieve strict tolerance alignment of the first intermediary layer 111 and the second intermediary layer 121 in the X and Y lateral directions by physically adjoining the edges 111-1 and 121-1 in an interlocking manner. Similarly, the cutting along the second dividing line 102-2 results in the formation of the second edge 111-2 of the first interposer layer 111 and the first edge 131-1 of the third interposer layer 131, wherein these edges 111-2 and 131-1 include corresponding alignment features (e.g., alignment edges) formed simultaneously as a result of the cutting process. These alignment features achieve strict tolerance alignment of the first interposer layer 111 and the third interposer layer 131 in the X and Y lateral directions by physically abutting the edges 111-1 and 131-1 in an interlocking manner.

[0051] Figure 2B illustrates an exemplary embodiment, wherein a first interposer layer 111 includes a first shape at least partially defined by its first edge 111-1 and second edge 111-2. Additionally, a second interposer layer 121 includes a second shape at least partially defined by its first edge 121-1, wherein the first and second shapes of the first and second interposer layers 111 and 121 are different. Furthermore, a third interposer layer 131 includes a third shape at least partially defined by its first edge 131-1, wherein the shapes of the second and third interposer layers 121 are identical.

[0052] Next, Figure 2C schematically illustrates a process 203 for constructing a plurality of quantum modules by bonding one or more quantum chips to each of the monomerized first interposer 111, second interposer 121, and third interposer 131. Specifically, in the exemplary embodiment of Figure 2C, a first module 110 is formed by bonding a quantum chip 112 to a bonding pad on the first interposer 111, a second module 120 is formed by bonding a quantum chip 122 to a bonding pad on the second interposer 121, and a third module 130 is formed by bonding a quantum chip 132 to a bonding pad on the third interposer 131. The quantum chip 112 is bonded to the first interposer 111, wherein a first portion 112-1 extends beyond a first edge 111-1 of the first interposer 111, and a second portion 112-2 extends beyond a second edge 111-2 of the first interposer 111.

[0053] In some embodiments, quantum chips 112, 122, and 132 are flip-chip bonded to respective interposers 111, 121, and 131 using solder bumps 140 (e.g., indium solder bumps). While exemplary modules 110, 120, and 130 are each shown as having a single quantum chip, it should be understood that quantum modules may be fabricated with two or more quantum chips depending on the application. Quantum chips 112, 122, and 132 each include a superconducting electronic integrated circuit system comprising various superconducting components such as qubits, tunable couplers, ground planes, signal coplanar waveguides, and readout resonators. Qubits may include various types of superconducting qubits, such as transmon qubits, fluxonium qubits, multimode qubits (e.g., two-junction qubits or tunable coupled qubits), and other suitable types of fixed-frequency or tunable-frequency qubits. Tunable couplers can be implemented using frequency-tunable qubits, which do not encode quantum information but are used to control / regulate the interactions between superconducting qubits (e.g., entanglement gate operation).

[0054] The first module 110, the second module 120, and the third module 130 are then assembled together to construct an exemplary package structure 100 as shown in FIG1. ​​As mentioned above, the first module 110, the second module 120, and the third module 130 are assembled by a process that includes placing the modules 110, 120, and 130 adjacent to each other in the same plane; and (i) achieving a strict tolerance alignment between the first module 110 and the second module 120 by abutting the first edge 111-1 of the first interposer layer 111 with the first edge 121-1 of the second interposer layer 121; and (ii) achieving a strict tolerance alignment between the first module 110 and the third module 130 by abutting the second edge 111-2 of the first interposer layer 111 with the first edge 131-1 of the third interposer layer 131. The edges 111-1 and 121-1 of the first interposer layer 111 and the second interposer layer 121 include corresponding alignment edges that are joined (e.g., physically adjacent) to cause a tight-precision alignment between components (e.g., qubits) on the first extension 112-1 of the quantum wafer 112 and components (e.g., transmission lines) on the second interposer layer 121. Similarly, the edges 111-2 and 131-1 of the first interposer layer 111 and the third interposer layer 131 include corresponding alignment edges that are joined (e.g., physically adjacent) to cause a tight-precision alignment between components (e.g., qubits) on the second extension 112-2 of the quantum wafer 112 and components (e.g., transmission lines) on the third interposer layer 131. In this configuration, the components (e.g., qubits) on the first extension 112-1 and the second extension 112-2 of the quantum chip 112 are aligned with each other (e.g., transmission lines) on the second interposer 121 and the third interposer 131 with strict accuracy in both the X and Y lateral directions in the XY plane, thereby achieving proper alignment and coupling of the quantum chip 112 of the first module 110 to the second module 120 and the third module 130.

[0055] Figures 3A and 3B schematically illustrate a modular package structure according to another exemplary embodiment of the present disclosure. Specifically, Figure 3A is a schematic perspective view of the modular package structure 300, and Figure 3B is a schematic cross-sectional view of the modular package structure 300 along a portion of line XX in Figure 3A. The modular package structure 300 includes a plurality of quantum modules, including a first module 310, a second module 320, and a third module 330. The first module 310 includes a first interposer 311 and a quantum wafer 312 bonded to the surface of the first interposer 311. The first interposer 311 includes a first edge 311-1 and a second edge 311-2. The second module 320 includes a second interposer 321 and a quantum wafer 322 bonded to the surface of the second interposer 321. The second interposer 321 includes a first edge 321-1. The third module 330 includes a third interposer 331 and a quantum chip 332 bonded to the surface of the third interposer 331. The third interposer 331 includes a first edge 331-1.

[0056] The exemplary modular package structure 300 has an architecture similar to the modular package structure 100 of FIG1 because the first interposer 311, the second interposer 321, and the third interposer 331 have the same or similar shapes as the first interposer 111, the second interposer 121, and the third interposer 131 of the modular package structure 100. Furthermore, similar to the quantum chip 112 shown in FIG1, the quantum chip 312 includes a first extension 312-1 that extends beyond the first edge 311-1 of the first interposer 311 and partially overlaps with a portion of the second interposer 321. Additionally, the quantum chip 312 includes a second extension 312-2 that extends beyond the second edge 311-2 of the first interposer 311 and partially overlaps with a portion of the third interposer 331.

[0057] The exemplary modular package structure 300 further includes a plurality of connectors 313 mounted on the surface of a first interposer 311, a plurality of connectors 323 mounted on the surface of a second interposer 321, and a plurality of connectors 333 mounted on the surface of a third interposer 331. Connectors 313 are configured to enable the transmission of I / O signals (data and control signals) between the quantum chip 312 on the first interposer 311 and a remote computing system or control electronics device. Similarly, connectors 323 are configured to enable the transmission of I / O signals (data and control signals) between the quantum chip 322 on the second interposer 321 and a remote computing system or control electronics device. Additionally, connectors 333 are configured to enable the transmission of I / O signals (data and control signals) between the quantum chip 332 on the third interposer 331 and a remote computing system or control electronics device. Connectors 323 and 333 can be implemented using any type of connector suitable for superconducting quantum computing.

[0058] Figure 3B schematically illustrates an exemplary embodiment, wherein quantum chips 312, 322, and 332 are flip-chip bonded to respective arrays of interconnects 314, 324, and 334 using solder bumps. Additionally, the modular package structure 300 includes various metallizations on the surfaces of the first interconnect 311, the second interconnect 321, and the third interconnect 331, including but not limited to planar signal transmission lines 325 and 335 (e.g., coplanar waveguides (CPW)), which are configured to transmit I / O signals between the quantum chips (e.g., quantum chips 322 and 332) and connectors (e.g., connectors 323 and 333, as specifically shown in Figure 3B) on the corresponding interconnects (e.g., the second interconnect 321 and the third interconnect 331, as specifically shown in Figure 3B).

[0059] Additionally, Figure 3B schematically illustrates a first extension 312-1 of the quantum chip 312 overlapping a portion of the second interposer 321. The first extension 312-1 includes a metallide 314, which is aligned and capacitively coupled to a metallide 327 on the second interposer 321 by abutting the edges 311-1 and 321-1 of the first interposer 311 and the second interposer 321, as shown. Furthermore, a second extension 312-2 of the quantum chip 312 is shown overlapping a portion of the third interposer 331. The second extension 312-2 includes a metallide 315, which is aligned and capacitively coupled to a metallide 337 on the third interposer 331 by abutting the edges 311-2 and 331-1 of the first interposer 311 and the third interposer 331. In some embodiments, metallizations 314 and 315 of the first extension portion 312-1 and the second extension portion 312-2 include quantum components, such as qubits, and metallizations 327 and 337 on the second interposer layer 321 and the third interposer layer 331 include transmission lines non-current coupled to the qubits via a vacuum gap capacitor structure.

[0060] Figure 4A schematically illustrates a modular package structure according to another exemplary embodiment of the present disclosure. More specifically, Figure 4A is a schematic top view of a modular package structure 400 comprising a plurality of quantum modules, including a first module 410 and a second module 420. The first module 410 includes a first interposer 411, a first quantum chip 412 bonded to the surface of the first interposer 411, and a second quantum chip 413 bonded to the surface of the first interposer 411. The second module 420 includes a quantum chip 422 bonded to the surface of a second interposer 421. The second quantum chip 413 of the first module 410 partially overlaps with and is coupled to the second interposer 421.

[0061] Figure 4A schematically illustrates an exemplary embodiment, wherein a first interposer layer 411 includes a first alignment feature 411-1 and a second interposer layer 421 includes a second alignment feature 421-1. The first alignment feature 411-1 includes a first pattern of features (e.g., a first pattern of finger elements and grooves) and the second alignment feature 421-1 includes a second pattern of features (e.g., a second pattern of finger elements and grooves), the features having corresponding opposing patterns that interlock with each other to link adjacent edges of the first interposer layer 411 and the second interposer layer 421 and cause one or more structures on the first interposer layer 411 to align with one or more structures on the second interposer layer 421.

[0062] Figures 4B, 4C, and 4D schematically illustrate a method for constructing the modular package structure 400 of Figure 4A according to another exemplary embodiment of this disclosure. Figure 4B schematically illustrates the initial stage of a manufacturing process starting from a substrate 402 (e.g., a portion of a semiconductor wafer), which is segmented (or demarcated) into a first region 411a and a second region 421a based on a dividing line 402-1. The first region 411a and the second region 421a correspond to respective first interposers 411 and second interposers 421. The substrate 402 may comprise silicon substrates as discussed above or other types of materials. A metallization process is performed to form patterned metallized structures in the different interposer regions 411a and 421a on the surface of the substrate 402, as desired for a given package design.

[0063] Next, Figure 4C schematically illustrates the result of the dicing process, wherein the substrate 402 is cut along dicing line 402-1 to separate the first interposer region 411a and the second interposer region 421a into separate individual first interposers 411 and second interposers 421. The cutting along dicing line 402-1 results in the formation of a first alignment feature 411-1 for the first interposer 411 and a corresponding second alignment feature 421-1 for the second interposer 421. The first alignment feature 411-1 includes a first pattern of finger elements and trenches forming a first zigzag edge of the first interposer 411. The second alignment feature 421-1 includes a second pattern of finger elements and trenches forming a second zigzag edge of the second interposer 421. The first alignment feature 411-1 and the second alignment feature 421-1 have corresponding patterns of fingers and grooves. These patterns interlock (or overlap) and are linked by abutting the first and second zigzag edges of the first interposer layer 411 and the second interposer layer 421, thereby causing alignment of one or more structures on the first interposer layer 411 with one or more structures on the second interposer layer 421. The corresponding first alignment feature 411-1 and the second alignment feature 421-1 are formed simultaneously as a result of cutting the substrate 402 along the dividing line 402-1. This is achieved by interlocking the corresponding fingers and grooves of the first alignment feature 411-1 and the second alignment feature 421-1 in an interlocking manner and abutting the first and second zigzag edges of the first interposer layer 411 and the second interposer layer 421 to achieve strict tolerance alignment of the first interposer layer 411 and the second interposer layer 421 in the X and Y lateral directions.

[0064] Next, Figure 4D schematically illustrates the process of constructing a first quantum module 410 and a second quantum module 420 by bonding one or more quantum chips to each of the monomerized first interposer layer 411 and second interposer layer 421. Specifically, in the exemplary embodiment of Figure 4D, the first module 410 is formed by bonding a first quantum chip 412 to a bonding pad on the first interposer layer 411 and bonding a second quantum chip 413 to a bonding pad on the first interposer layer 411. The bonding pads on the first interposer layer include bonding pads located on one or more of the finger elements of the first alignment feature 411-1. The second module 420 is formed by bonding a quantum chip 422 to a bonding pad on the second interposer layer 421.

[0065] The first module 410 and the second module 420 are then assembled together to construct an exemplary package structure 400 as shown in FIG. 4A. For example, the first module 410 and the second module 420 are assembled by a process that includes placing the modules 410 and 420 adjacent to each other in the same plane and causing a tight tolerance alignment between the first module 410 and the second module 420 by insertably fitting the fingers of the first alignment feature 411-1 and the second alignment feature 421-1 into corresponding grooves of the first alignment feature 411-1 and the second alignment feature 421-1 and abutting the first and second flexural edges of the first interposer layer 411 and the second interposer layer 421. This process causes strict tolerance alignment of qubits on a portion of the second quantum wafer 413 (which does not overlap with the first interposer 411) with signal transmission lines located on the trenches of the second alignment feature 421-1 and other areas on the surface of the second interposer 421 that overlap with the second quantum wafer 413 and coupled to qubits on the quantum wafer 422 on the second interposer 421.

[0066] Figure 5A schematically illustrates a modular package structure according to another exemplary embodiment of the present disclosure. More specifically, Figure 5A is a schematic top view of a modular package structure 500 comprising a plurality of quantum modules, including a first module 510 and a second module 520. The first module 510 includes a first interposer 511 and a first quantum wafer 512 and a second quantum wafer 513 bonded to the surface of the first interposer 511. The second module 520 includes a first quantum wafer 522 and a second quantum wafer 523 bonded to the surface of a second interposer 521. The second quantum wafer 513 of the first module 510 includes an extension 513-1 that extends beyond the edge of the first interposer 511 and is coupled to a region of the second interposer 521 that overlaps with the extension 513-1 of the quantum wafer 513.

[0067] Figure 5A schematically illustrates an exemplary embodiment, wherein a first intermediary layer 511 includes a first alignment feature 511-1 formed on its edge E1, and a second intermediary layer 521 includes a corresponding second alignment feature 521-1 formed on its edge E2. The first alignment feature 511-1 includes a tongue-shaped feature, and the second alignment feature 521-1 includes a corresponding groove-shaped feature. In some embodiments, as shown in Figure 5A, the first alignment feature 511-1 and the second alignment feature 521-1 include triangular or V-shaped features. The first alignment feature 511-1 is insertably fitted into the second alignment feature 521-1 to interlock the first interposer layer 511 and the second interposer layer 521 when edges E1 and E2 are physically adjacent. This causes alignment of one or more structures on the first interposer layer 511 with one or more structures on the second interposer layer 521, for example, causing alignment of the extension 513-1 of the quantum wafer 513 with a bonding pad on a region of the second interposer layer 521 that overlaps with the extension 513-1 of the quantum wafer 513. It should be noted that although the first alignment feature 511-1 and the second alignment feature 521-1 are shown as V-shaped features, in other embodiments, the first alignment feature 511-1 and the second alignment feature 521-1 may have other corresponding shapes, such as rectangular features, hemispherical features, etc. []

[0068] Figures 5B, 5C, and 5D schematically illustrate a method for constructing the modular package structure 500 of Figure 5A according to another exemplary embodiment of this disclosure. Figure 5B schematically illustrates the initial stage of a manufacturing process starting from a substrate 502 (e.g., a portion of a semiconductor wafer), which is segmented (or delineated) into a plurality of regions based on dividing lines 502-1 and 502-2, including regions 511a, 521a, 531a, and 541a, etc. For illustrative purposes, regions 511a and 521a correspond to respective first interposer 511 and second interposer 521. The substrate 502 may comprise the silicon substrate discussed above or other types of materials. A metallization process is performed to form patterned metallized structures on the surface of the substrate 502 in the different interposer regions 511a, 521a, 531a, and 541a, as desired for a given package design.

[0069] Next, Figure 5C schematically illustrates the result of the dicing process, in which the substrate 502 is cut along dicing lines 502-1 and 502-2 to separate the interposer regions 511a, 521a, 531a, and 541a into monomerized interposers, including, for example, individual first interposers 511 and second interposers 521. The cutting along dicing line 502-1 results in the formation of a first alignment feature 511-1 on the edge E1 of the first interposer 511 and a corresponding second alignment feature 521-1 on the edge E2 of the second interposer 521. The corresponding first alignment feature 511-1 and second alignment feature 521-1 are formed simultaneously as a result of cutting the substrate 502 along dicing line 502-1.

[0070] Next, Figure 5D schematically illustrates the process of constructing a first quantum module 510 and a second quantum module 520 by bonding one or more quantum chips to each of the monomerized first interposer layer 511 and second interposer layer 521. Specifically, in the exemplary embodiment of Figure 5D, the first module 510 is formed by bonding quantum chips 512 and 513 to the first interposer layer 511, wherein the extension portion 513-1 extends beyond the edge E1 of the first interposer layer. The second module 520 is formed by bonding quantum chips 522 and 523 to the second interposer layer 521.

[0071] The first module 510 and the second module 520 are then assembled together to construct an exemplary package structure 500 as shown in FIG. 5A. For example, the first module 510 and the second module 520 are assembled by a process that includes placing the modules 510 and 520 adjacent to each other in the same plane and causing self-alignment of the first module 510 and the second module 520 by insertably fitting a first alignment feature 511-1 into a second alignment feature 521-1 and abutting the edges E1 and E2 of the first interposer layer 511 and the second interposer layer 521. This process causes a tight alignment between qubits disposed on an extension 513-1 of the second quantum chip 513 and, for example, transmission lines located in a region of the second interposer layer 521 that overlaps with the extension 513-1 of the quantum chip 513.

[0072] It should be understood that other types of interposer patterns and shapes can be implemented to achieve self-alignment in two orthogonal lateral directions (e.g., X and Y directions) by edge adjacency of two or more interposers disposed in the same plane (e.g., the XY plane). Exemplary embodiments of these are now discussed in conjunction with Figures 6A, 6B, 7A, 7B, 8A, 8B, 9A, and 9B. Specifically, Figures 6A and 6B schematically illustrate a method for constructing an interposer for a modular package structure according to an exemplary embodiment of this disclosure. Figure 6A schematically illustrates a substrate 600 (e.g., a portion of a semiconductor wafer) segmented (or delineated) into a plurality of interposer regions, such as interposer regions 611a, 621a, and 631a, based on dividing lines (indicated by dashed lines). Each interposer region comprises a hexagonal polygon (e.g., a hexagon) of the same size and shape.

[0073] Figure 6B schematically illustrates the result of a dicing process, wherein a semiconductor substrate 600 is cut along a dicing line to separate the interposer region into individual interposers. For example, Figure 6B illustrates three individual interposers 611, 621, and 631 corresponding to the exemplary interposer regions 611a, 621a, and 631a in Figure 6A. In this configuration, the three individual interposers 611, 621, and 631 can be used to form a modular package structure, wherein self-alignment is achieved in the X and Y directions by adjoining the edges of the three individual interposers 611, 621, and 631 as shown. In this regard, hexagonal interposers utilize at least three hexagonal interposers (e.g., interposers 611, 621, and 631) to achieve tight tolerance alignment of the quantum module, as shown in Figure 6B, through a chain pattern to achieve tight tolerance alignment of the interposers.

[0074] Next, Figures 7A and 7B schematically illustrate a method for constructing an interposer layer according to an exemplary embodiment of the present disclosure. Specifically, Figure 7A schematically illustrates a semiconductor substrate 700 (e.g., a portion of a semiconductor wafer) segmented (or delineated) into a plurality of interposer regions based on dividing lines (indicated by dashed lines), such as interposer regions 711a, 721a, 731a, 741a, 751a, 761a, etc. Each interposer region comprises a triangular area of ​​the same size.

[0075] Figure 7B schematically illustrates the result of the partitioning process, wherein the substrate 700 is cut along the partition line to separate the interposer region into individual interposers. For example, Figure 7B shows six individual triangular interposers 711, 721, 731, 741, 751, and 761 corresponding to the exemplary interposer regions 711a, 721a, 731a, 741a, 751a, and 761a in Figure 7A. In this configuration, the six individual interposers 711, 721, 731, 741, 751, and 761 can be used to form a modular package structure, wherein self-alignment is achieved in the X and Y directions by adjoining the edges of the six individual interposers 711, 721, 731, 741, 751, and 761 as shown. In this regard, the triangular interposer layer uses at least six triangular interposer layers 711, 721, 731, 741, 751 and 761 to achieve strict tolerance alignment of the quantum module, as shown in Figure 7B, to achieve a chain pattern for strict tolerance alignment of the interposer layer.

[0076] Next, Figures 8A and 8B schematically illustrate a method for constructing an interposer layer for a modular package structure according to an exemplary embodiment of the present disclosure. Specifically, Figure 8A schematically illustrates a substrate 800 (e.g., a portion of a semiconductor wafer) segmented (or delineated) into a plurality of interposer regions based on dividing lines (indicated by dashed lines), such as interposer regions 811a, 821a, 831a, 841a, 851a, etc. A first plurality of interposer regions (e.g., regions 811a, 821a, 831a, 841a) each comprises an octagonal polygon (e.g., an octagon) of the same size and shape, and a second plurality of interposer regions (e.g., region 851a) comprises a square interposer region of the same size.

[0077] Figure 8B schematically illustrates the result of a dicing process, in which a semiconductor substrate 800 is cut along a dicing line to separate the interposer region into individual interposers. For example, Figure 8B shows four individual octagonal interposers 811, 821, 831, and 841 corresponding to the exemplary interposer regions 811a, 821a, 831a, and 841a in Figure 8A, and a square interposer 851 corresponding to interposer region 851a. In this configuration, the five individual interposers 811, 821, 831, 841, and 851 can be used to form a modular package structure, wherein self-alignment is achieved in the X and Y directions by adjoining the edges of the five individual interposers 811, 821, 831, 841, and 851 as shown. In this regard, different shaped interposers are used to achieve strict tolerance alignment of the quantum module using at least four octagonal interposers 811, 821, 831 and 841 and one square interposer 851, as shown in Figure 8B, to achieve a chain pattern of strict tolerance alignment of the interposers.

[0078] Next, Figures 9A, 9B, and 9C schematically illustrate a method for constructing an interposer layer for a modular package structure according to another exemplary embodiment of the present disclosure. Specifically, Figure 9A schematically illustrates a semiconductor substrate 900 (e.g., a portion of a semiconductor wafer) segmented (or delineated) into a plurality of interposer regions based on dividing lines (indicated by dashed lines), such as interposer regions 911a, 921a, 931a, 941a, 951a, etc. Each interposer region comprises a herringbone area of ​​the same size.

[0079] Figure 9B schematically illustrates the result of a partitioning process, wherein the substrate 900 is cut along a partition line to separate the interposer region into individual interposers. For example, Figure 9B illustrates three individual interposers 911, 921, and 931 corresponding to the exemplary interposer regions 911a, 921a, and 931a in Figure 9A. In this configuration, the three individual interposers 911, 921, and 931 can be used to form a modular package structure, wherein self-alignment is achieved in the X and Y directions by adjoining the edges of the three individual interposers 911, 921, and 931 as shown. Additionally, Figure 9C schematically illustrates an alternative embodiment, wherein two individual interposers 941 and 951 (corresponding to the exemplary interposer regions 941a and 951a in Figure 9A) can be used to form a modular package structure, wherein self-alignment is achieved in the X and Y directions by adjoining the edges of the two individual interposers 941 and 951 as shown. In this regard, the herringbone interposer uses at least two interposers, such as interposers 911 and 921 (Fig. 9B) and interposers 941 and 951 (Fig. 9C), to achieve a tight tolerance alignment of the quantum module, thereby achieving a chain pattern of tight tolerance alignment of the interposers.

[0080] The exemplary modular packaging structures discussed herein can be manufactured using currently advanced semiconductor manufacturing techniques. For example, Figure 10 illustrates a flowchart of a method 1000 for constructing a modular packaging structure according to an exemplary embodiment of this disclosure. A plurality of quantum wafers (block 1001) are fabricated on a first semiconductor wafer (quantum wafer wafer), and a plurality of interposers (block 1002) are fabricated on a second semiconductor wafer (interposer wafer). For example, on the quantum wafer wafer, various qubit granules are fabricated by photolithography patterns of superconducting material formed on the qubit wafer, wherein each qubit granule includes various components such as superconducting qubits, tunable couplers, ground planes, signal coplanar waveguides, coupler drive lines, qubit drive lines, readout resonators, coupling capacitor pads, coupling inductors, solder bump bonding pads, etc., and these photolithography patterns are formed using, for example, deposition, optical photolithography, etching, and stripping steps.

[0081] Furthermore, various interposer regions (or interposer dies) are fabricated on a given interposer wafer, as discussed above. Each interposer die contains various components, such as wiring for signal I / O, ground planes, solder bump bonding pads, and packaged I / O routes and interconnect transmission lines and bonding pads. These interposer regions contain lithographic demarcation patterns of superconducting material formed on the interposer wafer, which are formed using steps such as deposition, photolithography, etching, and lift-off. The metallizations on the interposer and quantum wafer can be formed using various types of superconducting materials suitable for a given application, including but not limited to elemental metals such as niobium (Nb), aluminum (Al), and tantalum (Ta) and compounds such as titanium nitride (TiN), niobium nitride (NbN), and titanium niobium nitride (NbTiN).

[0082] A first semiconductor wafer is diced to create individual quantum wafers (or individual qubit dies) (block 1003), and a second semiconductor wafer is diced to create individual interposers (block 1004). One or more quantum wafers are then flip-chip bonded to each of the plurality of interposers to create a quantum module (block 1005), as described above. In some embodiments, flip-chip bonding of a given quantum wafer to a given interposer is performed by depositing indium solder bumps onto and patterning the given interposer, and then flip-chip bonding the given quantum wafer to the given interposer using, for example, a thermal compression bonding process to create a current connection between the quantum wafer and the interposer.

[0083] Next, electrical tests are performed on individual quantum modules to determine and select modules that function as expected and have the desired performance (block 1006). Electrical tests may include tests performed at room temperature. Alternatively, electrical tests may be performed at low temperatures in a cryostat (e.g., a dilution refrigeration system) to test the functionality of superconducting qubits and other superconducting quantum components on the quantum chip. The selected individual quantum modules are then used to form a modular package structure (block 1007), wherein a given modular package structure is constructed by assembling two or more individual quantum modules together, as discussed above, wherein self-alignment of the quantum modules is achieved by utilizing the alignment features of corresponding intermediate layers.

[0084] Figure 11 schematically illustrates a quantum computing system according to an exemplary embodiment of the present disclosure, the quantum computing system including a quantum processor comprising a modular package structure using multiple quantum modules. Specifically, Figure 11 schematically illustrates a quantum computing system 1100, which includes a quantum computing platform 1110, a control system 1120, and a quantum processor 1130. In some embodiments, the control system 1120 includes a multi-channel arbitrary waveform generator (AWG) 1122 and a qubit readout control system 1124. In an exemplary embodiment, the quantum processor 1130 includes at least one modular package structure 1132, which can be implemented using any of the exemplary modular package structures discussed above, as may be required for a given application or quantum system configuration.

[0085] In some embodiments, the control system 1120 and quantum processor 1130 are housed in a dilution cryogenic system 1140, which generates low temperatures sufficient to operate the components of the control system 1120 for quantum computing applications. For example, the quantum processor 1130 may need to be cooled to near absolute zero, such as 10 to 15 milliklvin (mK), to allow superconducting qubits to exhibit quantum behavior. In some embodiments, the dilution cryogenic system 1140 includes a multi-stage dilution cryostat, wherein the components of the control system 1120 can be maintained at different low temperatures as needed. For example, while the quantum processor 1130 may need to be cooled to, for example, 10 to 15 mK, the circuitry of the control system 1120 may operate at temperatures above 10 to 15 mK depending on the configuration of the quantum computing system. In other embodiments, some or all of the components of the control system 1120 may comprise electronic components that are housed and operate at room temperature.

[0086] In some embodiments, the multi-channel AWG 1122 and other suitable microwave pulse signal generators are configured to generate microwave control pulses, which are applied to qubit drive lines and coupler drive lines to control the operation of superconducting qubits and associated qubit coupler circuitry when performing various gate operations to execute a given quantum information processing algorithm. In some embodiments, the multi-channel AWG 1122 includes a plurality of AWG channels that control individual superconducting qubits on a quantum wafer within the modular package structure 1132 of the quantum processor 1130. In some embodiments, each AWG channel includes a baseband signal generator, a digital-to-analog converter (DAC) stage, a filter stage, a modulation stage, an impedance matching network, and a phase-locked loop system to generate local oscillator (LO) signals (e.g., quadrature LO signals LO_I and LO_Q) for the respective modulation stages of the respective AWG channels.

[0087] In some embodiments, the multi-channel AWG 1122 includes an orthogonal AWG system configured to process orthogonal signals, wherein the orthogonal signals include in-phase (I) signal components and quadrature-phase (Q) signal components. In each AWG channel, a baseband signal generator is configured to receive baseband data as input (e.g., from a quantum computing platform) and generate digital orthogonal signals I and Q representing the input baseband data. In this process, the baseband data input to the baseband signal generator for a given AWG channel is separated into two orthogonal digital components comprising an in-phase (I) baseband component and a quadrature-phase (Q) baseband component. The baseband signal generator for a given AWG channel generates the necessary digital orthogonal baseband IQ signals required to generate an analog waveform (e.g., a sinusoidal voltage waveform) with a target center frequency, which is configured to operate or otherwise control one or more qubits coupled to the output of the given AWG channel.

[0088] The DAC stage for a given AWG channel is configured to convert a digital baseband signal (e.g., a digital IQ signal output from a baseband signal generator) into an analog baseband signal (e.g., analog baseband signals I(t) and Q(t)). The filter stage for a given AWG channel is configured to filter the IQ analog signal components output from the DAC stage to generate a filtered analog IQ signal. The modulation stage for a given AWG channel is configured to perform analog IQ signal modulation (e.g., single-sideband (SSB) modulation) by mixing the filtered analog signals I(t) and Q(t) output from the filter stage with quadrature LO signals (e.g., in-phase LO signals (LO_I) and quadrature-phase LO signals (LO_Q)) to generate and output an analog RF signal (e.g., a SSB-modulated RF output signal).

[0089] In some embodiments, the qubit readout control system 1124 includes: a microwave pulse signal generator configured to apply microwave pulse modulation to a given readout resonator line of a given superconducting qubit to perform a readout operation to read the state of the given superconducting qubit; and a circuit system configured to process the readout signal generated by the readout resonator line to determine the state of the given superconducting qubit using techniques known to those skilled in the art. For example, in some embodiments, the qubit readout line for a given qubit includes a coplanar waveguide resonator configured to have a resonant frequency detuned from the transition frequency of the given qubit to achieve a dispersive readout operation for reading the quantum state of the given qubit coupled to the given readout resonator. The dispersive readout operation involves applying an RF readout control signal (RF_RO) to the given readout resonator and detecting / processing the readout signal reflected from the given readout resonator. The RF readout control signal applied to a given readout resonator has a single-frequency tone that is the same as or similar to the resonant frequency of the readout resonator, a pulse envelope with a given pulse shape (e.g., a Gaussian pulse envelope), and a given pulse duration. In the dispersion mechanism of qubit resonator coupling, the RF readout control signal interacts with the given qubit / resonator system, and the resulting output readout signal reflected from the given readout resonator contains qubit state-dependent information (e.g., phase and / or amplitude).

[0090] The quantum computing platform 1110 includes a software and hardware platform. This platform includes various software layers configured to perform various functions, including but not limited to generating and implementing various quantum applications using a suitable quantum programming language, configuring and implementing various quantum gate operations, compiling quantum programs into a quantum comprehension language, and implementing and utilizing a suitable quantum instruction set architecture (ISA). Additionally, the quantum computing platform 1110 includes a hardware architecture such as a processor and memory, configured to control the execution of quantum applications and interfacing with the control system 1120 to (i) generate digital control signals, which are converted by the control system 1120 into analog microwave control signals to control the operation of the quantum processor 1130 when executing a given quantum application, and (ii) acquire and process digital signals received from the control system 1120, which represent the processing results generated by the quantum processor 1130 when executing various gate operations of a given quantum application.

[0091] In some exemplary embodiments, the quantum computing platform 1110 of the quantum computing system 1100 may be implemented using any suitable computing system architecture configured to implement methods supporting quantum computing operations by executing computer-readable program instructions embodied on a computer program product including one or more computer-readable storage media having such computer-readable program instructions for causing a processor to perform the control methods discussed herein.

[0092] Various embodiments of the present disclosure have been described for illustrative purposes, but such descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles, practical applications, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0093] 100: Modular packaging structure 102:Substrate 102-1: First dividing line 102-2: Second dividing line 110: First Module 111: First Intermediary Layer 111a: First Intermediate Layer Area 111-1: First Edge 111-2: Second Edge 112: Quantum Chip 112-1: First extension 112-2: Second Extension 120: Second Module 121: Second Intermediary Layer 121a: Second Intermediate Layer Area 121-1: First Edge 122: Quantum Chip 130: Third Module 131: Third Intermediary Layer 131a: Third Intermediate Layer Area 131-1: First Edge 132: Quantum Chip 200: Initial Stage 201: Segmentation Process 203: Program 300: Modular packaging structure 310: First Module 311: First Intermediary Layer 311-1: First Edge 311-2: Second Edge 312: Quantum Chip 312-1: First Extension 312-2: Second Extension 313: Connector 314: Metallization / Solder Bump Connection 315: Metallic compounds 320: Second Module 321: Second Intermediary Layer 321-1: First Edge 322: Quantum Chip 323: Connector 324: Solder bump connection 325: Planar signal transmission line 327: Metallic compounds 330: Third Module 331: Third Intermediary Layer 331-1: First Edge 332: Quantum Chip 333: Connector 334: Solder bump connection 335: Planar signal transmission line 337: Metallic compounds 400: Modular packaging structure 402:Substrate 402-1: Divider 410: First Quantum Module 411: First Intermediary Layer 411-1: First alignment feature 411a: First Intermediate Layer Area 412: The First Quantum Chip 413: Second Quantum Chip 420: Second Quantum Module 421: Second Intermediary Layer 421-1: Second Alignment Feature 421a: Second Intermediate Layer Area 422: Quantum Chip 500: Modular packaging structure 502:Substrate 502-1: Divider 502-2: Divider 510: First Module 511: First Intermediary Layer 511-1: First Alignment Feature 511a: Intermediate Layer Area 512: The First Quantum Chip 513: The Second Quantum Chip 513-1: Extension 520: Second Module 521: Second Intermediary Layer 521-1: Second Alignment Feature 521a: Intermediate Layer Area 522: The First Quantum Chip 523: The Second Quantum Chip 531a: Intermediate Layer Area 541a: Intermediate Layer Area 600: Semiconductor substrate 611: Intermediary Layer 611a: Intermediate Layer Area 621: Intermediary Layer 621a: Intermediate Layer Area 631: Intermediary Layer 631a: Intermediate Layer Area 700: Semiconductor substrate 711: Triangular Intermediate Layer 711a: Intermediate Layer Area 721: Triangular Intermediate Layer 721a: Intermediate Layer Area 731: Triangular Intermediate Layer 731a: Intermediate Layer Area 741: Triangular Intermediate Layer 741a: Intermediate Layer Area 751: Triangular Intermediate Layer 751a: Intermediate Layer Area 761: Triangular Intermediate Layer 761a: Intermediate Layer Area 800: Semiconductor substrate 811: Octagonal Intermediate Layer 811a: Intermediate Layer Area 821: Octagonal Intermediate Layer 821a: Intermediate Layer Area 831: Octagonal Intermediate Layer 831a: Intermediate Layer Area 841: Octagonal Intermediate Layer 841a: Intermediate Layer Area 851: Square Intermediate Layer 851a: Intermediate Layer Area 900: Semiconductor substrate 911: Intermediary Layer 911a: Intermediate Layer Area 921: Intermediary Layer 921a: Intermediate Layer Area 931: Intermediary Layer 931a: Intermediate Layer Area 941: Intermediary Layer 941a: Intermediate Layer Area 951: Intermediary Layer 951a: Intermediate Layer Area 1000: Method 1001: Block 1002: Block 1003: Block 1004: Block 1005: Block 1006: Block 1007: Block 1100: Quantum Computing System 1110: Quantum Computing Platform 1120: Control System 1122: Multi-channel Arbitrary Waveform Generator (AWG) 1124: Quantum Bit Readout Control System 1130: Quantum Processor 1132: Modular packaging structure 1140: Dilution Refrigeration System E1: Edge E2: Edge X: Direction Y: direction Z: Direction

Claims

1. A packaging structure comprising: a first interposer layer including a first alignment feature; a second interposer layer including a second alignment feature; and a quantum wafer bonded to the first interposer layer, wherein an extension of the first quantum wafer extends beyond a first edge of the first interposer layer; wherein the first interposer layer and the second interposer layer are arranged such that the first alignment feature and the second alignment feature engage to cause alignment and coupling of one or more components on the extension of the first quantum wafer with one or more components on the second interposer layer; wherein, The first intermediate layer and the second intermediate layer are disposed in a plane; and wherein the engagement of the first alignment feature and the second alignment feature causes the alignment in the first and second orthogonal directions of the plane.

2. As in the encapsulation structure of request item 1, wherein: The first alignment feature includes the first edge of the first interposer layer; the second alignment feature includes a second edge of the second interposer layer; and the engagement of the first alignment feature and the second alignment feature includes the first edge being adjacent to the second edge to cause the alignment and coupling of the one or more components on the extension of the quantum wafer with the one or more components on the second interposer layer.

3. The packaging structure of claim 1, wherein the first alignment feature is fitted within the second alignment feature to cause alignment and coupling of the one or more components on the extension of the quantum wafer with the one or more components on the second interposer layer.

4. As in the encapsulation structure of request item 1, wherein: The first alignment feature includes a trench feature; the second alignment feature includes a tongue feature, and the second alignment feature is fitted within the first alignment feature to cause the alignment and coupling of the one or more components on the extension of the quantum wafer with the one or more components on the second interposer layer.

5. The encapsulation structure as described in claim 4, wherein the trench feature and the tongue feature include a corresponding V-shaped feature.

6. As in the encapsulation structure of request item 1, wherein: The first alignment feature includes a first pattern of one alignment feature; the second alignment feature includes a second pattern of one alignment feature; and the first pattern of the alignment feature and the second pattern of the alignment feature interlock with each other to cause the alignment and coupling of the one or more components on the extension of the quantum wafer with the one or more components on the second interposer layer.

7. A packaging structure comprising: a first interposer layer including a first edge; a second interposer layer including a second edge; and a first quantum wafer bonded to the first interposer layer, wherein an extension of the first quantum wafer extends beyond the first edge of the first interposer layer; wherein the first interposer layer and the second interposer layer are disposed in a plane, wherein the first edge and the second edge are adjacent to cause alignment and coupling of one or more components on the extension of the first quantum wafer with one or more components on the second interposer layer, wherein the first edge and the second edge are adjacent to cause the alignment in a first and a second orthogonal direction in the plane.

8. As in the encapsulation structure of request item 7, wherein: The first intermediate layer includes a first shape at least partially defined by the first edge; the second intermediate layer includes a second shape at least partially defined by the second edge; and the first shape and the second shape are different shapes.

9. As in the encapsulation structure of request item 7, wherein: The first intermediate layer includes a first shape at least partially defined by the first edge; the second intermediate layer includes a second shape at least partially defined by the second edge; and the first shape and the second shape are the same shape.

10. As in the encapsulation structure of request item 7, wherein: The second interposer layer includes a second quantum chip; the one or more components on the second interposer layer include transmission lines coupled to the second quantum chip; and the one or more components on the extension portion of the first quantum chip include one or more qubits.

11. The encapsulation structure of claim 7 further includes a third intermediary layer, the third intermediary layer including a third edge, wherein: The first interposer includes a second edge; the first quantum wafer is bonded to the first interposer, wherein a second extension of the first quantum wafer extends beyond the second edge of the first interposer; the third interposer is disposed on the plane having the first interposer and the second interposer; and the second edge of the first interposer is adjacent to the third edge of the third interposer to cause alignment and coupling of one or more components on the second extension of the first quantum wafer with one or more components on the third interposer.

12. As in the encapsulation structure of request item 11, wherein: The first interposer layer includes a first shape at least partially defined by the first edge and the second edge of the first interposer layer; the second interposer layer includes a second shape at least partially defined by the second edge of the second interposer layer; the third interposer layer includes a third shape at least partially defined by the third edge of the third interposer layer; and the first shape, the second shape and the third shape are the same shape.

13. As in the encapsulation structure of request item 11, wherein: The first interposer layer includes a first shape at least partially defined by the first edge and the second edge of the first interposer layer; the second interposer layer includes a second shape at least partially defined by the second edge of the second interposer layer; the third interposer layer includes a third shape at least partially defined by the third edge of the third interposer layer; the second shape and the third shape are the same shape; and the first shape is different from the second shape and the third shape.

14. As in the encapsulation structure of request item 11, wherein: The third interposer layer includes a third quantum chip; the one or more components on the third interposer layer include transmission lines coupled to the third quantum chip; and the one or more components on the second extension of the first quantum chip include one or more qubits.

15. A packaging structure comprising: a first module including: a first interposer including a first edge; and a first quantum chip bonded to the first interposer, wherein an extension of the first quantum chip extends beyond the first edge of the first interposer; and a second module including: a second interposer including a second edge; a second quantum chip bonded to the second interposer; and a transmission line disposed on the second interposer and coupled to the second quantum chip; wherein the first interposer and the second interposer are disposed in a plane, wherein the first edge and the second edge are adjacent to cause alignment and coupling of one or more components on the extension of the first quantum chip to one or more of the transmission lines on the second interposer coupled to the second quantum chip, wherein the first edge and the second edge are adjacent to cause alignment in a first and a second orthogonal direction in the plane.

16. As in the encapsulation structure of request item 15, wherein: The first intermediate layer includes a first shape at least partially defined by the first edge; the second intermediate layer includes a second shape at least partially defined by the second edge; and the first shape and the second shape are one of different shapes and the same shape.

17. The packaging structure of claim 15, wherein the first module further includes a third quantum chip bonded to one of the first interposers and transmission lines disposed on the first interposer, the transmission lines coupling the first quantum chip and the third quantum chip.

18. A method for constructing a package structure, comprising: forming an interposer on a substrate; and dicing the substrate to separate the interposer into at least a first interposer including a first edge and a second interposer including a second edge; wherein the first edge and the second edge are configured to cause alignment of a structure on the first interposer with a structure on the second interposer when the first edge is adjacent to the second edge, wherein the first interposer and the second interposer are disposed in a plane, and wherein the alignment is caused in a first and a second orthogonal direction in the plane when the first edge is adjacent to the second edge.

19. As in request item 18, wherein: The first intermediate layer includes a first shape at least partially defined by the first edge; the second intermediate layer includes a second shape at least partially defined by the second edge; and the first shape and the second shape are different shapes.

20. As in request item 18, wherein: The first intermediate layer includes a first shape at least partially defined by the first edge; the second intermediate layer includes a second shape at least partially defined by the second edge; and the first shape and the second shape are the same shape.

21. A method for constructing a package structure, comprising: constructing a first module, the first module comprising: a first interposer having a first edge; and a first quantum chip bonded to the first interposer, wherein an extension of the first quantum chip extends beyond the first edge of the first interposer; constructing a second module, the second module comprising: a second interposer having a second edge; a second quantum chip bonded to the second interposer; and transmission lines disposed on the second interposer and coupled to the second quantum chip; and assembling the first module and the second module, wherein the first interposer and the second interposer are disposed in a plane, wherein the first edge and the second edge are adjacent to cause alignment and coupling of one or more components on the extension of the first quantum chip to one or more of the transmission lines on the second interposer coupled to the second quantum chip, wherein the first edge and the second edge are adjacent to cause alignment in a first and a second orthogonal direction in the plane.

22. As in request item 21, wherein: The first intermediate layer includes a first shape at least partially defined by the first edge; the second intermediate layer includes a second shape at least partially defined by the second edge; and the first shape and the second shape are one of different shapes and the same shape.

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