Semiconductor assembly with heat sink structure and method for manufacturing the same

Abstract

A semiconductor assembly is provided, comprising: a first semiconductor wafer, a memory stack, and a second semiconductor wafer. The memory stack is bonded to the first semiconductor wafer, and the second semiconductor wafer is bonded to the memory stack. The second semiconductor wafer includes a heat sink structure configured to dissipate heat generated by the first semiconductor wafer and the memory stack via a first heat conduction path and a second heat conduction path within the semiconductor assembly.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 746,386 (i.e., priority date "June 18, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to an electronic circuit, and more specifically, to a semiconductor assembly with a heat sink structure and a method for manufacturing the same. Prior Technology

[0003] Thermal management in 3D stacked chip packaging presents challenges, particularly in dissipating heat from densely stacked chips in the central region. This is especially critical for 3D stacked integrated circuit (IC) packages, such as those containing high bandwidth memory (HBM). Current package-level thermal management techniques, including the use of thermal interface materials and cavities between the chips, are insufficient to effectively dissipate the heat generated by the stacked chips in the central region. Additional measures, such as increasing the number of microbumps, are also ineffective in addressing this issue.

[0004] The discussion in the preceding technical paragraphs is provided for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor assembly including a first semiconductor wafer, a memory stack, and a second semiconductor wafer. The memory stack is bonded to the first semiconductor wafer, and the second semiconductor wafer is bonded to the memory stack. The second semiconductor wafer includes a heat sink structure configured to dissipate heat generated by the first semiconductor wafer and the memory stack via a first heat conduction path and a second heat conduction path within the semiconductor assembly.

[0006] Another aspect of this disclosure provides a semiconductor assembly including a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes a silicon substrate and a plurality of heat dissipation members formed on the silicon substrate to dissipate heat generated by the first semiconductor structure.

[0007] Another aspect of this disclosure provides a method comprising the steps of: providing a first semiconductor wafer, a memory stack, and a second semiconductor wafer; bonding the memory stack to the first semiconductor wafer to form a first semiconductor structure; and bonding the second semiconductor wafer to the first semiconductor structure to form a semiconductor assembly, wherein a first thermal path and a second thermal path are formed within the semiconductor assembly through corresponding plurality of edge regions of the first semiconductor wafer, the memory stack, and the second semiconductor wafer.

[0008] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims.

[0009] . Simple Explanation of the Diagram

[0010] When referring to the drawings in conjunction with the embodiments and the scope of the claim, a more comprehensive understanding of the disclosure of this application can be obtained, wherein in all the drawings, the same element symbols represent similar elements, and: Figures 1A and 1B are top views illustrating different wafers of some embodiments of this disclosure. Figures 2A to 2E are cross-sectional views illustrating various stages in the semiconductor die manufacturing process of some embodiments of this disclosure. Figure 2F is a top view illustrating the semiconductor structure 20D taken along the section line 2F-2F in Figure 2D. Figures 3A to 3E are cross-sectional views illustrating semiconductor structures at different stages of forming a 3D stacked integrated circuit package, according to some embodiments of this disclosure. Figures 4A to 4D are cross-sectional views illustrating various stages in the manufacturing process of a heat sink structure according to some embodiments of this disclosure. Figures 4E to 4G are bottom views, illustrating semiconductor structure 40D in Figure 4D. Figures 5A to 5F are cross-sectional views illustrating various stages in the formation of a semiconductor structure according to some embodiments of this disclosure. Figure 5G is a top view illustrating the semiconductor structure 50E taken along the section line 5G-5G in Figure 5E. Figure 6 is a cross-sectional view illustrating a semiconductor package according to some embodiments of this disclosure. Figure 7 is a flowchart illustrating a method for manufacturing a semiconductor assembly according to an embodiment of this disclosure. Implementation

[0011] The embodiments or exemplary cases of this disclosure shown in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally occur to those skilled in the art to which this disclosure pertains. Component symbols may be repeated throughout the embodiments, but this does not necessarily mean that one(s) feature of one embodiment is applicable to another embodiment, even if they share the same component symbols.

[0012] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section without departing from the teachings of this disclosure.

[0013] Throughout this specification, the terms "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is incorporated into at least one example of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing in different places throughout the specification do not necessarily refer to the same example. Furthermore, in one or more examples, a particular feature, structure, or characteristic can be combined in any suitable manner.

[0014] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context otherwise requires. It should be further understood that the terms "comprising" and "including," when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or elements, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, elements, or groups thereof.

[0015] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower," "below," "above," "upper," or other similar terms may be used herein to describe the relative relationship between one component or feature depicted in the diagram and another component or feature. In addition to the orientations depicted in the diagram, spatially related terms are intended to cover different orientations of an element in use or operation. For example, if an element in the diagram is flipped, a component described as "below," "below," or "below" other components or features will be oriented "above" other components or features. Thus, the illustrative terms "below" or "below" can encompass both "above" and "below." This element may be oriented in other ways (e.g., rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as being located "between" two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0016] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to that other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being "directly connected to" or "directly coupled to" another component, there are no intermediate components. Other terms used to describe the relative relationships between components should be interpreted in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.).

[0017] It should be understood that when a component or layer is said to be "formed on" another component or layer, it can be formed directly or indirectly on the other component or layer. That is, for example, there may be intermediate components or layers. Conversely, when a component or layer is said to be "directly formed on" another component, there are no intermediate components or layers. Other terms used to describe the relative relationships between components or layers should be interpreted in a similar manner (e.g., "located between" vs. "directly located between," "adjacent" vs. "directly adjacent," etc.).

[0018] Figures 1A and 1B are top views illustrating different wafers of some embodiments of this disclosure.

[0019] In some embodiments, as shown in FIG1, a semiconductor wafer 1 includes a plurality of semiconductor dies 110, each semiconductor die 110 being surrounded by a dicing region 121 such that every two adjacent semiconductor dies 110 are separated by the dicing region 121. The dicing region 121 is a non-functional area on the semiconductor wafer 1. Furthermore, one or more dicing paths may be defined on the dicing region 121. In some embodiments, the dicing paths may be from top to bottom and from left to right, or from bottom to top and from right to left, depending on the dicing equipment.

[0020] Specifically, semiconductor wafers or dies (e.g., memory wafers) are typically manufactured on a single semiconductor wafer along with hundreds (in some cases thousands) replicas of the same dies. The dicing process required to separate the individual dies on the semiconductor wafer is called "dicing" or "wafer dicing," and can be performed using a die saw (e.g., a diamond saw). Dividing is performed along a non-functional region of the semiconductor material, called a dicing line (i.e., dicing line region 121), which separates the semiconductor dies 110 on the semiconductor wafer 1. Each semiconductor die 110 can be manufactured as a semiconductor die 200D (e.g., a memory die) as shown in FIG. 2E, which will be described in more detail later.

[0021] In some embodiments, the semiconductor wafer 2 includes a plurality of semiconductor dies 130, each semiconductor die 130 being surrounded by a dicing region 141 such that every two adjacent semiconductor dies 130 are separated by the dicing region 141. The dicing region 141 is a non-functional region on the semiconductor wafer 2. Furthermore, one or more dicing paths may be defined on the dicing region 141. In some embodiments, the dicing paths may be from top to bottom and from left to right, or from bottom to top and from right to left, depending on the dicing equipment.

[0022] Similarly, the semiconductor wafer 2 shown in FIG1B can be diced along a non-functional region of the semiconductor material, called a dicing line (i.e., dicing line region 141), into a plurality of semiconductor dies 131, thus separating the semiconductor dies 130 on the semiconductor wafer 2. Each semiconductor die 130 can be fabricated into a semiconductor die 300 as shown in FIG3A (e.g., a memory controller integrated circuit), which will be described in more detail later.

[0023] Figures 2A to 2E are cross-sectional views illustrating various stages in the semiconductor die manufacturing process of some embodiments of this disclosure. Please refer to Figure 1 and Figures 2A to 2E.

[0024] In some embodiments, as shown in FIG2A, a semiconductor structure 20A (e.g., region 120 shown in FIG1A) includes two semiconductor dies 200A fabricated on a substrate 210 (e.g., semiconductor wafer 1 in FIG1A). In some embodiments, the substrate 210 may include a single-crystal substrate, a semiconductor-on-insulator (SOI) substrate, a silicon-doped substrate, an epitaxial film-on-semiconductor (EPI) substrate, or other similar materials. Furthermore, although various embodiments are described primarily with reference to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and / or carbon), this disclosure is not limited thereto. Rather, various embodiments can be implemented using any type of semiconductor material.

[0025] In some embodiments, a plurality of through-silicon vias (TSVs) 211 are formed within a substrate 210, as shown in FIG2A. A portion of each TSV 211 protrudes from the top surface 210s1 (e.g., the front side) of the substrate 210 and is located within a dielectric layer 220. The TSVs 211 are connected to contact pads 215 through a metal layer 212, a vertical interconnect 213 (e.g., a metal interconnect, such as copper), and a metal layer 214. The metal layers 212 and 214, together with the vertical interconnect 213, may be collectively referred to as the connection structure C1. The contact pads 215 may be aligned with the top surface 220s1 of the dielectric layer 220. The dielectric layer 220 may be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low dielectric constant dielectric materials (e.g., carbon-doped oxides), very low dielectric constant dielectric materials (e.g., porous carbon-doped silicon dioxide), combinations thereof, or similar materials. The dielectric layer 220 can be formed by processes such as chemical vapor deposition (CVD) or thermal oxidation, although any suitable process can be used, and the dielectric layer 220 can have a thickness between about 0.5 μm and about 5 μm, for example, it can be about 9.25 kÅ.

[0026] In some embodiments, metal layers 212 and 214 can be implemented using corresponding metal layers, such as silver (Ag), copper (Cu), gold (Au), aluminum nitride (AlN), silicon carbide (SiC), aluminum (Al), tungsten (W), zinc (Zn), or any combination thereof. Edge regions 221 may surround one or more semiconductor components disposed within an active region 222 (e.g., a circuit region) of each semiconductor die 200A. For simplicity, two silicon vias 211 and their corresponding connection structures C1 and contact pads 215 are shown in each active region 222. It should be noted that each active region 222 may include a plurality of transistors, capacitors, resistors, diodes, or other similar components formed in a front-end-of-line (FEOL) process.

[0027] In some embodiments, each semiconductor die 200A includes an edge region 221, and the silicon vias 211 in the edge region 221 and their corresponding connection structures C1 can be collectively considered as corresponding sealing rings (e.g., a first sealing ring R1 and a second sealing ring R2, as shown in FIG. 2F). The sealing rings may surround the active region 222. By surrounding the active region 222 with one or more sealing rings, unintended stress propagation into the semiconductor component during chemical mechanical polishing (CMP) or dicing can be prevented, thus preventing cracking of the layers in which the semiconductor element is embedded and / or delamination between adjacent layers of a stacked integrated circuit package. The sealing rings (e.g., edge region 221) can prevent stress propagation into the semiconductor component within the active region 222. In some embodiments, the sealing rings (e.g., edge region 221) may comprise copper (Cu) or any other suitable material. In some embodiments, the sealing rings may each comprise a multilayer structure. In some embodiments, the sealing rings may each comprise a barrier metal layer (not shown) that encapsulates the backbone of the sealing ring. In some embodiments, the barrier metal layer may include, but is not limited to, tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten silicon (WSi), titanium (Ti), titanium nitride (TiN), and titanium silicon nitride (TiSiN).

[0028] In some embodiments, a dicing region 202 (e.g., dicing region 121 shown in FIG. 1A) is defined between two semiconductor dies 200A. The dicing region 202 is a non-functional region, and one or more dicing paths may be defined on the dicing region 202.

[0029] Referring to FIG2B, in some embodiments, the semiconductor die 200A shown in FIG2A can be flipped, and the top surface 220s1 (e.g., the front side) of the dielectric layer 220 faces downward. Furthermore, a temporary bonding process is performed on the top surface 220s1 of the dielectric layer 220 to obtain a semiconductor structure 20B including the semiconductor die 200B as shown in FIG2B. For example, a temporary bonding layer 230 is formed on the top surface 220s1 of the dielectric layer 220. In some embodiments, the temporary bonding layer 230 includes a silicon-containing dielectric material (e.g., silicon oxide, silicon nitride, etc.) or other suitable dielectric material for bonding. An enlarged view of region 22 is shown here. For example, the side and bottom surfaces of the silicon via 211 in region 22 are surrounded by a barrier layer 216 and a pad layer 217, respectively, of the inner and outer layers. Additionally, the silicon via 211 may have a width T1 along the lateral direction. In some embodiments, the barrier layer 216 may also be considered a diffusion barrier layer, comprising a metallic material or conductive ceramic, such as cobalt (Co), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), indium trioxide (In₂O₃), tungsten nitride (W₂N, WN, or WN₂), and titanium nitride (TiN), but this disclosure is not limited thereto. The pad layer 217 may be an oxide pad comprising, for example, silicon dioxide (SiO₂), but this disclosure is not limited thereto.

[0030] Referring to FIG2C, in some embodiments, a back-side silicon via exposure process is performed on the semiconductor die 200B shown in FIG2B. For example, the back-side silicon via exposure process can be regarded as wafer back-side polishing or wafer thinning, which includes a mechanical polishing process or a chemical mechanical planarization (CMP) process performed on the bottom surface 210s2 (e.g., back side) of the substrate 210, such that silicon vias 211 are exposed from the bottom surface 210s2' of the thinned substrate 210' to obtain the semiconductor die 200C shown in FIG2C. In some other embodiments, the back-side silicon via exposure process may include a silicon trench etching (e.g., wet etching or dry etching) process performed on the bottom surface 210s2 (e.g., back side) of the substrate 210, such that the silicon via 211 is exposed from the bottom surface 210s2' of the thinned substrate 210' to obtain a semiconductor structure 20C including semiconductor grains 200C as shown in FIG2C.

[0031] Referring to FIG2D, in some embodiments, a pad formation process is performed on the semiconductor die 200C shown in FIG2C to obtain the semiconductor structure 20D including the semiconductor die 200D shown in FIG2D. For example, a first passivation layer 240A is first formed on the bottom surface 210s2' of the thinned substrate 210', and then a conductive pad 241 is formed on the first passivation layer 240A at the location corresponding to the silicon via 211. Subsequently, a second passivation layer 240B is formed on the first passivation layer 240A, and the top surface 240Bs1 of the second passivation layer 240B is substantially coplanar with the outer surface of the conductive pad 241. Furthermore, a top view of the semiconductor die 200D obtained along line 2F-2F in FIG2D is shown in FIG2F. For example, a first sealing ring R1 (e.g., an internal sealing ring) can be formed within the internal silicon via 211 (i.e., closer to the active region 222) and each of its corresponding edge regions 221, while a second sealing ring R2 (e.g., an external sealing ring) can be formed within the external silicon via 211 (i.e., closer to the edge of the semiconductor die 200D) and each of its corresponding edge regions 221. Since the active region 222 is surrounded by the first sealing ring R1 and the second sealing ring R2, unintended stress propagation into the semiconductor component during chemical mechanical polishing or dicing can be prevented, thus preventing cracking of the layers in which the semiconductor element is embedded and / or delamination between adjacent layers of a stacked integrated circuit package. The first sealing ring R1 and the second sealing ring R2 also prevent stress propagation into the semiconductor component within the active region 222.

[0032] Referring to Figure 2E, a debonding process and a dicing process (e.g., wafer dicing) are performed on the semiconductor structure shown in Figure 2D. For example, a debonding process is first performed to separate the temporary bonding layer 230 from the dielectric layer 220, and then a dicing process is performed to cut the semiconductor structure 20D to obtain a semiconductor die 200D, as shown in Figure 2E.

[0033] Figures 3A to 3E are cross-sectional views illustrating semiconductor structures at different stages of forming a 3D stacked integrated circuit package, according to some embodiments of this disclosure.

[0034] In some embodiments, as shown in FIG3A, semiconductor structure 30A (e.g., region 140 in FIG1B) includes two semiconductor dies 300 fabricated on a substrate 310 (e.g., semiconductor wafer 2 in FIG1B). In some embodiments, substrate 310 may include a single-crystal substrate, a semiconductor-on-insulator (SOI) substrate, a silicon-doped substrate, an epitaxial film-on-semiconductor (EPI) substrate, or other similar materials. Furthermore, although various embodiments are described primarily with reference to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and / or carbon), this disclosure is not limited thereto. Rather, various embodiments can be implemented using any type of semiconductor material.

[0035] For simplicity, semiconductor dies 300 (e.g., semiconductor die 130 shown in FIG. 1B) have been fabricated on substrate 310 (e.g., semiconductor wafer 2 shown in FIG. 1B), however, semiconductor dies 300 have not yet been separated, as shown in FIG. 3A. Each semiconductor die 130 may be a memory controller integrated circuit (IC) configured to control memory access of one or more memory chips (e.g., semiconductor dies 200D) stacked thereon. In some embodiments, semiconductor dies 300 may be fabricated in a manner similar to semiconductor die 200D, therefore its details will not be repeated. It should be noted that when semiconductor dies 200D are stacked on a 3D integrated circuit package using flip chip technology, the front side (e.g., top surface 320s1) of semiconductor die 300 faces upward, while the front side (e.g., top surface 220s1) of semiconductor die 200D faces downward.

[0036] In some embodiments, a plurality of silicon vias 311 are formed within a substrate 310, as shown in FIG3A. A portion of each silicon via 311 protrudes from the top surface 310s1 (e.g., the front side) of the substrate 310 and is located within a dielectric layer 320. The silicon vias 311 are connected to conductive pads 315 through metal layers 312, vertical interconnects 313, and metal layers 314. Metal layers 312 and 314, together with the vertical interconnects 313, may be collectively referred to as connection structure C2. Conductive pads 315 may be aligned with the top surface 320s1 of the dielectric layer 320. The dielectric layer 320 may be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low dielectric constant dielectric materials (e.g., carbon-doped oxides), very low dielectric constant dielectric materials (e.g., porous carbon-doped silicon dioxide), combinations thereof, or similar materials. The dielectric layer 320 can be formed by a process such as chemical vapor deposition (CVD), although any suitable process can be used, and the dielectric layer 320 can have a thickness between about 0.5 μm and about 5 μm, for example, it can be about 9.25 kÅ.

[0037] In some embodiments, metal layers 312 and 314 can be implemented using corresponding metal layers, such as silver (Ag), copper (Cu), gold (Au), aluminum nitride (AlN), silicon carbide (SiC), aluminum (Al), tungsten (W), zinc (Zn), or any combination thereof. Edge regions 321 may surround one or more semiconductor components disposed within the active region 322 (e.g., a circuit region) of each semiconductor die 300. For simplicity, two silicon vias 311 and their corresponding connection structures C2 and conductive pads 315 are illustrated in each active region 322. Furthermore, the metal layers within the active region 322 (e.g., the same metal layers as metal layers 312 and 314) and the vertical interconnects (e.g., the same metal layers as vertical interconnects 313) may be collectively referred to as redistribution layers. It should be noted that the edge regions 321 are designed for heat dissipation and are not electrically connected to the active region 322 within each semiconductor die 300.

[0038] Similar to semiconductor die 200D, the edge region 321 within each semiconductor die 300 is designed as a sealing ring to prevent unintended stress propagation into the semiconductor component during chemical mechanical polishing or dicing, thereby preventing cracking of the layers in which the semiconductor element is embedded and / or delamination between adjacent layers of a stacked integrated circuit package. The sealing ring (e.g., edge region 321) can prevent stress propagation into the semiconductor component within the active region 322. In some embodiments, the sealing ring (e.g., edge region 221) may comprise copper (Cu) or any other suitable material. In some embodiments, the sealing ring may each comprise a multilayer structure. In some embodiments, the sealing ring may each comprise a barrier metal layer (not shown) that encapsulates the backbone of the sealing ring. In some embodiments, the barrier metal layer may include, but is not limited to, tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), tungsten silicon (WSi), titanium (Ti), titanium nitride (TiN), and titanium silicon nitride (TiSiN).

[0039] In some embodiments, semiconductor die 200D is bonded to semiconductor die 300 via a bonding interface layer (not shown) using a hybrid bonding technique (e.g., chip-on-wafer technology) to obtain semiconductor structure 30B as shown in FIG. 3B. The bonding interface layer may include materials such as silicon carbide (SiCN), silicon dioxide (SiO2), silicon carbide (SiC), or combinations thereof, and may have a thickness of approximately several hundred nanometers.

[0040] Referring to Figure 3B, an enlarged view of region 32 is shown. For example, the side and bottom surfaces of the silicon via 311 within region 32 are surrounded by an inner and outer barrier layer 316 and a pad layer 317, respectively. Additionally, the silicon via 311 may have a width T2 along the lateral direction. In some embodiments, the barrier layer 316 may also be considered a diffusion barrier layer, comprising a metallic material or conductive ceramic, such as cobalt (Co), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), indium trioxide (In₂O₃), tungsten nitride (W₂N, WN, or WN₂), and titanium nitride (TiN), but this disclosure is not limited thereto. The pad layer 317 may be an oxide pad comprising, for example, silicon dioxide (SiO₂), but this disclosure is not limited thereto.

[0041] Referring to Figure 3C, in some embodiments, one or more semiconductor dies 200D are stacked on semiconductor structure 30B to obtain semiconductor structure 30C as shown in Figure 3C. Specifically, a memory stack 31 including a plurality of semiconductor dies 200D and a semiconductor die 200E can be stacked on each semiconductor die 300 (e.g., memory controller integrated circuit), and each memory stack 31 can be considered as a high-bandwidth memory (HBM). In some embodiments, the bottom surface 210s2 (e.g., back side) of the substrate 210 of the topmost semiconductor die 200E in each memory stack 31 of semiconductor structure 30C can be thinned without using wafer polishing or chemical mechanical polishing processes, and the active region 222 of the topmost semiconductor die 200E in each memory stack 31 does not include silicon vias 211.

[0042] Furthermore, each edge region 221 in each semiconductor die 200D within the same memory stack 31 is in contact with the corresponding edge region 221 in the vertically adjacent semiconductor die 200D, making the vertically connected edge region 221 thermally conductive. Moreover, each edge region 321 is also connected to the corresponding vertically connected edge region 221 via corresponding metal layers 312 and 314 and vertical interconnects 313, thus forming a thermal path. It should be noted that each thermal path is not electrically connected to the active region 322 within each semiconductor die 300 or the active region 222 within each semiconductor die 200D.

[0043] Referring to Figure 3D, in some embodiments, a molding material 34 is formed to completely encapsulate the memory stack 31 to obtain a semiconductor structure 30D. In some embodiments, the molding material 34 includes various materials, such as molding compounds, underfillers, epoxy resins, resins, or other similar materials. In some embodiments, the molding material 34 has high thermal conductivity, low moisture absorption, and high flexural strength.

[0044] Referring to Figure 3E, in some embodiments, a back-side via exposure process and a back-side bonding pad formation process are performed on the semiconductor structure 30D in Figure 3D to obtain the semiconductor structure 30E in Figure 3E. In some embodiments, the back-side via exposure process performed on the semiconductor structure 30D is similar to the process shown in Figures 2C to 2D. For example, the back-side via exposure process includes a mechanical polishing process or a chemical mechanical planarization (CMP) process performed on the molding material 34 and substrate 210 of the topmost semiconductor die 200E in each memory stack 31, such that the vias 211 of the edge region 221 are exposed. It should be noted that the bottom surface 210s2' of the thinned substrate 210' and the top surface 34s1 of the thinned molding material 34' are substantially coplanar. Then, a first passivation layer 340A is formed on the bottom surface 210s2' and top surface 34s1 of the thinned substrate 210' of the top semiconductor die 200D. Then, a metal pad 341 (e.g., copper or other suitable metal material) is formed on the first passivation layer 340A at the location of the silicon via 211 in the edge region 221 of the top semiconductor die 200D. Subsequently, a second passivation layer 340B is formed on the first passivation layer 340A, and the top surface 340Bs1 of the second passivation layer 340B is substantially coplanar with the outer surface of the metal pad 341.

[0045] Figures 4A-4D are sectional views illustrating various stages in the manufacturing process of the heat sink structure according to some embodiments of this disclosure.

[0046] Referring to Figure 4A, a semiconductor substrate 410 is provided to obtain a semiconductor structure 40A. In some embodiments, the semiconductor substrate 410 may include a single-crystal substrate, a semiconductor-on-insulator (SOI) substrate, a silicon-doped substrate, an epitaxial film-on-semiconductor (EPI) substrate, or other similar materials. Furthermore, although various embodiments are described primarily with reference to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and / or carbon), this disclosure is not limited thereto. Rather, various embodiments can be implemented using any type of semiconductor material.

[0047] Referring to Figure 4B, a silicon through-hole (STB) formation process is performed on the semiconductor substrate 410 to form a plurality of STBs 411, thereby obtaining a semiconductor structure 40B. For example, a passivation layer 420 is first formed on the top surface 410s1 of the semiconductor substrate 410. The passivation layer 420 can be one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low dielectric constant dielectric materials (e.g., carbon-doped oxides), very low dielectric constant dielectric materials (e.g., porous carbon-doped silicon dioxide), combinations thereof, or similar materials. The passivation layer 420 can be formed by processes such as chemical vapor deposition (CVD) or thermal oxidation, although any suitable process can be used. Furthermore, the silicon via 411 within region 41 is surrounded by a barrier layer 42, and the width T3 of the silicon via 411 is greater than the width T2 of the silicon via 311 shown in FIG. 3B, and greater than the width T1 of the silicon via 211 shown in FIG. 2E. The width T2 of the silicon via 311 may be different from the width T1 of the silicon via 211. In some embodiments, the barrier layer 42 may also be regarded as a diffusion barrier layer, which includes a metallic material or conductive ceramic, such as cobalt (Co), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), indium trioxide (In₂O₃), tungsten nitride (W₂N, WN, or WN₂), and titanium nitride (TiN), but this disclosure is not limited thereto.

[0048] Referring to Figure 4C, a metal layer 430 is formed on the top surface 420s1 of the passivation layer 420 to obtain the semiconductor structure 40C. In some embodiments, the metal layer 430 may continuously span across the top surface 420s1 of the passivation layer 420. Alternatively, the metal layer 430 may comprise a corresponding segment on the top surface 420s1 of the passivation layer 420 for each semiconductor die 400B.

[0049] Referring to Figure 4D, a metal pad formation process is performed. For example, a metal pad 441 (e.g., copper or other suitable metal material) is formed at a predetermined position on the top surface 430s1 of the metal layer 430, and then a passivation layer 440 is formed on the top surface 430s1 of the metal layer 430 to obtain a semiconductor structure 40D.

[0050] Figures 4E to 4G are bottom views illustrating the semiconductor structure 40D in Figure 4D. In some embodiments, the contact area 450 between each silicon via 411 and the metal layer 430 may be circular, as shown in Figure 4E. In some other embodiments, the contact area 450 between each silicon via 411 and the metal layer 430 may be rectangular or square, as shown in Figure 4F. In still other embodiments, the contact area 450 between each silicon via 411 and the metal layer 430 may be hexagonal, as shown in Figure 4G. It should be noted that the shape of the contact area 450 in this disclosure is not limited to the shapes described above, and other shapes may be used depending on actual needs.

[0051] Figures 5A to 5F are cross-sectional views illustrating various stages in the formation of a semiconductor structure according to some embodiments of this disclosure.

[0052] In some embodiments, as shown in FIG5A, a wafer-to-wafer hybrid bonding process is performed to bond the semiconductor structure 40D shown in FIG4 to the semiconductor structure 30E shown in FIG3E via a bonding interface layer (not shown) to obtain the semiconductor structure 50B shown in FIG5B. For example, the width of the semiconductor structure 40D can be substantially equal to the width of the semiconductor structure 30E shown in FIG3E. When the semiconductor structure 40D is vertically flipped, the position of the metal pad 441 can correspond to the metal pad 341 of the topmost semiconductor die 200E in the semiconductor structure 30E shown in FIG3E, so that the semiconductor structure 40D shown in FIG4D and the semiconductor structure 30E shown in FIG3E can be bonded.

[0053] Referring to Figure 5C, a back-side silicon via exposure process is performed to expose the silicon vias 411 of the semiconductor die 400D, thereby obtaining the semiconductor structure 50C shown in Figure 5C. The back-side silicon via exposure process includes a mechanical polishing process or a chemical mechanical planarization (CMP) process performed on the bottom surface 410s2' (e.g., the back side) of the semiconductor substrate 410 of the semiconductor die 400D, so that the silicon vias 411 are exposed from the bottom surface 410s2' of the thinned semiconductor substrate 410', thereby obtaining the semiconductor structure 50C shown in Figure 5C.

[0054] Referring to Figure 5D, a film deposition process is performed on the semiconductor structure 50C shown in Figure 5C to obtain the semiconductor structure 50D shown in Figure 5D. For example, a carbon film 510 is formed on the exposed silicon vias 411 and the thinned semiconductor substrate 410' using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. For example, the carbon film 510 can be used for heat dissipation.

[0055] Referring to Figure 5E, a back-side silicon via exposure process and a back-side bump formation process are performed on the semiconductor structure 50D shown in Figure 5D to obtain the semiconductor structure 50E shown in Figure 5E. For example, a back-side silicon via exposure process is performed on the bottom surface 310s2 of the substrate 310 of the semiconductor structure 50D to expose silicon vias 311. Subsequently, a plurality of bumps 521 are formed on the exposed silicon vias 311, and then a passivation layer 522 is formed on the bottom surface of the thinned substrate 310' to obtain the semiconductor structure 50E shown in Figure 5E. Figure 5G shows a top view of the semiconductor structure 50E as viewed from line 5G-5G. As can be seen from Figure 5G, sealing rings R3 and R4 can be considered as edge regions of each semiconductor die within the 3D memory stack 52 shown in Figure 5F.

[0056] Referring to Figure 5F, a dicing process is performed on the semiconductor structure 50E shown in Figure 5E to obtain the semiconductor assembly 50F shown in Figure 5F. For example, the semiconductor structure 50E is diced along the dicing line region 502, resulting in two semiconductor structures 50E. Specifically, the semiconductor assembly 50F shown in Figure 5F is a 3D integrated circuit package, which includes a memory controller integrated circuit 51 (e.g., semiconductor die 300E), a 3D memory stack 52 (e.g., a stack of semiconductor dies 200D and semiconductor dies 200E), and a heat sink structure 53 (e.g., semiconductor structure 40D). The heat generated by the semiconductor structure 50E can be dissipated by the heat sink structure 53 along the heat conduction path 55 through the memory controller integrated circuit 51, the 3D memory stack 52, and the heat sink structure 53. Specifically, the heat conduction path 55 is formed along the edge regions of the memory controller integrated circuit 51, the 3D memory stack 52, and the heat sink structure 53, constituting a sealing ring for the corresponding semiconductor die (e.g., sealing rings R1 and R2 shown in FIG. 2F). Furthermore, as described above, the edge regions of the semiconductor die are not electrically connected to the active regions within the corresponding semiconductor die, but they are thermally conductive. In this way, the heat generated by the active regions can be transferred to the edge regions of the corresponding semiconductor die and dissipated by the heat sink structure 53 along the heat conduction path 55.

[0057] It should be noted that the heat sink structure 53 includes a plurality of protrusions, each protrusion including a corresponding silicon via 411 covered by a carbon film 510. Furthermore, the semiconductor substrate 410 of the heat sink structure 53 can be used as a heat-conducting plate. Moreover, the width of the silicon via 411 is greater than the widths of silicon vias 211 and 311, allowing the heat generated by the semiconductor structure 50E to be effectively dissipated by the heat sink structure 53 through the silicon vias 411 and the carbon film 510.

[0058] Figure 6 is a cross-sectional view illustrating a semiconductor package according to some embodiments of this disclosure.

[0059] In some embodiments, the semiconductor assembly 50F and integrated circuit 600 shown in FIG. 5F can be disposed on a printed circuit board 610 via respective bumps 521 and bumps 602 to obtain the semiconductor package 60 shown in FIG. 6. For example, the integrated circuit 600 may be a processor, such as a central processing unit (CPU), digital signal processor (DSP), image signal processor (ISP), neural processing unit (NPU), etc. Alternatively, the integrated circuit 600 may be a logic integrated circuit, which includes one or more logic circuits to perform a specified function. Furthermore, the printed circuit board 610 includes a plurality of solder balls 611 disposed thereon, allowing the semiconductor package 60 to be electrically connected to other semiconductor package structures or integrated circuits. In addition, the semiconductor assembly 50F is electrically connected to the integrated circuit 600 through an interposer (not shown) within the printed circuit board 610. Therefore, semiconductor package 60 can be regarded as chip-on-wafer & wafer-on-substrate (CoWoS) package.

[0060] Figure 7 is a flowchart illustrating a method for manufacturing a semiconductor assembly according to some embodiments of this disclosure. Please refer to Figures 5F and 7.

[0061] In step S710, a first semiconductor wafer, a memory stack, and a second semiconductor wafer are provided. For example, the first semiconductor wafer can be seen in the memory controller integrated circuit 51 shown in FIG. 5F, which includes a plurality of semiconductor dies 300 as shown in FIG. 3A. The memory stack can be seen in the memory stack 52 shown in FIG. 5F, which includes semiconductor dies 200D and conductor dies 200E as shown in FIG. 3E. The second semiconductor wafer can be seen in the heat sink structure 53 shown in FIG. 5F, which includes the semiconductor structure 40D as shown in FIG. 4D.

[0062] In step S720, the memory is stacked and bonded to the first semiconductor wafer to form a first semiconductor structure. In some embodiments, a flip-chip hybrid bonding process can be performed to stack and bond the memory to the first semiconductor wafer via a bonding interface layer, as shown in FIG3B.

[0063] In step S730, a second semiconductor wafer is bonded to a first semiconductor structure to form a semiconductor assembly, wherein a first thermal conductive path and a second thermal conductive path are formed within the semiconductor assembly by passing through corresponding edge regions of the first semiconductor wafer, the memory stack, and the second semiconductor wafer. In some embodiments, a flip-chip hybrid bonding process may be performed.

[0064] In one aspect of this disclosure, a semiconductor assembly is provided, comprising a first semiconductor wafer, a memory stack, and a second semiconductor wafer. The memory stack is bonded to the first semiconductor wafer, and the second semiconductor wafer is bonded to the memory stack. The second semiconductor wafer includes a heat sink structure configured to dissipate heat generated by the first semiconductor wafer and the memory stack via a first heat conduction path and a second heat conduction path within the semiconductor assembly.

[0065] In some embodiments, the first semiconductor wafer includes a first semiconductor die, wherein the first semiconductor die is configured as a memory controller integrated circuit.

[0066] In some embodiments, the memory stack comprises a plurality of memory chips stacked vertically.

[0067] In some embodiments, each of the first semiconductor die and the plurality of memory dies includes an active region and a plurality of edge regions, wherein the plurality of edge regions surround the active region and are not electrically connected to the active region.

[0068] In some embodiments, each of the plurality of edge regions located within each of the first semiconductor die and each of the plurality of memory dies includes a first silicon via and a second silicon via, and a first thermal path and a second thermal path are respectively established along the first silicon via and the second silicon via located within each of the plurality of edge regions located within each of the first semiconductor die and each of the plurality of memory dies.

[0069] In some embodiments, the heat sink structure includes a silicon substrate and a plurality of third silicon through-holes, wherein the plurality of third silicon through-holes are formed on the silicon substrate and protrude from a top surface of the silicon substrate.

[0070] In some embodiments, the plurality of third silicon vias and the top surface of the silicon substrate are covered by a carbon film.

[0071] In some embodiments, a first width of each of the plurality of third silicon vias is greater than a second width of the first silicon via and a third width of the second silicon via located in each of the plurality of edge regions within the first semiconductor die and the plurality of memory dies.

[0072] In some embodiments, the first silicon via located in each of the plurality of edge regions is closer to the active region located in each of the first semiconductor die and the plurality of memory dies. The second silicon via located in each of the plurality of edge regions is farther from the active region. The first silicon via and the second silicon via located in each of the plurality of edge regions in each of the first semiconductor die and the plurality of memory dies respectively constitute a first sealing ring and a second sealing ring.

[0073] In some embodiments, each of the plurality of third silicon vias is surrounded by a first barrier layer.

[0074] In some embodiments, each of the plurality of first silicon vias and the plurality of second silicon vias is surrounded by a corresponding second barrier layer and a corresponding gasket layer.

[0075] In some embodiments, a metal layer is formed on a bottom surface of the silicon substrate and intersects with each of the plurality of third silicon vias.

[0076] In some embodiments, a contact area between each of the plurality of third silicon vias and the metal layer is circular, rectangular, or hexagonal.

[0077] In some embodiments, the memory stack is encapsulated by a molding material.

[0078] In some embodiments, the semiconductor assembly and an integrated circuit are disposed on a printed circuit board to form a semiconductor package structure.

[0079] In another aspect of this disclosure, a semiconductor assembly is provided, comprising a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure. The second semiconductor structure includes a silicon substrate and a plurality of heat dissipation members formed on the silicon substrate to dissipate heat generated by the first semiconductor structure.

[0080] In some embodiments, the first semiconductor structure includes a first semiconductor die and a memory stack bonded to the first semiconductor die, and the first semiconductor die is configured as a memory controller integrated circuit for controlling memory access of the memory stack.

[0081] In some embodiments, the memory stack is a high-bandwidth memory.

[0082] In some embodiments, the memory stack includes a plurality of memory dies. Each of the first semiconductor die and the plurality of memory dies includes an active region and a plurality of edge regions, wherein the plurality of edge regions surround the active region and are not electrically connected to the active region.

[0083] In some embodiments, each of the plurality of edge regions located within each of the first semiconductor die and each of the plurality of memory dies includes a first silicon via and a second silicon via, and a first thermal path and a second thermal path are respectively established along the first silicon via and the second silicon via located within each of the plurality of edge regions located within each of the first semiconductor die and each of the plurality of memory dies.

[0084] In some embodiments, the heat dissipation component includes a silicon substrate and a plurality of third silicon through-holes, wherein the plurality of third silicon through-holes are formed on the silicon substrate and protrude from a top surface of the silicon substrate.

[0085] In some embodiments, the plurality of third silicon vias and the top surface of the silicon substrate are covered by a carbon film.

[0086] In some embodiments, a first width of each of the plurality of third silicon vias is greater than a second width of the first silicon via and the second silicon via located in each of the plurality of edge regions within the first semiconductor die and the plurality of memory dies.

[0087] In some embodiments, the first silicon via located in each of the plurality of edge regions is closer to the active region located in each of the first semiconductor die and the plurality of memory dies. The second silicon via located in each of the regions is farther away from the active region. The first silicon via and the second silicon via located in each of the plurality of edge regions in each of the first semiconductor die and the plurality of memory dies respectively constitute a first sealing ring and a second sealing ring.

[0088] In some embodiments, each of the plurality of third silicon vias is surrounded by a first barrier layer. Each of the plurality of first silicon vias and each of the plurality of second silicon vias is surrounded by a corresponding second barrier layer and a corresponding gasket layer.

[0089] In another aspect of this disclosure, a method is provided, comprising the steps of: providing a first semiconductor wafer, a memory stack, and a second semiconductor wafer; bonding the memory stack to the first semiconductor wafer to form a first semiconductor structure; and bonding the second semiconductor wafer to the first semiconductor structure to form a semiconductor assembly, wherein a first thermal path and a second thermal path are formed within the semiconductor assembly through corresponding plurality of edge regions of the first semiconductor wafer, the memory stack, and the second semiconductor wafer.

[0090] In some embodiments, the first semiconductor wafer includes a first semiconductor die. The memory stack includes a plurality of memory dies. Each of the first semiconductor die and the plurality of memory dies includes an active region and a plurality of edge regions, wherein the plurality of edge regions surround the active region and are not electrically connected to the active region.

[0091] In some embodiments, each of the plurality of edge regions located within each of the first semiconductor die and each of the plurality of memory dies includes a first silicon via and a second silicon via, and a first thermal path and a second thermal path are respectively established along the first silicon via and the second silicon via located within each of the plurality of edge regions located within each of the first semiconductor die and each of the plurality of memory dies.

[0092] In some embodiments, the second semiconductor wafer includes a silicon substrate and a plurality of third silicon vias, wherein the plurality of third silicon vias are formed on the silicon substrate and protrude from a top surface of the silicon substrate.

[0093] In some embodiments, the plurality of third silicon vias and the top surface of the silicon substrate are covered by a carbon film.

[0094] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0095] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0096] 1: Semiconductor wafer 2: Semiconductor wafers 20A: Semiconductor Structure 20B: Semiconductor Structure 20C: Semiconductor Structure 20D: Semiconductor Structure 22: Area 30A: Semiconductor Structure 30B: Semiconductor Structure 30C: Semiconductor Structure 30D: Semiconductor Structure 30E: Semiconductor Structure 31: Memory Stacking 32: Area 34: Molding materials 34': Thinned molding material 34s1: Top surface 40A: Semiconductor Structure 40B: Semiconductor Structure 40C: Semiconductor Structure 40D: Semiconductor Structure 41: Area 42: Barrier Layer 50B: Semiconductor Structure 50C: Semiconductor Structure 50D: Semiconductor Structure 50E: Semiconductor Structure 50F: Semiconductor Assembly 51: Integrated circuit for memory controller 52: 3D Memory Stack 53: Heat sink structure 55: Heat conduction path 60: Semiconductor Packaging 110: Semiconductor die 120: Area 121: Cutting line area 130: Semiconductor die 140: Area 141: Cutting line area 131: Semiconductor die 200A: Semiconductor die 200B: Semiconductor die 200C: Semiconductor die 200D: Semiconductor die 200E: Semiconductor die 202: Cutting line area 210:Substrate 210': Thinned substrate 210s1: Top surface 210s2: Bottom surface 210s2': Bottom surface 211:Through silicon via 212: Metal layer 213: Vertical Interconnection 214: Metal layer 215: Contact pad 216: Barrier Layer 217: Lining layer 220: Dielectric layer 220s1: Top surface 221: Edge region 222: Active Region 230: Temporary bonding layer 240A: First passivation layer 240B: Second passivation layer 240Bs1: Top surface 241: Conductive pad 300: Semiconductor die 300E: Semiconductor die 310:Substrate 310': Thinned substrate 310s1: Top surface 310s2: Bottom surface 311:Through silicon via 312: Metal layer 313: Vertical Interconnection 314: Metallic layer 315: Conductive pad 316: Barrier Layer 317: Lining layer 320: Dielectric layer 320s1: Top surface 321: Edge region 322: Active Region 340A: First passivation layer 340B: Second passivation layer 340Bs1: Top surface 341: Metal Pad 400B: Semiconductor die 400D: Semiconductor die 410: Semiconductor substrate 410': Thinned semiconductor substrate 410s1: Top surface 410s2': Bottom surface 411:Through silicon via 420: Passivation layer 420s1: Top surface 420s2: Bottom surface 430: Metal layer 430s1: Top surface 440: Passivation layer 441: Metal Pad 450: Contact Area 502: Cutting line area 510: Carbon film 521: Bump 522: Passivation layer 600: Integrated Circuits 602: Bump 610: Printed Circuit Board 611: Welding ball C1: Connection Structure C2: Connection Structure R1: First sealing ring R2: Second sealing ring R3: Sealing ring R4: Sealing ring T1: Width T2: Width T3: Width

Claims

1. A semiconductor assembly, comprising: A first semiconductor wafer; A memory stack is bonded to the first semiconductor wafer; and a second semiconductor wafer bonded to the memory stack, wherein the second semiconductor wafer includes a heat sink structure configured to dissipate heat generated by the first semiconductor wafer and the memory stack via a first heat conduction path and a second heat conduction path within the semiconductor assembly; wherein the first semiconductor wafer includes a first semiconductor die configured as a memory controller integrated circuit; wherein the memory stack includes a plurality of vertically stacked memory dies; wherein each of the first semiconductor die and the plurality of memory dies includes an active region and a plurality of edge regions, wherein the plurality of edge regions surround the active region and are not electrically connected to the active region; Each of the plurality of edge regions located within each of the first semiconductor die and each of the plurality of memory dies includes a first silicon via and a second silicon via, and a first heat conduction path and a second heat conduction path are respectively established along the first silicon via and the second silicon via located within each of the plurality of edge regions located within each of the first semiconductor die and the plurality of memory dies; and the first silicon via and the second silicon via respectively constitute a first sealing ring and a second sealing ring; The heat sink structure includes a silicon substrate and a plurality of third silicon through-holes, wherein the plurality of third silicon through-holes are formed on the silicon substrate and protrude from a top surface of the silicon substrate, wherein the plurality of third silicon through-holes and the top surface of the silicon substrate are covered by a carbon film, and a first width of each of the plurality of third silicon through-holes is greater than a second width of the first silicon through-hole and a third width of the second silicon through-hole.

2. The semiconductor assembly as described in claim 1, wherein: The first silicon via located in each of the plurality of edge regions is closer to the active region located in each of the first semiconductor die and the plurality of memory dies.

3. The semiconductor assembly as claimed in claim 1, wherein each of the plurality of third silicon vias is surrounded by a first barrier layer.

4. The semiconductor assembly as claimed in claim 3, wherein each of the plurality of first silicon vias and the plurality of second silicon vias is surrounded by a corresponding second barrier layer and a corresponding pad layer.

5. The semiconductor assembly as claimed in claim 1, wherein a metal layer is formed on a bottom surface of the silicon substrate and intersects with each of the plurality of third silicon vias.

6. The semiconductor assembly as claimed in claim 5, wherein a contact area between each of the plurality of third silicon vias and the metal layer is circular, rectangular, or hexagonal.

7. The semiconductor assembly as described in claim 5, wherein the memory stack is encapsulated by a molding material.

8. The semiconductor assembly as described in claim 7, wherein the semiconductor assembly and an integrated circuit are disposed on a printed circuit board to form a semiconductor package structure.

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