Stacked package

Abstract

A stacked package structure includes at least a carrier plate, a plurality of conductive pillars, a semiconductor element, a plurality of electronic components, and a package body. The conductive pillars are disposed only in a conductive pillar placement area between an edge of a surface of the carrier plate and an electronic component placement area, and electrically connect the carrier plate and the semiconductor element through the conductive pillars, so that the electronic component placement area without the conductive pillars can be used to place the electronic components, thereby increasing the electrical functionality of the stacked package structure. The package body fills the space between the carrier plate and the semiconductor element to support the semiconductor element and seal the conductive pillars and the electronic components.

Description

Technical Field

[0001] This invention relates to a stacked package structure, and more particularly to a stacked package structure that enhances electrical functionality. Prior Technology

[0002] With the increasing electrical functions of electronic products and the demand for thinner and smaller designs, the size of packaging structures must be reduced. Therefore, it is a problem that existing packaging technology must solve to place multiple electronic components with different electrical functions on a single substrate within a limited space. Summary of the Invention

[0003] The main objective of this invention is to provide a stacked package structure in which an electronic component can be arranged in a space between a carrier and a semiconductor component according to electrical requirements, thereby improving the electrical functionality of the stacked package structure.

[0004] A stacked packaging structure of the present invention includes a carrier board, a plurality of conductive pillars, a semiconductor element, a plurality of electronic components, and a first package. The carrier board has a first surface, which includes a plurality of edges, at least one electronic component mounting area, and a conductive pillar mounting area. The conductive pillar mounting area is located only between one of the edges and the electronic component mounting area. The conductive pillars are disposed only in the conductive pillar mounting area, and a first end of the conductive pillars is electrically connected to the carrier board. The semiconductor element has a second surface facing the first surface, which includes a conductive pillar bonding area and a non-conductive bonding area. A conductive pillar bonding area is formed, with a second end of each conductive pillar bonded to the conductive pillar bonding area to electrically connect the semiconductor element. A non-conductive pillar bonding area is located above the electronic element placement area, forming a space between the non-conductive pillar bonding area and the electronic element placement area. The electronic elements are disposed in the electronic element placement area without the conductive pillars and are located in the space. The first package fills the space between the carrier and the semiconductor element, and covers the conductive pillars and the electronic elements located in the space. The first package also supports the non-conductive pillar bonding area without the conductive pillars.

[0005] The present invention, by having the conductive pillar placement area of ​​the carrier board located only between one of the edges and the electronic component placement area, allows the conductive pillars to be placed only in the conductive pillar placement area. This enables the electronic components to be placed in the space between the electronic component placement area of ​​the carrier board and the non-conductive pillar bonding area of ​​the semiconductor element according to electrical requirements, thereby improving the electrical function of the stacked package structure. Simple Explanation of the Diagram

[0006] Figure 1: A cross-sectional schematic diagram of the carrier plate of the present invention. Figures 2A to 2B: Top-view schematic diagrams of the carrier plate of the present invention. Figure 3: A cross-sectional view of the conductive pillars and electronic components disposed on the carrier plate according to the present invention. Figures 4A to 4B: Top-view schematic diagrams of the present invention with conductive pillars and electronic components disposed on a carrier plate. Figures 5A and 5B: Schematic diagrams of the present invention in which a conductive pillar and electronic components are sealed in a first package. Figure 6: A schematic diagram of the present invention where a semiconductor element is bonded to a conductive pillar. Figures 7A to 8B: Schematic diagrams of the present invention in which a semiconductor element is sealed in a second package and a heat dissipation layer is formed. Figures 9A to 9B: Schematic diagrams of the present invention in which a semiconductor element is sealed in a second package to form an electromagnetic shield. Implementation

[0007] Please refer to Figure 6. A stacked package structure 100 of the present invention includes at least a carrier plate 110, a plurality of conductive pillars 120, a semiconductor element 150, a plurality of electronic components 130, and a first package 140. Please refer to Figures 8A and 8B. The stacked package structure 100 further includes a second package 160 and a heat dissipation layer 170. Alternatively, please refer to Figures 9A and 9B. The stacked package structure 100 further includes the second package 160 and an electromagnetic shield 180.

[0008] Please refer to Figures 1, 2A, 2B and 6. The carrier plate 110 has a first surface 111. The first surface 111 includes a plurality of edges 111a, at least one electronic component placement area 111b and a conductive post placement area 111c. The conductive post placement area 111c is located only between one of the edges 111a and the electronic component placement area 111b. The conductive posts 120 are only disposed in the conductive post placement area 111c. A first end 121 of the conductive posts 120 is electrically connected to the carrier plate 110. Please refer to Figure 4A or 4B. In this embodiment, the conductive posts 120 are disposed in the conductive post placement area 111c only along one axial direction. Please refer to Figure 4A. The conductive posts 120 are disposed in the conductive post placement area 111c only along one axial direction Y. Alternatively, please refer to Figure 4B. The conductive posts 120 are disposed in the conductive post placement area 111c only along another axial direction X.

[0009] Please refer to Figure 6. The semiconductor element 150 has a second surface 151 facing the first surface 111. The second surface 151 includes a conductive post bonding region 151a and a non-conductive post bonding region 151b. A second end 122 of the conductive posts 120 is bonded to the conductive post bonding region 151a to electrically connect the semiconductor element 150. In this embodiment, the conductive post bonding region 151a is adjacent to an edge 151c of the second surface 151. The conductive post bonding region 151a is located between the non-conductive post bonding region 151b and the edge 151c, and the conductive post bonding region 151a is located above the conductive post mounting region 111c. The non-conductive post bonding region 151b is located above the electronic component mounting region 111b, so that a space S is formed between the non-conductive post bonding region 151b and the electronic component mounting region 111b.

[0010] Please refer to Figure 6. The electronic components 130 are disposed in the electronic component placement area 111b where the conductive pillars 120 are not provided and are located in the space S. The first package 140 fills the space between the carrier plate 110 and the semiconductor element 150, and covers the conductive pillars 120 and the electronic components 130 located in the space S. The semiconductor element 150 is supported by the first package 140 in the non-conductive pillar bonding area 151b where the conductive pillars 120 are not bonded.

[0011] Please refer to Figures 1 to 9B, and the stacked package structure 100 is manufactured by the following manufacturing method.

[0012] First, please refer to Figures 1, 2A, and 2B. A carrier A is provided, which can be selected from wafers, circuit boards, or glass substrates, etc. The carrier A can be disposed on an adhesive tape (not shown) for subsequent processes. The carrier A includes a plurality of adjacent carrier plates 110. Each carrier plate 110 has a first surface 111. The first surface 111 includes edges 111a, electronic component placement areas 111b, and conductive pillar placement areas 111c. Please refer to Figure 2A or 2B. The conductive pillar placement area 111c is located only between one of the edges 111a and the electronic component placement area 111b.

[0013] Next, referring to Figures 3, 4A, and 4B, the conductive pillars 120 are disposed in the conductive pillar placement area 111c only between one of the edges 111a and the electronic component placement area 111b, and the electronic components 130 are disposed in the electronic component placement area 111b. The conductive pillars 120 are electrically connected to the carrier plate 110 at the first end 121. The material of the conductive pillars 120 may be copper, but is not limited thereto. The electronic components 130 may be made of chips, filters, passive components, etc., and can be disposed according to electrical requirements. The electronic components 130 are electrically connected to the carrier plate 110.

[0014] Please refer to Figure 4A or 4B. The conductive pillars 120 are disposed in the conductive pillar placement area 111c only along one axial direction. Please refer to Figure 4A. The conductive pillars 120 are disposed in the conductive pillar placement area 111c only along the Y-axis. Alternatively, please refer to Figure 4B. The conductive pillars 120 are disposed in the conductive pillar placement area 111c only along the other axial direction X. This allows the electronic component placement area 111b, which does not have the conductive pillars 120, to be used to place the electronic components 130 according to electrical requirements.

[0015] Next, referring to Figure 5A, the first package 140 seals the conductive posts 120 and the electronic components 130. When the first package 140 covers the second end 122 of the conductive posts 120, the first package 140 can be ground to expose the second end 122 (see Figure 5B). Alternatively, referring to Figure 5B, when the first package 140 seals the conductive posts 120 and the electronic components 130, the second end 122 of the first package 140 is already exposed.

[0016] Next, referring to Figure 6, a semiconductor element 150 is provided, and the semiconductor element 150 is bonded to the second end 122 of the conductive pillars 120. In this embodiment, the semiconductor element 150 has a second surface 151, which includes the conductive pillar bonding region 151a and the non-conductive pillar bonding region 151b. The semiconductor element 150 faces the first surface 111 with the second surface 151 facing it, and the second end 122 of the conductive pillars 120 is bonded to the conductive pillar bonding region 151b. Region 151a is electrically connected to the conductive pillars 120 and the semiconductor element 150. In this embodiment, a space S is formed between the non-conductive pillar bonding region 151b and the electronic element placement region 111b. The space S is used to place the electronic elements 130 and fill the first package 140. The first package 140 not only covers the conductive pillars 120 and the electronic elements 130 located in the space S, but also supports the non-conductive pillar bonding region 151b that is not bonded to the conductive pillars 120.

[0017] Next, referring to Figure 7A, preferably, the semiconductor element 150 is sealed with the second package 160. In this embodiment, the second package 160 covers a surface 152 of the semiconductor element 150. Then, a heat dissipation layer 170 is formed on the second package 160. The heat dissipation layer 170 is disposed on the second package 160, and each stacked package structure 100 dissipates heat through the heat dissipation layer 170. Referring to Figure 8A, a cutting process is then performed to separate the stacked package structures 100.

[0018] Alternatively, referring to Figure 7B, when the second package 160 seals the semiconductor element 150 and covers the surface 152 of the semiconductor element 150, the second package 160 can be ground to expose the surface 152. The heat dissipation layer 170 is disposed on the surface 152 of the semiconductor element 150 so that the stacked package structure 100 dissipates heat through the heat dissipation layer 170. Then, referring to Figure 8B, a cutting process is performed to separate the stacked package structures 100.

[0019] Alternatively, referring to Figure 9A, after the second package 160 is formed to seal the semiconductor element 150, a dicing process is performed to separate the stacked package structures 100, and an electromagnetic shield 180 is formed on each of the stacked package structures 100. The electromagnetic shield 180 covers one side wall 141 of the second package 160 and the first package 140, and is electrically connected to the carrier plate 110.

[0020] Alternatively, referring to Figure 9A, after the second package 160 is formed to seal the semiconductor element 150, the second package 160 can be ground to expose the surface 152. Then, a cutting process is performed to separate the stacked package structures 100, and an electromagnetic shield 180 is formed on each of the stacked package structures 100. The electromagnetic shield 180 covers the second package 160, the surface 152 of the semiconductor element 150, the sidewall 141 of the first package 140, and is electrically connected to the carrier plate 110.

[0021] The stacked package structure 100 of the present invention, by having the conductive pillar placement area 111c of the carrier 110 located only between one of the edges 111a and the electronic component placement area 111b, allows the conductive pillars 120 to be disposed only in the conductive pillar placement area 111c, thereby increasing the usable area of ​​the electronic component placement area 111b of the carrier 110. Furthermore, the space S between the electronic component placement area 111b of the carrier 110 and the non-conductive pillar bonding area 151b of the semiconductor element 150 can be used to place the electronic components 130 in the space S according to electrical requirements, thereby improving the electrical function of the stacked package structure 100.

[0022] The scope of protection of this invention shall be determined by the appended claims. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of this invention shall fall within the scope of protection of this invention.

[0023] 100: Stacked Package Construction 110: Carrier board 111: First Surface 111a: Edge 111b: Electronic component placement area 111c: Conductive post setting area 120: Conductive column 121: First End 122: Second End 130: Electronic components 140: First package 141: Sidewall 150: Semiconductor components 151: Second Surface 151a: Conductive post junction area 151b: Non-conductive post junction area 151c: Edge 152: Surface 160: Second package 170: Heat dissipation layer 180: Electromagnetic shielding cover A: Carrier S: Space

Claims

1. A stacked package structure, comprising: a carrier substrate having a first surface, the first surface including a plurality of edges, at least one electronic component mounting area, and a conductive pillar mounting area, the conductive pillar mounting area being located only between one of the edges and the electronic component mounting area; a plurality of conductive pillars being disposed only in the conductive pillar mounting area, a first end of the conductive pillars being electrically connected to the carrier substrate; a semiconductor element having a second surface facing the first surface, the second surface including a conductive pillar bonding area and a non-conductive pillar bonding area, a second end of the conductive pillars being bonded to the conductive pillar bonding area to electrically connect the semiconductor element, the non-conductive pillar bonding area being located above the electronic component mounting area, such that a space is formed between the non-conductive pillar bonding area and the electronic component mounting area; and a plurality of electronic components being disposed in the electronic component mounting area where the conductive pillars are not provided, and located in the space; A first package is filled between the carrier and the semiconductor element, and covers the conductive pillars and the electronic components located in the space, and the first package supports the non-conductive pillar bonding area where the conductive pillars are not bonded; a second package seals the semiconductor element; and an electromagnetic shield covers one sidewall of the second package and the first package and is electrically connected to the carrier.

2. The stacked package structure as claimed in claim 1, wherein the conductive pillars are disposed only along one axial direction in the conductive pillar placement area.

3. The stacked package configuration of claim 1, wherein the second package exposes a surface of the semiconductor element and the electromagnetic shield covers the surface of the semiconductor element.

4. The stacked package configuration of claim 1, wherein the second surface includes an edge, the conductive post bonding area is adjacent to the edge, the conductive post bonding area is located between the non-conductive post bonding area and the edge, and the conductive post bonding area is located above the conductive post placement area.

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