Circuit and system for driving integrated semiconductor laser device

Abstract

This application claims protection for a charging unit for driving an integrated semiconductor laser. The charging unit may include a first input terminal for receiving input drive energy, a second input terminal configured to enable or disable the charging unit, a third input terminal configured to receive a charging control PWM signal, and a second plurality of output terminals. The charging unit may be configured to switch the second plurality of output terminals on / off in a predetermined pattern according to the charging control PWM signal.

Description

Technical Field

[0001] This application relates to an electronic circuit, and more specifically, but not limited to, circuits and systems for driving integrated semiconductor lasers. [Related Citations] [] []

[0002] This application claims priority and benefit to U.S. Patent Application No. 63 / 612,172, filed December 19, 2023, and the entire contents of the aforementioned patent application are herein incorporated. Prior Technology

[0003] Today, LiDAR is widely used in Advanced Driver Assistance Systems (ADAS) in automotive applications. One challenge for solid-state LiDAR is driving highly integrated semiconductor lasers with laser cell arrays, such as vertical-cavity surface-emitting lasers (“VCSEL”), to allow individual control of each laser cell in the array. Semiconductor lasers require laser drivers to provide pulsed currents to their semiconductor laser emitting cells. Existing semiconductor laser driving solutions are based on discrete gallium nitride field-effect transistors (hereinafter referred to as “GaN-based discrete solutions”). This approach does not meet the reliability requirements of automotive OEMs (“OEMs”) and is too large for limited installation space. Furthermore, Tier 1 suppliers consider GaN-based discrete solutions too expensive; for example, driving a semiconductor laser may require more than 10 discrete drivers to correspondingly drive more than 10 discrete GaN field-effect transistors to control more than 10 laser cells in that semiconductor laser. Summary of the Invention

[0004] This application provides a charging unit for driving an integrated semiconductor laser. The charging unit includes a first input terminal, a second input terminal, a third input terminal, and a plurality of second output terminals. The first input terminal is configured to receive input drive energy. The second input terminal is configured to enable or disable the charging unit. The third input terminal is configured to receive a charging control PWM signal. The charging unit is configured to enable or disable the plurality of second output terminals in a predetermined mode according to the charging control PWM signal. Simple Explanation of the Diagram

[0005] [Figure 1] shows a schematic diagram of a drive system 100 according to an embodiment of the present disclosure.

[0006] [Figure 2] shows a schematic diagram of a charging unit 200 according to an embodiment of the present disclosure, which can be applied to implement the charging unit 102 of the drive system 100 in FIG1.

[0007] [Figure 3A] shows a schematic waveform diagram 300 according to an exemplary embodiment of the present disclosure, which depicts exemplary operating waveforms of several signals of the drive system 100 in Figure 1.

[0008] [Figure 3B] shows a schematic waveform diagram 300B according to another exemplary embodiment of the present disclosure, which depicts exemplary operating waveforms of several signals of the drive system 100 in FIG1.

[0009] [Figure 4] shows a schematic diagram of a charging unit 400 according to an embodiment of the present disclosure, which can be applied to implement the charging unit 102 of the drive system 100 in FIG1.

[0010] [Figure 5A] shows a schematic waveform diagram 500 according to an exemplary embodiment of the present disclosure, which depicts exemplary operating waveforms of several signals of the drive system 100 in FIG1, wherein the charging unit 102 adopts the charging unit 400 shown in FIG4.

[0011] [Figure 5B] shows a schematic waveform diagram 500B according to an exemplary embodiment of the present disclosure, which depicts exemplary operating waveforms of several signals of the drive system 100 in FIG1, wherein the charging unit 102 adopts the charging unit 400 shown in FIG4.

[0012] [Figure 6] shows a schematic waveform diagram 600 according to an exemplary embodiment of the present disclosure, which depicts exemplary operating waveforms of several signals of the drive system 100 in FIG1, wherein the charging unit 102 adopts the charging unit 400 shown in FIG4.

[0013] [Figure 7] shows a schematic diagram of a discharge unit 700 according to an exemplary embodiment of the present disclosure, which can be used to implement the discharge unit 106 in FIG1.

[0014] [Figure 8] shows a package 800 encapsulating a charging unit 102 according to an embodiment of the present disclosure, the charging unit 102 being integrated into an integrated circuit die or wafer.

[0015] [Figure 9] shows a package 900 encapsulating a discharge unit 106 according to an embodiment of the present disclosure, the discharge unit 106 being integrated into an integrated circuit die or wafer.

[0016] [Figure 10] shows a package 950 encapsulating a discharge unit 700 according to an embodiment of the present disclosure, the discharge unit 700 being integrated into an integrated circuit die or wafer.

[0017] [Figure 11] shows a schematic diagram of a drive system 150 according to an embodiment of the present disclosure.

[0018] [Figure 12] shows a schematic diagram of a charging unit 250 according to an embodiment of the present disclosure, which may be used as an alternative implementation of the charging unit 102 in Figure 11.

[0019] [Figure 13] shows a schematic waveform diagram 350 according to an exemplary embodiment of the present disclosure, which illustrates exemplary operating waveforms of several signals of the drive system 150 of Figure 11.

[0020] [Figure 14] shows a schematic diagram of a charging unit 450 according to an embodiment of the present disclosure.

[0021] [Figure 15] shows a schematic waveform diagram 550 according to an exemplary embodiment of the present disclosure, which illustrates exemplary operating waveforms of several signals of the drive system 150 in Figure 11.

[0022] [Figure 16] shows a schematic waveform diagram 650 according to an exemplary embodiment of the present disclosure, which illustrates exemplary operating waveforms of several signals of the drive system 150 in Figure 11.

[0023] [Figure 17] illustrates a package 850 containing an integrated circuit die or wafer of a charging unit 102 according to one embodiment of the present disclosure, which provides another alternative implementation.

[0024] [Figure 18] shows an application board-level layout diagram related to the drive system 100 in FIG1 or the drive system 150 in FIG11 according to an embodiment of the present disclosure.

[0025] Figures 18A through 18F show application board layout diagrams of various layers of an embodiment of the present disclosure, which are related to the application board layout diagram of the drive system 100 in FIG1 or the drive system 150 in FIG11.

[0026] [Figure 18G] shows a plan view of the top surface of the first board level 180(1) according to another embodiment of the present disclosure.

[0027] [Figure 18H] shows a plan view of the bottom surface of a multilayer circuit board 1800 according to another embodiment of the present disclosure.

[0028] [Figure 19] shows a schematic diagram of a drive system 1000 according to an embodiment of the present disclosure.

[0029] [Figure 20] shows a schematic diagram of a drive system 1500 according to an embodiment of the present disclosure.

[0030] [Figure 21A] shows an application board-level layout diagram related to the drive system 1000 in FIG19 or the drive system 1500 in FIG20 according to an embodiment of the present disclosure.

[0031] Figures 21B through 21G show application board-level layout diagrams of each layer associated with the drive system 1000 in Figure 19 or the drive system 1500 in Figure 20, according to an embodiment of the present disclosure.

[0032] [Figure 22] shows a schematic diagram of a drive system 2000 according to an embodiment of the present disclosure.

[0033] [Figure 23] shows a schematic waveform diagram 2300 according to an exemplary embodiment of the present disclosure, which illustrates exemplary operating waveforms of several signals when the drive system 150 in Figure 11 is operating in parallel output mode. Implementation

[0034] In the following description, specific details, such as schematic diagrams of circuits and circuit elements, are included to provide a thorough understanding of the embodiments. However, those skilled in the art will understand that this disclosure may be practiced without one or more of these specific details, or using other methods, elements, materials, etc. In other instances, well-known structures, materials, processes, or operations have not been shown or described in detail to avoid obscuring aspects of the invention.

[0035] Throughout this specification and the scope of the claims, the terms “left,” “right,” “inner,” “outer,” “front,” “back,” “upper,” “lower,” “top,” “above,” “bottom,” “cover,” “under,” “above,” and “below” are used for descriptive purposes only and are not necessarily used to describe permanent relative positions. It should be understood that these terms are interchangeable where appropriate so that embodiments of the technology described herein can operate in directions other than those shown or described herein. As used in this disclosure, “connection” or “coupled” is defined as a direct or indirect connection in an electrical or non-electrical manner. When an element is described as “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be one or more intermediate elements. Conversely, when an element is referred to as “directly connected” or “directly coupled” to another element, there are no intermediate elements. Throughout this specification, references to “an embodiment,” “an example,” or “example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of this disclosure. Therefore, the phrases “in one embodiment,” “in an embodiment,” “an example,” or “example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example, although they may refer to the same embodiment. Furthermore, these features, structures, or characteristics may be combined in one or more embodiments or examples. The term “or” is equivalent herein to the term “and / or” unless the context clearly indicates otherwise. Where a field-effect transistor (“FET”) or a bipolar junction transistor (“BJT”) may be used as an embodiment of a transistor, the terms “gate,” “drain,” and “source” encompass “base,” “collector,” and “emitter,” respectively, and vice versa. The term “based on” is not exclusive and allows for basing on other factors not described unless the context clearly indicates otherwise. The term “circuit” means at least one single element or multiple elements, whether active and / or passive, connected together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. Those skilled in the art will understand that the meanings of the above terms are not necessarily limiting, but merely illustrative examples of these terms.

[0036] The terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, meaning that when a process, method, or apparatus includes a list of expressly listed elements, it is not necessarily limited to including only those expressly listed elements, but may include other elements not expressly listed or elements inherent to the process, method, or apparatus.

[0037] Figure 1 shows a schematic diagram of a drive system 100 according to an embodiment of the present disclosure. The drive system 100 is adapted to be configured to drive an integrated semiconductor laser 101, such as an integrated vertical-cavity surface-emitting laser (“VCSEL”) unit. The integrated semiconductor laser (e.g., semiconductor laser) 101 may comprise a series (e.g., represented by an integer variable N) of laser units (e.g., VCSEL units) 101(1), 101(2), …, 101(N) arranged in an array or matrix. Hereinafter, this series (e.g., N laser units) 101(1), 101(2), …, 101(N) may be referred to or represented as {101(i), i=1, 2, …, N}. Where N is an integer variable not less than 1, representing the total number of laser units {101(i), i=1, 2, …, N} included in the integrated semiconductor laser 101. This total number can be set or determined by the customer / user in actual application according to the actual application requirements. That is, the variable i iterates through integers from 1 to N. Each of the first plurality (e.g., N) laser units {101(i), i=1, 2, …, N} can have a first terminal (e.g., anode) and a second terminal (e.g., cathode). In one example, the integrated semiconductor laser 101 may include 28 laser units {101(i), i=1, 2, …, 28}, where N=28 in this example. Those skilled in the art should understand that this is only to provide an example and is not intended to be limiting. The total number of laser units {101(i), i=1, 2, …, N} included in the integrated semiconductor laser 101 is not limited to 28 and can be any other number depending on the actual application requirements. In this disclosure, the integer variable N is used to describe or represent the total number of laser cells {101(i), i=1, 2, …, N} included in the integrated semiconductor laser 101 for ease of reference and understanding.

[0038] The drive system 100 may include a drive energy input terminal IN for receiving input drive energy. In one example, the input drive energy is expressed in the form of a supply voltage VIN; however, this is merely an example and not intended to be limiting. Those skilled in the art will understand that the input drive energy may be other forms suitable for use or processing by the drive system 100, such as supply current or supply power. As shown in Figure 1, in one example, the input drive energy, expressed in the form of a supply voltage VIN, may be provided by upstream power supply circuitry, which may obtain energy from, for example, the power source PS of an automotive battery pack. As shown in Figure 1, in one example, the upstream power supply circuitry may include a front-end voltage regulator 10 and a buck voltage regulator 20. As an example, the front-end voltage regulator 10 and the buck voltage regulator 20 may respectively include the MPQ5850 and MPQ4323 from Monolithic Power Systems. However, those skilled in the art will understand that this is merely an example and not intended to be limiting. The upstream power supply circuitry may be implemented using other power supply devices or may include other circuit elements.

[0039] According to an exemplary embodiment, the drive system 100 may further include a charging unit 102. The charging unit 102 has a first input terminal, for example, a power supply terminal IN1 connected to the drive energy input terminal IN. The charging unit 102 may include a series of output terminals OUT(1), OUT(2), …, OUT(M) (e.g., represented by an integer variable M). Hereinafter, the series of output terminals OUT(1), OUT(2), …, OUT(M) may be referred to or represented as {OUT(j), j=1, 2, …, M}. Here, M is an integer variable representing the total number of output terminals {OUT(j), j=1, 2, …, M} included in the charging unit 102. That is, the variable j iterates through integers from 1 to M. According to an exemplary embodiment, M is not less than N, i.e., M≥N. For example, the charging unit 102 may include 32 output terminals {OUT(j), j=1, 2, …, 32}, in which case M=32. Those skilled in the art will understand that this is merely an example and not intended to be limiting. The total number of output terminals {OUT(j), j=1, 2, …, M} included in the charging unit 102 is not limited to 32, and can be set to any other number according to actual application requirements. In this disclosure, the integer variable M is used to describe or represent the total number of output terminals {OUT(j), j=1, 2, …, M} of the charging unit 102 for ease of reference and understanding.

[0040] According to an exemplary embodiment, the charging unit 102 may further include a second input terminal, such as an enable terminal EN configured to receive an enable signal EN_C. The charging unit 102 may be configured to be enabled or disabled in response to the enable signal EN_C received by the enable terminal EN. In one example, when the charging unit 102 is enabled, this means that the charging unit 102 (including all sub-circuits or sub-elements of the charging unit 102) is operable, i.e., capable of processing signals or performing a predetermined function. When the charging unit 102 is disabled, it may mean that the charging unit 102 is inoperable or has been turned off. In one example, the charging unit 102 may be configured to be enabled when the enable signal EN_C received by the enable terminal EN is in a first logic state (e.g., logic high) or when the enable signal EN_C reaches or exceeds an enable threshold, and may be further configured to be disabled when the enable signal EN_C is in a second logic state (e.g., logic low) or when the enable signal EN_C is below an enable threshold.

[0041] According to an exemplary embodiment, the charging unit 102 may further include a third input terminal, for example, a pulse width modulation (“PWM”) terminal PWM1 configured to receive a charging control PWM signal PWM_C. The charging unit 102 may also be further configured to switch the M output terminals {OUT(j), j=1, 2, …, M} on / off according to the charging control PWM signal PWM_C in a predetermined mode (which may be a pre-programmable mode by the client or user). In an exemplary embodiment, for each of the M output terminals {OUT(j), j=1, 2, …, M}, for example, the j-th output terminal OUT(j), it may be configured to provide energy in the form of voltage or current when switched to the on state, and to stop providing energy when switched to the off state. In an exemplary embodiment, for each of the M output terminals {OUT(j), j=1, 2, …, M}, for example, the j-th output terminal OUT(j), when it is switched to the on state, the duration or time window of the on state may be referred to as the j-th charging time window Tcg(j) for the purposes of description and understanding below.

[0042] According to one exemplary embodiment, the M output terminals {OUT(j), j=1, 2, …, M} can be sequentially switched to the on state according to a plurality of successive charging pulses of the charging control PWM signal PWM_C (i.e., switched on in the order from OUT(1) to OUT(M)). For example, for each j from 1 to M, the j-th output terminal OUT(j) is switched to the on state during the j-th charging time window Tcg(j) according to the j-th charging pulse of the charging control PWM signal PWM_C. However, those skilled in the art should understand that this is merely to provide an example and is not intended to be limiting. In other exemplary embodiments, the predetermined mode of switching the M output terminals {OUT(j), j=1, 2, …, M} on / off can be flexibly controlled or programmed, for example by the customer or user, and does not necessarily need to be switched to the on state sequentially according to a plurality of successive charging pulses of the charging control PWM signal PWM_C (i.e., switched on in the order from OUT(1) to OUT(M)). In other words, for each j from 1 to M, the j-th charging time window Tcg(j) when the j-th output terminal OUT(j) is switched to the on state does not necessarily correspond to the j-th charging pulse of the charging control PWM signal PWM_C.

[0043] Furthermore, those skilled in the art should understand that the first charging pulse of the charging control PWM signal PWM_C may not be the actual initial pulse or the first pulse of PWM_C. Instead, the first charging pulse may refer to a pulse that appears or is generated by the charging control PWM signal PWM_C after a predetermined time Tready has elapsed since the drive system 100 or charging unit 102 is powered on. During the predetermined time Tready, the drive system 100 or charging unit 102 prepares for normal and stable operation. In one exemplary embodiment, the first charging pulse, the second charging pulse, ..., the jth charging pulse, etc., of the charging control PWM signal PWM_C refer to a series of consecutive pulses of the charging control PWM signal PWM_C. Those skilled in the art should understand that this is merely to provide an example and is not intended to be limiting. In other exemplary embodiments, the first charging pulse, the second charging pulse, ..., the jth charging pulse, etc., of the charging control PWM signal PWM_C refer to every two or three adjacent and consecutively generated pulses in the charging control PWM signal PWM_C.

[0044] According to an exemplary embodiment, the charging unit 102 may further include a reference ground terminal GND1. The charging unit 102 and all its sub-circuits or sub-components may be configured to use the reference ground potential at the reference ground terminal GND1 as the ground potential of the charging unit 102. In one example, the reference ground terminal GND1 of the charging unit 102 may be coupled to the reference ground terminal GND of the drive system 100.

[0045] According to an exemplary embodiment, the charging unit 102 can be coupled to the integrated semiconductor laser 101 and provide energy to the N laser units {101(i), i=1, 2, …, N} through the M output terminals {OUT(j), j=1, 2, …, M} in a predetermined mode determined by the charging control PWM signal PWM_C. For example, in an exemplary embodiment, a first group (e.g., N) of output terminals corresponding to the N laser units {101(i), i=1, 2, …, N} can be selected from the M output terminals {OUT(j), j=1, 2, …, M}, and the first group (e.g., N) of output terminals can be coupled to the N laser units {101(i), i=1, 2, …, N} in a one-to-one correspondence. In other words, the corresponding first group (e.g., N) of output terminals selected from the M output terminals {OUT(j), j=1, 2, …, M} matches at least in number the N laser units {101(i), i=1, 2, …, N}. Hereinafter, the first group (e.g., N) of output terminals selected from the M output terminals {OUT(j), j=1, 2, …, M} of the charging unit 102 and coupled to the N laser units {101(i), i=1, 2, …, N} is referred to as the first group (e.g., N) of selected output terminals and denoted as {OUT(i), j=1, 2, …, N} for reference, description, and understanding in the remainder of this disclosure.

[0046] Here is an example, as shown in Figure 1, where the first N consecutive output terminals {OUT(j), j=1, 2, …, M} selected from M output terminals {OUT(j), j=1, 2, …, N} are configured to be coupled to the N laser units {101(i), i=1, 2, …, N} respectively. However, this is only for illustrative purposes and is not intended to be limiting.

[0047] Those skilled in the art will understand that, since the total number of output terminals M of the charging unit 102 is not less than the total number of laser units N, any N output terminals can be randomly selected from the M output terminals {OUT(j), j=1, 2, …, M} of the charging unit 102 to drive the N laser units {101(i), i=1, 2, …, N}. That is, each output terminal in the first group of selected output terminals from the M output terminals {OUT(j), j=1, 2, …, M} of the charging unit 102 can be coupled to a corresponding laser unit in the N laser units {101(i), i=1, 2, …, N}. In the following description, among the first set of selected output terminals chosen from, for example, M output terminals {OUT(j), j=1, 2, …, M} of the charging unit 102, the output terminal coupled to the i-th laser unit 101(i) among the N laser units {101(i), i=1, 2, …, N} may be referred to as the selected i-th output terminal and labeled or renumbered as OUT(i) for ease of reference, description and understanding in the remainder of this disclosure. The selected i-th output terminal OUT(i) may be connected to the first terminal of the corresponding i-th laser unit 101(i). Those skilled in the art should understand that, in the exemplary embodiment, the first consecutive N output terminals {OUT(j), j=1, 2, …, M} selected from the M output terminals {OUT(j), j=1, 2, …, N} are coupled to the N laser units {101(i), i=1, 2, …, N} respectively. In this example, the first plurality of consecutively numbered output terminals {OUT(j), j=1, 2, …, N} selected from the second plurality of output terminals {OUT(i), i=1, 2, …, M} and the first plurality of selected output terminals {OUT(i), i=1, 2, …, N} have the same meaning. For each i from 1 to N, i=j, that is, the j-th output terminal OUT(j), the ith output terminal OUT(i), and the selected ith output terminal OUT(i) refer to the same output terminal.However, it will also be apparent to those skilled in the art that the first plurality (e.g., N) selected output terminals {OUT(i), i=1, 2, ..., N} are not always equal to the first plurality of consecutively numbered N output terminals {OUT(j), j=1, 2, ..., N} in the second plurality (e.g., M) output terminals {OUT(j), j=1, 2, ..., N}, but rather the first plurality (e.g., N) selected output terminals {OUT(i), i=1,2,...,N} are renumbered according to the corresponding first plurality of laser units {101(i), i=1,2,...,N}.

[0048] According to an exemplary embodiment, the first set of selected output terminals {OUT(i), i=1, 2, …, N} can be sequentially switched to the on state according to a plurality of consecutive charging pulses of the charging control PWM signal PWM_C (i.e., switched on in the order from OUT(1) to OUT(M)). For example, for each i traversing 1 to N, the selected i-th output terminal coupled to the i-th laser unit 101(i) of the N laser units {101(i), i=1, 2, …, N} can be switched to the on state during a period referred to herein as the i-th charging time window Tcg(i). In an exemplary embodiment, for each i traversing 1 to N, the i-th charging time window Tcg(i) may occur after the i-th charging pulse of the charging control PWM signal PWM_C. For example, in one embodiment, for each i traversing 1 to N, the i-th charging time window Tcg(i) may occur between the i-th charging pulse and the (i+1)-th charging pulse of the charging control PWM signal PWM_C. In other words, in this example, for each i traversing 1 to N, the switching mode or sequence of the selected i-th output terminal's on / off state is determined by the i-th charging pulse of the charging control PWM signal PWM_C. However, those skilled in the art should understand that this is merely to provide an example and is not intended to be limiting. In other exemplary embodiments, for each i traversing 1 to N, the switching mode or sequence of the selected i-th output terminal's on / off state, i.e., the occurrence position of the i-th charging time window Tcg(i), can be flexibly controlled or programmed, and is not necessarily the i-th charging pulse of the charging control PWM signal PWM_C. Those skilled in the art will understand that, in the exemplary embodiment, the first consecutive N output terminals {OUT(j), j=1, 2, …, M} selected from the M output terminals {OUT(j), j=1, 2, …, N} are coupled to the N laser units {101(i), i=1, 2, …, N} respectively. In this example, for each i traversing from 1 to N, i=j, and the j-th charging time window Tcg(j) associated with the j-th output terminal OUT(j) and the i-th charging time window Tcg(i) associated with the selected i-th output terminal refer to the same charging time window.

[0049] According to an exemplary embodiment, the charging unit 102 may further include at least one controllable power switch 103, which can be configured to perform on / off switching when the charging unit 102 is enabled. In an exemplary embodiment, when the charging unit 102 is enabled, the at least one controllable power switch 103 can be configured to perform on / off switching in response to a charging control PWM signal PWM_C received at a third input terminal (e.g., PWM terminal PWM1) of the charging unit 102. For example, during each cycle T PWMC of the charging control PWM signal PWM_C, the at least one controllable power switch 103 is switched to the on state in response to the first transition edge (e.g., rising edge) of the charging control PWM signal PWM_C, at which point the charging control PWM signal PWM_C changes from a first voltage level or logic level (e.g., logic low) to a second voltage level or logic level (e.g., logic high), and is switched to the off state in response to the second transition edge (e.g., falling edge) of the charging control PWM signal PWM_C, at which point the charging control PWM signal PWM_C changes from a second voltage level or logic level (e.g., logic high) to a first voltage level or logic level (e.g., logic low). However, this is only an example and is not intended to limit the scope; in other embodiments, the at least one controllable power switch 103 may not perform on and off switching in each operating cycle or cycle T PWMC of the charging control PWM signal PWM_C. For example, at least one controllable power switch 103 can be turned on in response to a first transition edge (e.g., rising edge) of each charging pulse of the charging control PWM signal PWM_C, at which edge the charging control PWM signal PWM_C changes from a first voltage level or logic potential (e.g., logic low) to a second voltage level or logic potential (e.g., logic high), and can also be turned on in response to a second transition edge (e.g., rising edge) of each charging pulse of the charging control PWM signal PWM_C. The second transition edge (e.g., falling edge) of each charging pulse of the charging control PWM signal PWM_C can be turned off when the charging control PWM signal PWM_C changes from the second voltage level or logic potential (e.g., logic high) to the first voltage level or logic potential (e.g., logic low).

[0050] Ideally, the at least one controllable power switch 103 allows current to flow when turned on and cuts off current flow when turned off. For example, the at least one controllable power switch 103 may include a field-effect transistor ("FET"), such as a metal-oxide-semiconductor field-effect transistor ("MOSFET"), a double-diffused metal-oxide-semiconductor field-effect transistor ("DMOS"), a gallium nitride field-effect transistor ("GaN FET"), a silicon carbide field-effect transistor ("SiC FET"), or a field-effect junction field-effect transistor ("JFET"). Those skilled in the art will understand that the at least one controllable power switch 103 may be implemented using other controllable switching devices, such as bipolar transistors ("BJT") or insulated-gate bipolar transistors ("IGBT"). Alternatively, in other examples, the at least one controllable power switch 103 may include a combination of one or more of the above-described transistors. The at least one controllable power switch 103 can be used to control or regulate the amount of energy transferred from the drive energy input terminal IN to the charging unit 102. For example, in one embodiment, at least one controllable power switch 103 can be used to control or regulate the amount of energy transferred from the drive energy input terminal IN to the power output terminal BSTO of the charging unit 102. Thus, the charging unit 102 can be configured to convert the supply voltage VIN into a regulated output voltage Vo provided at the power output terminal BSTO.

[0051] According to an exemplary embodiment, the charging unit 102 may further include a switching terminal SW, which may be configured to provide, for example, a switching signal. When the inductive energy storage element L is coupled to the switching terminal SW of the charging unit 102, the charging unit 102 may be configured to operate as part of a power conversion device. For example, as shown in FIG1, at least one controllable power switch 103 may be coupled between the switching terminal SW and the power output terminal BSTO. The inductive energy storage element L may be coupled between a first input terminal (e.g., power terminal IN1) of the charging unit 102 and the switching terminal SW. The power conversion device may further include a second power switch 105, which, in the example shown in FIG1, may be coupled between the switching terminal SW and the power output terminal BSTO. In one example, the second power switch 105 may be a diode. In another example, the second power switch 105 may include a controllable transistor, such as a MOSFET, DMOS, GaN FET, SiC FET, BJT, or IGBT. The second power switch 105 can be a discrete device disposed outside the charging unit 102 or an integrated device disposed inside the charging unit 102. In an exemplary embodiment, the second power switch 105 can be configured to perform on / off switching in a complementary manner to at least one controllable power switch 103. That is, when the at least one controllable power switch 103 is switched to the on state, the second power switch 105 is in the off state, and when the at least one controllable power switch 103 is switched to the off state, the second power switch 105 is in the on state. In the example shown in FIG1, the charging unit 102 is exemplary configured to operate as part of a power conversion device having a boost converter topology. Those skilled in the art will understand that this is merely to provide an example and is not intended to be limiting. In other embodiments, the charging unit 102 can be configured to operate as part of a power conversion device having other topologies, such as a buck converter topology, a buck-boost converter topology, a flyback converter topology, etc.

[0052] According to an exemplary embodiment, the charging unit 102 may further include M charging path control circuits 104(1), 104(2), ..., 104(M) corresponding to the M output terminals {OUT(j), j=1, 2, ..., M}. Hereinafter, the M charging path control circuits 104(1), 104(2), ..., 104(M) may be referred to or represented as {104(j), j=1, 2, ..., M}. In other words, the M charging path control circuits {104(j), j=1, 2, ..., M} match the M output terminals {OUT(j), j=1, 2, ..., M} at least in number. In one embodiment, the M charging path control circuits {104(j), j=1, 2, ..., M} may be coupled to the M output terminals {OUT(j), j=1, 2, ..., M} in a one-to-one correspondence. In other words, each of the M charging path control circuits {104(j), j=1, 2, …, M} can be coupled to a corresponding output terminal in the M output terminals {OUT(j), j=1, 2, …, M}. Or, in other words, for each j traversing from 1 to M, any one of the M charging path control circuits {104(j), j=1, 2, …, M}, such as the j-th charging path control circuit 104(j), can be coupled to a corresponding output terminal, such as the j-th output terminal OUT(j) in the M output terminals {OUT(j), j=1, 2, …, M}. Here, the integer variable M is also used to describe or represent the total number of charging path control circuits {104(j), j=1, 2, …, M} included in the charging unit 102. In other words, the total number of charging path control circuits {104(j), j=1, 2, …, M} included in the charging unit 102 should match or be the same as the total number of output terminals {OUT(j), j=1, 2, …, M} included in the charging unit 102. In the example where the charging unit 102 has 32 output terminals {OUT(j), j=1, 2, …, 32}, the charging unit 102 may include 32 charging path control circuits {104(j), j=1, 2, …, 32}, which correspond to the 32 output terminals {OUT(j), j=1, 2, …, 32} and are coupled to each of the 32 output terminals {OUT(j), j=1, 2, …, 32}.

[0053] According to an exemplary embodiment, for each j traversing from 1 to M, each of the M charging path control circuits {104(j), j=1, 2, …, M}, i.e. the j-th charging path control circuit 104(j), can be switched to an on or off state in response to the charging control PWM signal PWM_C received from the third input terminal (e.g., PWM terminal PWM1) of the charging unit 102. For each j traversing from 1 to M, each of the M charging path control circuits {104(j), j=1, 2, …, M} (i.e., the j-th charging path control circuit 104(j)) can be configured to enable the energy transfer / conduction path from the power output terminal BSTO to the corresponding output terminal (i.e., the j-th output terminal OUT(j)) among the M output terminals {OUT(j), j=1, 2, …, M} when switched to the on state, and can be further configured to disable or cut off the energy transfer / conduction path from the power output terminal BSTO to the corresponding output terminal, such as the j-th output terminal OUT(j), when switched to the off state. In other words, for each j traversing 1 to M, the j-th charging path control circuit 104(j) can be configured to enable the energy transfer / conduction path from the power output terminal BSTO to the corresponding j-th output terminal OUT(j) when switched to the on state, and can be further configured to disable or disconnect the energy transfer / conduction path from the power output terminal BSTO to the corresponding j-th output terminal OUT(j) when switched to the off state. Those skilled in the art will understand that for each j traversing 1 to M, when the j-th charging path control circuit 104(j) enables the energy transfer / conduction path from the power output terminal BSTO to the corresponding j-th output terminal OUT(j), the enabled energy transfer / conduction path is already prepared or suitable for transferring energy from the output terminal BSTO to the corresponding j-th output terminal OUT(j). In other words, for each j traversing 1 to M, once the energy transfer / conduction path from the power output terminal BSTO to the corresponding j-th output terminal OUT(j) is enabled, it does not mean that this enabled energy transfer / conduction path will immediately begin energy transfer, although this may be possible. Enabling means that this enabled energy transfer / conduction path is in a ready or suitable state for transferring energy (e.g., it is conductive).For example, in one embodiment, for each j traversing 1 to M, when the j-th charging path control circuit 104(j) is switched to the on state and enables the energy transfer / conduction path from the power output terminal BSTO to the corresponding j-th output terminal OUT(j), the charging unit 102 may wait for other conditions to be met before starting to transfer / conduct energy from the power output terminal BSTO to the corresponding j-th output terminal OUT(j) through the enabled energy transfer / conduction path. Energy transfer / conduction can be in the form of voltage, current, or charge. Conversely, for each j traversing 1 to M, when the j-th charging path control circuit 104(j) is switched to the off state to disable or disconnect the energy transfer / conduction path from the power output terminal BSTO to the corresponding j-th output terminal OUT(j), the disabled energy transfer / conduction path may no longer be suitable for transferring energy from the output terminal BSTO to the corresponding j-th output terminal OUT(j). This means that the disabled energy transfer / conduction path is in a state that prevents energy transfer (e.g., not conductive or disconnected from the power output terminal BSTO and the corresponding j-th output terminal OUT(j)).

[0054] According to an exemplary embodiment, for each j traversing from 1 to M, each charging path control circuit in the M charging path control circuits {104(j), j=1, 2, …, M}, i.e., the j-th charging path control circuit 104(j), may have a first terminal n1, a second terminal n2, and a control terminal n3. In an exemplary embodiment, multiple first terminals n1 of the charging path control circuits {104(j), j=1, 2, …, M} may be coupled together to the power output terminal BSTO. The second terminal n2 of each charging path control circuit in the M charging path control circuits {104(j), j=1, 2, …, M} (i.e., the second terminal n2 of the j-th charging path control circuit 104(j)) may be correspondingly coupled to the j-th output terminal OUT(j) in the M output terminals {OUT(j), j=1, 2, …, M}. Each control terminal n3 of the charging path control circuit {104(j), j=1, 2, …, M} can be controlled according to the pulse of the charging control PWM signal PWM_C, thereby switching the charging path control circuit {104(j), j=1, 2, …, M} on / off in a predetermined mode or sequence. This mode or sequence can be programmable by the customer or user.

[0055] According to an exemplary embodiment, for each i traversing 1 to N, the charging unit 102 can be configured to switch the charging path control circuit coupled to the i-th output terminal to on during a selected i-th on-time window Ton(i), wherein the i-th output terminal is one of a first set of N selected output terminals from M output terminals {OUT(j), j=1, 2, …, M}, and the i-th on-time window Ton(i) is associated with the charging path control circuit of the i-th output terminal OUT(i). The charging unit 102 can be configured to switch the charging path control circuit coupled to the i-th output terminal to off during periods other than the selected i-th on-time window Ton(i). The charging unit 102 can also be configured to control the selected i-th on-time window Ton(i) associated with the charging path control circuit coupled to the i-th output terminal OUT(i) according to the pulse of the charging control PWM signal PWM_C, for example, based on the charging pulse of the charging control PWM signal PWM_C.

[0056] According to an exemplary embodiment, for each i traversing 1 to N, the charging unit 102 can be configured to switch the charging path control circuit coupled to the i-th output terminal to the on state at some point during the period when the controllable power switch 103 remains on. In one example, it can be switched to the on state in response to the i-th charging pulse of the PWM signal PWM_C. That is, the time when the charging path control circuit coupled to the selected i-th output terminal OUT(i) is switched to the on state is no earlier than the time when the controllable power switch 103 is switched to the on state in response to the i-th charging pulse of the charging control PWM signal PWM_C, and no later than the time when the controllable power switch 103 is switched to the off state in response to the i-th charging pulse of the charging control PWM signal PWM_C. Those skilled in the art will understand that the moment when the controllable power switch 103 is switched off in response to the i-th charging pulse of the charging control PWM signal PWM_C is also the moment when the i-th charging time window Tcg(i) associated with the i-th output terminal OUT(i) begins, thereby switching the i-th output terminal OUT(i) on to begin charging the corresponding capacitive energy storage device CR(i) coupled to the i-th output terminal OUT(i).

[0057] For each i from 1 to N, the charging unit 102 can be further configured to switch the charging path control circuit coupled to the i-th output terminal OUT(i) off at the moment when the controllable power switch 103 is switched off in response to the (i+1)-th charging pulse of the charging control PWM signal PWM_C. The moment when the controllable power switch 103 is switched off in response to the (i+1)-th charging pulse of the charging control PWM signal PWM_C is also the moment when the s-th charging time window Tcg(s) associated with the s-th output terminal OUT(s) begins, where the s-th output terminal OUT(s) is the next selected output terminal after the i-th output terminal OUT(i), and s represents the number or index of the selected output terminal OUT(s). The output terminal OUT(s) will be switched on after the i-th output terminal OUT(i), and s can be selected from 1 to N. In one example, the next selected output terminal OUT(s) to be switched to the on state after the i-th output terminal OUT(i) can be the (i+1)-th output terminal OUT(i+1). In this embodiment, the first group (e.g., N) output terminals {OUT(i), i=1, 2, …, N} will be switched to the on state consecutively and sequentially, i.e., switched to the on state in the order from OUT(1) to OUT(N). In another example, the next output terminal OUT(s) to be switched to the on state after the i-th output terminal OUT(i) does not necessarily have to be the (i+1)-th output terminal OUT(i+1). In this embodiment, the first group (e.g., N) output terminals {OUT(i), i=1, 2, …, N} will not be switched to the on state consecutively and sequentially.

[0058] In other words, the charging unit 102 can be configured to control the i-th conduction time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i), causing it to begin at a certain moment within the time period during which the controllable power switch 103 remains in the on state. In one example, the controllable power switch 103 can be switched on in response to the i-th charging pulse of the PWM signal PWM_C. Furthermore, the charging unit 102 can also be configured to control the i-th conduction time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i), causing it to terminate no later than the moment when the controllable power switch 103 is switched off in response to the (i+1)-th charging pulse. In this way, the charging unit 102 can be configured to flexibly adjust the i-th conduction time window Ton(i) to ensure that the charging path control circuit coupled to the i-th output terminal OUT(i) is switched on before the start of the i-th charging time window Tcg(i) associated with the i-th output terminal OUT(i) to enable the energy transfer path from the power output terminal BSTO to the i-th output terminal OUT(i); and to ensure that the charging path control circuit coupled to the i-th output terminal OUT(i) is switched off before the start of the charging time window Tcg(s) associated with the next selected output terminal OUT(s) (which will be switched on after the i-th output terminal OUT(i)) to disable the energy transfer path from the power output terminal BSTO to the i-th output terminal OUT(i).

[0059] According to an exemplary embodiment, for each i traversing 1 to N, the charging unit 102 can be configured to turn on the charging path control circuit coupled to the i-th output terminal during the i-th charging time window Tcg(i) between the i-th charging pulse and the (i+1)-th charging pulse of the charging control PWM signal PWM_C, where the i-th output terminal is one of the first group (e.g., N) of selected output terminals from M output terminals {OUT(j), j=1, 2, …, M}. Those skilled in the art will understand that this is merely to provide an example and is not intended to be limiting; the charging unit 102 can be configured to keep the charging path control circuit coupled to the i-th output terminal on in various other alternative ways, as long as control of the i-th conduction time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i) as described above can be achieved. These methods cannot all be described in detail here, but do not depart from the spirit and scope of the various embodiments of this disclosure.

[0060] As shown in Figure 1, according to an exemplary embodiment, for each of the M charging path control circuits {104(j), j=1, 2, …, M} traversing from 1 to M, i.e., the j-th charging path control circuit 104(j), it may include at least one switch. Figure 2 shows a schematic diagram of a charging unit 200 according to an embodiment of the present disclosure, which can be applied to implement the charging unit 102 of the drive system 100 in Figure 1. As shown in Figure 2, at least one switch in each charging path control circuit, i.e., at least one switch in the j-th charging path control circuit 104(j), may include a controllable transistor, such as a MOSFET, DMOS, GaN FET, SiC FET, BJT, or IGBT, etc.

[0061] According to an exemplary embodiment of this application, FIG3A shows a schematic waveform diagram 300A, which depicts exemplary operating waveforms of several signals of the drive system 100 in FIG1. ​​FIG3B shows a schematic waveform diagram 300B, which depicts another exemplary embodiment of the drive system 100 in FIG1. ​​As can be seen from FIG3A and FIG3B, in this example, for each i traversing 1 to N, the selected i-th output terminal OUT(i) coupled to the corresponding i-th laser unit 101(i) in the N laser units {101(i), i=1, 2, …, N} can be switched to the on state during the i-th charging time window Tcg(i) between the i-th charging pulse and the (i+1)-th charging pulse of the charging control PWM signal PWM_C.

[0062] In the illustrative waveform diagrams shown in Figures 3A and 3B, the graph labeled 103_G represents an illustrative waveform of a control signal (also referred to simply as 103_G for simplicity and ease of understanding) used to control at least one controllable power switch 103. In some examples, at least one controllable power switch 103 includes a field-effect transistor ("FET"), and the control signal 103_G can be applied to or provided to the gate of at least one controllable power switch 103. Those skilled in the art will understand that, for the examples shown in Figures 3A and 3B, a logic high level in the waveform diagram of the control signal 103_G indicates that at least one controllable power switch 103 is switched to the on state, the inductor current iL flowing through the inductive energy storage element L may gradually increase, energy is stored in the inductive energy storage element L, and the power output terminal BSTO is charged. A logic low level in the waveform diagram of the control signal 103_G indicates that at least one controllable power switch 103 is switched to the off state, and the inductor current iL flowing through the inductive energy storage device L gradually decreases.

[0063] The control signal 103_G may be provided or generated based on the charging control PWM signal PWM_C. For example, in the exemplary embodiment of FIG3A, the control signal 103_G may be synchronized and phase-coordinated with the charging control PWM signal PWM_C. At least one controllable power switch 103 may be switched to the on state in response to each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C, and switched to the off state in response to each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C.

[0064] In other embodiments, such as the exemplary embodiment shown in FIG3B, the control signal 103_G may be out of sync with the charging control PWM signal PWM_C, i.e., out of phase. This is because, in physical implementation, the actual integrated circuit requires some time to respond. Therefore, in each period T PWMC of the charging control PWM signal PWM_C, a first delay time T d1 is introduced between each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C and the corresponding first transition edge (e.g., rising edge) of the control signal 103_G, and a second delay time T d2 is introduced between each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C and the corresponding second transition edge (e.g., falling edge) of the control signal 103_G. In this context, it can be understood that at least one controllable power switch 103 is switched to the ON state in response to each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C and after a first delay time Td1, and is switched to the OFF state in response to each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C and after a second delay time Td2. Those skilled in the art should understand that "in response to each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C and after a first delay time Td1" means "responding only at the moment when the first delay time Td1 ends, after each first transition edge (e.g., each rising edge) of the charging control PWM signal PWM_C." Similarly, "in response to each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C and after a second delay time Td2" means "responding only at the moment when the second delay time Td2 ends, after each second transition edge (e.g., each falling edge) of the charging control PWM signal PWM_C."

[0065] In another example, the control signal 103_G may not need to respond to every pulse, or in other words, to every first transition edge (e.g., every rising edge) and every second transition edge (e.g., every falling edge) of the charging control PWM signal PWM_C. Instead, for any i traversing 1 to N, the control signal 103_G can be configured to respond to the i-th charging pulse of the charging control PWM signal PWM_C. For example, for any i traversing 1 to N, the corresponding first transition edge (e.g., rising edge) of the control signal 103_G can be generated after responding to the first transition edge (e.g., every rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a first delay time Td1, and the corresponding second transition edge (e.g., falling edge) of the control signal 103_G can be generated after responding to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a second delay time Td2. This can also be understood with reference to Figure 3B, which exemplarily shows a series of consecutive pulses of the charging control PWM signal PWM_C. In this context, it can be understood that at least one controllable power switch 103 can be switched to the on state in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and after experiencing a first delay time Td1, and can be switched to the off state in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and after experiencing a second delay time Td2. Those skilled in the art should understand that "responding to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a first delay time Td1" means "responding only at the moment when the first delay time Td1 ends, after the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C". Similarly, "responding to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a second delay time Td2" means "responding only at the moment when the second delay time Td2 ends, after the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C".

[0066] In the illustrative waveform diagrams shown in Figures 3A and 3B, for each i traversing from 1 to N, the graphical representation labeled 104(i)_G represents the illustrative waveform of the control signal (also simply referred to as 104(i)_G for simplicity and ease of understanding) used to control the i-th charging path control circuit 104(i) among the M charging path control circuits {104(j), j=1, 2, …, M}. The control signal 104(i)_G can be provided to the control terminal n3 of the i-th charging path control circuit 104(i), where the i-th charging path control circuit 104(i) is coupled to the selected i-th output terminal OUT(i). Those skilled in the art will understand that, in the example shown in Figures 3A and 3B, for each i traversing 1 to N, a logic high level in the waveform of control signal 104(i)_G indicates that the i-th charging path control circuit 104(i) is switched on to enable the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i); while a logic low level in the waveform of control signal 104(i)_G indicates that the i-th charging path control circuit 104(i) is switched off to disable the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i). Control signal 104(i)_G can be provided or generated based on the charging control PWM signal PWM_C.

[0067] For example, in the exemplary embodiment of FIG3A, for each i traversing 1 to N, the control signal 104(i)_G may respond to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C, and after a predetermined turn-on delay time Tdon1, change from the first control voltage level or the first control logic level (e.g., logic low) to the second control voltage level or the second control logic level (e.g., logic high), that is, generate the first transition edge (e.g., rising edge) of the control signal 104(i)_G to switch the i-th charging path control circuit 104(i) to the on state, thereby enabling the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i). Similarly, the control signal 104(i)_G can respond to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C, and after a predetermined shutdown delay time T_doff1, change from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low), thus generating the second transition edge (e.g., falling edge) of the control signal 104(i)_G to switch the i-th charging path control circuit 104(i) to the off state, thereby disabling the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i). In this way, the i-th on-time window Ton(i) of the i-th charging path control circuit 104(i) can be adaptively adjusted and flexibly controlled according to the charging control PWM signal PWM_C. Those skilled in the art will understand that "responding to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C, and after a predetermined turn-on delay time T_don1" means "responding only at the moment when the predetermined turn-on delay time T_don1 ends, after the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C". Similarly, "responding to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C, and after a predetermined turn-off delay time T_doff1" means "responding only at the moment when the predetermined turn-off delay time T_doff1 ends, after the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C".

[0068] Referring again to Figure 3A, in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C, and after a predetermined conduction delay time Tdon1 (i.e., at the moment when the predetermined conduction delay time Tdon1 ends after the first transition edge (e.g., rising edge) of the first charging pulse), the control signal 104(1)_G for controlling the first charging path control circuit 104(1) coupled to the first output terminal OUT(1) can be changed from the first control logic potential (e.g., logic low) to the second control logic potential (e.g., logic high) to switch the first charging path control circuit 104(1) to on and enable the energy transfer path from the power output terminal BSTO to the selected first output terminal OUT(1), wherein the first output terminal OUT(1) is adapted to be coupled to the first laser unit 101(1). In response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C, and after a predetermined shutdown delay time Tdoff1 (i.e., at the moment when the predetermined shutdown delay time Tdoff1 ends after the second transition edge (e.g., falling edge) of the first charging pulse), the control signal 104(1)_G for controlling the first charging path control circuit 104(1) coupled to the first output terminal OUT(1) can transition from the second control logic potential (e.g., logic high) to the first control logic potential (e.g., logic low) to switch the first charging path control circuit 104(1) to off, thereby disabling the energy transfer path from the power output terminal BSTO to the selected first output terminal OUT(1). It will be apparent to those skilled in the art that the above description of the control signal 104(1)_G also applies to the control signals 104(2)_G, ..., 104(N)_G, and will not be repeated here.

[0069] In another embodiment, as shown in Figure 3B, for any i traversing 1 to N, in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and after a predetermined on-time Tdon2, the control signal 104(i)_G can transition from the first control voltage level or the first control logic level (e.g., logic low) to the second control voltage level or the second control logic level (e.g., logic high). In other words, this response process generates a first transition edge (e.g., rising edge) of the control signal 104(i)_G to switch the i-th charging path control circuit 104(i) to the on state and enable the energy transfer path from the power output terminal BSTO to the selected i-th output terminal OUT(i). In response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the first transition edge of the (i+1)th charging pulse, and after a predetermined shutdown delay time T_doff2, the control signal 104(i)_G can change from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low). In other words, this response process generates the second transition edge (e.g., falling edge) of the control signal 104(i)_G to switch the i-th charging path control circuit 104(i) to the off state and disable the energy transfer path from the power output terminal BSTO to the selected i-th output terminal OUT(i). Those skilled in the art will understand that "responding to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and after a predetermined turn-on delay time T_don2" means "responding only at the moment when the predetermined turn-on delay time T_don2 ends, after the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C". "Responding to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the first transition edge of the (i+1)-th charging pulse, and after a predetermined turn-off delay time T_doff2" means "responding only at the moment when the predetermined turn-off delay time T_doff2 ends, after the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, or the first transition edge of the (i+1)-th charging pulse".

[0070] Those skilled in the art will understand that, as shown in Figures 3A and 3B, the implementation of the charging unit 102 being configured to control the i-th charging path control circuit 104(i) by changing the control voltage level or control logic level of the control signal 104(i)_G in response to the charging pulse of the charging control PWM signal PWM_C is merely exemplary and not intended to be limiting. The charging unit 102 may be configured to change the control voltage level or control logic level of the control signal 104(i)_G in response to changes in the charging control PWM signal PWM_C in various other ways to provide the control signal 104(i)_G. These methods cannot be described in detail here. As long as the i-th conduction time window Ton(i) of the charging path control circuit coupled to the i-th output terminal OUT(i) can be controlled to start at a moment during the time period when the controllable power switch 103 is kept on (e.g., in response to the i-th charging pulse of the charging control PWM signal PWM_C) and end at the moment when the controllable power switch 103 is switched off in response to the (i+1)-th charging pulse of the charging control PWM signal PWM_C, such a method does not depart from the spirit and scope of this disclosure.

[0071] Figure 4 shows a schematic diagram of a charging unit 400 according to an embodiment of the present disclosure, which can be applied to implement the charging unit 102 of the drive system 100 in Figure 1. In the example of Figure 4, for each j traversing 1 to M, each of the M charging path control circuits {104(j), j=1, 2, …, M}, i.e., the j-th charging path control circuit 104(j), can include a high-side switch MH and a low-side switch ML. Each of the high-side switch MH and the low-side switch ML can include a controllable transistor, such as a MOSFET, DMOS, GaN FET, SiC FET, BJT, or IGBT, etc. For this exemplary embodiment, for each j traversing 1 to M, when the high-side switch MH of the j-th charging path control circuit 104(j) is switched to the on state, the j-th charging path control circuit 104(j) is considered to be switched to the on state, and when the high-side switch MH of the j-th charging path control circuit 104(j) is switched to the off state, the j-th charging path control circuit 104(j) is considered to be switched to the off state. Figure 5A shows a schematic waveform diagram 500A, which depicts exemplary operating waveforms of several signals of the drive system 100 in Figure 1, wherein the charging unit 102 adopts the charging unit 400 shown in Figure 4. Figure 5B shows another schematic waveform diagram 500B, which depicts exemplary operating waveforms of several signals of the drive system 100 in Figure 1, wherein the charging unit 102 also adopts the charging unit 400 shown in Figure 4. As can be seen from Figures 5A and 5B, in these examples, for each i traversing from 1 to N, the selected i-th output terminal OUT(i) correspondingly coupled to the i-th laser unit 101(i) in the N laser units {101(i), i=1, 2, …, N} can be switched to the on state during the i-th charging time window Tcg(i) between the i-th charging pulse and the (i+1)-th charging pulse of the charging control PWM signal PWM_C.

[0072] Similar to Figures 3A and 3B, in the illustrative waveform diagrams shown in Figures 5A and 5B, the graph labeled 103_G represents an illustrative waveform of a control signal (also referred to as 103_G for simplicity and ease of understanding) used to control at least one controllable power switch 103. In some examples, at least one controllable power switch 103 includes a field-effect transistor ("FET"), and the control signal 103_G can be applied to or provided to the gate of at least one controllable power switch 103. Those skilled in the art will understand that the detailed descriptions of the control signal 103_G associated with Figures 3A and 3B also apply to the examples in Figures 5A and 5B, and will not be repeated here.

[0073] In the illustrative waveform diagrams shown in Figures 5A and 5B, for each i traversing from 1 to N, the graph labeled 104(i)_GH represents the illustrative waveform of the high-side control signal (also referred to as 104(i)_GH for simplicity and ease of understanding) used to control the high-side switch MH within the i-th charging path control circuit 104(i) of the M charging path control circuits {104(j), j=1, 2, …, M}. The high-side control signal 104(i)_GH can be applied to or provided to the control terminal n3 of the high-side switch MH of the i-th charging path control circuit 104(i), wherein the i-th charging path control circuit 104(i) is coupled to the selected i-th output terminal OUT(i). Those skilled in the art will understand that, in this example, for each i traversing 1 to N, a logic high level in the waveform of the high-side control signal 104(i)_GH indicates that the high-side switch MH in the i-th charging path control circuit 104(i) is switched to the on state, thereby enabling the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i). A logic low level in the waveform of the high-side control signal 104(i)_GH indicates that the high-side switch MH in the i-th charging path control circuit 104(i) is switched to the off state, thereby disabling the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i). The high-side control signal 104(i)_GH can be provided or generated based on the charging control PWM signal PWM_C.

[0074] Those skilled in the art will understand that the detailed description above of the control signal 104(i)_G responding to the charging control PWM signal PWM_C and changing its control voltage level or control logic level, as illustrated with reference to Figures 3A and 3B, also applies to the high-side control signal 104(i)_GH in the examples of Figures 5A and 5B, and will not be repeated here. For each i traversing 1 to N, when the high-side switch MH of the i-th charging path control circuit 104(i) is switched to the on state, the i-th charging path control circuit 104(i) can be considered to be switched to the on state; when the high-side switch MH of the i-th charging path control circuit 104(i) is switched to the off state, the i-th charging path control circuit 104(i) can be considered to be switched to the off state. In this way, for each i traversing 1 to N, the on-time window Ton(i) of the i-th charging path control circuit 104(i) can be adaptively adjusted and flexibly controlled according to the charging control PWM signal PWM_C.

[0075] Referring again to the illustrative waveforms shown in Figures 5A and 5B, for each i traversing from 1 to N, the graph labeled 104(i)_GL represents the illustrative waveform of the low-side control signal (also referred to simply as 104(i)_GL for simplicity and ease of understanding) used to control the low-side switch ML of the i-th charging path control circuit 104(i) in the M charging path control circuits {104(j), j=1, 2, …, M}. This low-side control signal 104(i)_GL can be applied to or provided to the control terminal of the low-side switch ML of the i-th charging path control circuit 104(i), wherein the i-th charging path control circuit 104(i) is correspondingly coupled to the selected i-th output terminal OUT(i). Those skilled in the art will understand that, in the examples shown in Figures 5A and 5B, for each i traversing 1 to N, a logic high level in the waveform of the low-side control signal 104(i)_GL indicates that the low-side switch ML in the i-th charging path control circuit 104(i) is switched to the on state to discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. Conversely, a logic low level in the waveform of the low-side control signal 104(i)_GL indicates that the low-side switch ML in the i-th charging path control circuit 104(i) is switched to the off state to cut off the discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. The low-side control signal 104(i)_GL can be provided or generated based on the charging control PWM signal PWM_C.

[0076] For example, in the exemplary embodiment of FIG5A, for each i traversing 1 to N, the low-side control signal 104(i)_GL may respond to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C, changing from the third control voltage level or the third control logic level (e.g., logic high) to the fourth control voltage level or the fourth control logic level (e.g., logic low), i.e. generating the first transition edge (e.g., falling edge) of the low-side control signal 104(i)_GL to switch the low-side switch ML of the i-th charging path control circuit 104(i) to the off state, thereby preventing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. Furthermore, the low-side control signal 104(i)_GL can respond to the first transition edge (e.g., rising edge) of the (i+1)th charging pulse of the charging control PWM signal PWM_C, changing from the fourth control voltage level or the fourth control logic level (e.g., logic low) to the third control voltage level or the third control logic level (e.g., logic high), thereby generating the second transition edge (e.g., rising edge) of the low-side control signal 104(i)_GL to switch the low-side switch ML of the i-th charging path control circuit 104(i) to the on state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. This will help to discharge residual energy / electricity on the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400 before the i-th charging path control circuit 104(i) is switched to the on state, or before the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i) is enabled. This also ensures that the discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 is disabled during the period from the occurrence of the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C to the occurrence of the first transition edge (e.g., rising edge) of the (i+1)-th charging pulse. The predetermined turn-on delay time Tdon1 can help reduce the risk of any damage caused by the simultaneous switching of the high-side switch MH and the low-side switch ML in the i-th charging path control circuit 104(i) to the on state. The predetermined shutdown delay time T doff1 can help reduce the risk of any damage that may be caused by the high-side switch MH and the low-side switch ML in the i-th charging path control circuit 104(i) being switched on at the same time.

[0077] Referring again to Figure 5A, in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C), the low-side control signal 104(1)_GL for controlling the low-side switch ML of the first charging path control circuit 104(1) changes from the third control logic potential (e.g., logic high) to the fourth control logic potential (e.g., logic low) to close the low-side switch ML of the first charging path control circuit 104(1), thereby terminating the discharge from the first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. The first charging path control circuit 104(1) is coupled to the first output terminal OUT(1), which is adapted to be coupled to the first laser unit 101(1). In response to the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C), the low-side control signal 104(1)_GL changes from the fourth control logic potential (e.g., logic low) to the third control logic potential (e.g., logic high) to turn on the low-side switch ML in the first charging path control circuit 104(1) and allow discharge from the first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. It will be apparent to those skilled in the art that the description of the low-side control signal 104(1)_GL herein also applies to the low-side control signals 104(2)_GL, ..., 104(N)_GL, and therefore will not be repeated here.

[0078] In another example, as shown in Figure 5B, for any i traversing from 1 to N, in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C, the low-side control signal 104(i)_GL changes from the third control voltage level or the third control logic level (e.g., logic high) to the fourth control voltage level or the fourth control logic level (e.g., logic low). That is, this response process generates the first transition edge (e.g., falling edge) of the low-side control signal 104(i)_GL to turn off the low-side switch ML of the i-th charging path control circuit 104(i) and disable the discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. And, in response to the first transition edge (e.g., rising edge) of the (i+1)-th charging pulse of the charging control PWM signal PWM_C, the low-side control signal 104(i)_GL changes from the fourth control voltage level or the fourth control logic level (e.g., logic low) to the third control voltage level or the third control logic level (e.g., logic high). This response process generates a second transition edge (e.g., rising edge) of the low-side control signal 104(i)_GL to turn on the low-side switch ML of the i-th charging path control circuit 104(i) and allows discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. This helps to release the remaining energy / charge on the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400 before the i-th charging path control circuit 104(i) is turned on or before the energy transfer path from the power output terminal BSTO to the i-th output terminal OUT(i) is enabled, and at the same time ensures that the discharge path from the i-th output terminal OUT(i) to the reference ground terminal GND1 is disabled at least from the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C to the arrival of the first transition edge (e.g., rising edge) of the (i+1)-th charging pulse. The predetermined turn-on delay time T_don2 helps reduce the risk of damage caused by the simultaneous activation of the high-side switch MH and the low-side switch ML in the i-th charging path control circuit 104(i). The predetermined turn-off delay time T_doff2 helps reduce the risk of damage caused by the simultaneous activation of the high-side switch MH and the low-side switch ML in the i-th charging path control circuit 104(i).

[0079] Referring again to Figure 5B, in response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the second transition edge (e.g., falling edge)), the low-side control signal 104(1)_GL for controlling the low-side switch ML in the first charging path control circuit 104(1) changes from the third control voltage level or the third control logic potential (e.g., logic high) to the fourth control voltage level or the fourth control logic potential (e.g., logic low) to turn off the low-side switch ML of the first charging path control circuit 104(1) and disable the discharge from the selected first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. The first charging path control circuit 104(1) is coupled to the selected first output terminal OUT(1), which is adapted to be coupled to the first laser unit 101(1). In response to the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C (i.e., at the moment of the first transition edge (e.g., rising edge)), the low-side control signal 104(1)_GL transitions from the fourth control voltage level or the fourth control logic potential (e.g., logic low) to the third control voltage level or the third control logic potential (e.g., logic high) to turn on the low-side switch ML of the first charging path control circuit 104(1) and allow discharge from the selected first output terminal OUT(1) to the reference ground terminal GND1 of the charging unit 400. It will be apparent to those skilled in the art that the description of the low-side control signal 104(1)_GL herein also applies to the low-side control signals 104(2)_GL, ..., 104(N)_GL, and therefore will not be repeated here.

[0080] Those skilled in the art will understand that the detailed description above, illustrating with reference to Figures 5A and 5B, of the low-side control signal 104(i)_GL for controlling the low-side switch ML in the i-th charging path control circuit 104(i) by changing its control voltage level or control logic level in response to the charging control PWM signal PWM_C, is merely illustrative and not intended to be limiting. The charging unit 400 can be configured to change the control voltage level or control logic level of the low-side control signal 104(i)_GL in response to changes in the charging control PWM signal PWM_C in various other ways to provide the low-side control signal 104(i)_GL. These methods cannot all be described in detail here, and are permissible as long as they do not depart from the spirit and scope of this disclosure. As long as the low-side control signal 104(i)_GL can keep the low-side switch ML of the i-th charging path control circuit 104(i) closed at least during the period T off(i), from the moment the high-side switch MH of the i-th charging path control circuit 104(i) is turned on until the moment the first transition edge (e.g., rising edge) of the (i+1)-th charging pulse of the charging control PWM signal PWM_C arrives, to ensure that the discharge path from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 is disabled during the period T off(i), and the low-side control signal 104(i)_GL can turn on the low-side switch ML of the i-th charging path control circuit 104(i) at least during a predetermined time window outside the period T off(i) to release the remaining energy / charge on the i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400, such a method is in accordance with the spirit and scope of this application.

[0081] To provide another exemplary embodiment, FIG6 shows a schematic waveform diagram depicting exemplary operating waveforms of several signals of the drive system 100 in FIG1, wherein the charging unit 102 adopts the charging unit 400 shown in FIG4. The exemplary embodiment shown in FIG6 differs from the exemplary embodiments shown in FIG5A and FIG5B in that the control logic of the low-side control signal 104(i)_GL is changed. For example, in the example of FIG6, for each i traversing 1 to N, the low-side control signal 104(i)_GL may be configured to provide a predetermined pre-discharge time window Tpre in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C. During this pre-discharge time window Tpre, the low-side control signal 104(i)_GL may have a third control logic potential (e.g., logic high) to control the low-side switch ML in the i-th charging path control circuit 104(i) to be in the open state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. In one embodiment, for each i traversing 1 to N, the low-side control signal 104(i)_GL can be configured to generate a pre-discharge pulse with a pre-discharge pulse width Tpre to define the pre-discharge time window Tpre. For each i traversing 1 to N, the low-side control signal 104(i)_GL can be configured to control the low-side switch ML in the i-th charging path control circuit 104(i) to be in the off state outside the pre-discharge time window Tpre. In this way, the residual energy / charge on the selected i-th output terminal OUT(i) can be discharged before the high-side switch MH in the i-th charging path control circuit 104(i) is switched to the on state, or before the energy transfer / conduction path from the power output terminal BSTO to the selected i-th output terminal OUT(i) is enabled, which helps to improve the control accuracy of the charging unit 400. The pre-discharge time window Tpre is shorter than the predetermined conduction delay time Tdon1.

[0082] Referring again to FIG6, in one embodiment, for each i traversing 1 to N, the low-side control signal 104(i)_GL is set to provide a predetermined post-discharge time window Tpost in response to the first transition edge (e.g., rising edge) of the (i+1)th charging pulse of the charging control PWM signal PWM_C. During this post-discharge time window Tpost, the low-side control signal 104(i)_GL may have a third control logic potential (e.g., logic high) and is configured to control the low-side switch ML in the i-th charging path control circuit 104(i) to be in the on state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. In one embodiment, for each i traversing 1 to N, the low-side control signal 104(i)_GL may be configured to generate a post-discharge pulse with a predetermined post-discharge pulse width Tpost to define the predetermined post-discharge time window Tpost. For each i traversing from 1 to N, the low-side control signal 104(i)_GL can be configured to keep the low-side switch ML in the i-th charging path control circuit 104(i) in the off state outside a predetermined post-discharge time window T_post. This helps to further release the residual energy / charge on the selected i-th output terminal OUT(i) before the high-side switch MH of the i-th charging path control circuit 104(i) is switched on again, or before the energy transfer / transmission path from the power output terminal BSTO to the selected i-th output terminal OUT(i) is enabled again, which helps to improve the control accuracy of the charging unit 400. The predetermined post-discharge time window T_post can be shorter than the predetermined turn-on delay time T_don1.

[0083] In one embodiment, for each i traversing 1 to N, the low-side control signal 104(i)_GL can be configured to respond to the first transition edge (e.g., rising edge) of the i-th charging pulse and the first transition edge (e.g., rising edge) of the (i+1)-th charging pulse of the charging control PWM signal PWM_C, respectively, and provide a predetermined pre-discharge time window Tpre and a predetermined post-discharge time window Tpost, respectively. For each i traversing 1 to N, during the predetermined pre-discharge time window Tpre and the predetermined post-discharge time window Tpost, the low-side control signal 104(i)_GL can be configured to control the low-side switch ML in the i-th charging path control circuit 104(i) to be in the on state, thereby allowing discharge from the selected i-th output terminal OUT(i) to the reference ground terminal GND1 of the charging unit 400. For each i traversing from 1 to N, the low-side control signal 104(i)_GL can also be configured to control the low-side switch ML in the i-th charging path control circuit 104(i) to be in the closed state outside of the predetermined pre-discharge time window Tpre and the predetermined post-discharge time window Tpost.

[0084] Those skilled in the art should understand that embodiments of the charging unit 102 are not limited to the examples described above in conjunction with Figures 1 to 6.

[0085] According to an exemplary embodiment, the charging unit 102 may further include a logic control circuit and a drive circuit module. The logic control circuit and the drive circuit module may be jointly configured to control at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M} based on a charging control PWM signal PWM_C. In the example of FIG4, a logic control circuit 401 and a drive circuit module 402 are exemplarily shown.

[0086] According to an exemplary embodiment, the charging unit 102 may further include a fourth input terminal (e.g., a chip select terminal) OS. In one example, the fourth input terminal OS may be configured to receive a chip select signal OS_C. The charging unit 102 may be configured to perform operations to activate or deactivate at least one controllable power switch 103 and the, for example, M charging path control circuits {104(j), j=1, 2, …, M} in response to the chip select signal OS_C received at the fourth input terminal OS. In one example, when the charging unit 102 performs the operation to activate the at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M}, this means that the at least one controllable power switch 103 and the charging path control circuits {104(j), j=1, 2, …, M} are operable or capable of processing signals or performing their respective functions. When the charging unit 102 performs the operation of disabling the at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M}, it means that when the charging unit 102 performs the deactivation operation, the at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M} are inoperable or disabled. In one example, when the chip selection signal OS_C received at the fourth input terminal OS is in a first logic state (e.g., logic high) or when the chip selection signal OS_C reaches or exceeds a start-up threshold, the charging unit 102 may be configured to perform the operation of starting the at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M}. When the chip selection signal OS_C received at the fourth input terminal OS is in a second logic state (e.g., logic low) or when the chip selection signal OS_C is below the start-up threshold, the charging unit 102 may be further configured to perform the operation of disabling the at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M}. In the following text, the charging unit 102 is considered to be in an on state when it is enabled and operable, and the at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M} are activated and operable. The charging unit 102 is considered to be in an off state when it is disabled and inoperable, or when the at least one controllable power switch 103 and the M charging path control circuits {104(j), j=1, 2, …, M} are deactivated and inoperable.

[0087] According to one embodiment, the operability of the charging unit 102, the at least one controllable power switch 103, and the M charging path control circuits {104(j), j=1, 2, …, M} are related to the logic states of the enable signal EN_C and the chip select signal OS_C as shown in the table below.

[0088] Returning to Figure 1, according to an exemplary embodiment, the drive system 100 may further include N capacitive energy storage devices CR(1), CR(2), ..., CR(N) corresponding to the N laser units {101(i), i=1, 2, ..., N}. Hereinafter, the corresponding N capacitive energy storage devices CR(1), CR(2), ..., CR(N) may be referred to or represented as {CR(i), i=1, 2, ..., N}. In other words, at least in quantity, the corresponding N capacitive energy storage devices {CR(i), i=1, 2, ..., N} are matched with the N laser units {101(i), i=1, 2, ..., N}. In one example, the N capacitive energy storage devices {CR(i), i=1, 2, ..., N} may include capacitors, such as 0402 NP0 capacitors or other capacitors compatible with and meeting the application requirements. In one embodiment, the N capacitive energy storage devices {CR(i), i=1, 2, …, N} can be connected to the N laser units {101(i), i=1, 2, …, N} in a one-to-one correspondence. That is, each of the N capacitive energy storage devices {CR(i), i=1, 2, …, N} can be connected to one of the corresponding laser units (e.g., a VCSEL unit) in the N laser units {101(i), i=1, 2, …, N}. In other words, for each i traversing from 1 to N, each of the N capacitive energy storage devices {CR(i), i=1, 2, …, N}, i.e., the i-th capacitive energy storage device CR(i), can be connected to one of the corresponding laser units in the N laser units {101(i), i=1, 2, …, N}, i.e., the i-th laser unit 101(i). For each i traversing 1 to N, the first end of the i-th capacitive energy storage device CR(i) can be coupled to the first end (e.g., the anode) of the corresponding i-th laser unit 101(i), while the second end of the i-th capacitive energy storage device CR(i) can be connected to the reference ground GND of the drive system 100. Here, the integer variable N is also used to describe or represent the total number of capacitive energy storage devices {CR(i), i=1, 2, …, N} included in the drive system 100 in this disclosure. In other words, the total number of capacitive energy storage devices {CR(i), i=1, 2, …, N} that the drive system 100 may include should match or be the same as the total number of laser units {101(i), i=1, 2, …, N} that the integrated semiconductor laser 101 may include.For example, in an integrated semiconductor laser 101 comprising 28 laser units {101(i), i=1, 2, …, 28}, the drive system 100 may include 28 capacitive energy storage devices {CR(i), i=1, 2, …, 28}, each corresponding to one of the 28 laser units {101(i), i=1, 2, …, 28}, and connected to each of these 28 laser units {101(i), i=1, 2, …, 28}.

[0089] According to an exemplary embodiment, the drive system 100 may further include a discharge unit 106. The discharge unit 106 may be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND of the drive system 100. In an exemplary embodiment, the discharge unit 106 may be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND in a predetermined pattern in response to a discharge control PWM signal PWM_D, which may be customer- or user-programmable.

[0090] According to an exemplary embodiment, for each N traversing 1 to N, the discharge unit 106 can be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND during the discharge time window (i.e., the i-th discharge time window T dg(i)) after the end of the i-th charging time window T cg(i). That is, the drive system 100 or the discharge unit 106 can be configured to operate correspondingly to a first set (e.g., N) of discharge time windows, which correspond to the N laser units {101(i), i=1, 2, …, N} or the N capacitive energy storage devices {CR(i), i=1, 2, …, N}. Hereinafter, the first set (e.g., N) of discharge time windows T dg(1), T dg(2), …, T dg(N) can be referred to or represented as {T dg(i), i=1, 2, …, N}. Here, N is an integer variable not less than 1, which can be set or determined by the customer / user according to actual application requirements. For example, for each N traversing from 1 to N, the discharge unit 106 can be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND during the i-th discharge time window T dg(i) between the i-th charging time window T cg(i) and the (i+1)-th charging time window T cg(i+1). In another example, for each N traversing from 1 to N, the discharge unit 106 can be configured to release energy from the integrated semiconductor laser 101 to the reference ground terminal GND during the i-th discharge time window T dg(i) between the i-th charging time window T cg(i) and the (i+1)-th charging pulse of the charging control PWM signal PWM_C. According to an exemplary embodiment, the discharge control PWM signal PWM_D can have multiple pulses, which are configured to control the first group (e.g., N) of discharge time windows {T dg(i), i=1, 2, …, N}. In an exemplary embodiment, the first discharge time window T dg(1), the second discharge time window T dg(2), …, the i-th discharge time window T dg(i), etc., can be controlled or determined by a series of continuous pulses of the discharge control PWM signal PWM_D. However, this is only an example and is not intended to be limiting.

[0091] In one exemplary embodiment, the discharge unit 106 may have a first input terminal, such as an energy input terminal DRAIN. The first input terminal DRAIN of the discharge unit 106 may be coupled to the integrated semiconductor laser 101. In one example, the first input terminal DRAIN of the discharge unit 106 may be coupled to the second terminal of the N laser units {101(i), i=1, 2, …, N} of the integrated semiconductor laser 101.

[0092] According to an exemplary embodiment, the discharge unit 106 may further include a reference ground terminal GND2. The discharge unit 106, and all sub-circuits or sub-elements that may be included in the discharge unit 106, may be configured to use the reference ground potential on the reference ground terminal GND2 as the ground potential. In one example, the reference ground terminal GND2 of the discharge unit 106 may be connected to the reference ground terminal GND of the drive system 100.

[0093] According to an exemplary embodiment, the discharge unit 106 may further include a second input terminal, such as a PWM terminal PWM2. In one example, the second input terminal PWM2 of the discharge unit 106 may be configured to receive a discharge control PWM signal PWM_D. Although in the example of FIG1, the second input terminal PWM2 of the discharge unit 106 is shown as a single terminal, this is not intended to limit its form.

[0094] Figure 7 shows an exemplary schematic diagram of a discharge unit 700 according to an exemplary embodiment of the present disclosure. As an alternative exemplary embodiment of the present application, as shown in Figure 7, the second input terminal (e.g., PWM terminal) PWM2 of the discharge unit 106 may include a second positive input terminal PWM2+ and a second negative input terminal PWM2-. The discharge unit 700 can be used to implement the discharge unit 106 in Figure 1 as another implementation. In one example, the second positive input terminal PWM2+ of the discharge unit 106 can be configured to receive a first discharge control signal PWM_D+, and the second negative input terminal PWM2- of the discharge unit 106 can be configured to receive a second discharge control signal PWM_D-. In this case, the first discharge control signal PWM_D+ and the second discharge control signal PWM_D- define or determine the discharge control PWM signal PWM_D. For those skilled in the art, using the first discharge control signal PWM_D+ and the second discharge control signal PWM_D- allows for more flexible and simple adjustment or control of the first group (e.g., N) discharge time windows {T dg(i), i=1, 2, …, N}. For example, compared to not using the first discharge control signal PWM_D+ and the second discharge control signal PWM_D-, using the first discharge control signal PWM_D+ and the second discharge control signal PWM_D- allows each pulse of the discharge control PWM signal PWM_D to have a narrower pulse width (representing a narrower or shorter discharge time window). The narrower pulse width or narrower discharge time window of the discharge control PWM signal PWM_D is beneficial for meeting the practical needs of laser drive applications.

[0095] According to an exemplary embodiment, the discharge unit 106 may further include a discharge path switching circuit 107. The discharge path switching circuit 107 may be configured to perform an on / off switching in response to the discharge control PWM signal PWM_D or in response to the first discharge control signal PWM_D+ and the second discharge control signal PWM_D-. When the discharge path switching circuit 107 is switched to the on state, it may be configured to cause energy to be transferred from the first input terminal DRAIN of the discharge unit 106 to the reference ground terminal GND2 of the discharge unit 106, and when the discharge path switching circuit 107 is switched to the off state, it may also be configured to stop or cut off the energy transfer from the first input terminal DRAIN to the reference ground terminal GND2. The energy transfer may be in the form of voltage, current, or charge. According to an exemplary embodiment, the discharge path switching circuit 107 may be switched to the on state within a first set (e.g., N) discharge time windows, i.e., within the i-th discharge time window T dg(i). The discharge path switching circuit 107 can be switched to the off state outside the first group (e.g., N) discharge time windows {T dg(i), i=1, 2, …, N}.

[0096] According to an exemplary embodiment, the discharge path switching circuit 107 may include a controllable transistor. The controllable transistor may have a first terminal, a second terminal, and a control terminal. Its first terminal is coupled to the first input terminal DRAIN of the discharge unit 106, its second terminal is coupled to the reference ground terminal GND2 of the discharge unit 106, and its control terminal is configured to receive a control signal. In the example of FIG1, the discharge path switching circuit 107 is shown as including a metal-oxide-semiconductor field-effect transistor (MOSFET). However, this is merely an example and not intended to be limiting. In other embodiments, the discharge path switching circuit 107 may also be selected to include other types of controllable transistors, such as DMOS, GaN FET, SiC FET, bipolar transistor (BJT), insulated-gate bipolar transistor (IGBT), or any combination thereof.

[0097] According to an exemplary embodiment, the discharge unit 106 may further include a control circuit configured to control the discharge path switching circuit 107. In one embodiment, the discharge unit 106 may further include a drive circuit coupled between the control circuit and the discharge path switching circuit 107. The drive circuit is configured to drive the control terminal of the discharge path switching circuit 107 according to the output signal of the control circuit. For example, the drive circuit may be configured to provide a control signal to the control terminal of the controllable transistor in the discharge path switching circuit 107. An exemplary illustration of the control circuit 701 and the drive circuit 702 is shown in the example of FIG. 7.

[0098] According to an exemplary embodiment, the discharge unit 106 may further include a third input terminal, such as the discharge unit power supply terminal VCC. The discharge unit power supply terminal VCC may be configured to receive a supply voltage suitable for providing operating power to the discharge unit 106. For example, in the example of FIG. 7, a supply voltage of 3.3V is provided to the discharge unit power supply terminal VCC. However, this is merely an example and not an intentional limitation.

[0099] According to an exemplary embodiment, the discharge unit 106 may further include a fault reporting terminal FLT2, which is configured to report any fault condition, such as undervoltage (VCC UVLO), overtemperature (OTSD), etc. As shown in FIG7, the discharge unit 106 may further include protection circuitry configured to provide protection against undervoltage (VCC UVLO), overtemperature (OTSD), and / or other faults. If the application does not require the discharge unit 106 to provide fault reporting functionality, the fault reporting terminal FLT2 can be omitted.

[0100] According to an exemplary embodiment, the charging unit 102 can be integrated on an integrated circuit (“IC”) die or wafer and can be encapsulated in a package 800 as shown in FIG. 8. In one example, the IC die or wafer in which the charging unit 102 is integrated may include a flip-chip die or wafer, and accordingly, the package 800 may have a flip-chip package form. The M output terminals (e.g., OUT(j), j=1, 2, …, M) of the charging unit 102 are arranged in an output terminal array 801 with X rows and Y columns in the form of corresponding M conductive pads. The output terminal array 801 is disposed on the active surface of the package 800. Here, the variables X and Y are integers not less than 1, representing the total number of rows and the total number of columns of the output terminal array 801, respectively, and satisfying the relationship X*Y=M. For example, in the example of FIG8, package 800 is shown to include a charging unit 102 having 32 output terminals {OUT(j), j=1, 2, …, 32}, which are arranged in a 4x8 output terminal array 801. That is, in this particular example, M=32, X=4, Y=8. In the example of FIG8, other terminals of charging unit 102, such as the first input terminal (e.g., power terminal) IN1, the second input terminal (e.g., enable terminal) EN, the third input terminal (e.g., PWM terminal) PWM1, the reference ground terminal GND1, the fourth input terminal (e.g., select terminal) OS, the indicator terminal (e.g., fault indicator terminal) FLT1, the switch terminal SW, the power output terminal BSTO, etc., may be arranged in one or more other terminal arrays, which are also arranged on the active surface of package 800. According to an exemplary embodiment, one or more other terminal arrays may have multiple conductive pads. According to an exemplary embodiment, one or more other terminal arrays may be disposed on one or more sides of the output terminal array 801. In the example of Figure 8, it is exemplarily illustrated that the other terminals of the charging unit 102 are arranged in an additional terminal array 802 disposed at the bottom of the output terminal array 801. It will be understood by those skilled in the art that this is merely an example and not intended to be limiting.

[0101] According to an exemplary embodiment, the discharge unit 106 can be integrated on an integrated circuit (“IC”) die or wafer and can be encapsulated in a package 900 as shown in FIG. 9. In one example, the IC die or wafer in which the discharge unit 106 is integrated may include a flip-chip die or wafer, and accordingly, the package 900 may have a flip-chip package form. The first input terminal (e.g., energy input terminal) DRAIN, the reference ground terminal GND2, the second input terminal (e.g., PWM terminal) PWM2, the third input terminal (e.g., discharge unit power terminal) VCC, and the fault reporting terminal FLT2 (if any) of the discharge unit 106 can be implemented in the form of a plurality of corresponding conductive pads and can be arranged on the active surface of the package 900. In one embodiment, for the reference ground terminal GND2, at least two conductive pads can be formed and symmetrically arranged on both sides of the center line (indicated by dashed lines in FIG. 9) of the discharge unit 106 encapsulated in the package 900 to enhance its energy release capability.

[0102] Figure 10 illustrates a package 950 containing a discharge unit 700, which is integrated on an integrated circuit die / wafer according to one embodiment of the present disclosure. The extensive description of the discharge unit 106 in package 900 with reference to Figure 9 is applicable to the discharge unit 700 in package 950, as, as previously stated, the discharge unit 700 can be considered as one implementation of the discharge unit 106. In the example of Figure 10, the second input terminal PWM is exemplified as a second positive input terminal PWM2+ and a second negative input terminal PWM2-, while the fault reporting terminal FLT2 can be omitted on the active side of package 950.

[0103] Figure 11 shows a schematic diagram of a drive system 150 according to an embodiment of the present disclosure. The drive system 150 differs from the drive system 100 in that its charging unit 102 may further include a set of (e.g., represented by an integer variable K) selection terminals SEL(0), SEL(1), ..., SEL(K-1). Hereinafter, the set of (e.g., K) selection terminals SEL(0), SEL(1), ..., SEL(K-1) may be referred to or represented as K selection terminals {SEL(q), q=0, 1, ..., K-1}. Here, K is an integer variable representing the total number of selection terminals {SEL(q), q=0, 1, ..., K-1} included in the charging unit 102. Wherein, q is an integer variable iterating from 0 to K-1. The K selection terminals {SEL(q), q=0, 1, …, K-1} can be configured to control or program the M output terminals {OUT(j), j=1, 2, …, M} to perform on / off switching in a predetermined sequence or predetermined mode. In one example, the K selection terminals {SEL(q), q=0, 1, …, K-1} can be configured to control or program the M charging path control circuits {104(j), j=1, 2, …, M} of the charging unit 102 to perform on / off switching in a predetermined sequence or predetermined mode. As described above and in the examples of Figures 3A, 3B, 5A, 5B and 6, in these examples, the M output terminals {OUT(j), j=1, 2, …, M} can be switched to the on state sequentially (i.e., in order from OUT(1) to OUT(M)) according to multiple successive charging pulses of the charging control PWM signal PWM_C. Unlike these examples, in the example shown in Figure 11, the predetermined mode or sequence of switching on / off of the i-th output terminal OUT(i) can be controlled or programmed by the K selection terminals {SEL(q), q=0, 1, …, K-1}. In one embodiment, in order for the predetermined mode or sequence of switching on / off of the M output terminals {OUT(j), j=1, 2, …, M} to be programmable / controllable, the integer variable K must satisfy 2K≥M.

[0104] Figure 12 illustrates an exemplary embodiment of the charging unit 250, which can serve as an alternative embodiment to the charging unit 102 in Figure 11. Compared to the charging unit 200 shown in Figure 2, the charging unit 250 of Figure 12 further includes K selection terminals {SEL(q), q=0, 1, …, K-1}. Those skilled in the art will understand that much of the related description of the embodiments of Figures 1 and 2 is applicable to the embodiments of Figures 11 and 12, differing only in the predetermined mode or sequence of the on / off switching of the M output terminals {OUT(j), j=1, 2, …, M}. In the embodiments of Figures 11 and 12, the predetermined mode or sequence of the on / off switching of the M output terminals {OUT(j), j=1, 2, …, M} can be controlled / programmed via the K selection terminals {SEL(q), q=0, 1, …, K-1}.

[0105] According to an exemplary embodiment, the K selection terminals {SEL(q), q=0, 1, …, K-1} are adapted to receive corresponding plurality (e.g., K) selection control signals {SEL_C(q), q=0, 1, …, K-1}. In one embodiment, these plurality (e.g., K) selection control signals {SEL_C(q), q=0, 1, …, K-1} can be implemented as a K-bit command signal. For example, for each selection control signal, the q-th selection control signal SEL_C(q) corresponds to the q-th bit in the K-bit command signal. In this way, the customer or user can programmatically control the activation operation of one of the M output terminals {OUT(j), j=1, 2, …, M} or one of the M charging path control circuits {104(j), j=1, 2, …, M} of the charging unit 102 at the start of each charging pulse of the charging control PWM signal PWM_C. For example, the K selection control signals {SEL_C(q), q=0, 1, …, K-1} may include logic signals. At the beginning of each charging pulse of the charging control PWM signal PWM_C, the charging unit 102 can check the logic state of the K selection control signals {SEL_C(q), q=0, 1, …, K-1} to determine whether one of the M output terminals {OUT(j), j=1, 2, …, M} or one of the M charging path control circuits {104(j), j=1, 2, …, M} should be turned on. If the s-th output terminal OUT(s) of the M output terminals {OUT(j), j=1, 2, …, M} or the s-th charging path control circuit 104(s) of the M charging path control circuits {104(j), j=1, 2, …, M} should be turned on, where s is an integer variable, then this integer variable s can be represented by the following equation (1). In equation (1), for each q traversing from 0 to (K-1), if the selection control signal SEL_C(q) is at logic low at the beginning of each charging pulse of the charging control PWM signal PWM_C, then SEL_C(q) = 0; if the selection control signal SEL_C(q) is at logic high at the beginning of each charging pulse of the charging control PWM signal PWM_C, then SEL_C(q) = 1.In the following text, for ease of description and understanding, the s-th output terminal OUT(s) of the M output terminals {OUT(j), j=1, 2, …, M} programmed to be turned on according to equation (1) is referred to as the programmed s-th output terminal OUT(s), and the s-th charging path control circuit 104(s) of the M charging path control circuits {104(j), j=1, 2, …, M} associated with the s-th output terminal OUT(s) is referred to as the programmed s-th charging path control circuit 104(s).

[0106] Equation (1)

[0107] For example, Figure 13 shows a schematic waveform diagram 350, which illustrates exemplary operating waveforms of several signals of the drive system 150 in Figure 11. In this example, the charging unit 102 includes the charging unit 250 shown in Figure 12, and by way of example has 5 selection terminals {SEL(q), q=0, 1, …, 4}, that is, K=5. Those skilled in the art will understand that the waveforms exemplarily described in Figures 3A and 3B can be applied to the waveform shown in Figure 13, the difference being that in the example of Figure 13, the predetermined mode or sequence of the on / off switching of each of the M output terminals {OUT(j), j=1, 2, …, M} can be controlled / programmed through the K selection terminals {SEL(q), q=0, 1, …, K-1}, while in the example shown in Figure 13, K=5. In other words, for each j traversing from 1 to M, the position or order of the j-th charging time window Tcg(j) where the j-th output terminal OUT(j) is switched to the on state can be controlled / programmed by the K selection terminals {SEL(q), q=0, 1, …, K-1}. Therefore, in some embodiments, the first group of output terminals {OUT(i), i=1, 2, …, M} selected from the M output terminals {OUT(j), j=1, 2, …, M} drives the first group (e.g., N laser units) {101(i), i=1, 2, …, N} respectively. For any i traversing from 1 to N, the i-th charging time window Tcg(i) where the i-th output terminal OUT(i) is on does not necessarily have to be located after the i-th charging pulse of the charging control PWM signal PWM_C, as in the examples shown in Figures 3A and 3B. Conversely, the order or position of the i-th charging time window Tcg(i), i.e., the time window in which the selected i-th output terminal OUT(i) is turned on, can be controlled / programmed through multiple (e.g., K) selection terminals {SEL(q), q=0, 1, …, K-1}. In the example shown in Figure 13, K=5.

[0108] As shown in Figure 13, in this example, during the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {1, 0, 0, 0, 0}, which means s = 1 + 1*2 0 + 0*2 1 + 0*2 2 + 0*2 3 + 0*2 4 = 2. Therefore, in this example, based on the first charging pulse of the charging control PWM signal PWM_C, the second output terminal OUT(2) of the M output terminals {OUT(j), j=1, 2, …, M} or the second charging path control circuit 104(2) of the M charging path control circuits {104(j), j=1, 2, …, M} will be turned on by the program design. That is, in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don1 (similar to the description in FIG3A), or in response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don2 (similar to the description in FIG3B), the control signal 104(2)_G for controlling the second charging path control circuit 104(2) in the M charging path control circuits {104(j), j=1, 2, …, M} can transition from the first control voltage level or the first control logic level (e.g., logic low) to the second control voltage level or the second control logic level (e.g., logic high) to turn on the second charging path control circuit 104(2) and enable the energy transfer path from the power output terminal BSTO to the second output terminal OUT(2). Furthermore, in response to the second transition edge (e.g., falling edge) of the first charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined shutdown delay time T doff1 (similar to the description in FIG3A), or in response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the second charging pulse, and experiencing a predetermined shutdown delay time T doff2 (similar to the description in FIG3B), the control signal 104(2)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to shut down the second charging path control circuit 104(2) and disable the energy transfer path from the power output terminal BSTO to the second output terminal OUT(2).In this way, by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}, the second output terminal OUT(2) in the example can be turned on during the second charging time window Tcg(2) after the first charging pulse of the charging control PWM signal PWM_C.

[0109] Similarly, in the example of Figure 13, during the second charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {0, 0, 0, 0, 0}, which means s = 1 + 0*2 0 + 0*2 1 + 0*2 2 + 0*2 3 + 0*2 4 = 1. Therefore, in this example, based on the second charging pulse of the charging control PWM signal PWM_C, the first output terminal OUT(1) of the M output terminals {OUT(j), j = 1, 2, …, M} or the first charging path control circuit 104(1) of the M charging path control circuits {104(j), j = 1, 2, …, M} will be turned on by the program design. That is, in response to the first transition edge (e.g., rising edge) of the second charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don1 (similar to the description in FIG3A), or in response to the second transition edge (e.g., falling edge) of the second charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don2 (similar to the description in FIG3B), the control signal 104(1)_G for controlling the first charging path control circuit 104(1) in the M charging path control circuits {104(j), j=1, 2, …, M} can transition from the first control voltage level or the first control logic level (e.g., logic low) to the second control voltage level or the second control logic level (e.g., logic high) to turn on the first charging path control circuit 104(1) and enable the energy transfer path from the power output terminal BSTO to the first output terminal OUT(1). Furthermore, in response to the second transition edge (e.g., falling edge) of the second charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined shutdown delay time T doff1 (similar to the description in FIG3A), or in response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the third charging pulse, and experiencing a predetermined shutdown delay time T doff2 (similar to the description in FIG3B), the control signal 104(1)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to shut down the first charging path control circuit 104(1) and disable the energy transfer path from the power output terminal BSTO to the first output terminal OUT(1).In this way, by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}, the first output terminal OUT(1) in the example can be turned on during the first charging time window Tcg(1) after the second charging pulse of the charging control PWM signal PWM_C.

[0110] During the twelfth charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {1, 1, 1, 0, 0}, which means s = 1 + 1*2 0 + 1*2 1 + 1*2 2 + 0*2 3 + 0*2 4 = 8. Therefore, in this example, based on the twelfth charging pulse of the charging control PWM signal PWM_C, the eighth output terminal OUT(8) of the M output terminals {OUT(j), j=1, 2, …, M} or the eighth charging path control circuit 104(8) of the M charging path control circuits {104(j), j=1, 2, …, M} will be turned on by the program design. That is, in response to the first transition edge (e.g., rising edge) of the twelfth charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don1 (similar to the description in FIG3A), or in response to the second transition edge (e.g., falling edge) of the twelfth charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don2 (similar to the description in FIG3B), the control signal 104(8)_G for controlling the eighth charging path control circuit 104(8) in the M charging path control circuits {104(j), j=1, 2, …, M} can transition from a first control voltage level or a first control logic level (e.g., logic low) to a second control voltage level or a second control logic level (e.g., logic high) to turn on the eighth charging path control circuit 104(8) and enable the energy transfer path from the power output terminal BSTO to the eighth output terminal OUT(8). Furthermore, in response to the second transition edge (e.g., falling edge) of the twelfth charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined shutdown delay time T doff1 (similar to the description in FIG3A), or in response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the thirteenth charging pulse and experiencing a predetermined shutdown delay time T doff2 (similar to the description in FIG3B), the control signal 104(8)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to shut down the eighth charging path control circuit 104(8) and disable the energy transfer path from the power output terminal BSTO to the eighth output terminal OUT(8).In this way, by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}, the eighth output terminal OUT(8) in the example can be turned on during the eighth charging time window Tcg(8) after the twelfth charging pulse of the charging control PWM signal PWM_C.

[0111] Those skilled in the art will understand that, with respect to the examples of Figures 12 and 13, the above description applies to a more general case, namely, the s-th output terminal OUT(s) of the M output terminals {OUT(j), j=1, 2, …, M} or the s-th charging path control circuit 104(s) of the M charging path control circuits {104(j), j=1, 2, …, M} associated with the s-th output terminal OUT(s) can be programmed to be turned on during the i-th charging pulse of the charging control PWM signal PWM_C according to Equation (1). For example, in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don1 (similar to the description in FIG3A), or in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined turn-on delay time T_don2 (similar to the description in FIG3B), the control signal 104(s)_G for controlling the s-th charging path control circuit 104(s) in the M charging path control circuits {104(j), j=1, 2, …, M} can transition from a first control voltage level or a first control logic level (e.g., logic low) to a second control voltage level or a second control logic level (e.g., logic high) to turn on the s-th charging path control circuit 104(s) and enable the energy transfer path from the power output terminal BSTO to the s-th output terminal OUT(s). Furthermore, in response to the second transition edge (e.g., falling edge) of the i-th charging pulse of the charging control PWM signal PWM_C and experiencing a predetermined shutdown delay time T doff1 (similar to the description in FIG3A), or in response to the first transition edge (e.g., rising edge) of the next charging pulse of the charging control PWM signal PWM_C, i.e., the (i+1)-th charging pulse and experiencing a predetermined shutdown delay time T doff2 (similar to the description in FIG3B), the control signal 104(s)_G transitions from the second control voltage level or the second control logic level (e.g., logic high) to the first control voltage level or the first control logic level (e.g., logic low) to shut down the s-th charging path control circuit 104(s) and disable the energy transfer path from the power output terminal BSTO to the s-th output terminal OUT(s). In this way, for each i traversing from 1 to N, the s-th output terminal OUT(s) can be turned on during the s-th charging time window Tcg(s) after the i-th charging pulse following the charging control PWM signal PWM_C by controlling or programming the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)}.

[0112] Those skilled in the art will understand that the detailed description above, illustrating with reference to Figures 12 and 13, of the control signal 104(s)_G in the charging unit 250 for controlling the s-th charging path control circuit 104(s) in response to the charging control PWM signal PWM_C changing its control voltage level or control logic level, is merely illustrative and not intended to be limiting. The charging unit 250 can be configured to change the control voltage level or control logic level of the control signal 104(s)_G in response to changes in the charging control PWM signal PWM_C in various other ways to provide the control signal 104(s)_G. These methods cannot all be described in detail here, and are permissible as long as they do not depart from the spirit and scope of this disclosure. As long as the s-th conduction time window Ton(s) of the s-th charging path control circuit 104(s) coupled to the s-th output terminal OUT(s) (which is programmed to be turned on when the i-th charging pulse of the charging control PWM signal PWM_C is turned on) can be controlled to start during the period when the controllable power switch 103 remains on (e.g., turned on in response to the i-th charging pulse of the charging control PWM signal PWM_C) and end no later than the moment when the controllable power switch 103 is turned off in response to the (i+1)-th charging pulse of the charging control PWM signal PWM_C, such a method is in accordance with the spirit and scope of this application. In this way, the charging unit 250 can be configured to flexibly adjust the s-th on-time window Ton(s) to ensure that the charging path control circuit 104(s) coupled to the programmed s-th output terminal OUT(s) is turned on no later than the start of the s-th charging time window Tcg(s) associated with the s-th output terminal OUT(s), thereby enabling the energy transfer path from the power output terminal BSTO to the programmed s-th output terminal OUT(s), and the charging path control circuit 104(s) coupled to the programmed s-th output terminal OUT(s) is turned off no later than the start of the s-th charging time window Tcg(s) associated with the next programmed s-th output terminal OUT(s), thereby disabling the energy transfer path from the power output terminal BSTO to the programmed s-th output terminal OUT(s), wherein the next programmed s-th output terminal OUT(s) is turned on after the current programmed s-th output terminal OUT(s).

[0113] Figure 14 shows an exemplary schematic diagram of a charging unit 450 according to another exemplary embodiment of the present disclosure. This charging unit 450 can be used as an alternative embodiment to the charging unit 102 in Figure 11. Compared to the charging unit 400 shown in Figure 4, the charging unit 450 of Figure 14 further includes the K selection terminals {SEL(q), q=0, 1, …, K-1}. Those skilled in the art will understand that the embodiments shown in Figures 1 and 4 and their corresponding descriptions can be applied to the embodiments in Figures 11 and 14, the difference being that in the embodiments of Figures 11 and 14, the predetermined mode or sequence of the on / off switching of each of the M output terminals {OUT(j), j=1, 2, …, M} can be controlled / programmed through the K selection terminals {SEL(q), q=0, 1, …, K-1}.

[0114] Figure 15 shows a schematic waveform diagram 550, which illustrates exemplary operating waveforms of several signals of the drive system 150 in Figure 11. In this example, the charging unit 102 includes the charging unit 450 shown in Figure 14, and by way of example has five selection terminals {SEL(q), q=0, 1, …, 4}, that is, K=5. Those skilled in the art will understand that the waveforms exemplarily described in Figures 5A and 5B can be applied to the example shown in Figure 15, the difference being that in the example of Figure 15, the predetermined mode or predetermined sequence of the on / off switching of each of the M output terminals {OUT(j), j=1, 2, …, M} can be controlled / programmed through the K selection terminals {SEL(q), q=0, 1, …, K-1}, where K=5 in the example shown in Figure 15. For each j traversing from 1 to M, the position or order of the j-th charging time window Tcg(j) when the j-th output terminal OUT(j) is switched to the on state can be controlled / programmed by the K selection terminals {SEL(q), q=0, 1, …, K-1}. Therefore, in the exemplary embodiment, when a set (e.g., N) of output terminals are selected from the M output terminals {OUT(j), j=1, 2, …, M} to drive the N laser units {101(i), i=1, 2, …, N}, for each i traversing from 1 to N, the i-th charging time window Tcg(i) when the i-th output terminal OUT(i) is switched to the on state is no longer necessarily located after the i-th charging pulse of the charging control PWM signal PWM_C, as shown in Figures 5A and 5B. Conversely, the position or order of the i-th charging time window Tcg(i) to which the i-th output terminal OUT(i) is switched to the on state can be controlled / programmed by the K selection terminals {SEL(q), q=0, 1, …, K-1}, where K=5 in the example shown in Figure 15.

[0115] Similar to the waveform shown in the example in Figure 13, it can be seen from the example in Figure 15 that during the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {1, 0, 0, 0, 0}, which means that s = 1 + 1*2 0 + 0*2 1 + 0*2 2 + 0*2 3 + 0*2 4 = 2. Therefore, in this example, the second output terminal OUT(2) of the M output terminals {OUT(j), j=1, 2, …, M} or the second charging path control circuit 104(2) of the M charging path control circuits {104(j), j=1, 2, …, M} is turned on during the first charging pulse of the charging control PWM signal PWM_C. During the second charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} may be {0, 0, 0, 0, 0}, which means s=1+0*2 0+0*2 1+0*2 2+0*2 3+0*2 4=1. Therefore, in this example, the program design enables the first output terminal OUT(1) of the M output terminals {OUT(j), j=1, 2, …, M} or the first charging path control circuit 104(1) of the M charging path control circuits {104(j), j=1, 2, …, M} to be turned on during the second charging pulse of the charging control PWM signal PWM_C. During the twelfth charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} may be {1, 1, 1, 0, 0}, which means s=1+1*2 0+1*2 1+1*2 2+0*2 3+0*2 4=8.Therefore, in this example, the program is designed so that the eighth output terminal OUT(8) of the M output terminals {OUT(j), j=1, 2, …, M} or the eighth charging path control circuit 104(8) of the M charging path control circuits {104(j), j=1, 2, …, M} is turned on during the twelfth charging pulse of the charging control PWM signal PWM_C.

[0116] More specifically, in the examples of Figures 14 and 15, the on / off switching of the programmable output terminal OUT(s) via multiple (e.g., K) selection terminals {SEL(q), q=0, 1, …, K-1} can be achieved by controlling the high-side switch MH and the low-side switch ML in the charging path control circuit 104(s) coupled to or associated with the programmable output terminal OUT(s). Those skilled in the art will understand that the detailed description of the changes in the control voltage level or control logic level of the control signal 104(s)_G generated in response to the charging control PWM signal PWM_C, as illustrated in the examples of Figures 12 and 13, also applies to the high-side control signal 104(s)_GH in the examples of Figures 14 and 15, and will not be repeated here for the sake of brevity.

[0117] Regarding the low-side control signal 104(s)_GL, it is understood that the description of the low-side control signal 104(i)_GL of the low-side switch ML in the i-th charging path control circuit 104(i) with reference to the examples of FIG5A and FIG5B applies to the low-side control signal 104(s)_GL of the low-side switch ML of the programmed charging path control circuit 104(s) in the examples of FIG14 and FIG15. In other words, the low-side control signal 104(s)_GL can keep the low-side switch ML of the programmed s-th charging path control circuit 104(s) closed for at least during the period T off(i), from the moment when the high-side switch MH of the s-th charging path control circuit 104(s) is turned on based on the i-th charging pulse of the charging control PWM signal PWM_C, to the moment when the first transition edge (e.g., rising edge) of the (i+1)-th charging pulse of the charging control PWM signal PWM_C arrives. This ensures that the discharge path from the programmed s-th output terminal OUT(s) to the reference ground terminal GND1 is disabled during the period T off(i). Furthermore, the low-side control signal 104(s)_GL can turn on the low-side switch ML of the s-th charging path control circuit 104(s) for at least a predetermined time window outside of the T off(s) period to release the remaining energy / charge on the programmed s-th output terminal OUT(s) to the reference ground terminal GND1 of the charging unit 450.

[0118] Figure 16 shows a schematic waveform diagram 650, depicting exemplary operating waveforms of several signals of the drive system 150 in Figure 11. In this example, the charging unit 102 can still be considered to include the charging unit 450 shown in Figure 14, and by way of example has five selection terminals {SEL(q), q=0, 1, …, 4}, that is, K=5. The exemplary embodiment shown in Figure 16 differs from the exemplary embodiment shown in Figure 15 in that the control logic of the low-side control signal 104(s)_GL has changed, while the control logic of the high-side control signal 104(s)_GH is the same as described in Figure 15. Those skilled in the art will understand that the control logic of the low-side control signal 104(s)_GL in the example of Figure 16 is similar to that in the example described in Figure 6. In other words, according to the example of Figure 16, in any charging pulse of the charging control PWM signal PWM_C (e.g., the i-th charging pulse, ranging from 1 to M), the s-th output terminal OUT(s) of the M output terminals {OUT(j), j=1,2,...,M} or the s-th charging path control circuit 104(s) associated with the s-th output terminal OUT(s) of the M charging path control circuits {104(j), j=1,2,...,M} can be programmed to be turned on according to Equation (1). In one embodiment, the low-side control signal 104(s)_GL provides a predetermined pre-discharge time window Tpre in response to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C. During the pre-discharge time window Tpre, the low-side control signal 104(s)_GL may have a third control logic potential (e.g., logic high) to control the low-side switch ML in the s-th charging path control circuit 104(s) to be in the open state, thereby allowing discharge from the programmed s-th output terminal OUT(s) to the reference ground terminal GND1 of the charging unit 450, and the low-side control signal 104(s)_GL may be configured to control the low-side switch ML in the s-th charging path control circuit 104(s) to be in the closed state outside the pre-discharge time window Tpre.In another embodiment, in response to the first transition edge (e.g., rising edge) of the next charging pulse (i.e., the (i+1)th charging pulse after the i-th charging pulse of the charging control PWM signal PWM_C), the low-side control signal 104(s)_GL may be configured to generate a predetermined post-discharge time window T post during which the low-side control signal 104(2)_GL may have a third control logic potential (e.g., logic high) and may be adapted to control the low-side switch ML in the programmed s-th charging path control circuit 104(s) to be in the on state, and cause energy to be discharged from the programmed s-th output terminal OUT(s) to the reference ground terminal GND1 of the charging unit 450, and the low-side control signal 104(s)_GL may be adapted to control the low-side switch ML in the programmed s-th charging path control circuit 104(s) to be in the off state outside the predetermined post-discharge time window T post. In another embodiment, the low-side control signal 104(s)_GL may be adapted to respond to the first transition edge (e.g., rising edge) of the i-th charging pulse of the charging control PWM signal PWM_C and the first transition edge (e.g., rising edge) of the (i+1)-th charging pulse of the charging control PWM signal PWM_C, respectively, providing a predetermined pre-discharge time window Tpre and a predetermined post-discharge time window Tpost.

[0119] For example, as can be seen from the exemplary and illustrative waveforms shown in Figure 16, during the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} are {1, 0, 0, 0, 0}, which means that s = 1 + 1*2 0 + 0*2 1 + 0*2 2 + 0*2 3 + 0*2 4 = 2, so that the second output terminal OUT(2) or the second charging path control circuit 104(2) is switched to the on state, and the control logic of the high-side control signal 104(2)_GH of the high-side switch MH in the second charging path control circuit 104(2) can be the same as that described in the example in Figure 15. For the low-side control signal 104(2)_GL, in response to the first transition edge (e.g., rising edge) of the first charging pulse of the charging control PWM signal PWM_C, the low-side control signal 104(2)_GL may be adapted to provide a predetermined pre-discharge time window Tpre. Within this time window, the low-side control signal 104(2)_GL may have a third control logic potential (e.g., logic high) to control the low-side switch ML in the second charging path control circuit 104(2) to turn on, and is adapted to cause energy to discharge from the second output terminal OUT(2) to the reference ground terminal GND1 of the charging unit 450. The low-side control signal 104(2)_GL may be further adapted to provide a predetermined post-discharge time window T post at the first transition edge (e.g., rising edge) of the next charging pulse (i.e., the second charging pulse here) following the first charging pulse of the charging control PWM signal PWM_C, in order to control the low-side switch ML in the second charging path control circuit 104(2) to turn on and cause energy to discharge from the second output terminal OUT(2) to the reference ground terminal GND1 of the charging unit 450 during the post-discharge time window T post. A similar explanation applies to the low-side control signal 104(1)_GL. In the example shown, during the second charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} are {0,0,0,0,0}, which means that s=1+0*2 0+0*2 1+0*2 2+0*2 3+0*2 4=1, so that the first output terminal OUT(1) or the first charging path control circuit 104(1) is switched to the on state.A similar explanation applies to the low-side control signal 104(8)_GL. In the example shown, during the 12th charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} are {1, 1, 1, 0, 0}, which means s = 1 + 1*2 0 + 1*2 1 + 1*2 2 + 0*2 3 + 0*2 4 = 8, thus controlling or programming the eighth output terminal OUT(8) or the eighth charging path control circuit 104(8) to be switched to the on state.

[0120] According to another embodiment of this disclosure, the charging unit 102 can be integrated on an integrated circuit (“IC”) die or wafer and can be encapsulated in a package 850 as shown in FIG. 17. The package 850 shown in FIG. 17 differs from the package 800 shown in FIG. 8 in that the package 850 may further include the K select terminals {SEL(q), q=0, 1, …, K-1}. In one example, the K select terminals {SEL(q), q=0, 1, …, K-1} are arranged in a select terminal array 851 of the package 850 in the form of corresponding K conductive pads. This select terminal array 851 is arranged on the active surface of the package 850. In the example of FIG. 17, the charging unit 102 encapsulated in the package 850 may include the charging unit 250 shown in FIG. 12 or the charging unit 450 shown in FIG. 14. Figure 17 illustrates 32 output terminals {OUT(j), j=1, 2, …, 32}, arranged in a 4x8 output terminal array 801 (i.e., M=32, X=4 and Y=8). Therefore, in this example, to ensure that the switching mode or sequence of the on / off state of each of the 32 output terminals {OUT(j), j=1, 2, …, 32} is programmable / controllable, the value of K can be determined to be 5 based on 2K≥M=32.

[0121] Figure 18 is an application board-level layout diagram corresponding to the drive system 100 or 150 of Figure 1 or Figure 11 according to an embodiment of the present disclosure. According to an exemplary embodiment of the present disclosure, Figures 18A to 18F show application board-level layout diagrams corresponding to the drive system 100 in Figure 1 or the drive system 150 in Figure 11. In one embodiment, the drive system 100 or 150 is placed on a multilayer circuit board, such as a printed circuit board (PCB) 1800. The multilayer circuit board level 1800 for the drive system 100 or 150 will now be described with reference to Figures 18 and 18A to 18F. The multilayer circuit board 1800 may include multiple (e.g., represented by integer variables H) board levels 180(1), 180(2), ..., 180(H). Subsequently, the multiple (e.g., H) board levels 180(1), 180(2), ..., 180(H) may be referred to as or represented by {180(h), h=1,2,...,H}. Here, H is an integer variable not less than 1, representing the total number of board levels 180(1), 180(2), ..., 180(H) that the multi-layer circuit board level 1800 may include. In practical applications, it can be set or determined by the customer / user according to the actual application requirements. In one embodiment, multiple (e.g., H) circuit board levels {180(h), h=1, 2, ...,H} can be arranged one after another in the order from 180(1) to 180(H). That is, the first board level 180(1) can be the top layer of the multi-layer circuit board level 1800, and the Hth board level 180(H) can be the bottom layer of the multi-layer circuit board level 1800. The remaining board levels 180(2) to 180(H-1) (if any) can be intermediate board levels sandwiched between the first board level 180(1) and the Hth board level 180(H). For each h from 1 to (H-1), the h-th board level 180(h) is placed on top of the (h+1)-th board level 180(h+1). In the example shown in Figures 18 and 18A to 18F, the multilayer board level 1800 includes six board levels {180(h), h=1,2,...,6}, that is, H=6 in this example. Figures 18A to 18F show the plan view of each layer in the six board levels {180(h), h=1,2,...,6}, respectively. However, this is only illustrative and not restrictive.

[0122] In one embodiment, referring to the top view of FIG18A, the integrated semiconductor laser 101 can be placed and mounted on a first board level 180(1) of a multilayer circuit board level 1800, located in a predetermined laser mounting area 181 on the top surface of the first board level 180(1). It is understood that the top surface of the first board level 180(1) can also be referred to as the top surface of the multilayer circuit board level 1800. Here, an integrated semiconductor laser 101 having a first plurality of (e.g., N=28) laser cells {101(i), i=1, 2, ..., 28} is used as an example. On the top surface of the multilayer circuit board 1800, a corresponding first plurality of (e.g., N=28) electrical connection structures 184 can be provided at a predetermined connection structure area 183. In one embodiment, each electrical connection structure 184 may include a pad portion 1841 (indicated by small circles in the exemplary drawings) connected to an interlayer connection via 188 and a connection trace 1842 connected to the pad portion 1841. The corresponding first plurality of (e.g., N=28) electrical connection structures 184 may be configured to provide electrical interconnect availability between the integrated semiconductor laser 101 and other components (e.g., the first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} and charging unit 102 in the drive system 100 or 150). For example, in one embodiment, the first terminals of the first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} are respectively connected to the corresponding first plurality of (e.g., N=28) electrical connection structures 184 in a one-to-one correspondence. That is, the first end (e.g., anode) of each unit in the first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} is connected to a corresponding electrical connection structure 184, for example, via a bonding wire 185. In Figure 18A, the first terminal (e.g., anode) of each laser unit in the first plurality (e.g., N=28) laser units {101(i), i=1, 2, ..., 28} is represented by a small orange square. The second terminals (e.g., cathodes) of the first plurality (e.g., N=28) laser units {101(i), i=1, 2, ..., 28} of the integrated semiconductor laser 101 are electrically connected together via a conductive sheet 182 (shown in red in Figure 18A). The conductive sheet 182 is placed in a predetermined laser mounting area 181 on the top surface of the first plate level 180(1) and is located below the integrated semiconductor laser 101. The corresponding first plurality (e.g., N=28) electrical connection structures 184 are separated from each other and electrically isolated from the conductive sheet 182.

[0123] As shown in Figure 18A, in one embodiment, the first portion of a corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} can be arranged and mounted in a predetermined capacitive device mounting area 186 on the top surface of the first board level 180(1). The predetermined capacitive device mounting area 186 on the top surface of the multilayer board level 1800 can be as close as possible to the predetermined laser mounting area 181, for example, located on the first side of the predetermined laser mounting area 181D (the upper side indicated by the upward arrow 180U in the examples of Figures 18 to 18F) or the second side of the predetermined laser mounting area 181 (the lower side indicated by the downward arrow 180D in the examples of Figures 18 to 18F). A predetermined connection structure area 183 can be arranged between the predetermined laser mounting area 181 and the predetermined capacitive device mounting area 186 on the top surface of the multilayer board level 1800. In this way, the interconnection between the integrated semiconductor laser 101 and the corresponding first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} can be more easily achieved, and the interconnection resistance will also be smaller.

[0124] Referring now to the plan view of the bottom surface of the multilayer circuit board level 1800 shown in Figure 18F, which can also be considered as a bottom view viewed from the bottom surface of the lowest H-th board level 180(H) (H=6 in this example), the second portion of the corresponding first plurality (e.g., 28) capacitive energy storage devices {CR(i), i=1,2,...,28} can be arranged and mounted on a predetermined capacitive device mounting area 187 on the bottom surface of the H-th board level 180(H). It is understood that the bottom surface of the H-th board level 180(H) can also be referred to as the bottom surface of the multilayer circuit board level 1800. This will help improve space utilization and save the overall size or board area of ​​the multilayer circuit board level 1800 required to implement and mount the drive system 100 or 150. In one embodiment, the position of the predetermined capacitive device mounting area 187 on the bottom surface of the multilayer circuit board level 1800 can be matched with the position of the predetermined capacitive device mounting area 186 on the top surface of the multilayer circuit board level 1800. For example, the projection of the predetermined top surface capacitive device mounting area 187 of the multilayer circuit board level 1800 can coincide with the predetermined capacitive device mounting area 186.

[0125] In one embodiment, the first portion of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} comprises a first number NUM1 capacitive energy storage devices within the first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28}. The second portion of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} comprises a second number NUM2 capacitive energy storage devices within the first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28}. In one embodiment, the first number NUM1 and the second number NUM2 are substantially the same. For example, in a specific example where N=28, the first portion may include the first 14 capacitive energy storage devices {CR(i), i=1, 2, …, 7 and i=15, 16, …, 21}, while the second portion may include the last 14 capacitive energy storage devices {CR(i), i=8, 9, …, 14 and i=22, 23, …, 28}. However, those skilled in the art will understand that in other embodiments, the first quantity NUM1 and the second quantity NUM2 are not necessarily exactly the same, and customers or users may set other appropriate values. In another embodiment, all the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1, 2, ..., 28} may be placed on the top or bottom surface of the multilayer circuit board level 1800.

[0126] In one embodiment, a corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} can be electrically coupled to a corresponding first plurality (e.g., N=28) electrical connection structure 184 to be coupled to a first plurality (e.g., N=28) laser unit {101(i), i=1,2,...,28} of the integrated semiconductor laser 101. That is, each of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} can be electrically coupled to one of the corresponding first plurality (e.g., N=28) electrical connection structures 184. For example, the first terminal of each capacitive energy storage device in the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} is electrically coupled to a corresponding electrical connection structure 184. In the examples shown in Figures 18 to 18F, the first terminal of each of the first portions of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} can be connected to a connection trace 1842 of a corresponding electrical connection structure 184 within the top surface of the multilayer circuit board level 1800. That is, an electrical connection between the first portion of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} and the corresponding electrical connection structure 184 can be implemented on the first board level 180(1) within the top surface of the multilayer circuit board level 1800. The first terminal of each of the second portions of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1, 2, ..., 28} can be coupled to a connection trace 1842 of a corresponding electrical connection structure 184 via an interlayer connection via 188. The interlayer connection via 188 is formed between every two adjacent circuit board levels in a plurality of (e.g., H) circuit board levels {180(h), h=1,2,...,H} (e.g., H=6) according to actual connection requirements. That is, the electrical connection between the second portion of the corresponding first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} disposed on the bottom surface of the multilayer circuit board level 1800 and the corresponding electrical connection structure 184 disposed on the top surface of the multilayer circuit board level 1800 can be achieved through the interlayer connection via 188. It should be understood below that the interlayer connection via 188 can be flexibly formed according to the electrical connections required between circuit board levels, a point readily understood by those skilled in the art, and therefore requires no further detailed description or explanation herein. Each interlayer connection via 188 is filled with a conductive material.As shown in Figures 18 to 18F, the interlayer connection vias 188 formed between each circuit board level {180(h), h=1,2,...,H} and the immediately following circuit board level are represented by small circles in the plan view of each circuit board level. The slightly larger circles shown in the figures, corresponding to each small circle, represent conductive pads formed on each circuit board level {180(h), h=1,2,...,H} to receive a corresponding interlayer connection via 188.

[0127] In one embodiment, as shown in FIG18A, the discharge unit 106 may be mounted on the first board level 180(1) with its active side facing down on a predetermined discharge unit mounting area 189 on the top surface of the multilayer board level 1800. The discharge unit 106 may be in the form of a packaged IC as described with reference to FIG9 or FIG10. Since the discharge unit 106 is positioned with its active side facing down on the top surface of the multilayer board level 1800, a plurality of terminals on the active side of the discharge unit 106 are indicated by dashed lines in the top view shown in FIG18A. The active side includes a first input terminal (e.g., energy input terminal) DRAIN, a reference ground terminal GND2, a second input terminal (e.g., PWM terminal) PWM2 or a second positive input terminal PWM2+ and a second negative input terminal PWM2-, a third input terminal (e.g., discharge unit power terminal) VCC, and a fault reporting terminal FLT2 (if any). The predetermined discharge unit mounting region 189 on the top surface of the multilayer circuit board level 1800 can be located as close as possible to the predetermined laser mounting region 181. For example, it can be located on a first side of the predetermined laser mounting region 181 (e.g., the upper side indicated by the upward arrow 180U in the examples of Figures 18 to 18F), or it can be located on a second side of the predetermined laser mounting region 181 (e.g., the lower side indicated by the downward arrow 180D in the examples of Figures 18 to 18F). In one embodiment, the predetermined discharge unit mounting region 189 and the predetermined capacitive device mounting region 186 can be arranged on the same side of the top surface of the multilayer circuit board level 1800 (e.g., the first side in the embodiments shown in Figures 18 to 18F). In this way, the interconnection between the integrated semiconductor laser 101, the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28}, and the discharge unit 106 can be more easily achieved, and the interconnection resistance is smaller.

[0128] In one embodiment, the first input terminal DRAIN (the conductive pad of the first input terminal DRAIN) of the discharge unit 106 can be electrically connected to the conductive sheet 182 via, for example, a conductive trace 190 (also shown in red in FIG. 18A), thereby electrically connecting to the second terminals of the first plurality of (e.g., N=28) laser cells {101(i), i=1, 2, ..., 28} of the integrated semiconductor laser 101. In one example, the discharge unit 106 can be symmetrically placed along the center line 180M of the multilayer circuit board level 1800, that is, the discharge unit 106 is mounted such that the center line of the discharge unit 106 substantially coincides with the center line 180M of the multilayer circuit board level 1800. This will help improve the energy discharge performance of the integrated semiconductor laser 101, for example, from the second terminal of each of the first plurality of (e.g., N=28) laser cells {101(i), i=1, 2, ..., 28} to the discharge unit 106, and then to the reference ground terminal GND. The conductive trace 190 extends from below the first input terminal DRAIN to the conductive sheet 182 and is connected thereto.

[0129] Referring to FIG18A, in one embodiment, the conductive pad of the reference ground terminal GND2 of the discharge unit 106 can be electrically coupled to the second terminal of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} via, for example, a conductive sheet 191, which is symmetrically distributed on both sides of the center line 180M on the top surface of the multilayer circuit board level 1800. The conductive sheet 191 extends from below the conductive pad of the reference ground terminal GND2 of the discharge unit 106 and extends below the second terminal of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28}. The conductive sheet 191 is separated from and electrically isolated from the conductive trace 190. The conductive sheet 191 can be configured as the reference ground GND on the first board level 180(1) of the multilayer circuit board 1800 and can be connected to the reference ground GND of the drive system 100 or 150. In one embodiment, the conductive trace 190 may run approximately along the center line 180M of the multilayer circuit board level 1800 and between the symmetrically arranged conductive sheets 191, starting below the first input terminal DRAIN and extending to and connecting to the conductive sheet 182.

[0130] The electrical connections of the other terminals in the discharge unit 106, including the second input terminal (e.g., the PWM terminal) PWM2, the third input terminal (e.g., the discharge unit power terminal) VCC, and the fault report terminal FLT2 (if any), can be implemented using various printed circuit wiring schemes as needed, which is obvious to those skilled in the art and need not be described in detail here.

[0131] As shown in FIG18A, in one embodiment, the charging unit 102 may be mounted with its active side down in a predetermined charging unit mounting area 192 on the top surface of the multilayer circuit board level 1800 on the first board level 180(1). The charging unit 108 may be in the form of a packaged IC as described with reference to FIG8 or FIG17. Since the active surface of the discharge unit 102 is mounted face down on the top surface of the multilayer circuit board level 1800, the terminals of the discharge unit 102 are formed on the active surface of the charging unit 102, which are shown as dashed lines in the top view shown in FIG18A. The terminals of the discharge unit 102 include a second plurality of (e.g., M=32) output terminals {OUT(j), j=1, 2, ..., M=32) second plurality of (e.g., M=32) conductive pads, a first input terminal (e.g., power terminal) IN1, a second input terminal (e.g., enable terminal) EN, a third input terminal (e.g., PWM terminal) PWM2, a reference ground terminal GND1, a fourth input terminal (e.g., select terminal) OS, an indicator terminal (e.g., fault indicator terminal) FLT1, a switch terminal SW, a power output terminal BSTO, and select pins (if any, for example, the five select pins SEL(0), SEL(1), ..., SEL(4) shown in FIG18 to FIG18F), etc. The predetermined charging device mounting region 192 on the top surface of the multilayer circuit board level 1800 can be located as close as possible to the predetermined capacitive device mounting region 186. For example, it can be located on a first side of the predetermined laser mounting region 181 (e.g., the upper side indicated by the upward arrow 180U in the examples of Figures 18 to 18F), or it can be located on a second side of the predetermined laser mounting region 181 (e.g., the lower side indicated by the downward arrow 180D in the examples of Figures 18 to 18F). In one embodiment, the predetermined discharge unit mounting region 189 and the predetermined capacitive device mounting region 186 can be arranged on the same side of the top surface of the multilayer circuit board level 1800 (e.g., the first side in the embodiments shown in Figures 18 to 18F). However, this does not imply limitation. In another embodiment, the predetermined charging device mounting area 192 may be located on the opposite side (e.g., the first side indicated by arrow 180U in the examples shown in Figures 18 to 18F) to the side where the predetermined capacitive device mounting area 186 is located (e.g., the second side indicated by arrow 180D in the examples shown in Figures 18 to 18F). Therefore, in this embodiment, the second power switch 105 and the inductive energy storage device L may be arranged and mounted on the top surface of the multilayer circuit board level 1800 near the charging unit 102, which makes it easier to form a power conversion device.

[0132] In one embodiment, electrical coupling from a second plurality of (e.g., M=32) output terminals {OUT(j), j=1,2,...,32} to a first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} and corresponding first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1, 2, ..., 28} can be achieved through intermediate board levels 180(2) to 180(H-1) sandwiched between the first board level 180(1) and the Hth board level 180(H). In the example shown in Figures 18 to 18F, H=6. In the plan views of each intermediate board level 180(2) to 180(H-1) shown in Figures 18B to 18F, the charging unit 102 is indicated by a dashed line to illustrate that the charging unit 102 is not actually mounted on each intermediate board level, but only to help to better understand the relative positions and electrical coupling relationships described below.

[0133] Referring now to the plan view of the top surface of the second board level 180(2) shown in Figure 18B, which in this embodiment can also be regarded as a top view of the top surface of the second board level 180(2), a conductive bus 193 is formed to connect the first set of output terminals in the second plurality of (e.g., M=32) output terminals {OUT(j), j=1,2,...,32} to the corresponding first set of laser units in the first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} and the corresponding first set of capacitive energy storage devices in the first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28}. In this example, the first set of output terminals shown includes output terminals OUT(2) to OUT(8). The output terminals OUT(2) to OUT(8) are selectively coupled to the first set of laser units 101(1) to 101(7) and the first set of capacitive energy storage devices CR(1) to CR(7), respectively. Therefore, in this example, the first set of output terminals OUT(2) to OUT(8) are the renumbered selected output terminals OUT(1) to OUT(7) respectively coupled to the first set of laser units 101(1) to 101(7). This helps to better understand the description made with reference to Figures 1 to 17, that is, how the customer randomly selects or selects any of the first set of output terminals {OUT(j), j=1,2,...,M} from the second set of output terminals {OUT(j), j=1,2,...,M} to drive the first set of laser units {101(i), i=1,2,...,28} accordingly. In one embodiment, a conductive sheet 194 may be formed on the second board level 180(2) for receiving and connecting to an interlayer connection via 188 for connecting the conductive sheet 191 of the reference ground terminal GND on the first board level 180(1).

[0134] Referring now to the plan view of the top surface of the third board level 180(3) shown in Figure 18C, which in this embodiment can also be regarded as a top view of the top surface of the third board level 180(3), a conductive bus 195 is formed to connect the second set of output terminals in the second plurality (e.g., M=32) of output terminals {OUT(j), j=1,2,...,32} to the corresponding second set of laser units in the first plurality (e.g., N=28) of laser units {101(i), i=1,2,...,28} and the corresponding second set of capacitive energy storage devices in the first plurality (e.g., N=28) of capacitive energy storage devices {CR(i), i=1,2,...,28}. In this example, the second set of output terminals shown includes output terminals OUT(10) to OUT(16). The output terminals OUT(10) to OUT(16) are selected to be coupled to the second group of laser units 101(8) to 101(14) and the second group of capacitive energy storage devices CR(8) to CR(14), respectively. Therefore, in this example, the second group of output terminals OUT(10) to OUT(16) are the renumbered selected output terminals OUT(8) to OUT(14) respectively coupled to the second group of laser units 101(8) to 101(16). In one embodiment, a conductive sheet 196 may be formed on the third board level 180(3) for receiving and connecting to an interlayer connection via 188 for connecting a conductive sheet 194 of a reference ground terminal GND on the second board level 180(2).

[0135] Referring now to the plan view of the top surface of the fourth board level 180(4) shown in Figure 18D, which in this embodiment can also be regarded as a top view of the top surface of the fourth board level 180(4), a conductive bus 197 is formed to connect the third set of output terminals in the second plurality of (e.g., M=32) output terminals {OUT(j), j=1,2,...,32} to the corresponding third set of laser units in the first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} and the corresponding third set of capacitive energy storage devices in the first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28}. In this example, the third set of output terminals includes output terminals OUT(18) to OUT(24). The output terminals OUT(18) to OUT(24) are selected to be coupled to the third group of laser units 101(15) to 101(21) and the third group of capacitive energy storage devices CR(15) to CR(21), respectively. Therefore, in this example, the third group of output terminals OUT(18) to OUT(24) are the renumbered selected output terminals OUT(15) to OUT(21) respectively coupled to the third group of laser units 101(15) to 101(21). In one embodiment, a conductive sheet 198 may be formed on the fourth board level 180(4) for receiving and connecting to an interlayer connection via 188 for connecting a conductive sheet 196 of the reference ground terminal GND on the third board level 180(3).

[0136] Referring now to the plan view of the top surface of the fifth board level 180(5) shown in Figure 18E, which in this embodiment can also be regarded as a top view of the top surface of the fifth board level 180(5), a conductive bus 199 is formed to connect the fourth group of output terminals in the second plurality of (e.g., M=32) output terminals {OUT(j), j=1,2,...,32} to the corresponding fourth group of laser units in the first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} and the corresponding fourth group of capacitive energy storage devices in the first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28}. In this example, the fourth group of output terminals includes output terminals OUT(26) to OUT(32). The output terminals OUT(26) to OUT(32) are selected to be coupled to the fourth group of laser units 101(22) to 101(28) and the fourth group of capacitive energy storage devices CR(22) to CR(28), respectively. Therefore, in this example, the fourth group of output terminals OUT(26) to OUT(32) are the renumbered selected output terminals OUT(22) to OUT(28) respectively coupled to the fourth group of laser units 101(22) to 101(28). In one embodiment, a conductive sheet 1991 may be formed on the fifth board level 180(5) for receiving and connecting to an interlayer connection via 188 for connecting the conductive sheet 198 of the reference ground terminal GND on the fourth board level 180(4).

[0137] In the specific embodiment shown in Figures 18-18F, the charging unit 102 has selected from a second plurality of (e.g., M=32) output terminals {OUT(j), j=1, 2, …, 32} for correspondingly driving the first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} ... The charging unit 102 can be mounted on a multilayer circuit board 1800 and can be electrically coupled from a first plurality of (e.g., N=28) selected output terminals to a first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} and corresponding first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1, 2, ..., 28} via an intermediate board level sandwiched between a first board level 180(1) and an Hth board level 180(H) (H=6 in this example). Although in this example, the first plurality of (e.g., N=28) selected output terminals are divided into four groups, it should be understood that in other embodiments, the first plurality of (e.g., N=28) selected output terminals may be divided into more or fewer groups, and more or fewer intermediate board levels may be formed accordingly to achieve electrical coupling from the first plurality of (e.g., N=28) selected output terminals to the first plurality of (e.g., N=28) laser units {101(i, i=1, 2, ..., 28} and the corresponding first plurality of (e.g., N=28) capacitive energy storage devices {CR(i), i=1, 2, ..., 28}. Those skilled in the art will understand that in other embodiments, the number of intermediate board levels 180(2) to 180(H-1) included in the multilayer board level 1800 and the total number H of board levels 180(1) to 180(H) may depend on the number N of the first plurality of laser units {101(i), i=1, 2, ..., N} to be driven, and the number of intermediate board levels {OUT(i), ..., N} to be driven. The number of groups of the first plurality of selected output terminals renumbered in the order i=1, 2, ... , N}, and / or the number of rows (e.g., X rows) of the output terminal matrix 801 of the package containing the charging unit 102.

[0138] Other terminals of the charging unit 102 can be implemented using different printed circuit wiring schemes according to connection requirements, which is obvious to those skilled in the art and need not be described in detail here. The other terminals include the first input terminal (e.g., power terminal) IN1, the second input terminal (e.g., enable terminal) EN, the third input terminal (e.g., PWM terminal) PWM1, the reference ground terminal GND1, the fourth input terminal (e.g., select terminal) OS, the indicator terminal (e.g., fault indicator terminal) FLT1, the switch terminal SW, the power output terminal BSTO, and the select pins (if any, such as the five select pins SEL(0), SEL(1), ..., SEL(4) in the examples of Figures 18-18F).

[0139] Referring again to Figure 18F, conductive sheet 1992 can be formed and used as the reference ground terminal GND of the bottommost H-level plate 180(H) (in this example, H=6). Conductive sheet 1992 can be electrically connected to conductive sheet 1991, which serves as the reference ground terminal GND on the fifth level plate 180(5). In this example, the fifth level plate 180(5) is located above the bottommost sixth level plate 180(6). The first terminal of each of the first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} in the second part (e.g., in this example, including capacitive energy storage devices CR(15) to CR(28)) can be connected to a connection trace 1993 formed on the bottom surface of the multilayer circuit board level 1800, and then coupled to a connection trace 1842 of a corresponding electrical connection structure 184 on the top surface of the multilayer circuit board level 1800 through an interlayer connection via 188. The interlayer connection via 188 can be formed between every two adjacent circuit board levels in a plurality (e.g., H) circuit board levels {180(h), h=1,2,...,H} (in this example, H=6) as needed for actual connection. The second terminal of each of the second portions of the corresponding first plurality (e.g., N=28) capacitive energy storage devices {CR(i), i=1,2,...,28} (e.g., in this example, including capacitive energy storage devices CR(15) to CR(28)) can be connected to a conductive sheet 1992, which is connected to the reference ground terminal GND of the drive system 100 or 150.

[0140] In another embodiment, the charging unit 102 may be mounted with its active side facing down on the bottommost H-th board level 180(H), where H=6 in the example shown in Figures 18G to 18H. Figure 18G shows a plan view of the top surface of the first board level 180(1), which may also be considered as a top view viewed from the top surface of the first board level 180(1) in an alternative embodiment. Figure 18H shows a plan view of the bottom surface of the multilayer circuit board level 1800, which may also be considered as a bottom view viewed from the bottom surface of the bottommost H-th board level 180(H), where H=6 in this alternative example. It will be understood by those skilled in the art that the substantial description given with reference to the examples of Figures 18 to 18F applies to the examples of Figures 18G to 18H. The difference may be that, in this alternative embodiment, the predetermined charging device mounting area 192 may be arranged on the bottom surface of the multilayer circuit board level 1800. Accordingly, in one embodiment, the second power switch 105 and the inductive energy storage device L can be arranged and mounted on the bottom surface of the multilayer circuit board stage 1800 close to the charging unit 102 in the alternative embodiment, which makes it easier to form a power conversion device.

[0141] It will be apparent to those skilled in the art that, in the alternative examples shown in Figures 18G to 18H, the description and illustration of the intermediate circuit board levels 180(2) to 180(5) formed between the first circuit board level 180(1) and the bottommost Hth circuit board level 180(H) (e.g., H=6) can be similar to the description and illustration with reference to Figures 18B to 18E, except that the positions of the conductive buses (e.g., 193, 195, 197 and 199) need to be changed according to the position of the predetermined charging unit mounting area 192 (and the position of the charging unit 102), which need not be described in detail here.

[0142] Figure 19 shows a schematic diagram of a drive system 1000 according to an embodiment of the present disclosure. The drive system 1000 includes two drive systems 100. The drive system 1000 can be configured to drive an integrated semiconductor laser 1001, the number of laser units included in the integrated semiconductor laser 1001 (e.g., 2*N) being twice the number of laser units (e.g., N) of the semiconductor laser 101. The integrated semiconductor laser 1001 can be considered to contain two semiconductor lasers 101. In one embodiment, the operating order of the two charging units 102 in the drive system 1000, and the operating order of the two drive systems 100, can be set by a customer or user via a fourth input terminal (e.g., a chip select terminal) OS of each charging unit 102. For example, when system 1000 is enabled by an enable signal EN_C provided to the enable terminal EN of each charging unit 102, the first charging unit 102 can be programmed to turn on first to drive a first group of N laser units in the integrated semiconductor laser 1001 by providing a chip select signal OS_C1 to the chip select terminal OS of the first charging unit 102 (e.g., the one on the left in FIG. 19). As another example, by providing a chip select signal OS_C2 to the chip select terminal OS of the second charging unit 102 (e.g., the one on the right in FIG. 19), the second charging unit 102 can be programmed to turn on after the first charging unit 102 is turned off to drive a second group of N laser units in the integrated semiconductor laser 1001. The chip select signal OS_C1 and the chip select signal OS_C2 may have complementary logic potentials to ensure that the first charging unit 102 and the second charging unit 102 are not simultaneously in the on state. That is, when the chip select signal OS_C1 is in the logic high state, the chip select signal OS_C2 should be in the logic low state, and vice versa. Those skilled in the art should understand that when the first charging unit 102 and the second charging unit 102 are in the on state, their operation follows the description above with respect to Figures 1 to 17, and will not be repeated here. The charging control PWM signal PWM_C1 provided to the third input terminal (e.g., PWM terminal) PWM1 of the first charging unit 102, and the charging control PWM signal PWM_C2 provided to the third input terminal (e.g., PWM terminal) PWM1 of the second charging unit 102, may come from the same charging control PWM signal PWM_C, or they may be different. However, when the first charging unit 102 is in the on state, the function of the charging control PWM signal PWM_C1 can be referred to the charging control PWM signal PWM_C in Figures 1 to 17 and their corresponding descriptions. The function of the charging control PWM signal PWM_C2 when the second charging unit 102 is in the on state is also the same, and will not be repeated here.The discharge control PWM signal PWM_D1 provided to the second input terminal PWM2 of the first discharge unit 106, and the discharge control PWM signal PWM_D2 provided to the second input terminal PWM2 of the second discharge unit 106, can originate from the same discharge control PWM signal PWM_D, or they can be different. However, when the first charging unit 102 (and the corresponding first driving system 100) is in the ON state, the function of the discharge control PWM signal PWM_D1 is the same as that of the discharge control PWM signal PWM_D in Figures 1 to 17 and their corresponding descriptions. Similarly, when the second charging unit 102 (and the corresponding first driving system 100) is in the ON state, the function of the discharge control PWM signal PWM_D2 is the same, and will not be repeated here.

[0143] Figure 20 shows a schematic diagram of a drive system 1500 according to an embodiment of the present disclosure. The drive system 1500 can be considered to include two drive systems 150. The drive system 1500 can be configured to drive an integrated semiconductor laser 1001, the number of laser units included in the integrated semiconductor laser 1001 (e.g., 2*N) being twice the number of laser units (e.g., N) in the semiconductor laser 101. The integrated semiconductor laser 1001 can be considered to include two semiconductor lasers 101. In one embodiment, similar to the example in Figure 19 above, the operating sequence of the two charging units 102 in the drive system 1500, and the corresponding operating sequence of the two drive systems 150, can be set by a customer or user via the fourth input terminal (e.g., chip select terminal) OS of each charging unit 102. For example, when system 1500 is enabled by an enable signal EN_C provided to the enable terminal EN of each charging unit 102, the first charging unit 102 can be programmed to first turn on to drive a first group of N laser units of the integrated semiconductor laser 1001 in system 1500 by providing a chip select signal OS_C1 to the chip select terminal OS of the first charging unit 102 (e.g., the one on the left in FIG. 20). As another example, by providing a chip select signal OS_C2 to the chip select terminal OS of the second charging unit 102 (e.g., the one on the right in FIG. 20), the second charging unit 102 can be programmed to turn on after the first charging unit 102 is turned off to drive a second group of N laser units of the integrated semiconductor laser 1001 in system 1500. The chip select signal OS_C1 and the chip select signal OS_C2 may have complementary logic levels. Those skilled in the art will understand that when the first charging unit 102 and the second charging unit 102 are in the ON state, their operation follows the description above regarding Figures 11 to 17, and will not be repeated here. The charging control PWM signal PWM_C1 provided to the third input terminal (e.g., PWM terminal) PWM1 of the first charging unit 102, and the charging control PWM signal PWM_C2 provided to the third input terminal (e.g., PWM terminal) PWM1 of the second charging unit 102, can come from the same charging control PWM signal PWM_C, or they can be different. However, when the first charging unit 102 (and its corresponding first drive system 150) is in the ON state, the function and role of the charging control PWM signal PWM_C1 can be referred to the charging control PWM signal PWM_C in Figures 11 to 17 and their corresponding descriptions above, and the function and role of the charging control PWM signal PWM_C2 when the second charging unit 102 (and its corresponding second drive system 150) is in the ON state are also similar, and will not be repeated here.The discharge control PWM signal PWM_D1 provided to the second input terminal PWM2 of the first discharge unit 106, and the discharge control PWM signal PWM_D2 provided to the second input terminal PWM2 of the second discharge unit 106, can originate from the same discharge control PWM signal PWM_D, or they can be different. However, when the first charging unit 102 (and the corresponding first driving system 150) is in the ON state, the function of the discharge control PWM signal PWM_D1 is the same as that of the discharge control PWM signal PWM_D in Figures 11 to 17 and their corresponding descriptions. Similarly, when the second charging unit 102 (and the corresponding first driving system 150) is in the ON state, the function of the discharge control PWM signal PWM_D2 is also the same, and will not be repeated here.

[0144] Figure 21A shows an application board-level layout diagram related to the drive system 1000 in Figure 19 or the drive system 1500 in Figure 20 according to an embodiment of the present disclosure.

[0145] Figures 21B to 21G show application board-level layout diagrams of each layer associated with the drive system 1000 in Figure 19 or the drive system 1500 in Figure 20, according to an embodiment of the present disclosure.

[0146] In one embodiment, the drive system 1000 or 1500 is mounted on a multilayer circuit board, such as a printed circuit board (PCB) 2100. The multilayer circuit board 2100 for the drive system 1000 or 1500 will now be described with reference to Figures 21A to 21G. The multilayer circuit board 2100 may include multiple (e.g., represented by an integer variable H) board levels 210(1), 210(2), ..., 210(H). Hereafter, the multiple (e.g., H) board levels 210(1), 210(2), ..., 210(H) may be referred to as or represented by {210(h), h=1,2,...,H}. Here, H is an integer variable not less than 1, representing the total number of board levels 210(1), 210(2), ..., 210(H) that the multilayer circuit board 2100 may include, which can be set or determined by the customer / user according to actual application requirements in practical applications. That is, h is a variable that iterates through integers from 1 to H. In one embodiment, multiple (e.g., H) board levels {210(h), h=1,2,...,H} can be arranged one after another in the order from 210(1) to 210(H). That is, the first board level 210(1) can be the top layer of the multilayer circuit board 2100, and the Hth board level 210(H) can be the bottom layer of the multilayer circuit board 2100. The remaining board levels 210(2) to 210(H-1) (if any) can be intermediate board levels sandwiched between the first board level 210(1) and the Hth board level 210(H). For each h from 1 to (H-1), the hth board level 210(h) is placed on top of the (h+1)th board level 210(h+1). In the examples shown in Figures 21A to 21G, the multilayer circuit board 2100 includes six board levels {210(h), h=1,2,...,6}, that is, H=6 in this example. Figures 21B to 21G show the plan view of each of the six board levels {210(h), h=1,2,...,6}, respectively. However, this is only an example and is not restrictive.

[0147] In one embodiment, referring to the top view of FIG21B, the integrated semiconductor laser 1001 can be arranged and mounted on the first board level 210(1) of the multilayer circuit board 2100, in a predetermined laser mounting area 181 on the top surface of the first board level 210(1). It is understood that the top surface of the first board level 210(1) can also be referred to as the top surface of the multilayer circuit board 2100. As described previously in FIGS. 19 and 20, the integrated semiconductor laser 1001 can be considered to include two semiconductor lasers 101, the number of laser units of the integrated semiconductor laser device 1001 being twice the number of the first plurality of (e.g., N=28) laser units {101(i), i=1,2,...,28} in the semiconductor lasers 101. For example, compared to the example shown in FIGS. 18 to 18H, here we take 2*N=56 laser units 2*{101(i), i=1,2,...,28} as an example. For ease of description, the predetermined laser mounting area on the top surface of the first board level 210(1) for receiving the integrated semiconductor laser 1001 is still labeled as 181.

[0148] It will be readily understood by those skilled in the art that the board-level layout diagram implemented on the multilayer circuit board 2100 corresponding to the drive system 1000 of FIG. 19 or the drive system 1500 of FIG. 20 (as shown in FIG. 21A to 21G) can be considered as a modification of the board-level layout diagram corresponding to the drive system 100 of FIG. 1 or the drive system 150 of FIG. 11 (as shown in FIG. 18 to 18H). For example, by including two layouts (including layer-by-layer layout and electrical coupling) implemented on the multilayer circuit board 1800 including the drive system 100 of FIG. 19 or the drive system 1500 of FIG. 20, the board-level layout diagram implemented on the multilayer circuit board 2100 corresponding to the drive system 1000 of FIG. 19 or the drive system 1500 of FIG. 20 can be obtained, except that the integrated semiconductor laser 101 installed in the predetermined laser mounting area 181 is replaced by the integrated semiconductor laser 1001. For ease of description and understanding, the board-level layout (including the layout of each layer and the electrical coupling between each board level and between each two board levels) implemented on the multilayer circuit board 1800 by the drive system 100 in Figure 1 or the drive system 150 in Figure 11 can be referred to as an N-laser unit drive system layout unit. That is, the board-level layout implemented on the multilayer circuit board 2100 can be regarded as including two such N-laser unit drive system layout units, referred to here as the first N-laser unit drive system layout unit U(1) and the second N-laser unit drive system layout unit U(2), respectively. Each of the two N-laser unit drive system layout units can be flexibly arranged within the multilayer circuit board 2100 according to the actual design considerations. The first N-laser unit drive system layout unit U(1) is configured at least to implement the mounting and electrical coupling of the first charging unit 102 and the first discharging unit 106, so as to cooperate with the first N capacitive energy storage devices {CR(i), i=1,2,...,N} in the drive system 1000 or 1500, thereby driving the first N laser units {101(i), i=1,2,...,N} of the integrated semiconductor laser 1001. The second N-laser unit drive system layout unit U(2) is configured at least to implement the mounting and electrical coupling of the second charging unit 102 and the second discharging unit 106, so as to cooperate with the second N capacitive energy storage devices {CR(i), i=1,2,...,N} in the drive system 1000 or 1500, thereby driving the second N laser units {101(i), i=1,2,...,N} of the integrated semiconductor laser 1001, where N=28 in the examples shown in Figures 21A to 21G.

[0149] For example, as shown in Figures 21A to 21G, the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2) are respectively disposed on the first side 180U and the second side 180D of the predetermined laser mounting area 181, for receiving and mounting the integrated semiconductor laser 1001. In this embodiment, the integrated semiconductor laser 1001 can be regarded as including two semiconductor lasers 101. Those skilled in the art will understand that the description with reference to Figures 18A to 18H is basically applicable to the first N laser unit drive system layout unit U(1) and the second N laser unit drive system layout unit U(2), and therefore need not be repeated here.

[0150] In the examples shown in Figures 21A to 21G, each of the first N laser unit drive system layout units U(1) and the second N laser unit drive system layout units U(2) is a copy of the layouts shown in Figures 18 to 18F. The second N laser unit drive system layout units U(2) are arranged such that they coincide with the first N laser unit drive system layout units U(1) when the reference center line 180M of the multilayer circuit board 2100 is rotated by 180°. In another embodiment, the first N laser unit drive system layout units U(1) and the second N laser unit drive system layout units U(2) may be arranged and aligned symmetrically with reference to another center line 180M' perpendicular to the center line 180M of the multilayer circuit board 2100. In another embodiment, each unit in the first N laser unit drive system layout units U(1) and the second N laser unit drive system layout units U(2) may not be a complete repeat of the layouts shown in Figures 18 to 18F. For example, in one embodiment, the first discharge unit 106 and the corresponding first N capacitive energy storage devices {CR(i), i=1, 2, …, N} in the first N laser unit drive system layout unit U(1) and the second discharge unit 106 and the corresponding second N capacitive energy storage devices {CR(i), i=1, 2, …, N} in the second N laser unit drive system layout unit U(2) can be symmetrically arranged with reference to another center line 180M' of the multilayer circuit board 2100, while the first charging unit 102 in the first N laser unit drive system layout unit U(1) and the second charging unit 102 in the second N laser unit drive system layout unit U(2) are not necessarily symmetrically arranged with reference to another center line 180M' of the multilayer circuit board 2100.

[0151] Figure 22 shows a schematic diagram of a drive system 2000 according to an embodiment of the present disclosure. The drive system 2000 can be considered to include a plurality of (e.g., z) drive systems 150 (or drive systems 100). Although the example in Figure 22 shows z drive systems 150, those skilled in the art will understand that in another embodiment, the drive system 2000 may include z drive systems 100, and the description provided herein also applies to the case of z drive systems 100. Here, z is an integer variable not less than 1, representing the total number of drive systems 150 (or drive systems 100) included in the drive system 2000, and z can be set by the customer / user in actual application according to actual application requirements. The drive system 2000 can be configured to drive an integrated semiconductor laser, the number of laser units (e.g., z*N) of which is z times the number of laser units (e.g., N) in the semiconductor laser 101. Therefore, the drive system 2000 can be considered to be configured to drive a plurality of (e.g., z) semiconductor lasers 101. In one embodiment, the operating order of the plurality of (e.g., z) charging units 102 in the drive system 2000, and the corresponding operating order of the plurality of (e.g., z) drive systems 150 (or 100) can be set by a customer or user via the fourth input terminal (e.g., chip select terminal) OS of each charging unit 102. For example, when system 2000 is enabled by an enable signal EN_C provided to the enable terminal EN of each charging unit 102, the z charging units 102 (and the corresponding z driving systems 150 or 100) can be programmed to be turned on one by one by setting the chip select signal (e.g., labeled OS_C(r)) of the chip select terminal OS provided to one of the charging units 102 (e.g., the r-th charging unit 102 in z charging units 102) to a logic high level to turn on that r-th charging unit 102, while setting the chip select signals of the chip select terminal OS provided to the remaining charging units 102 to a logic low level to turn them all off. Here, r is an integer variable iterating from 1 to z. Those skilled in the art will understand that the operation of each of the z charging units 102 when turned on follows the description in Figures 1 to 17 above, and will not be repeated here. For each r traversing 1 to z, the charging control PWM signal PWM_C(r) provided to the third input terminal (e.g., PWM terminal) PWM1 of the r-th charging unit 102 can come from the same charging control PWM signal PWM_C, or they can be different. However, when the r-th charging unit 102 (correspondingly, the r-th drive system 150 or 100) is in the on state, the function and role of the charging control PWM signal PWM_C1 can be referred to the charging control PWM signal PWM_C in Figures 1 to 17 and their corresponding descriptions above, and will not be repeated here.The discharge control PWM signal PWM_D(r) provided to the second input terminal PWM2 of the r-th discharge unit 106 can come from the same discharge control PWM signal PWM_D, or they can be different. However, when the r-th charging unit 102 (correspondingly, the r-th drive system 150 or 100) is in the on state, the function and role of the discharge control PWM signal PWM_D(r) can be referred to the discharge control PWM signal PWM_D in Figures 1 to 18 and their corresponding descriptions above, and will not be repeated here.

[0152] Those skilled in the art will understand that the drive system 2000 can be implemented and mounted on a multilayer circuit board such as a printed circuit board (PCB), similar to the implementation and mounting of the drive systems 100 or 150 on the multilayer circuit board 1800 and the implementation and mounting of the drive systems 1000 or 1500 on the multilayer circuit board 2100. The multilayer circuit board used to implement the drive system 2000 can be considered as including multiple (e.g., z) N laser unit drive system layout units.

[0153] Figure 23 illustrates an illustrative waveform diagram 2300 according to an exemplary embodiment of the present disclosure, showing exemplary operating waveforms of several signals when the drive system 150 in Figure 11 is operating in parallel output mode. In parallel output mode, a group of T output terminals in a second plurality (e.g., M) of output terminals {OUT(j), j=1,2,...,M} can be programmed to be turned on simultaneously and in parallel each time, for example, during each T duty cycle or during each T charging pulse of the charging control PWM signal PWM_C. The variable T is an integer variable not less than 1 and not greater than M, representing the total number of output terminals programmed to be turned on simultaneously and in parallel each time. In the example of Figure 23, it is illustrated that a group of three output terminals in a second plurality (e.g., M) of output terminals {OUT(j), j=1, 2, ..., M} can be programmed to be turned on simultaneously and in parallel each time, for example, during each three duty cycles or during each three charging pulse of the charging control PWM signal PWM_C, i.e., M=3 in this example. However, this does not imply limitation. Those skilled in the art should understand that the variable T can be set to other values, such as 4 or 5, depending on the actual application requirements.

[0154] To illustrate the parallel output mode, an exemplary illustration with T=3 in Figure 23 will be used. In parallel output mode, at the start of each charging pulse of the charging control PWM signal PWM_C, the charging unit 102 checks the logic state of a plurality of (e.g., K) selection control signals {SEL_C(q), q=0,1,...,K-1} and determines, according to equation (1), which of the second plurality of (e.g., M) output terminals {OUT(j), j=1,2,...,M} or the second plurality of (e.g., M) charging path control circuits {104(j), j=1,2,...,M} will be programmed to be simultaneously and concurrently turned on in the current T group (e.g., T=3) output terminals. That is, at the start of each charging pulse of the charging control PWM signal PWM_C, according to equation (1), the s-th output terminal OUT(s) or the s-th charging path control circuit 104(s) is programmed to be in the current T group (e.g., T=3) output terminals so that they are simultaneously and concurrently turned on and recorded. Once all current T-group (e.g., T=3) output terminals have been recorded, the recorded current T-group (e.g., T=3) output terminals can be controlled according to the charging pulse control PWM signal PWM_C for each T charging pulse (e.g., the 3 charging pulses of the 1st group are the 1st-3rd charging pulses, the 3 charging pulses of the 2nd group are the 4th-6th charging pulses, the 3 charging pulses of the 3rd group are the 6th-9th charging pulses, and so on), in a manner similar to that described in the examples with reference to Figures 12 to 16, to control the programmed s-th output terminal OUT(s) and the s-th charging path control circuit 104(s), which can be clearly and easily understood by those skilled in the art in conjunction with the illustrations in Figure 23, and need not be repeated in detail here.

[0155] As can be seen from the example in Figure 23, during the first charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} are {0, 0, 0, 0, 0}, respectively. This means that s = 1 + 0*2 0 + 0*2 1 + 0*2 2 + 0*2 3 + 0*2 4 = 1. Therefore, in this example, the first output terminal OUT(1) is programmed as one of the current T group (e.g., T = 3) output terminals, and is simultaneously turned on and recorded during the first charging pulse. During the second charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} may be {1, 0, 0, 0, 0}, which means s = 1 + 1*2 0 + 0*2 1 + 0*2 2 + 0*2 3 + 0*2 4 = 2. Therefore, in this example, the second output terminal OUT(2) is programmed as one of the current T group (e.g., T = 3) output terminals, and is simultaneously turned on and recorded during the second charging pulse. During the third charging pulse of the charging control PWM signal PWM_C, the logic states of the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)} provided to the selection terminals {SEL(0), SEL(1), SEL(2), SEL(3), SEL(4)} may be {0, 1, 0, 0, 0}, which means s = 1 + 0*2 0 + 1*2 1 + 0*2 2 + 0*2 3 + 0*2 4 = 3. Therefore, in this example, the third output terminal OUT(3) is programmed as one of the current T group (e.g., T = 3) output terminals, and is simultaneously turned on and recorded during the third charging pulse.

[0156] During the third charging pulse of the charging control PWM signal PWM_C, all output terminals OUT(1), OUT(2), and OUT(3) programmed to be in the current T (e.g., T=3) group are recorded and thus simultaneously activated in parallel during the charging time window Tcg(1) / Tcg(2) / Tcg(3) following the third charging pulse. It should be understood that in this case, the charging time window Tcg(1) of the relevant output terminal OUT(1), the charging time window Tcg(2) of the relevant output terminal OUT(2), and the charging time window Tcg(3) of the relevant output terminal OUT(3) are the same and overlap with each other. Then, after the charging time window Tcg(1) / Tcg(2) / Tcg(3) ends, the discharge unit 106 can be configured to absorb or release energy to the reference ground GND simultaneously and in parallel from the output terminals OUT(1), OUT(2) and OUT(3) of the integrated semiconductor laser 101 during the discharge time window Tdg(1) / Tdg(2) / Tdg(3).

[0157] Similarly, in the next three charging pulses, namely the 4th, 5th, and 6th charging pulses of the charging control PWM signal PWM_C, the 4th output terminal OUT(4), the 5th output terminal OUT(5), and the 6th output terminal OUT(6) are programmed and recorded as the next group of T (e.g., T=3) output terminals being simultaneously turned on in parallel, according to the selection control signals {SEL_C(0), SEL_C(1), SEL_C(2), SEL_C(3), SEL_C(4)}. Therefore, in this example, at the 6th charging pulse of the charging control PWM signal PWM_C, all the next group of T (e.g., T=3) programmed output terminals OUT(4), OUT(5), and OUT(6) are recorded, so that they are simultaneously turned on in parallel during the charging time window Tcg(4) / Tcg(5) / Tcg(6) after the 6th charging pulse. It should be understood that, in this case, the charging time window Tcg(4) of the relevant output terminal OUT(4), the charging time window Tcg(5) of the relevant output terminal OUT(5), and the charging time window Tcg(6) of the relevant output terminal OUT(6) are the same and overlap each other. Then, after the charging time window Tcg(4) / Tcg(5) / Tcg(6) ends, the discharge unit 106 can be configured to absorb or release energy to the reference ground GND from the output terminals OUT(4), OUT(5), and OUT(6) of the integrated semiconductor laser 101 simultaneously and in parallel during the discharge time window Tdg(4) / Tdg(5) / Tdg(6). A similar description applies to the remainder of each group of T (e.g., T=3) programmed output terminals that will be turned on and discharged simultaneously and in parallel.

[0158] The advantages of the various embodiments disclosed are not limited to those described above. These and other advantages will become more apparent upon reading the full detailed description and studying the various figures in the drawings.

[0159] As can be seen from the foregoing, the specific embodiments of this disclosure have been described for illustrative purposes, and various modifications can be made without departing from the technical specifications. Many elements in one embodiment may be combined with or substituted for elements in other embodiments. Therefore, the present invention is limited only to the scope of the appended claims.

[0160] 10: Front-end voltage regulator 20: Buck Voltage Regulator 100, 150, 1000, 1500: Drive system 101: Integrated Semiconductor Laser 101(1)…101(N): Laser unit 102, 200, 400, 450: Charging unit 103: Controllable power switch 104(1), 104(2)…104(M): Charging path control circuit 105: Second power switch 106: First Discharge Unit 107: Discharge Path Switching Circuit 180(1),180(2),......,180(H),210(1),210(2),...,210(H): Board level 181: Planned laser installation area 182, 191, 194, 196, 198, 1991, 1992: Conductive sheets 183: Pre-defined connection structure area 184: Electrical connection structure 185: Bond wire 186, 187: Pre-determined capacitive device installation area 188: Interlayer connection through hole 189: Pre-determined installation area for discharge unit 190: Conductive trace 192: Pre-planned charging unit installation area 193, 195, 197, 199: Conductive busbars 300, 300A, 300B, 350, 500, 500A, 500B, 550, 600, 650, 2300: Illustrative waveform diagrams 401: Logic Control Circuit 402: Drive circuit module 700: Discharge Unit 701: Control Circuit 702: Drive Circuit 800, 850, 900, 950: Package 801: Output Terminal Array 802: Other Terminal Arrays 851: Select Terminal Array 1001: Integrated Semiconductor Laser 1800, 2100: Multilayer circuit boards 1841: Pad section 1842, 1993: Connection wiring

Claims

1. A charging unit for driving an integrated semiconductor laser, comprising: The first input terminal is configured to receive input drive energy; the second input terminal is configured to enable or disable the charging unit. A third input terminal is configured to receive a charging control PWM signal; and a plurality of output terminals; wherein the charging unit is configured to turn the plurality of output terminals on or off in a predetermined pattern according to the charging control PWM signal; wherein the charging control PWM signal has a plurality of charging pulses, and the charging unit is configured to switch one of the plurality of output terminals to a conducting state after each current charging pulse of the charging control PWM signal and maintain the conducting state within a charging time window associated with the output terminal, wherein the end time of the charging time window is no later than the time when the next charging pulse arrives.

2. The charging unit as claimed in claim 1, wherein each of the plurality of output terminals is adapted to provide energy when switched to an on state and to stop providing energy when switched to an off state.

3. The charging unit as claimed in claim 1, wherein the charging unit is configured to enable the plurality of output terminals in the predetermined mode in response to the plurality of charging pulses in response to the charging control PWM signal.

4. The charging unit as claimed in claim 1, wherein for each of the plurality of output terminals, the time period during which the output terminal is in the on state defines a charging time window associated with that output terminal.

5. The charging unit as claimed in claim 1, wherein the charging unit is configured to sequentially turn on the plurality of output terminals in response to the plurality of charging pulses in response to the charging control PWM signal.

6. The charging unit as claimed in claim 1, wherein the predetermined mode includes each of the plurality of output terminals being turned on sequentially or in a programmed order.

7. The charging unit as claimed in claim 1, further comprising a fourth input terminal configured to receive a chip select signal, the charging unit further configured to control at least one controllable power switch in the charging unit to be in an operable or inoperable state in response to the chip select signal.

8. The charging unit as claimed in claim 1, wherein the output terminal switched to the on state has the associated charging time window and is adapted to provide energy within the charging time window.

9. The charging unit as claimed in claim 1, further comprising: The power output terminal is configured to provide a regulated output voltage. Multiple charging path control circuits are respectively associated with the multiple output terminals, and each charging path control circuit is coupled between the power output terminal and the output terminal corresponding to the charging path control circuit.

10. The charging unit as claimed in claim 1, further comprising: At least one controllable power switch is configured to switch on and off in response to the charging control PWM signal when the charging unit is enabled.

11. The charging unit of claim 10, wherein the at least one controllable power switch is configured to be turned on with or without a first time delay in response to a first transition edge of a charging pulse of the charging control PWM signal, and is further configured to be turned off with or without a second time delay in response to a second transition edge of the charging control PWM signal pulse.

12. The charging unit as claimed in claim 1, further comprising: Switching terminals are configured to provide switching signals.

13. The charging unit as claimed in claim 12, wherein when the inductive energy storage element is coupled to the switching terminal, the charging unit is adapted to be configured as part of a power conversion device.

14. The charging unit as claimed in claim 12, further comprising: At least one controllable power switch is coupled between the switch terminal and the reference ground terminal and configured to control the energy transferred from the first input terminal of the charging unit to the power output terminal of the charging unit.

15. The charging unit as claimed in claim 1, wherein each of the plurality of output terminals is coupled to a corresponding charging path control circuit, the corresponding charging path control circuit being configured to be turned on or off in response to the charging control PWM signal.

16. The charging unit as claimed in claim 15, wherein the corresponding charging path control circuit is configured to, when switched to an on state, enable an energy transfer path from the power output terminal of the charging unit to the output terminal correspondingly coupled to the charging path control circuit.

17. The charging unit of claim 15, wherein the corresponding charging path control circuit is configured to, when switched to an off state, to shut off the energy transfer path from the power output terminal of the charging unit to the output terminal correspondingly coupled to the charging path control circuit.

18. The charging unit as claimed in claim 15, further configured to control the conduction time window for which the charging path control circuit corresponding to each of the plurality of output terminals is turned on.

19. The charging unit as claimed in claim 1, further comprising: Multiple charging path control circuits are provided, corresponding to the multiple output terminals and coupled to the multiple output terminals in a one-to-one correspondence.

20. The charging unit as claimed in claim 19, wherein for each of the plurality of charging path control circuits, the charging unit is further configured to control the conduction time window during which the conduction of the charging path control circuit is sustained.

21. The charging unit as claimed in claim 19, wherein: The plurality of output terminals consist of M output terminals {OUT(j), j=1, 2, …, M}, where M is an integer greater than 1; wherein the charging unit is configured such that the charging path control circuit coupled to the j-th output terminal OUT(j) is turned on in response to the first transition edge of the j-th charging pulse of the charging control PWM signal after a predetermined turn-on delay time, and the charging path control circuit coupled to the j-th output terminal OUT(j) is turned off in response to the second transition edge of the j-th charging pulse of the charging control PWM signal after a predetermined turn-off delay time.

22. The charging unit as claimed in claim 19, wherein: Each charging pulse of the charging control PWM signal has a first transition edge and a second transition edge; the plurality of output terminals consist of M output terminals {OUT(j), j=1, 2, …, M}, where M is an integer greater than 1; the charging unit is configured to enable the charging path control circuit coupled to the j-th output terminal OUT(j) to turn on after a predetermined delay on time in response to the second transition edge of the j-th charging pulse of the charging control PWM signal, and to enable the charging path control circuit coupled to the j-th output terminal OUT(j) to turn off after a predetermined delay off time in response to the first transition edge of the (j+1)-th charging pulse of the charging control PWM signal.

23. The charging unit as claimed in claim 19, further comprising: At least one controllable power switch is configured to switch on and off in response to the charging control PWM signal; and the plurality of output terminals are composed of M output terminals {OUT(j), j=1, 2, …, M}, where M is an integer greater than 1; and the charging unit is configured to turn on the charging path control circuit coupled to the j-th output terminal OUT(j) at a moment during the period when the at least one controllable power switch is held on in response to the current j-th charging pulse of the charging control PWM signal, and turn off the charging path control circuit coupled to the j-th output terminal OUT(j) at a moment no later than the time when the at least one controllable power switch is turned off in response to the (j+1)-th charging pulse of the charging control PWM signal.

24. The charging unit as claimed in claim 19, further comprising: At least one controllable power switch is configured to switch on and off in response to the charging control PWM signal; and wherein the plurality of output terminals consists of M output terminals {OUT(j), j=1, 2, …, M}, where M is an integer greater than 1; and wherein for each j=1, 2, …, M, the charging unit is configured to control the j-th conduction time window when the charging path control circuit coupled to the j-th output terminal OUT(j) is turned on, such that the j-th conduction time window begins at a time before the j-th charging pulse of the charging control PWM signal is turned off, and ends at a time before the (j+1)-th charging pulse of the charging control PWM signal is turned off.

25. The charging unit as claimed in claim 19, wherein: The plurality of output terminals consist of M output terminals {OUT(j), j=1, 2, …, M}, where M is an integer greater than 1; and for each j=1, 2, …, M, the charging unit is configured to control the conduction of the j-th output terminal OUT(j) for the j-th charging time window, such that the j-th charging time window is located between the j-th charging pulse and the (j+1)-th charging pulse of the charging control PWM signal.

26. The charging unit as claimed in claim 19, wherein each of the plurality of charging path control circuits has a first terminal coupled to a power output terminal of the charging unit, a second terminal coupled to a corresponding output terminal of the plurality of output terminals, and a control terminal adapted to control the on or off switching of the charging path control circuit.

27. The charging unit as claimed in claim 19, wherein the charging unit is configured to turn on or off the plurality of charging path control circuits in a predetermined pattern or in a predetermined sequence based on a plurality of charging pulses of the charging control PWM signal.

28. The charging unit as claimed in claim 19, wherein each of the plurality of charging path control circuits includes at least one switch.

29. The charging unit of claim 19, wherein each of the plurality of charging path control circuits comprises: a first controllable transistor coupled between a power output terminal of the charging unit and an output terminal corresponding to the charging path control circuit; and a second controllable transistor coupled between the output terminal corresponding to the charging path control circuit and a reference ground terminal of the charging unit.

30. The charging unit as claimed in claim 1, wherein each of the plurality of output terminals is configured to be coupled to a laser unit of the semiconductor laser device.

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