The continuity of the operable region is used as a method to determine whether a memory is operable.

Abstract

One method for determining the operability of memory is the continuity of the operable range. This method utilizes three criteria: the offset of the center point of the operable range in each operable range test graph generated by each operable range test must be less than 30%; the operable ranges of the operable range test graphs generated by several operable range tests must be able to overlap continuously to form a safe and operable overlap space (margin); and the overlap range of this overlap space must occupy at least 50% of the operable range area of ​​all operable range test graphs (the definition of this overlap range varies depending on the brand, such as 50%). When all criteria are met, the test is considered passed; if any criterion is not met, the test is considered failed. This method allows for the rapid and accurate identification of defective memory devices under test (DUTs).

Description

Technical Field

[0001] This invention relates to the continuity of an operable range as a function of memory. The judgment method, especially one that uses three judgment criteria to analyze the operable interval test chart and its operable interval range, particularly one that can quickly and accurately identify defective memory under test (DUT). Prior Technology

[0002] With technological advancements, chips must undergo various tests before entering the market. These tests include... These include continuity checks, boundary scan chain tests, automatic test pattern generation (ATPG) tests, burn-in tests, and stress tests.

[0003] Given that IC testing is essential to verify the stability of the design across all process corners, and To help improve yield, it is essential to develop a testing solution that can be used to optimize processes, designs, and final verification. Summary of the Invention

[0004] The main objective of this invention is to overcome the aforementioned problems encountered in the prior art and to improve... A method is provided to determine the operability of memory by using three judgment criteria to quickly and accurately determine the continuity of the operable range of a faulty memory element under test.

[0005] To achieve the above objectives, the present invention provides a continuous operable range as a memory. An operable determination method includes at least the following steps: Step 1: Place several device under test (DUT) components on a test socket; Step 2: Activate a measurement unit connected to the test socket. The measurement unit has a test parameter. Based on the test parameter, the measurement unit performs several operability interval tests on the DUT components on the test socket, and stores the state of each operability interval test of each DUT component in a database, while simultaneously transmitting it to an analysis unit. Each operability interval test state includes an operability interval test graph and its operability interval range. The operability interval test graph is drawn by plotting the change in operating voltage and the change in operating timing of each operability interval test. The voltage operating range and timing operating range on the operability interval test graph are defined as the operability interval range, and the midpoint of the operability interval test graph is used as the center point of the operating area; Step 3: The analysis unit receives the... The test analyzes the operational range status of the memory device under test through several operational range tests, and performs three judgment criteria: the offset of the center point of the operational range test map generated by each operational range test must be <30%; the operational range of the operational range test maps generated by several operational range tests must be able to overlap continuously to form a safe and operable overlap space (margin); and the overlap range of the overlap space must occupy at least 50% of the operational range area of ​​all operational range test maps. When all judgment criteria are met, the test is considered passed. If any judgment criterion is not met, the test is considered failed. An analysis result is generated accordingly. Step four: The analysis result is stored in the database and simultaneously transmitted to an output unit for direct display, or output to an electronic device for remote display through a communication interface.

[0006] In the above embodiments of the present invention, the output unit is electrically connected to the analysis unit. The analysis unit is electrically connected to the measurement unit and the database, and is used to receive or retrieve the status of the memory devices under test for several operational interval tests from the measurement unit or the database.

[0007] In the above embodiments of the present invention, the memory elements under test are integrated circuits. (Integrated circuit, IC) chip, or implemented in a modular form.

[0008] In the above embodiments of the present invention, the operable interval test graph is a two-dimensional graph. (2-dimensional, 2-D) or three-dimensional (3-D) graph.

[0009] In the above embodiments of the present invention, the measurement unit provides a reference voltage (VREF). The power supply voltage (VDD) and operating timing are used as test parameters to perform tests on these memory devices under test. Perform several operational interval tests to obtain these operational interval test maps and their several operational interval ranges, and stack consecutive 2-D operational interval test maps to form a 3-D operational interval test map.

[0010] In the above embodiments of the present invention, the output unit is a tablet computer, a notebook computer, or... Display screen.

[0011] In the above embodiments of the present invention, the electronic device is a smartphone, a tablet computer, etc. Laptop, projector, or display screen.

[0012] In the above embodiments of the present invention, the communication interface is an interface circuit, a Wi-Fi transmission interface, Infrared transmission interface or Bluetooth communication interface. Simple Explanation of the Diagram

[0013] Figure 1 is a flowchart of the present invention. Figure 2 is a block diagram of the present invention. Figure 3 is a schematic diagram of the operable range test diagram of the present invention. Figure 4 is a schematic diagram of the operable interval offset when comparing several operable interval test charts according to the present invention. Figure 5 is a schematic diagram comparing the area of ​​the operable interval in two operable interval test charts according to the present invention. Figure 6 is a schematic diagram of the present invention, which shows how several 2-D operable interval test charts are stacked consecutively to form a 3-D operable interval test chart. Implementation

[0014] Please refer to Figures 1 through 6, which are schematic diagrams of the process of this invention. The invention includes a block diagram, a diagram of the operable interval test chart, a diagram comparing the operable interval offset of several operable interval test charts, a diagram comparing the operable interval area of ​​two operable interval test charts, and a diagram of stacking several 2-D operable interval test charts to form a 3-D operable interval test chart. As shown in the figures: This invention is a method for determining the operability of memory based on the continuity of operable intervals, implemented by a memory operable interval normal operation determination device, which includes a test base 1, several device under test (DUT) elements 2, a measurement unit 3, an analysis unit 4, and an output unit 5. This method for determining the operability of memory based on the continuity of operable intervals includes the following steps: Step 1s1: Place the several memory components 2 to be tested on the test base 1. Step 2 s2: Start the measurement unit 3 connected to the test base 1. The measurement unit 3 has a test parameter. The measurement unit 3 performs several operable range tests on the memory components 2 under test on the test base 1 according to the test parameter, and stores the state of each operable range test of each memory component 2 under test in a database 31, and transmits it to the analysis unit 4. The state of each operable range test includes an operable range test diagram and its operable range. The operable range test diagram is drawn by plotting the change of operating voltage and the change of operating timing of each operable range test. The voltage operating range and timing operating range on the operable range test diagram are defined as the operable range, and the midpoint of the operable range test diagram is used as the center point of the operating area. Step 3 (s3): The analysis unit 4 receives the status of several operational interval tests of the memory components under test 2 and performs three judgment criteria: the offset of the center point of the operational interval test map generated by each operational interval test must be <30%; the operational interval ranges of the operational interval test maps generated by several operational interval tests must be able to continuously overlap each other to form a safe and operable overlapping space (margin); and the overlapping range of the overlapping space must occupy at least 50% of the operational interval area of ​​all operational interval test maps (the judgment criteria for this overlapping range may vary depending on the brand, such as 50%). When all judgment criteria are met, the test is considered passed. If any judgment criterion is not met, the test is considered failed, and an analysis result is generated accordingly. Step 4: The analysis results are stored in the database 31 and simultaneously transmitted to an output unit 5 for direct display, or output to an electronic device 6 for remote display via a communication interface 41. If so, The continuity of a new operational range, constructed through the aforementioned disclosed process, serves as a criterion for the operability of memory. Determine the method.

[0015] In application, this invention places several memory elements 2 to be tested on the test socket 1. The memory devices under test 2 can be integrated circuit (IC) chips or modular implementations. A reference voltage (VREF), a power supply voltage (VDD), and operating timing are provided by the measurement unit 3 as test parameters. Assuming VREF = 0.75 VDD, 0.5 VDD, and VDD = 0.9 V, 1.1 V, 1.3 V, the operational range of these memory devices under test 2 is tested. Each memory device under test 2 will generate its own two-dimensional (2-D) operational range test chart and its operational range. As shown in Figure 3, the operational range test chart is obtained by plotting changes in operating voltage and operating timing. In the figure, plus signs (+) represent operational areas, dots (…) represent inoperable areas, and the two arrows inside the figure represent the operational range, i.e., the operating range of the voltage and the operating range of the timing. The circled area in the center of the graph represents the center point of the operational range. After several operational interval tests, several operational interval test charts and their operational interval ranges can be obtained. These are then stacked in succession to form a three-dimensional (3-D) operational interval test chart, as shown in Figure 6.

[0016] Analysis unit 4 receives and analyzes the memory elements under test 2 after passing through the operable area several times. The operational interval test diagram and its operational interval range after the interval test. The following three criteria are used as the basis for judgment: 1. The operable interval test charts generated by each operable interval test should be similar, that is, the offset of the center point of the operable interval should be less than 30%. As shown in the upper part of Figure 4, the operable interval test charts have the center point of the operable interval not offset by more than 30% on both the X and Y axes, indicating that their operable intervals are similar; while the operable interval test chart at the bottom of the figure has the center point of the operable interval offset by more than 30% on the X axis, indicating that it is not in the similarity zone. 2. The operable interval ranges of the operable interval test charts generated from several operable interval tests should be able to overlap continuously to create a safe and operable overlap space (margin). 3. The overlap range of this overlapping space must occupy at least the area of ​​the operable intervals of all operable interval test maps. More than 50%. As shown in Figure 4, the areas of the operable intervals for all operable interval test charts are respectively 231, 235, and 237 are all above 50%; in contrast, Figure 5 shows operable interval areas of 235 and 65 respectively, indicating that the operable interval area of ​​the operable interval test chart on the right is <50%.

[0017] When all the above criteria are met, the test is considered passed. If any of them are not met, the test is considered passed. If a judgment criterion is not met, the test fails, and an analysis result is generated. This analysis result can be stored in the database 31 and displayed directly by the output unit 5, or output to the electronic device 6 for remote display via the communication interface 41. The judgment process of the analysis unit 4 is as follows:

[0018] Each memory element under test 2 will undergo several operational range checks. If a single memory element under test... If the operational range test pattern of memory element 2 is different each time it is tested, or if its operational range is offset, the test fails. If the operational range test patterns of a single memory element 2 are similar each time (i.e., operational range offset <30%), and the operational range is consistent, it means that this parameter is feasible (for example, assuming the voltage is 356 voltage in 512, ±10% is an acceptable range). Other memory elements 2 under test are tested in the same way. When integrated, the operational ranges of these operational range test patterns must have a safe overlap space (margin). If there is no overlap, the test fails. Finally, the overlap space must be large enough, occupying at least 50% of the operational range area of ​​all operational range test patterns. If the overlap space is too small, the test also fails.

[0019] In one preferred embodiment of the present invention, the output unit 2 is electrically connected to the [missing information - likely a component name]. Analysis unit 4 is electrically connected to measurement unit 3 and database 31, and is used to receive or retrieve the status of several operable interval tests of the memory elements 2 under test from measurement unit 3 or database 31.

[0020] In one preferred embodiment of the present invention, the operable interval test pattern is a 2-D diagram. Alternatively, a 3-D diagram. As shown in Figure 6, a 3-D diagram is formed by stacking all the 2-D operable interval test diagrams consecutively. This diagram integrates the test results of Figures 4 and 5 above. Therefore, except for operable interval test diagrams with operable interval offset >30% and operable interval test diagrams with operable interval area <50%, the operable intervals of the remaining operable interval test diagrams are similar.

[0021] In one preferred embodiment of the present invention, the output unit 5 is a tablet computer or a pen. Notebook computer or display screen.

[0022] In one preferred embodiment of the present invention, the communication interface 41 is an interface circuit. Wi-Fi transmission interface, infrared transmission interface, or Bluetooth communication interface.

[0023] In one preferred embodiment of the present invention, the electronic device 6 is a smartphone. Tablet computers, laptops, projectors, or display screens.

[0024] In summary, this invention relates to the continuity of an operable range as a memory mechanism. The proposed method can effectively improve upon the shortcomings of conventional methods. By utilizing three judgment criteria, it can quickly and accurately identify defective device under test (DUT) memory components. This makes the invention more advanced, practical, and user-friendly, and thus meets the requirements for an invention patent application. Therefore, a patent application is filed in accordance with the law.

[0025] However, the above description is merely a preferred embodiment of the present invention and should not be construed as limiting it. The scope of this invention is defined as follows: therefore, any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the invention specification shall still fall within the scope of this invention.

[0026] 1: Test base 2: Memory element under test 3: Measurement Unit 31: Database 4: Analysis Unit 41: Communication Interface 5: Output Unit 6: Electronic devices s1~s4: Step 1~Step 4

Claims

1. A method for determining the operability of a memory by measuring the continuity of its operable range, comprising at least the following steps: Step 1: Placing several memory devices under test (DUTs) on a test socket; Step 2: Activating a measurement unit connected to the test socket, wherein the measurement unit has a test parameter, and the measurement unit performs several operable range tests on the DUTs on the test socket according to the test parameter, and stores the state of each DUT in each operable range test in a database, and transmits it to an analysis unit, wherein the state of each operable range test includes an operable range test graph and its operable range, and the operable range test graph is plotted by plotting the change in operating voltage and the change in operating timing of each operable range test, the voltage operating range and the timing operating range on the operable range test graph are defined as the operable range, and the midpoint of the operable range test graph is taken as the center point of the operating area; Step 3: The analysis unit receives the status of several operable interval tests of the memory devices under test and performs three judgment criteria: the offset of the center point of the operable interval test map generated by each operable interval test must be <30%; the operable interval ranges of the operable interval test maps generated by several operable interval tests must be able to overlap continuously to form a safe and operable overlapping space (margin); and the overlapping range of the overlapping space must occupy at least 50% of the operable interval area of ​​all operable interval test maps. When all judgment criteria are met, the test is considered passed. If any judgment criterion is not met, the test is considered failed, and an analysis result is generated accordingly. Step 4: The analysis result is stored in the database and transmitted to an output unit for direct display, or output to an electronic device for remote display through a communication interface.

2. The continuity of the operable region as described in claim 1 is used as a method for determining the operability of memory, wherein, The output unit is electrically connected to the analysis unit, which is electrically connected to the measurement unit and the database, and is used to receive or retrieve the status of the memory devices under test for several operational interval tests from the measurement unit or the database.

3. The continuity of the operable region as described in claim 1 is used as a method for determining the operability of memory, wherein, These memory devices under test are integrated circuit (IC) chips or implemented in a modular form.

4. Using the continuity of the operable region as described in claim 1 as a method for determining the operability of memory, wherein, The operational interval test graph is a two-dimensional (2-D) or three-dimensional (3-D) graph.

5. Using the continuity of the operable region as described in claim 1 of the patent application as a method for determining the operability of memory, wherein, The measurement unit provides a reference voltage (VREF), a power supply voltage (VDD), and operating timing as test parameters to perform several operational range tests on the memory devices under test, thereby obtaining the operational range test charts and several operational ranges, and stacking consecutive 2-D operational range test charts to form a 3-D operational range test chart.

6. Using the continuity of the operable region as described in claim 1 of the patent application as a method for determining the operability of memory, wherein, The output unit can be a tablet, laptop, or display screen.

7. Using the continuity of the operable region as described in claim 1 as a method for determining the operability of memory, wherein, The electronic device can be a smartphone, tablet, laptop, projector, or display screen.

8. Using the continuity of the operable region as described in claim 1 of the patent application as a method for determining the operability of memory, wherein, The communication interface can be an interface circuit, a Wi-Fi transmission interface, an infrared transmission interface, or a Bluetooth communication interface.

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