Enhanced error correction code for error detection and correction in multi-level cell-based memory devices

Abstract

This invention provides a method for enhanced error correction codes (ECCs) for error detection and correction in multilevel cell (MLC) based memory devices. The method includes: receiving data encoded using ECC information from the MLC based memory device on an error correction code (ECC) decoder hardware device; calculating the error value and error location of an error in the data using RS error correction codes; determining the error type of the error, wherein the error type includes one of no error, a single symbol error in the data, or multiple symbol errors in the data, and the determination of the error type is based on a +1 / -1 constraint; and rereading the data from the MLC based memory device in response to the error type including multiple symbol errors.

Description

[Technical Field]

[0001] Embodiments of the present invention generally relate to error detection and correction in a multi-level cell-based memory device including a resistive random access memory (RRAM) device, and more specifically, to enhanced error correction codes for error detection and correction in a multi-level cell-based memory device. [Previous Technology]

[0002] A memory device based on multilevel (multi-stage) cells refers to a storage structure having multiple storage cells capable of storing more than one bit of information. A storage cell can consist of a single floating-gate metal-oxide-semiconductor field-effect transistor (MOSFET). An example type of memory device based on multilevel cells is a memristor (also known as resistive random-access memory (RRAM or ReRAM)).

[0003] RRAM is characterized by low power consumption and small size, but as part of its characteristics, it also has a relatively high translation read error rate. Therefore, Error Correction Code (ECC) is used to handle this error rate. One type of error correction code used to control errors, such as those occurring in RRAM and other multilevel cell-based memory devices, is the Reed-Solomon (RS) code. The RS code is an efficient encoding method for correcting errors during data translation. However, the RS code has limitations; in multilevel cell-based memory devices, it can only detect and correct a limited number of symbolic errors. If the number of errors exceeds the upper limit of the RS code's error correction capability, the RS code cannot detect these errors, which may lead to a high error rate when reading data from memory. [Summary of the Invention]

[0004] The following is a simplified summary of the invention to provide a basic understanding of some aspects of the invention. This summary is not a broad overview of the invention. It is intended neither to identify key or critical elements of the invention, nor to describe any scope of a particular implementation of the invention or any scope of the claims. Its sole purpose is to present some concepts of the invention in a simplified form as a preface to the more detailed description that follows.

[0005] According to one or more aspects of the present invention, a method for enhanced error correction code (ECC) for error detection and correction in a multilevel cell-based memory device is provided. The method includes receiving data encoded with ECC information from a multilevel cell-based memory device on an error correction code (ECC) decoding hardware device; calculating an error value and error location using an RS error correction code; determining an error type of the error, wherein the error type includes one of no error, a single symbol error in the data, or multiple symbol errors in the data, wherein determining the error type is based on a +1 / -1 error constraint; and rereading the data from the multilevel cell-based memory device in response to the error type including multiple symbol errors.

[0006] In some embodiments, the multi-level cell-based memory device includes a resistive random access memory (RRAM) device.

[0007] In some embodiments, the method further includes, in response to the error type including a single symbol error, using the error correction circuitry of the ECC decoder hardware to correct the error value at the error location.

[0008] In some embodiments, the method further includes causing the data to be transmitted from the ECC decoder hardware device in response to the error type including no error, wherein the error type includes no error when the error value is equal to 0.

[0009] In some embodiments, determining the error type of the error further includes: performing modulo-2 addition on the error value and message symbols in the data that have positions that are not continuous with the error position; and setting a plurality of error flags to indicate the error type of the plurality of symbol errors in response to the result of the modulo-2 addition being an even non-zero value.

[0010] In some embodiments, the method further includes setting a single error flag to indicate the error type of a single symbol error when the error type is neither no error nor multiple symbol errors.

[0011] In some embodiments, calculating the error value using RS ECC further includes applying a first RS ECC adjoint equation using multiple symbols in the data and at least one message polynomial corresponding to the data.

[0012] In some embodiments, calculating the error location using RS ECC further includes: applying a second RS ECC adjoint equation using a plurality of symbols of the data, the at least one message polynomial corresponding to the data, and Galois field (GF) elements corresponding to each of the plurality of symbols.

[0013] According to one or more aspects of the present invention, an error correction code (ECC) decoder hardware device for error detection and correction in a multilevel cell-based memory device is described. The ECC decoder hardware device includes: error correction hardware circuitry; and error detection hardware circuitry communicatively coupled to the error correction hardware circuitry, wherein the error detection hardware circuitry is configured to: receive data encoded using ECC information from the multilevel cell-based memory device; calculate the error value and error location of errors in the data using RS ECC; determine the error type of the error, wherein the error type includes one of no error, a single symbol error in the data, or multiple symbol errors in the data, and the determination of the error type is based on a +1 / -1 constraint; and in response to the error type including multiple symbol errors, reread the data from the multilevel cell-based memory device.

[0014] In some embodiments, the multi-level cell-based memory device includes a resistive random access memory (RRAM) device.

[0015] In some embodiments, in response to the error type including a single symbol error, the error correction hardware circuitry is used to correct the error value at the error location.

[0016] In some embodiments, in response to the error type including no error, the error detection circuit is further configured to cause the data to be transmitted from the ECC decoder hardware device, and the error type including no error when the error value is equal to 0.

[0017] In some embodiments, the error detection hardware circuit for determining the error type of the error further includes the error detection hardware circuit for: performing modulo-2 addition on the error value and message symbols in the data that have positions discontinuous with the error position; and setting a plurality of error flags to indicate the error type of the plurality of symbol errors in response to the result of the modulo-2 addition being an even non-zero value.

[0018] In some embodiments, when the error type is neither no error nor multiple symbol errors, the error detection hardware circuit is further configured to set a single error flag to indicate the error type of a single symbol error.

[0019] According to one or more aspects of the present invention, a system for enhanced error correction codes for error detection and correction in a multilevel cell-based memory device is described, the system comprising: a multilevel cell-based memory device including a plurality of storage cells configured to store more than a single bit of data; an error correction code (ECC) encoding device for encoding input data using ECC information to generate encoded data transmitted to the multilevel cell-based memory device; and an ECC decoding device for: receiving data encoded using ECC information from the multilevel cell-based memory device; calculating an error value and error location in the data using RS ECC; determining an error type of the error, wherein the error type includes one of no error, a single symbol error in the data, or multiple symbol errors in the data, and determining the error type is based on a +1 / -1 constraint; and rereading the data from the multilevel cell-based memory device in response to the error type including multiple symbol errors.

[0020] In some embodiments, the multi-level cell-based memory device includes a resistive random access memory (RRAM) device.

[0021] In some embodiments, in response to the error type including the single symbol error, the ECC decoding device is used to correct the error value at the error location.

[0022] In some embodiments, in response to the error type including no error, the ECC decoding device is further configured to cause the data to be transmitted from the ECC decoder hardware device, and the error type including no error when the error value is equal to 0.

[0023] In some embodiments, the ECC decoding device for determining the error type of the error further includes the ECC decoding device for: performing modulo-2 addition on the error value and message symbols in the data that have positions discontinuous with the error position; and setting a plurality of error flags to indicate the error type of the plurality of symbol errors in response to the result of the modulo-2 addition being an even non-zero value.

[0024] In some embodiments, when the error type is neither no error nor multiple symbol errors, the ECC decoding device is further configured to set a single error flag to indicate the error type of a single symbol error.

Implementation Method

[0030] This invention provides an enhanced error correction code mechanism for error detection and correction in multi-level cell-based memory devices. A multi-level cell-based memory device can refer to a storage structure having multiple storage cells capable of storing more than one bit of information. A storage cell can consist of a single floating-gate metal-oxide-semiconductor field-effect transistor (MOSFET). An example type of multi-level cell-based memory device is a memristor (also known as resistive random access memory (RRAM or ReRAM)).

[0031] Although embodiments of the present invention may be applicable to any kind of multilevel cell-based memory device, the description of the invention may specifically refer to an example type of multilevel cell-based memory device referred to as a resistive random access memory (RRAM) device. A resistive random access memory (RRAM) device is a passive device with a programmable resistor at both ends. In response to the application of a suitable programming signal, the RRAM device can be electrically switched between a high-resistance state and a low-resistance state. The formation process may refer to programming the RRAM device from an initial state. In a setup process (also known as a “SET” operation), the RRAM device can be programmed from a high-resistance state to a lower-resistance state. In a reset process (also known as a “RESET” operation), the RRAM device can be programmed from a low-resistance state.

[0032] RRAM is characterized by low power consumption and small size, but at the same time, it may have a relatively high conversion read error rate. Therefore, RRAM may utilize Error Correction Code (ECC) to handle this conversion read error rate. Error correction code is a technique used in digital systems to detect and correct errors that occur during data transmission or storage. It involves adding extra information to the data being sent or stored; this extra information is often referred to as parity bits. This extra information allows the receiver to identify and correct errors caused by noise, interference, or other problems that may damage the data. Some examples of error correction codes include Hamming codes, Cyclic Redundancy Code (CRC), and RS codes.

[0033] Embodiments of the present invention focus on RS codes, which are known for their versatility and ability to correct various errors, including burst errors and random errors. RS codes treat blocks of data as a set of finite field elements called symbols. An RS code is defined by RS(n,k), where n is the codeword length and k is the message length, both expressed in terms of the number of symbols. The size m of a symbol is the number of bits in each symbol. For example, for an RS(15,13) code with m = 4, the codeword length is 15 × 4 bits and the message length is 13 × 4 bits. The error-correcting capability of an RS code is defined by t = (n - k) / 2, where t is the number of symbol errors that the RS code can correct. Theoretically, an RS code can detect / correct up to t symbol errors. When the number of symbol errors exceeds t, the RS code can neither correct nor detect the error. Continuing with the example of the RS(15,13) code above, this RS code yields t = 1, meaning it can correct one symbol error.

[0034] The characteristics of RS codes are naturally suited to multi-level memory, such as RRAM, in which data converters (e.g., analog-to-digital converters, ADCs) are used to convert stored information from the analog domain to the digital domain. Such conversions are prone to errors, and RS codes can be used to correct these potential errors. Since each symbol in an RS code can correspond to a single converter (e.g., ADC), RS codes can correct errors in up to t converters.

[0035] Although the characteristics of RS codes are highly compatible with RRAM applications, it is still necessary to keep the t value as small as possible, because the smaller the t value, the fewer parity bits are used. This ultimately translates to a reduction in semiconductor manufacturing costs. However, when the t value is small (e.g., t=1), its error correction capability will be correspondingly limited.

[0036] In embodiments of the present invention, an enhanced ECC method for error detection and correction in multilevel cell-based memory devices is provided. The enhanced error correction code in this embodiment utilizes the error characteristics of data converters (such as ADCs) in multilevel cell-based memory devices to provide an implementation of an RS code with an error detection capability greater than t. The enhanced error correction code method in this embodiment is based on the fact that most errors occurring in data converters (e.g., ADCs) are not random, but rather +1 or -1 errors caused by least significant bit (LSB) precision issues. When the enhanced error correction code of the present invention detects a number of errors greater than t, the RRAM (or other multilevel cell-based memory devices) can be reread (or the data can be reconverted by the data converter (e.g., ADCs)) because the probability of consecutive conversion errors is low. This rereading of the memory can correct t detected errors.

[0037] Embodiments of the present invention provide technical advantages for addressing the problems discussed above. For example, compared to conventional RS codes, the error correction code method of the present invention, which uses enhanced RS codes for error detection and correction, can reduce the error rate of memory devices based on multi-level cells. A further detailed description of the enhanced error correction code method for error detection and correction will be given below in conjunction with Figures 1 to 5.

[0038] FIG1 is a schematic diagram illustrating an example digital system 100 according to some embodiments of the present invention. As shown, the digital system 100 includes a multilevel cell-based memory 120 having ECC protection provided by an ECC encoder 110 and an ECC decoder 130. In embodiments of the present invention, the multilevel cell-based memory 120 may be a memory structure having a plurality of storage units capable of storing more than a single bit of information. As previously mentioned, an example type of multilevel cell-based memory 120 discussed in this invention is RRAM.

[0039] In an embodiment of the present invention, an enhanced ECC method can be implemented for the multi-level cell-based memory 120. As part of the enhanced ECC method, input data 140 can be provided to the ECC encoder 110. The ECC encoder 110 processes the input data using RS codes to add additional information, such as parity bits, to the input data 140, thereby generating encoded data 150. The encoded data 150 can be sent to the multi-level cell-based memory 120 for storage.

[0040] When data is requested from the multilevel cell-based memory 120, as part of the response to the data request, a data converter 125, such as an ADC or other type of data conversion hardware circuit, can convert the encoded data from analog format to digital format. However, this data conversion may introduce errors into the encoded data 150. Therefore, erroneous encoded data 160 may be output from the multilevel cell-based memory 120.

[0041] The ECC decoder 130 can be used to analyze the erroneous encoded data 160 to detect and / or correct any errors found in the erroneous encoded data 160. Then, the ECC decoder 130 can output the decoded data 170.

[0042] In an embodiment of the invention, the ECC decoder 130 is enhanced by an enhanced ECC detector 135. The enhanced ECC detector 135 may be hardware circuitry configured to apply an enhanced RS code to erroneously encoded data 160 to provide error detection capability exceeding t errors. The enhanced ECC detector 135 utilizes the characteristics of errors in the data converter 125 within the multi-level cell memory 120 to provide an implementation of an RS code with an error detection capability greater than t. The aforementioned characteristics include statistical characteristics, i.e., most errors occurring in the data converter 125 are not random but rather +1 or -1 errors due to LSB precision issues. The enhanced ECC detector 135 may utilize the probability of these +1 / -1 errors to implement circuitry to determine when the number of detected errors exceeds the t value of the RS code and set a flag to indicate this occurrence. Accordingly, when the enhanced ECC detector 135 determines that the number of detected errors is greater than t, it can perform a reread of the multi-level cell-based memory 120, which will trigger the data converter 125 to reconvert the data. Since the probability of consecutive conversion errors is low, the reread of the memory can lead to the correction of multiple detected errors (t). Further details of the enhanced ECC detection implemented by the ECC decoder 130 are described below with reference to Figure 2.

[0043] FIG2 is a schematic diagram illustrating an example digital system having a multi-level unit-based memory 210 and an ECC decoder for providing enhanced ECC detection, according to an embodiment of the present invention. In one embodiment, the multi-level unit-based memory 210 is the same as the multi-level unit-based memory 120 described with reference to FIG1, and the ECC decoder 220 is the same as the ECC decoder 130 depicted in FIG1.

[0044] The multi-level unit-based memory 210 can store encoded data containing ECC information, such as parity bits. When the data is requested, a converter 215 in the multi-level unit-based memory 210 can convert the data from a first format to a second format, for example, from analog format to digital format. This conversion process of the converter 215 may introduce errors into the stored data, and therefore, the ECC decoder 220 processes the erroneous encoded data received through the Din port 230.

[0045] The ECC decoder 220 may include hardware circuitry for error correction 222 and enhanced ECC error detection 225. Initially, the enhanced ECC error detection 225 receives erroneous encoded data via the data input (Din) port 230 for analysis using RS codes. In the RS code, when t=1, if the roots of the generator polynomial of the RS code are ⍺0 and ⍺1, the syndrome can be expressed as: where S is the syndrome, n is the index of the received message symbol, m is the message symbol, ⍺ is a Galois field (GF) element, and the summation operation uses modulo-2 addition. The syndrome equation S0 can determine the value of the error in the message symbol, while the syndrome equation S1 can locate the error position.

[0046] Once an error occurs, S becomes non-zero due to the characteristics of the RS code. At t=1, correctable errors only occur when a single error mi is corrupted. However, as mentioned earlier, in the error characteristics of data converters, such as ADCs, the type of error can be constrained to a +1 / -1 type error. This +1 / -1 constraint introduces the following new characteristics to the RS code: First, the error value that occurs is always odd. Second, the modulo-2 addition of any two odd numbers is usually even.

[0047] The above two characteristics enable the enhanced ECC error detection 225 to distinguish between one symbol error and two symbol errors (or multiple symbol errors). Therefore, instead of correcting or detecting only one symbol error (t=1), the enhanced ECC error detection 225 can utilize the above two characteristics to further detect multiple (e.g., two) symbol errors.

[0048] The embodiments of the present invention are based on the +1 / -1 constraint, that is, when the generator polynomial is chosen as g(x) = (xa^0)(xa^1), two +1 / -1 error symbols should not generate a pseudo +1 / -1 error. Based on this theory and the +1 / -1 constraint, multiple (e.g., two or more) symbol errors can be detected by RS codes using the enhanced ECC method described in the embodiments of the present invention.

[0049] For example, for any RS(n, n-2), the generator polynomial can be: g(x) = (xa^0)(xa^1)

[0050] Furthermore, the adjoint equation is as follows:

[0051] Where, , and are the encoded data received by the ECC decoder 220 at the Din port 230. Further, n is the index of the received message symbol, m is the message symbol, ⍺ is a Galois field (GF) element, and the summation operation is modulo-2 addition. All data is received at the same time.

[0052] In an embodiment of the present invention, the enhanced ECC error detection 225 includes hardware circuitry configured to perform the following steps: (1) calculating an error value “e”; (2) finding an error location “y”; and (3) determining an error type. The error value e can be calculated using the above equation S0. The error location can be calculated using the above equation S1.

[0053] Then, the enhanced ECC error detection 225 can determine the error type based on the determined "e" and "y" values, for example, as shown below:

[0054] Based on the determined error type, the enhanced ECC error detection 225 can adopt different processing procedures. As described above, if the e-value indicates no error, the decoded data is output through the ECC decoder 220 at the data output (Dout) port 240. If a single error is determined, the enhanced ECC error detection 225 can set a single error flag 250, which will cause the data to pass through the error correction 222 circuit to correct the single error using RS code. Then, the corrected data can be output from the ECC decoder 220 using the Dout port 240.

[0055] If multiple error types are detected, the enhanced ECC error detection 225 can set a multi-error flag 260. When the multi-error flag 260 is set, it will trigger a data re-request to repeatedly read data from the multilevel cell-based memory 210 270. This data re-read will trigger the converter 215 to re-convert the data, which can correct the data error in most cases. In this way, when two (or more) symbolic errors are detected, the user can perform multiple read operations until no error is detected or a single error is detected. Therefore, two symbolic errors can also be corrected. In some embodiments, the ECC decoder 220 can be programmed to configure the enhanced ECC error detection 225 to implement the process 300 of FIG3 and / or the process 400 in FIG4.

[0056] In the field of digital data transmission and storage, the enhanced ECC method described in this invention offers significant technical advantages, aiming to address common challenges in the real world. When errors frequently manifest as small offsets of +1 / -1 in the original signal, the enhanced ECC encoding of this scheme exhibits superior performance. This innovation has wide applications in various fields, and its improved error detection and correction capabilities bring value to different industries. It not only ensures data accuracy and integrity but also builds a cross-industry reliable data processing mechanism characterized by a fault-tolerant digital ecosystem.

[0057] First, data storage systems, such as hard disk drives (HDDs), solid-state drives (SSDs), and optical storage devices, will significantly benefit from this innovation. The enhanced ECC method in this embodiment of the invention acts as a powerful guardian of data integrity, effectively preventing data corruption during read and write operations. This is particularly important for enterprise data centers and massive data archiving solutions, as these scenarios require the long-term preservation of large data assets while minimizing the risk of errors.

[0058] Secondly, the enhanced ECC method of the present invention can significantly improve the reliability of communication systems. In fields such as wireless communication, satellite links, and fiber optic networks, data transmission often faces interference from complex noise environments. This enhancement scheme can ensure the stability and accuracy of information transmission. This characteristic is particularly important in scenarios where data integrity may affect critical results, such as emergency communication systems or high-frequency trading platforms.

[0059] Furthermore, in the automotive industry, which is gradually moving towards the era of autonomous driving, the enhanced ECC method described in this invention can provide technical support for safety and reliability. In this scenario, error-free data transmission from various sensors and communication systems is crucial.

[0060] Furthermore, the healthcare industry, which increasingly relies on digital devices and networks, can also benefit from the enhanced ECC method described in this invention. Medical devices used for remote patient monitoring and telemedicine heavily depend on accurate data transmission. The enhanced ECC solution described in this invention can effectively ensure the integrity of patient data transmitted over the network, thereby improving the level of medical services and patient treatment outcomes.

[0061] Finally, in the military and defense fields, communication systems and data storage often need to operate in extremely harsh environments. The enhanced ECC method of the present invention can provide them with additional security and reliability guarantees. Even under adverse conditions, this method can still ensure the integrity and security of data, ultimately enhancing the effectiveness of defense operations.

[0062] Figure 3 is a flowchart illustrating an example process 300 of enhanced error correction codes according to some embodiments of the present invention for error detection and correction in a multilevel cell-based storage device. Process 300 can be used to perform RS code-based enhanced ECC error detection operations on a multilevel cell-based memory structure (storage device, storage element, etc.). The multilevel cell-based storage device may be a multilevel cell-based memory 120 employing an enhanced ECC detector 135 as described in conjunction with Figure 1, and / or a multilevel cell-based memory 210 employing an enhanced ECC error detection module 225 as described in conjunction with Figure 2.

[0063] Process 300 begins at 310, which involves reading data from a multi-level cell-based storage device. In one embodiment, the multi-level cell-based storage device is an RRAM device.

[0064] In 320, RS ECC is used to calculate the error value of the data.

[0065] In 330, RS ECC is used to calculate the error location of the data.

[0066] In step 340, the error type of the error is determined. In one embodiment, the error type may be one of no error, a single error in the data, or multiple errors in the data. In one embodiment, the error type is determined based on a +1 / -1 error constraint.

[0067] In 350, in response to an error type including multiple symbol errors, the data read operation of the multi-level unit-based storage device is repeatedly performed.

[0068] FIG4 is a flowchart illustrating an exemplary process 400 for error detection and correction using enhanced error correction codes in a multi-level cell-based memory device according to some embodiments of the present invention.

[0069] Process 400 can perform enhanced ECC error detection operations in a multilevel cell-based memory structure (storage device, storage element, etc.) using RS codes. The multilevel cell-based memory device can be a multilevel cell-based memory 120 using an enhanced ECC detector 135 as described in FIG. 1 and / or a multilevel cell-based memory 210 using an enhanced ECC error detection 225 as described in FIG. 2.

[0070] Process 400 may begin at 410, wherein ECC-encoded data is received from a multilevel cell-based memory device. In one embodiment, the ECC-encoded data includes a plurality of symbols. In one embodiment, the multilevel cell-based memory device is an RRAM device.

[0071] In 420, the error value e of the encoded data is calculated by applying a first RS code association equation using multiple symbols of the ECC encoded data and at least one message polynomial corresponding to the ECC encoded data.

[0072] In 430, the error position y of the ECC-coded data is calculated by using a plurality of symbols, the at least one message polynomial, and GF elements corresponding to each of the plurality of message symbols, by applying a second RS adjoint equation.

[0073] In 440, in response to the error value e being 0, the plurality of symbols are output as an output indicating that no error was detected.

[0074] In 450, in response to determining that the result of modulo-2 addition of one of the error value e and a message symbol having a position discontinuous with the error position y is an even non-zero value, a plurality of error flags are set to indicate that a plurality of errors have been detected in the data. In one embodiment, setting the plurality of error flags triggers a reread of the data from the multilevel cell-based memory element.

[0075] In 460, in response to the absence of a no-error detection and the absence of multiple errors, a single error flag is set to indicate that a single error has been detected in the data. In one embodiment, setting the single error flag triggers an ECC code at position y to correct the error e.

[0076] For ease of explanation, the method of the present invention is described and illustrated as a series of operational steps. However, according to the present invention, these steps may be performed in different orders and / or in parallel, and may be combined with other steps not listed in the present invention. Furthermore, implementing the method described in the present invention does not require performing all illustrated steps. In addition, those skilled in the art should understand and appreciate that the method can also be characterized by a state diagram or a sequence of events, in the form of a set of interrelated states.

[0077] Figure 5 illustrates a block diagram of a machine in the form of a computer system 500, within which a set of instructions can be executed to cause the machine to perform any or more methods discussed in this invention. In alternative embodiments, the machine may be connected (e.g., via a network) to other machines in a local area network (LAN), corporate intranet, corporate extranet, or internet. In a client-server network environment, the machine may act as a server or client machine, or in a peer-to-peer (or distributed) network environment, it may act as a peer machine. The machine may be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential instructions or other instructions) specifying that the machine should take action. Furthermore, although only one machine is shown in the figure, the term "machine" should also be understood to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more methods discussed in this invention.

[0078] The computer system 500 includes a processing device (processor) 602, main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random-access memory (DRAM), such as synchronous dynamic random-access memory (SDRAM) or Rambus dynamic random-access memory (RDRAM), etc.), static memory 506 (e.g., flash memory, static random-access memory (SRAM), etc.), and data storage device 518, which communicate with each other via a bus 508.

[0079] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, processing device 502 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of multiple instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 to perform the operations and steps discussed in this invention.

[0080] The computer system 500 may also include a network interface device 522. The computer system 500 may also include an image display unit (e.g., a liquid crystal display (LCD), a cathode ray tube (CRT), or a touch screen), an alphanumeric input device 512 (e.g., a keyboard), a cursor control device 514 (e.g., a mouse), and a signal generation device 520 (e.g., a speaker).

[0081] The data storage device 518 may include a computer-readable storage medium 524 on which one or more sets of instructions 526 (e.g., software) are stored, embodying any one or more methods or functions described in this invention. During the execution of the instructions 526 by the computer system 500, these instructions may also reside wholly or at least partially in main memory 504 and / or processing device 502, which also constitute computer-readable storage media. The instructions 526 may also be transmitted or received on a network 574 via a network interface device 522.

[0082] In one embodiment, instructions 526 include instructions and / or software libraries for implementing process 300 in FIG3 and / or process 400 in FIG4. Although in the exemplary implementation, computer-readable storage medium 524 is shown as a single medium, the term "computer-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more sets of instructions. The term "computer-readable storage medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of machine-executable instructions and enabling the machine to perform any one or more methods of the present invention. Therefore, the term "computer-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0083] As used in this invention, the terms "about," "about," and "substantially" can refer to normal tolerances in the art, for example, within two standard deviations of the average, within ±20% of the target size in some embodiments, within ±10% of the target size in some embodiments, within ±5% of the target size in some embodiments, within ±2% of the target size in some embodiments, within ±1% of the target size in some embodiments, and even within ±0.1% of the target size in some embodiments. The terms "about" and "about" can include the target size. Unless otherwise expressly stated or obvious from the context, all numerical values ​​described in this invention are modified with "about."

[0084] In this invention, a range includes all values ​​within that range. For example, the range from 1 to 10 may include any single digit, digit combination, subrange, and fraction of 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0085] Many details have been mentioned in the foregoing description of the present invention. However, it is obvious that the present invention can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagrams rather than in specific details in order to highlight the content of the present invention.

[0086] The terms “first,” “second,” “third,” “fourth,” etc., used in this invention are markers used to distinguish different elements and do not necessarily have the ordinal meaning of the numerical code used.

[0087] The terms “example” or “exemplary” as used in this invention mean used as an example, instance, or illustration. Any aspect or design described as “example” or “exemplary” in this invention is not necessarily to be construed as being more preferred or superior than other aspects or designs. Rather, the use of the term “example” or “exemplary” is intended to present the concept in a concrete manner. The term “or” as used in this application is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clearly apparent from the context, “X includes A or B” is intended to mean any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” holds true in any of the foregoing cases. Furthermore, the articles “a” and “an” used in this application and the appended claims should generally be interpreted as “one or more” unless otherwise specified or clearly apparent from the context as referring to the singular form. Throughout this specification, references to "an embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrase "an embodiment" or "one embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment.

[0088] As used in this invention, when an element or layer is referred to as being "above" another element or layer, the element or layer may be directly above the other element or layer, and there may also be intermediate elements or layers. Conversely, when an element or layer is referred to as being "directly above" another element or layer, there are no intermediate elements or layers.

[0089] Although many variations and modifications to the present invention will undoubtedly become apparent to those skilled in the art after reading the foregoing description, it should be understood that any particular embodiment shown and described by way of example is in no way intended to be limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which themselves only enumerate those features considered to be part of the present invention. [Simplified Explanation of the Diagram]

[0025] The invention will be more fully understood through the following detailed description and the accompanying drawings of various embodiments thereof. However, these drawings should not be construed as limiting the invention to the specific embodiments; they are for explanation and understanding only.

[0026] Figure 1 is a schematic diagram illustrating an example digital system according to some embodiments of the present invention;

[0027] Figure 2 is a schematic diagram illustrating an example digital system having a memory based on multi-level units and an error correction code (ECC) decoder for providing enhanced error correction code detection, according to an embodiment of the present invention;

[0028] Figures 3 and 4 are flowcharts illustrating an example process of enhanced error correction codes for error detection and correction in a multi-level cell-based memory device according to some embodiments of the present invention;

[0029] Figure 5 shows an illustrative representation of a machine presented as an example of a computer system according to some embodiments of the present invention.

Claims

1. A method for error correction, characterized in that it includes: On an error correction code (ECC) decoder hardware device, encoded data with ECC information is received from a multilevel cell-based memory device; the error value and error location of an error are calculated using RS error correction codes; the error type of the error is determined, wherein the error type includes one of no error, a single symbol error in the data, or multiple symbol errors in the data, wherein the determination of the error type is based on a +1 / -1 error constraint; and in response to the error type including multiple symbol errors, the data is reread from the multilevel cell-based memory device.

2. The method as described in request item 1, wherein, The memory devices based on multi-level units include resistive random access memory (RRAM) devices.

3. The method as described in request item 1, wherein, It further includes, in response to the error type including a single symbol error, using the error correction circuitry of the ECC decoder hardware to correct the error value at the error location.

4. The method as described in request item 1, wherein, The method further includes causing the data to be transmitted from the ECC decoder hardware in response to the error type including no error, wherein the error type includes no error when the error value is equal to 0.

5. The method as described in claim 4, wherein determining the error type of the error further comprises: Perform modulo-2 addition on the error value and the message symbols in the data that have positions discontinuous with the error position; In response to the result of the modulo 2 addition being an even non-zero value, multiple error flags are set to indicate the error type of multiple sign errors.

6. The method as described in claim 5, wherein, It also includes setting a single symbol flag to indicate the error type of a single symbol error when the error type is neither no error nor multiple symbol errors.

7. The method of claim 1, wherein calculating the error value using RS ECC further comprises applying a first RS ECC adjoint equation using a plurality of symbols in the data and at least one message polynomial corresponding to the data.

8. The method as described in claim 7, wherein calculating the error location using RS ECC further comprises: The second RS ECC adjoint equation is applied using multiple symbols of the data, the at least one message polynomial corresponding to the data, and the Galois field (GF) element corresponding to each of the multiple symbols.

9. A hardware device for an error correction code (ECC) decoder, characterized in that it comprises: Error correction hardware circuitry; An error detection hardware circuit communicatively coupled to the error correction hardware circuit, wherein the error detection hardware circuit is configured to: receive data encoded using ECC information from a multilevel cell-based memory device; calculate the error value and error location of errors in the data using RS ECC; determine the error type of the error, wherein the error type includes one of no error, a single symbol error in the data, or multiple symbol errors in the data, and the determination of the error type is based on a +1 / -1 constraint; and in response to the error type including multiple symbol errors, reread the data from the multilevel cell-based memory device.

10. The ECC decoder hardware device as described in claim 9, wherein, The memory devices based on multi-level units include resistive random access memory (RRAM) devices.

11. The ECC decoder hardware device as described in claim 9, wherein, In response to the error type including a single symbol error, the error correction hardware circuitry is used to correct the error value at the error location.

12. The ECC decoder hardware device as described in claim 9, wherein, In response to the error type including no error, the error detection circuit is further configured to enable the data to be transmitted from the ECC decoder hardware device, and the error type including no error is when the error value is equal to 0.

13. The ECC decoder hardware device of claim 12, wherein the error detection hardware circuitry for determining the error type of the error further comprises the error detection hardware circuitry for: performing modulo-2 addition on the error value and message symbols in the data having positions discontinuous with the error position; and setting a plurality of error flags to indicate the error type of the plurality of symbol errors in response to the result of the modulo-2 addition being an even non-zero value.

14. The ECC decoder hardware device as described in claim 13, wherein, When the error type is neither no error nor multiple symbol errors, the error detection hardware circuit is also used to set a single error flag to indicate the error type of a single symbol error.

15. A system for error correction, characterized in that it comprises: A multi-level cell-based memory device includes multiple storage cells configured to store more than a single bit of data. An error correction code (ECC) encoding device is used to encode input data using ECC information to generate encoded data to be transmitted to the multilevel cell-based memory device; and an ECC decoding device is used to: receive data encoded using ECC information from the multilevel cell-based memory device; The error values ​​and error locations in the data are calculated using RS ECC; the error type is determined, wherein the error type includes one of no error, a single symbol error in the data, or multiple symbol errors in the data, and the error type is determined based on a +1 / -1 constraint; and in response to the error type including multiple symbol errors, the data is reread from the multilevel cell-based memory device.

16. The system as described in claim 15, wherein, The memory devices based on multi-level units include resistive random access memory (RRAM) devices.

17. The system as described in claim 15, wherein, In response to the error type including the single symbol error, the ECC decoding device is used to correct the error value at the error location.

18. The system as described in claim 15, wherein, In response to the error type including no error, the ECC decoding device is further configured to cause the data to be transmitted from the ECC decoding device, and the error type including no error when the error value is equal to 0.

19. The system as described in claim 18, wherein, The ECC decoding device for determining the error type of the error further includes the ECC decoding device for: performing modulo-2 addition on the error value and message symbols in the data that have positions discontinuous with the error position; and setting a plurality of error flags to indicate the error type of the plurality of symbol errors in response to the result of the modulo-2 addition being an even non-zero value.

20. The system as described in claim 19, wherein, When the error type is neither no error nor multiple symbol errors, the ECC decoding device is also used to set a single error flag to indicate the error type of a single symbol error.

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