Display device

Abstract

This application provides a display device. The display device includes: a display area having a plurality of pixels for displaying an image; a non-display area outside the display area, the non-display area including a pad area; a power shorting bar disposed on one side of the display area within the non-display area; a power pad disposed in the pad area; and a bottleneck portion connecting the power shorting bar to the power pad. The power shorting bar has a mesh structure, wherein a plurality of first power lines extending along a first direction are interconnected with a plurality of second power lines extending along a second direction.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, for example, but not limited to, to a display device capable of reducing the concentration of current in a device to which a source voltage is applied. Prior Art

[0002] With the development of an information-based society, the demand for display devices in various forms has increased. Various types of display devices, such as liquid crystal displays (LCDs), plasma display panels (PDPs), quantum dot light emitting displays (QLEDs), and organic light emitting displays (OLEDs), have been widely adopted.

[0003] The descriptions provided in the discussion of the prior art section should not be assumed to be prior art simply because they are mentioned in or related to this section. The discussion of the prior art section may contain information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the invention. Summary of the Invention

[0004] A display device consists of two substrates, with multiple pixels arranged between them to display images. Power is supplied to these pixels via power lines. High voltage can be applied to these power lines, and when current is concentrated in a certain area, it generates significant heat. This can damage the power lines, or static electricity can build up between them and surrounding signal lines, leading to explosions.

[0005] One aspect of the present disclosure is to provide a display device capable of reducing the concentration of current in a component to which a source voltage is applied.

[0006] Another aspect of the present disclosure is to provide a display device that can achieve ESG (Environment / Social / Governance) by reducing greenhouse gases generated during the manufacturing process of the display device.

[0007] Those skilled in the art will clearly understand the following description or learn from the practice of this disclosure other advantages and features of the present disclosure. The objectives and other advantages of the disclosure can be achieved and obtained through the written description of this specification, the scope of the patent claims, and the structures particularly pointed out in the drawings.

[0008] As embodied and broadly described herein, to achieve the aforementioned advantages and other advantages according to the present disclosure, a display device is provided, comprising: a display area having a plurality of pixels disposed therein for displaying an image; a non-display area disposed outside the display area, the non-display area including a pad area; a power shorting bar disposed on one side of the display area within the non-display area; a power pad disposed within the pad area; and a bottleneck portion connecting the power shorting bar to the power pad. The power shorting bar has a mesh structure, wherein a plurality of first power lines extending along a first direction are interconnected with a plurality of second power lines extending along a second direction.

[0009] A display device is also provided herein, comprising: a display area having a plurality of pixels for displaying an image; a non-display area disposed outside the display area, the non-display area including a pad area; a power shorting bar disposed on one side of the display area within the non-display area; a power pad disposed in the pad area; and a bottleneck portion connecting the power shorting bar to the pad. The power shorting bar has a mesh structure, wherein a plurality of first power lines extending in a first direction are interconnected with a plurality of second power lines extending in a second direction. The widths of the first and second power lines are designed to be different.

[0010] It is to be understood that both the foregoing general description of the present disclosure and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. Simple diagram description

[0011] The accompanying drawings are incorporated into and constitute a part of this disclosure to provide a further understanding of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of examples of the present disclosure.

[0012] FIG. 1 is a perspective view schematically showing a display device according to an exemplary embodiment of the present disclosure.

[0013] FIG. 2 is a schematic plan view showing a display panel according to an exemplary embodiment of the present disclosure.

[0014] FIG. 3 is a plan view schematically illustrating an example of sub-pixels included in a display panel according to an exemplary embodiment of the present disclosure.

[0015] FIG. 4 is a circuit diagram illustrating an example of the sub-pixel of FIG. 3 .

[0016] FIG. 5 is a cross-sectional schematic diagram illustrating an example of elements provided in the non-light-transmitting region and the light-transmitting region of FIG. 3 .

[0017] FIG6 is a plan view schematically illustrating a power shorting bar and a bottleneck portion according to an exemplary embodiment of the present disclosure.

[0018] FIG. 7 is an enlarged schematic diagram of region A in FIG. 6 .

[0019] FIG. 8 is a schematic cross-sectional view illustrating an example of a stacked structure of a power shorting bar and a pixel power line.

[0020] FIG. 9 is a schematic diagram illustrating current flows in a power shorting bar and a pixel power line according to an exemplary embodiment of the present disclosure.

[0021] FIG. 10 is a schematic diagram illustrating current flow when the first power line and the second power line have a certain width.

[0022] FIG. 11 is a schematic diagram illustrating current flows in a first power line and a second power line according to an exemplary embodiment of the present disclosure.

[0023] FIG. 12 is a schematic diagram showing an example of current flow when the inflow portion of the bottleneck portion has a certain width.

[0024] FIG. 13 is a schematic diagram illustrating current flow in an inflow portion of a bottleneck portion according to an exemplary embodiment of the present disclosure.

[0025] Throughout the drawings and the specification, unless otherwise specified, the same reference numerals in the drawings should be understood to refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, regions, and elements, as well as their depictions, may be exaggerated for clarity, illustration, and convenience. Implementation Method

[0026] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is provided as an example; however, the order of the steps and / or operations is not limited herein and may be modified according to knowledge in the art, but the steps and / or operations must occur in the specified order. The names of various elements used in the following explanation may be selected solely for convenience in writing the specification and may therefore differ from the names used in the actual product.

[0027] The advantages and features of this specification, as well as their implementation methods, will be explained below with reference to illustrative embodiments and accompanying drawings. However, this disclosure may be embodied in various forms and should not be construed as limited to the exemplary embodiments herein. However, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the methods of the claims.

[0028] The shapes (size, length, width, height, thickness, position, radius, diameter, and area) disclosed in the drawings to describe the embodiments of the present disclosure are merely examples; therefore, the details shown in the drawings do not limit the present disclosure. Similar reference symbols throughout the drawings refer to similar elements. In the following description, when it is believed that a detailed description of related conventional functions or configurations would obscure the key points of the present disclosure, they will not be repeated. Unless the phrase "only" is used, when the phrase "including," "having," or "comprising" is used, additional parts may be included. Unless otherwise specified, terms in the singular may include the plural.

[0029] During the analysis of the component, although not explicitly stated, the component was interpreted as including a margin of error.

[0030] During the construction of a component, although not explicitly stated, the component is constructed to include a range of errors.

[0031] In the description of positional relationships, for example, when the positional relationship between two components is described as "on," "above," "below," and "adjacent," one or more other components may be disposed between the two components, unless more restrictive terms such as "just" or "directly" are used.

[0032] Terms such as "below," "lower," "above," and "upper" may be used herein to describe the relationship between elements or items shown in the drawings. It should be understood that these terms are spatially relative and based on the orientation described in the drawings.

[0033] In descriptions of temporal relationships, for example, when the time sequence is described as "after", "subsequently", "next", and "before", discontinuities may be included unless words such as "immediately" or "directly" are used.

[0034] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of this disclosure.

[0035] The term "at least one" should be understood to include any and all combinations of one or more of the listed items. For example, "at least one of the first, second, and third items" means all combinations of the first, second, and third items, as well as any combination of two or more of the first, second, and third items.

[0036] The features of the various embodiments of the present disclosure may be coupled or combined in part or in whole, and may interact and influence each other in various ways. The exemplary embodiments of the present disclosure may be performed independently of each other or in combination with each other.

[0037] An example of a display device according to the present disclosure is described below with reference to the accompanying drawings. When assigning reference numerals to components in each drawing, identical components, even when shown in different drawings, may be given identical numerals whenever possible. Furthermore, when a detailed description of conventional technology is determined to be unnecessary and obscure to the key points of the present disclosure, the detailed description will be omitted or simplified.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It should be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the art and should not be interpreted as idealized or overly formal unless explicitly defined in the text. For example, the term "component" or "unit" can apply to, for example, an independent circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as understood by one of ordinary skill in the art.

[0039] The following will describe the embodiments of the present disclosure in detail with reference to the accompanying drawings. For ease of explanation, the scales of the components in the drawings may differ from the actual scales, and therefore the present disclosure is not limited to the scales shown in the drawings.

[0040] Fig. 1 is a perspective view of a display device 100 according to an exemplary embodiment of the present disclosure. Fig. 2 is a plan view of a display panel according to an exemplary embodiment of the present disclosure.

[0041] Here, the X-axis may represent a direction parallel to the scan line, the Y-axis may represent a direction parallel to the data line, and the Z-axis may represent a height direction of the display device 100 .

[0042] The display device 100 according to the exemplary embodiment of the present disclosure may be primarily described as being implemented as an organic light-emitting display, but the present disclosure is not limited thereto. Alternatively, the display device 100 may be implemented as a liquid crystal display (LCD), a plasma display panel (PDP), a quantum dot light-emitting display (QLED), a micro light-emitting diode (microLED) display device, or an electrophoretic display.

[0043] As shown in FIG. 1 and FIG. 2 , a display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110 , a source driver integrated circuit (IC) 210 , a flexible film 220 , a circuit board 230 , and a timing controller 240 .

[0044] The display panel 110 may include a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first and second substrates 111, 112 may comprise transparent materials.

[0045] The display panel 110 can be divided into a display area DA, where pixels are arranged to display images, and a non-display area NDA, where no images are displayed. The non-display area NDA may refer to an area outside the display area DA. Various types of signal lines may be disposed in the display area DA and connected to various types of driving circuits.

[0046] A first signal line SL1, a second signal line SL2, and a plurality of sub-pixels may be disposed in the display area DA, and a pad area PA in which pads are disposed and at least one scan driver 205 may be disposed in the non-display area NDA.

[0047] The first signal line SL1 may extend along a first direction (e.g., the Y-axis direction) and may intersect the second signal line SL2 in the display area DA, but this is not a limitation of the present disclosure. The first signal line SL1 may include a pixel power line, a data line, and a common power line. In an exemplary embodiment, the first signal line SL1 may further include a reference line.

[0048] The pixel power line can transmit a first source voltage to a driving transistor in each of the plurality of sub-pixels. The common power line can transmit a second source voltage to a cathode electrode in each of the plurality of sub-pixels. For example, the second source voltage can be a common power source commonly provided to the plurality of sub-pixels.

[0049] The reference line can transmit an initialization voltage (or reference voltage) to a driving transistor of each of the plurality of sub-pixels, and the data line can transmit a plurality of data voltages to the sub-pixels respectively.

[0050] The second signal line SL2 may extend along a second direction (e.g., the X-axis direction) and may intersect the first signal line SL1 in the display area DA, but the present disclosure is not limited thereto. The second signal line SL2 may include a scan line. The scan line transmits a scan signal to a plurality of sub-pixels. Alternatively, the first signal line SL1 may extend along the second direction (e.g., the X-axis direction), and the second signal line SL2 may extend along the first direction (e.g., the Y-axis direction).

[0051] The sub-pixels may be disposed in a region where the first signal line SL1 is disposed or in a region where the first signal line SL1 intersects with the second signal line SL2 and can emit a certain amount of light to display an image.

[0052] A plurality of pads may be provided in the pad area PA. The first substrate 111 may be larger than the second substrate 112, so that a portion of the first substrate 111 may be exposed and not covered by the second substrate 112. Multiple pads, such as power pads and data pads, may be provided in the portion of the first substrate 111 that is exposed and not covered by the second substrate 112.

[0053] The scan driver 205 can be connected to scan lines (also known as gate lines) and can provide scan signals (also known as gate signals). The scan driver 205 can be formed as a gate-in-panel (GIP) type in a non-display area NDA outside one or both sides of the display area DA of the display panel 110, but this is not a limitation of the present disclosure. Alternatively, the scan driver 205 can be manufactured as a driver chip and mounted on a flexible film, and attached to the non-display area NDA outside one or both sides of the display area DA of the display panel 110. Furthermore, the scan driver 205 can be disposed in the display area DA of the display panel 110.

[0054] The source driver integrated circuit 210 can receive digital video data and data control signals from the timing controller 240. Based on the data control signals, the source driver integrated circuit 210 can convert the digital video data into analog data voltages to provide to the data lines. If the source driver integrated circuit 210 is manufactured as a driver chip, the source driver integrated circuit 210 can be mounted on the flexible film 220 in a chip-on-film (COF) or chip-on-panel (COP) package. The timing controller 240 can be implemented using various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a processor, and / or the like, but this does not limit the present disclosure.

[0055] Multiple circuits connecting the bonding pads to the source driver integrated circuit 210 and multiple circuits connecting the bonding pads to the circuit board 230 can be formed in the flexible film 220. The flexible film 220 can be attached to the bonding pads using an anisotropic conductive film, thereby connecting the bonding pads to the circuits on the flexible film 220.

[0056] The circuit board 230 can be attached to the flexible film 220. Multiple circuits can be implemented as driver chips mounted on the circuit board 230. For example, the timing controller 240 can be mounted on the circuit board 230. The circuit board 230 can be a printed circuit board (PCB) or a flexible printed circuit board (FPCB), but this is not a limitation of the present disclosure.

[0057] The timing controller 240 can receive digital video data and timing signals from an external system board. The timing controller 240 can be electrically connected to the scan driver 205 and the source driver integrated circuit 210. Based on the timing signal, the timing controller 240 can generate a scan control signal for controlling the operating timing of the scan driver 205 and a data control signal for controlling the source driver integrated circuit 210. The timing controller 240 can provide the scan control signal to the scan driver 205 and can provide the data control signal to the source driver integrated circuit 210 through one or more predefined interfaces. For example, such an interface can include a low voltage differential signaling (LVDS) interface, an embedded clock point-point interface (EPI), a serial peripheral interface (SPI), etc.

[0058] FIG3 is a schematic plan view illustrating an example of a sub-pixel included in a display panel 110 according to an exemplary embodiment of the present disclosure. FIG4 is a circuit diagram illustrating an example of a sub-pixel in FIG3 . FIG5 is a schematic cross-sectional view illustrating an example of elements disposed in the non-light-transmitting region and the light-transmitting region in FIG3 .

[0059] The display panel 110 according to an exemplary embodiment of the present disclosure may include a display area DA and a non-display area NDA (see FIG. 2 ). The display area DA may include a first area having a plurality of sub-pixels disposed therein and a second area not having a plurality of sub-pixels disposed therein. For example, the display area DA shown in FIG. 3 may include a first area NTA having a plurality of sub-pixels SP1 to SP4 disposed therein and a second area TA not having a plurality of sub-pixels SP1 to SP4 disposed therein. The first area NTA may be a non-light-transmitting area that does not transmit most incident light from the outside, while the second area TA may be a light-transmitting area that transmits most incident light from the outside.

[0060] For example, the light-transmitting area TA may have a light transmittance greater than α%, while the light-non-transmitting area NTA may have a light transmittance less than β%. Here, α may be a value greater than β. Based on the plurality of light-transmitting areas TA, the display panel 110 can make objects or backgrounds disposed on the rear surface of the display panel 110 visible.

[0061] The plurality of sub-pixels SP1 to SP4, the plurality of circuit devices, and the plurality of signal lines SL1 and SL2 may be disposed in the non-transparent area NTA and may be unable to transmit most of the incident light from the outside, but this does not constitute a limitation to the present disclosure.

[0062] The plurality of signal lines may include a first signal line SL1 and a second signal line SL2. The first signal line SL1 may extend along a first direction (e.g., the Y-axis direction) within the non-transparent area NTA. The first signal line SL1 may include a pixel power line VDDL, a data line DL, and a common power line VSSL, but this is not a limitation of the present disclosure. In an exemplary embodiment, the first signal line SL1 may further include a reference line.

[0063] The pixel power line VDDL can transmit a first source voltage to the drive transistor of each of the plurality of sub-pixels SP1 to SP4. The common power line VSSL can transmit a second source voltage to the cathode electrode of each of the plurality of sub-pixels SP1 to SP4. For example, the second source voltage can be a common power supply commonly provided to the plurality of sub-pixels SP1 to SP4. Furthermore, the common power line VSSL can be separated from the pixel power line VDDL, with a light-transmitting area TA therebetween.

[0064] The reference line may transmit an initialization voltage (or reference voltage) to a driving transistor of each of the plurality of sub-pixels SP1 to SP4 , and the data line DL may transmit a plurality of data voltages to the plurality of sub-pixels SP1 to SP4 .

[0065] The second signal line SL2 may extend in a second direction (e.g., the X-axis direction) within the non-transparent area NTA, but this is not a limitation of the present disclosure. The second signal line SL2 may intersect with the first signal line SL1. The second signal line SL2 may include a scan line SCANL. The scan line SCANL can transmit a scan signal to the plurality of sub-pixels SP1 to SP4.

[0066] Each of the sub-pixels SP1 to SP4 may be included in the non-light-transmitting area NTA and may emit light to display an image.

[0067] Subpixels SP1 to SP4 can be, respectively, one of a first subpixel SP1 emitting light of a first color, a second subpixel SP2 emitting light of a second color, a third subpixel SP3 emitting light of a third color, and a fourth subpixel SP4 emitting light of a fourth color, but this is not a limitation of the present disclosure. For example, subpixels SP1 to SP4 can be one of a first subpixel SP1 emitting red light, a second subpixel SP2 emitting green light, a third subpixel SP3 emitting blue light, and a fourth subpixel SP4 emitting white light, but this is not a limitation of the present disclosure. Other subpixels can also emit light of different colors, such as cyan, magenta, or yellow. A unit pixel P can include two or more subpixels. For example, a unit pixel P can include a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel SP4. As another example, one unit pixel P can include a first subpixel SP1 and a second subpixel SP2, while another unit pixel P can include a second subpixel SP2 and a third subpixel SP3, but this is not a limitation of the present disclosure. The arrangement order of the sub-pixels SP1 to SP4 may be varied.

[0068] Each of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 may include a circuit device and a light-emitting device. Referring to FIG. 4 , each of the sub-pixels SP1 to SP4 may have a 2T (transistor) 1C (capacitor) structure, including two transistors (a drive transistor DT and a switch transistor ST) and a capacitor Cst, but this is not a limitation of the present disclosure. Each of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 may also include a compensation circuit CC. For example, each of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 may have various structures, such as 3T1C, 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, or 7T2C.

[0069] Each of the driving transistor DT and the switching transistor ST in each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 may include a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are not fixed and can change based on the voltage applied to the gate electrode and the direction of the current. Therefore, one of the source electrode and the drain electrode can be referred to as the first electrode, and the other can be referred to as the second electrode. The driving transistor DT and the switching transistor ST in each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 can use at least one of a polycrystalline silicon semiconductor, an amorphous silicon semiconductor, and an oxide semiconductor, but this does not constitute a limitation of the present disclosure. The driving transistor DT and the switching transistor ST can be a P-type transistor, an N-type transistor, or a combination of P-type and N-type transistors.

[0070] The light-emitting device ED may include an anode electrode connected to a drive transistor DT, a cathode electrode supplied with a second source voltage EVSS via a second power line VSSL, and a light-emitting layer located between the anode and cathode electrodes. The anode electrode may be an independent electrode for each light-emitting device, while the cathode electrode may be a common electrode shared by all light-emitting devices. A low-potential common voltage may be applied to this common electrode. When a drive current is supplied from the drive transistor DT, electrons from the cathode electrode are injected into the light-emitting layer, while holes from the anode electrode are injected into the light-emitting layer. Recombination of the electrons with the holes in the light-emitting layer causes the fluorescent material or phosphorescent material to emit light. Consequently, the light-emitting device ED can emit light with a brightness proportional to the current value of the drive current.

[0071] For example, the anode electrode can be a pixel electrode, and the cathode electrode can be a common electrode, but this does not limit the present disclosure. Conversely, the anode electrode can be a common electrode, and the cathode electrode can be a pixel electrode. For ease of description, the following assumes that the anode electrode is a pixel electrode and the cathode electrode is a common electrode.

[0072] The light emitting layer may include one or more of a hole injection layer (HIL), a hole transmitting layer (HTL), an electron transmitting layer (ETL), and an electron injection layer (EIL), but the present disclosure is not limited thereto.

[0073] In each of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4, a driving transistor DT may be connected between the anode electrode of the light-emitting device ED and a first power line VDDL transmitting a first source voltage EVDD. Here, the first source voltage EVDD may be applied to a first electrode of the driving transistor DT.

[0074] The driving transistor DT may be a transistor for driving the light emitting device ED, and may be controlled based on a voltage applied to its gate electrode to supply current to the light emitting device ED.

[0075] In each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4, a switching transistor ST can be connected between the first node N1 of the driving transistor DT and the data line DL. The switching transistor ST can be controlled by a scan signal Scan provided by a scan line SCANL to apply a data voltage Vdata provided by the data line DL to the first node N1. For example, the switching transistor ST can be turned on in response to the scan signal Scan provided by the scan line SCANL to apply the data voltage Vdata to the first node N1.

[0076] In each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4, a capacitor Cst may be connected to the first node N1 and may be charged by the voltage applied to the first node N1. The capacitor Cst may provide a charging driving voltage for the driving transistor DT. The capacitor Cst may be a storage capacitor.

[0077] The compensation circuit CC can be configured to compensate for the threshold voltage of the driving transistor DT. A capacitor Cst can be connected between the first node N1 and the compensation circuit CC. The compensation circuit CC can be configured with one or more transistors. The compensation circuit CC can include one or more transistors and capacitors, and can be configured in various ways depending on the compensation method. Pixels incorporating the compensation circuit CC can have various structures, such as 3T1C, 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and so on.

[0078] Hereinafter, elements provided in the non-light-transmitting area NTA and the light-transmitting area TA will be described in more detail with reference to FIG. 5 .

[0079] 5 , the display panel 110 according to an exemplary embodiment of the present disclosure may include a first substrate 111 and a second substrate 112 facing each other, and a circuit device, a light-emitting device ED, an encapsulation layer 180, a color filter CF, and a black matrix BM may be disposed between the first substrate 111 and the second substrate 112.

[0080] The circuit device may be disposed in each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4 within the non-transparent area NTA and may include various signal lines, thin film transistors (TFTs), and capacitors. The signal lines may include a pixel power line, a common power line, a scan line, and a data line. The TFTs may include a switching transistor ST and a driving transistor DT. For example, the switching transistor ST may be turned on in response to a scan signal Scan provided via a scan line SCANL, thereby applying a data voltage Vdata to the first node N1 (see FIG. 4 ). The switching transistor may be turned on in response to the scan signal provided to the scan line and may charge the capacitor using the data voltage provided by the data line.

[0081] The driving transistor DT can be turned on based on the data voltage charged in the capacitor Cst (see FIG. 4 ), and can generate a data current (see FIG. 4 ) from a power source provided via the pixel power line VDDL to provide the data current to the first electrode E1 of each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4. The driving transistor DT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0082] Specifically, a light-blocking layer LS can be provided on the first substrate 111. For example, the light-blocking layer LS can be provided on a portion of the first substrate 111. The light-blocking layer LS can be provided to overlap the region where the drive transistor DT is formed, thereby blocking external light from entering the active layer ACT of the drive transistor DT. For example, the light-blocking layer LS can be provided to overlap the drive transistor DT below the drive transistor DT. The display panel 110 including the light-transmitting region TA can be used extensively in environments exposed to the outside rather than to the inside. This can increase the time the display panel 110 is exposed to external light, thereby changing the characteristics of circuit devices such as the transistor DT. This change in the characteristics of the circuit devices can reduce the brightness of the display panel 110, resulting in a darker screen.

[0083] In the display panel 110 according to the exemplary embodiment of the present disclosure, a light-blocking layer LS can be disposed below the driving transistor DT to prevent external light from entering the driving transistor DT. The display panel 110 according to the exemplary embodiment of the present disclosure can prevent the characteristics of the driving transistor DT from being altered and maintain high brightness of the sub-pixels.

[0084] The light blocking layer LS may be formed of a single layer or multiple layers, including a layer of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, but the present disclosure is not limited thereto.

[0085] The buffer layer 120 may be disposed on the light-blocking layer LS. For example, the buffer layer 120 may be disposed on the light-blocking layer LS and a portion of the first substrate 111. The buffer layer 120 can protect the transistor DT from moisture that penetrates the first substrate 111, which easily transmits moisture. To this end, the buffer layer 120 may be included in the non-transparent area NTA and the transparent area TA. The buffer layer 120 may be formed of an inorganic layer, such as silicon oxide (SiOx), silicon nitride (SiNx), or a multilayer thereof, but the present disclosure is not limited thereto.

[0086] The active layer ACT of the driving transistor DT may be disposed on the buffer layer 120. For example, the active layer ACT of the driving transistor DT may be disposed on a portion of the buffer layer 120. The active layer ACT of the driving transistor DT may include a silicon-based semiconductor material or an oxide-based semiconductor material, but the present disclosure is not limited thereto.

[0087] A gate insulating layer 130 may be disposed on the active layer ACT of the driver transistor DT. The gate insulating layer 130 may be included in the non-transparent area NTA and the transparent area TA. The gate insulating layer 130 may be formed of an inorganic layer, such as SiOx, SiNx, or a multilayer thereof, but the present disclosure is not limited thereto.

[0088] The gate electrode GE, source electrode SE, and drain electrode DE of the driving transistor DT may be disposed on the gate insulation layer 130. As shown in FIG5 , the gate electrode GE, source electrode SE, and drain electrode DE of the driving transistor DT may be formed of the same material in the same layer, but the present disclosure is not limited thereto. In another embodiment, the source electrode SE and drain electrode DE of the driving transistor DT may be formed of different materials in a layer different from the gate electrode GE. The source electrode SE and drain electrode DE may be connected to the active layer ACT via a first contact hole CH1 penetrating the gate insulation layer 130.

[0089] The gate electrode GE, source electrode SE and drain electrode DE of the driving transistor DT may be composed of a single layer or multiple layers, including a layer of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or their alloys, but the present disclosure is not limited thereto.

[0090] The first interlayer insulating layer 140 and the second interlayer insulating layer 150 can be disposed on the gate electrode GE, source electrode SE, and drain electrode DE of the driving transistor DT. Specifically, the first interlayer insulating layer 140 can be disposed on the gate electrode GE, source electrode SE, and drain electrode DE of the driving transistor DT, and the second interlayer insulating layer 150 can be disposed on the first interlayer insulating layer 140. To increase the transmittance of the light-transmitting area TA, the first interlayer insulating layer 140 and the second interlayer insulating layer 150 can only be included in the non-light-transmitting area NTA and cannot be included in the light-transmitting area TA. Each of the first interlayer insulating layer 140 and the second interlayer insulating layer 150 can be formed of an inorganic layer, for example, SiOx, SiNx, or a multilayer thereof, but the present disclosure is not limited thereto.

[0091] A planarization layer 160 may be disposed on the second interlayer insulating layer 150 to planarize the step height caused by the driving transistor DT. The planarization layer 160 may be provided to protect the driving transistor DT. The planarization layer 160 may be formed from an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but the present disclosure is not limited thereto. The planarization layer 160 may be disposed in the non-transparent area NTA and may not be disposed in at least a portion of the transmissive area TA. In the display panel 110 according to an exemplary embodiment of the present disclosure, the planarization layer 160 is not provided in the transmissive area TA, thereby enhancing the light transmittance of the transmissive area TA.

[0092] Multiple light-emitting devices ED may be disposed on the planarization layer 160. Each light-emitting device includes a first electrode E1, a light-emitting layer EL, a second electrode E2, and a bank 165. Each of the first electrode E1 and the second electrode E2 may comprise a metal material such as gold (Au), tungsten (W), platinum (Pt), silicon (Si), iridium (Ir), silver (Ag), copper (Cu), nickel (Ni), titanium (Ti), or chromium (Cr), or alloys thereof. Alternatively, each of the first electrode E1 and the second electrode E2 may comprise a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0093] The first electrode E1 may be disposed on the planarization layer 160 and may be electrically connected to the driving transistor DT. Specifically, the first electrode E1 may be connected to one of the source electrode SE or the drain electrode DE of the driving transistor DT via a second contact hole CH2 that penetrates the first interlayer insulating layer 140, the second interlayer insulating layer 150, and the planarization layer 160.

[0094] The first electrode E1 may be included in each of the first to fourth subpixels SP1 to SP4, but not in the light-transmitting area TA. A bank 165 may be provided between adjacent first electrodes E1, so that adjacent first electrodes E1 may be electrically insulated from each other.

[0095] The first electrode E1 may comprise a metal material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), a stacked structure of a silver alloy and ITO (ITO / silver alloy / ITO), a MoTi alloy, or a stacked structure of a MoTi alloy and ITO (ITO / MoTi alloy / ITO). The silver alloy may be an alloy of silver, palladium, and copper. The MoTi alloy may be an alloy of Mo and Ti. The first electrode E1 may be an anode electrode, but the present disclosure is not limited thereto.

[0096] The bank 165 can be disposed on the planarization layer 160. Furthermore, the bank 165 can be formed to cover the edge of the first electrode E1 and expose a portion of the first electrode E1. Thus, the bank 165 can solve the problem of reduced luminous efficiency caused by current concentration at one end of the first electrode E1.

[0097] The bank 165 can define the light-emitting area EA of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4. The light-emitting area EA of each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4 can represent the region where the first electrode E1, the light-emitting layer EL, and the second electrode E2 are stacked in this order. Therefore, holes in the first electrode E1 and electrons in the second electrode E2 can combine in the light-emitting layer EL to produce light. For example, the region where the bank 165 is formed cannot emit light and can therefore be the non-light-emitting area NEA. The region where the bank 165 is not formed and the first electrode E1 is exposed can be the light-emitting area EA. The bank 165 can be disposed in the non-transparent area NTA and cannot be disposed in at least a portion of the light-transparent area TA.

[0098] The bank 165 may be formed of an organic layer (such as an acrylic-based material, an epoxy-based material, a phenolic-based material, a polyamide-based material, or a polyimide-based material), but the present disclosure is not limited thereto. Furthermore, the bank 165 may contain carbon black, but is not limited to carbon black.

[0099] The light-emitting layer EL may be disposed on the first electrode E1. The light-emitting layer EL may include an emission material layer (EML) containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. The light-emitting layer EL may have a multilayer structure. For example, the light-emitting layer EL may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, when a voltage is applied to the first electrode E1 and the second electrode E2, holes and electrons may respectively migrate through the hole transport layer and the electron transport layer to the light-emitting material layer and may combine with each other in the light-emitting material layer to emit light.

[0100] In an exemplary embodiment, the light-emitting layer EL may be a shared layer formed in all sub-pixels SP1 to SP4. For example, the light-emitting layer EL may be a white light-emitting layer that emits white light. In addition to the sub-pixels SP1 to SP4, the light-emitting layer EL may also be formed in the non-light-emitting area NEA between the sub-pixels SP1 to SP4. The light-emitting layer EL may be formed continuously within the sub-pixels SP1 to SP4 and between the sub-pixels SP1 to SP4. Furthermore, the light-emitting layer EL may also be disposed in the light-transmitting area TA and the non-light-transmitting area NTA including the light-emitting area EA and the non-light-transmitting area NEA, but the present disclosure is not limited thereto. Alternatively, the light-emitting layer EL may be patterned and formed only in the non-light-transmitting area NTA including the light-emitting area EA and the non-light-transmitting area NEA.

[0101] In another embodiment, a light-emitting material layer may be formed in each of the first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 in the light-emitting layer EL. A first light-emitting layer emitting a first type of light may be formed in the first sub-pixel SP1, a second light-emitting layer emitting a second type of light may be formed in the second sub-pixel SP2, a third light-emitting layer emitting a third type of light may be formed in the third sub-pixel SP3, and a fourth light-emitting layer emitting a fourth type of light may be formed in the fourth sub-pixel SP4. For example, a green light-emitting layer emitting green light may be formed in the first sub-pixel SP1, a red light-emitting layer emitting red light may be formed in the second sub-pixel SP2, a blue light-emitting layer emitting blue light may be formed in the third sub-pixel SP3, and a white light-emitting layer emitting white light may be formed in the fourth sub-pixel SP4, but the present disclosure is not limited thereto. It is also possible that other sub-pixels emit light of different colors, such as cyan, magenta, or yellow. For example, the light-emitting material layer of the light-emitting layer EL cannot be formed within the light-transmitting area TA. In addition to the light-emitting material layer, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) may be formed in the shared first to fourth sub-pixels SP1 to SP4 and the light-transmitting area TA.

[0102] The second electrode E2 may be disposed on the light-emitting layer EL. The second electrode E2 may be a common layer formed in all sub-pixels SP1 to SP4. In addition to the light-emitting area EA, the second electrode E2 may also be formed in the non-light-emitting area NEA between the sub-pixels SP1 to SP4. The second electrode E2 may be formed continuously within the sub-pixels SP1 to SP4 and between the sub-pixels SP1 to SP4.

[0103] The second electrode E2 can comprise a transparent conductive material (TCO), such as light-transmitting ITO or indium zinc oxide (IZO), or a semi-transparent conductive material, such as magnesium (Mg), silver, or an alloy of Mg and silver. When the second electrode E2 comprises a semi-transparent conductive material, the microcavity can be used to improve luminous efficiency. The second electrode E2 can be a cathode electrode, but the present disclosure is not limited thereto.

[0104] An encapsulation layer 180 may be provided on the light-emitting device ED. The encapsulation layer 180 may be formed on the second electrode E2 to cover the second electrode E2. The encapsulation layer 180 prevents oxygen or water from penetrating into the light-emitting layer EL and the second electrode E2. To this end, the encapsulation layer 180 may include at least one inorganic layer and at least one organic layer. The encapsulation layer 180 may be formed in a structure in which inorganic and organic layers are alternately stacked, but the present disclosure is not limited to this. For example, the encapsulation layer 180 may have a structure in which at least one organic layer is disposed between inorganic layers, but the present disclosure is not limited to this structure.

[0105] A color filter CF may be provided on the encapsulation layer 180. The color filter CF may be patterned and formed in each of the first subpixel SP1, the second subpixel SP2, the third subpixel SP3, and the fourth subpixel SP4. Specifically, the color filter CF may include a plurality of filters, such as a first filter, a second filter, a third filter, and a fourth filter. The first filter may be provided to correspond to the first subpixel SP1, and for example, the first filter may be a red filter that transmits red light. The second color filter may be provided to correspond to the second subpixel SP2, and for example, may be a green filter that transmits green light. The third color filter may be provided to correspond to the third subpixel SP3, and for example, may be a blue filter that transmits blue light. The fourth color filter may be provided to correspond to the fourth subpixel SP4, and for example, may be a white filter that transmits white light. The white filter may include a transparent organic material that transmits white light, but the present disclosure is not limited thereto.

[0106] A black matrix BM can be provided between the color filters CF. The filters are patterned and formed in each of the sub-pixels SP1 to SP4. The black matrix BM can be provided between the sub-pixels SP1 to SP4 to prevent color mixing between adjacent sub-pixels SP1 to SP4. Furthermore, the black matrix BM prevents externally incident light from being reflected by the multiple signal lines provided between the sub-pixels SP1 to SP4.

[0107] Furthermore, a black matrix BM may be disposed between the light-transmitting area TA and the plurality of sub-pixels SP1 to SP4, and may prevent light emitted from each of the plurality of sub-pixels SP1 to SP4 from traveling to the light-transmitting area TA. The black matrix BM may include a light-absorbing material, and for example, may include a black dye that absorbs all light within the visible wavelength range.

[0108] The first substrate 111 including the color filter CF and the black matrix BM can be bonded to the second substrate 112 via a separate adhesive layer 190. For example, the adhesive layer 190 can be an optically clear resin (OCR) layer or an optically clear adhesive (OCA) film.

[0109] Figure 6 is a schematic plan view schematically showing a power shorting rod and a bottleneck portion according to an exemplary embodiment of the present disclosure. Figure 7 is an enlarged schematic view of area A in Figure 6. Figure 8 is a schematic cross-sectional view showing an example of a stacked structure of a power shorting rod and a pixel power line. Figure 9 is a schematic view showing the flow of current in the power shorting rod and the pixel power line according to an exemplary embodiment of the present disclosure. Figure 10 is a schematic view showing the flow of current when the first power line and the second power line have a certain width. Figure 11 is a schematic view showing the flow of current in the first power line and the second power line according to an exemplary embodiment of the present disclosure. Figure 12 is a schematic view showing an example of the flow of current when the inflow portion of the bottleneck portion has a certain width. Figure 13 is a schematic view showing the flow of current in the inflow portion of the bottleneck portion according to an exemplary embodiment of the present disclosure.

[0110] As shown in FIG. 6 , the display panel 110 according to an exemplary embodiment of the present disclosure can be divided into a display area DA, which provides pixels for displaying images, and a non-display area NDA, which does not display images. The non-display area NDA may include a pad area PA, which is provided with a plurality of power pads. The power pads may include a first power pad PAD1 to which a first source voltage EVDD (high-level source voltage) is applied, and a second power pad PAD2 to which a second source voltage EVSS (low-level source voltage) is applied. A flexible film 220 (see figure) may be attached to the first power pad PAD1 and the second power pad PAD2, and may be externally supplied with the first source voltage EVDD (high-level source voltage) and the second source voltage EVSS (low-level source voltage).

[0111] In the display panel 110 according to the exemplary embodiment of the present disclosure, a power shorting bar 610 and a bottleneck portion 620 may be disposed in the non-display area NDA.

[0112] The power shorting bar 610 can be disposed on one side of the display area DA within the non-display area NDA. Specifically, the power shorting bar 610 can be disposed on one of the multiple sides of the display area DA where the bonding pad area PA is disposed. The power shorting bar 610 can be disposed between the display area DA and the bonding pad area PA.

[0113] The power shorting bar 610 may extend in a second direction (e.g., the X-axis direction) between the display area DA and the pad area PA. The power shorting bar 610 may be connected to a plurality of common power lines VSSL disposed in the display area DA and may provide a second source voltage EVSS (low-level source voltage) to these common power lines VSSL.

[0114] Multiple common power lines VSSL may extend in a first direction (e.g., the Y-axis direction) within the display area DA. Multiple common power lines VSSL may be disposed within the non-transparent area NTA, separated from each other (see FIG. 3 ). The multiple common power lines VSSL may extend upward from the display area DA to the non-display area NDA and may be connected to the power shorting bar 610 at one end. The multiple common power lines VSSL and the power shorting bar 610 may be formed within the same layer, but the present disclosure is not limited thereto. The multiple common power lines VSSL and the power shorting bar 610 may be disposed in different layers, for example, and may be connected to the power shorting bar 610 through a contact hole at one end.

[0115] The plurality of common power lines VSSL may be connected to the plurality of light emitting devices ED in the display area DA and may transmit the second source voltage EVSS (low-level source voltage) provided from the power shorting bar 610 to the cathode electrode E2 of each of the plurality of light emitting devices ED.

[0116] The bottleneck portion 620 can be disposed between the power shorting bar 610 and the second power pad PAD2 and can connect the power shorting bar 610 to the second power pad PAD2. The bottleneck portion 620 can contact the power shorting bar 610 on one side and the second power pad PAD2 on the other side. The power shorting bar 610, the bottleneck portion 620, and the second power pad PAD2 can be formed in the same layer from the same material. In other words, the power shorting bar 610, the bottleneck portion 620, and the second power pad PAD2 can be provided as a single unit, but the present disclosure is not limited thereto.

[0117] The bottleneck portion 620 can be formed with a first width W1 that is smaller than the width of the power shorting bar 610 and can be provided with multiple widths. Here, the first width W1 can refer to the length of the side in contact with the power shorting bar 610. The first width W1 can be the width in the second direction (e.g., the X-axis direction). Multiple bottleneck portions 620 can be provided, separated from each other. The multiple bottleneck portions 620 can be respectively connected to the multiple second power pads PAD2 and can receive the second source voltage EVSS (low-level source voltage) from the outside through the multiple second power pads PAD2. The second source voltage EVSS (low-level source voltage) can be applied to the power shorting bar 610 through the multiple bottleneck portions 620 and can be applied to the multiple common power lines VSSL in the display area DA through the power shorting bar 610. The multiple common power lines VSSL can transmit the second source voltage EVSS (low-level source voltage) provided by the power shorting bar 610 to the cathode electrode E2 of each of the multiple light-emitting devices ED.

[0118] As previously described, when the second source voltage EVSS (low-level source voltage) is applied to the power shorting bar 610 and the bottleneck portion 620, current may flow from the power shorting bar 610 to the bottleneck portion 620. For example, because the bottleneck portion 620 has a first width W1 smaller than that of the power shorting bar 610, current may be concentrated in a local area of the bottleneck portion 620. Because a large amount of heat is generated in the area where the current is concentrated, the bottleneck portion 620 may be damaged.

[0119] In the display panel 110 , according to the exemplary embodiment of the present disclosure, the power shorting bars 610 may form a mesh structure, which may reduce the current concentration in the bottleneck portion 620 .

[0120] Specifically, as shown in FIG7 , the power shorting bar 610 can have a mesh structure, wherein a plurality of first power lines 612 extending in a first direction (e.g., the Y-axis direction) are connected to a plurality of second power lines 614 extending in a second direction (e.g., the X-axis direction). The plurality of first power lines 612 and the plurality of second power lines 614 can be provided as a single unit on the same layer. The plurality of first power lines 612 and the plurality of second power lines 614 can be formed from the same material and in the same layer as the gate electrode GE (see FIG5 ) of the drive transistor DT (see FIG5 ).

[0121] The plurality of first power lines 612 may extend between the pad area PA and the display area DA along a first direction (e.g., the Y-axis direction) and be arranged to be separated from each other in a second direction (e.g., the X-axis direction). A portion of the plurality of first power lines 612 may contact the bottleneck portion 620, while another portion of the plurality of first power lines 612 may not. The plurality of first power lines 612 may be grouped into a first group G1, one end of which contacts the bottleneck portion 620, and a second group G2, one end of which does not contact the bottleneck portion 620. The first power lines 612 included in the second group G2 may be arranged to be separated from the bottleneck portion 620. That is, the first power lines 612 included in the first group G1 may contact the bottleneck portion 620 at one end, while the first power lines 612 included in the second group G2 may not contact the bottleneck portion 620 at one end.

[0122] At least one of the first power lines 612 included in the second group G2 and the first power lines 612 included in the first group G1 may have different widths. The width of the first power lines 612 included in the second group G2 may be smaller than the width of at least one first power line 612 included in the first group G1. At least one of the first power lines 612 included in the first group G1 has the second width. Among the first power lines 612 included in the first group G1, those located in areas other than the edge regions may have the second width. The first power lines 612 included in the second group G2 may have a third width that is smaller than the second width. In other words, among the first power lines 612 that do not contact the bottleneck portion 620, the plurality of first power lines 612 that do contact the bottleneck portion 620 may be relatively thin. On the other hand, the majority of the first power lines 612 that contact the bottleneck portion 620 may be relatively thick.

[0123] Resistance can be inversely proportional to cross-sectional area. Therefore, within first power lines 612, resistance can decrease when the cross-sectional area is larger, and increase when the cross-sectional area is smaller. Among the plurality of first power lines, most first power lines 612 in contact with bottleneck portion 620 can have a relatively large second width, thereby creating a larger cross-sectional area and reducing resistance. Current can be inversely proportional to resistance. Therefore, as shown in FIG9 , a relatively large current can flow through the first power lines 612 included in the first group G1.

[0124] On the other hand, the first power lines 612 among the plurality of first power lines 612 that do not contact the bottleneck portion 620 can have a smaller third width, thereby forming a smaller cross-sectional area and increasing resistance. Therefore, as shown in FIG9 , the current flowing through the first power lines 612 included in the second group G2 can be lower than the current flowing through the first power lines 612 included in the first group G1.

[0125] Furthermore, at least some of the first power lines 612 included in the first group G1 can have different widths than other first power lines 612 included in the first group G1. In other words, the plurality of first power lines 612 included in the first group G1 can have different widths. Specifically, the first power lines 612 included in the first group G1 can be grouped into a first subgroup G11 disposed in a first region, a second subgroup G12 disposed in a second region to one side of the first region, and a third subgroup G13 disposed in a third region to the other side of the first region.

[0126] The second subgroup G12 may include the first power line 612 located at the leftmost outer portion of the plurality of first power lines 612 in the first group G1. The second subgroup G12 may include only one first power line 612 located at the leftmost outer portion of the plurality of first power lines 612 in the first group G1, but the present disclosure is not limited thereto. The second subgroup G12 may include the plurality of first power lines 612 located in the left edge region of the first power lines 612 in the first group G1.

[0127] The third subgroup G13 may include the first power line 612 located at the rightmost outer portion of the plurality of first power lines 612 in the first group G1. The third subgroup G13 may include only one first power line 612 located at the rightmost outer portion of the plurality of first power lines 612 in the first group G1, but the present disclosure is not limited thereto. The third subgroup G13 may include the plurality of first power lines 612 located in the right edge region of the first power lines 612 in the first group G1.

[0128] The first power lines 612 included in the first subgroup G11 may have a different width than the first power lines 612 included in the second subgroup G12 and the third subgroup G13. The first power lines 612 included in the second subgroup G12 and the third subgroup G13 may have a smaller width than the first power lines 612 included in the first subgroup G11.

[0129] The first power lines 612 included in the first subgroup G11 may have a second width. The first power lines 612 included in the second subgroup G12 and the third subgroup G13 may have a fourth width that is smaller than the second width. In an exemplary embodiment, the first power lines 612 included in the second subgroup G12 and the third subgroup G13 may have the same width as the first power lines 612 included in the second group G2. In other words, the fourth width of the first power lines 612 included in the second subgroup G12 and the third subgroup G13 may be equal to the third width of the first power lines 612 included in the second group G2. In other words, the width of the first power lines 612 included in the first subgroup G11 may be greater than the widths of the first power lines 612 included in the second subgroup G12, the third subgroup G13, and the second group G2.

[0130] The plurality of second power lines 614 may extend between the pad area PA and the display area DA along a second direction (e.g., the X-axis direction) and may be spaced apart from each other in a first direction (e.g., the Y-axis direction). A portion of the topmost second power line 614 may contact the bottleneck portion 620, while other portions of the topmost second power line 614 may not contact the bottleneck portion 620.

[0131] Some of the plurality of second power lines 614 may have different widths than the other second power lines 614. The width of a second power line 614 separated by a first distance from the bottleneck 620 may be different than the width of a second power line 614 separated by a second distance from the bottleneck 620. The first distance may be smaller than the second distance. For example, a second power line 614 separated by the first distance from the bottleneck 620 may have a fifth width. A second power line 614 separated by the second distance from the bottleneck 620 may have a sixth width that is greater than the fifth width. In other words, a second power line 614 located near the bottleneck 620 may be thinner than a second power line 614 located farther from the bottleneck 620.

[0132] The second power line 614 disposed near the bottleneck 620 can have a smaller fifth width, thereby forming a smaller cross-sectional area and increasing resistance. Therefore, as shown in FIG9 , a relatively low current can flow through the second power line 614 disposed near the bottleneck 620.

[0133] On the other hand, the second power line 614 located farther from the bottleneck 620 can have a relatively larger sixth width, thereby forming a larger cross-sectional area and reducing resistance. Current is inversely proportional to resistance. Therefore, as shown in FIG9 , a relatively higher current can flow through the second power line 614 farther from the bottleneck 620 than through the second power line 614 closer to the bottleneck 620.

[0134] 7 , the widths of the second power lines 614 may gradually increase in a direction away from the bottleneck 620. For example, the current flowing through the second power lines 614 may gradually increase in a direction away from the bottleneck 620.

[0135] In the display panel 110, according to an exemplary embodiment of the present disclosure, the power shorting bar 610 can be formed in a mesh structure configured with multiple first power lines 612 and multiple second power lines 614, and the widths of the multiple first power lines 612 and the multiple second power lines 614 can be designed differently.

[0136] In the display panel 110 according to the exemplary embodiment of the present disclosure, the widths of the plurality of first power lines 612 can be designed differently. Specifically, in the display panel 110 according to the exemplary embodiment of the present disclosure, the first power lines 612 that do not contact the bottleneck portion 620 can be formed as thin first power lines, thereby allowing a relatively low amount of current to flow through the first power lines 612 that do not contact the bottleneck portion 620.

[0137] Furthermore, in the display panel 110 according to an exemplary embodiment of the present disclosure, the first power lines 612 disposed at the outermost portion of the first power lines 612 in contact with the bottleneck portion 620 can be formed as thin first power lines. Current flowing through the first power lines 612 not in contact with the bottleneck portion 620 can flow through the second power lines 614 into the first power lines 612 in contact with the bottleneck portion 620. For example, if the first power lines 612 in contact with the bottleneck portion 620 have the same thickness, as shown in the figure, current can be concentrated in the outermost first power lines 612, which have the shortest distance.

[0138] In the display panel 110 according to the exemplary embodiment of the present disclosure, the outermost first power lines 612 among the first power lines 612 contacting the bottleneck portion 620 can be formed as thin first power lines 612, thereby preventing current from concentrating in the outermost first power lines 612. In the display panel 110 according to the exemplary embodiment of the present disclosure, the first power lines 612 disposed in the central region of the first power lines 612 contacting the bottleneck portion 620 can be formed as relatively thick first power lines 612, thereby allowing current to flow to the first power lines 612 disposed in the central region.

[0139] Furthermore, in the display panel 110 according to the exemplary embodiment of the present disclosure, the widths of the plurality of second power lines 614 can be designed differently. Specifically, in the display panel 110 according to the exemplary embodiment of the present disclosure, the second power lines 614 located near the bottleneck portion 620 can be thin, while the second power lines 614 located farther from the bottleneck portion 620 can be thick. Therefore, the display panel 110 according to the exemplary embodiment of the present disclosure can allow a relatively low amount of current to flow through the second power lines 614 located near the bottleneck portion 620, while allowing a relatively high amount of current to flow through the second power lines 614 located farther from the bottleneck portion 620.

[0140] In the display panel 110 according to the exemplary embodiment of the present disclosure, since the widths of the plurality of first power lines 612 and the plurality of second power lines 614 are designed differently as described above, the current flowing from the plurality of first power lines 612 and the plurality of second power lines 614 to the bottleneck portion 620 can be dispersed, as shown in FIG. 11 .

[0141] Current can flow to the portion of the resistor with the shortest distance. Therefore, if the widths of the plurality of first power lines 612 and the plurality of second power lines 614 are designed to be constant, as shown in FIG10 , current flowing through the first power lines 612 and the second power lines 614 that do not contact the bottleneck 620 can flow to the edge of the bottleneck 620 via the shortest distance. Consequently, current can be concentrated at the edge of the bottleneck 620.

[0142] On the other hand, in the display panel 110 according to the exemplary embodiment of the present disclosure, the widths of the plurality of first power lines 612 and the plurality of second power lines 614 can be designed differently, thus allowing the plurality of first power lines 612 and the plurality of second power lines 614 to have different resistances. In the display panel 110 according to the exemplary embodiment of the present disclosure, the first power lines 612 in contact with the central region of the bottleneck portion 620 and the second power lines 614 located away from the bottleneck portion 620 can have low resistances, as shown in FIG11 . This allows the relatively large current flowing from the common power line VSSL to the power shorting bar 610 to be dispersed and flowed in the central region of the bottleneck portion 620. Therefore, in the display panel 110 according to the exemplary embodiment of the present disclosure, the current concentration at the edge region of the bottleneck portion 620 can be reduced.

[0143] Furthermore, in the display panel 110 according to the exemplary embodiment of the present disclosure, the power shorting bars 610 are formed in a mesh structure, thereby reducing metal stress, compared to a case where the power shorting bars 610 are provided as a common electrode. The power shorting bars 610 may overlap with the pixel power line VDDL in at least a partial region. The pixel power line VDDL may extend upward from the display area DA to the pad area PA in the non-display area NDA and may be connected to the first power pad PAD1. The pixel power line VDDL may transmit the first source voltage EVDD (high-level source voltage) provided by the first power pad PAD1 to the anode electrode E1 of each of the plurality of light-emitting devices ED disposed within the display area DA. The pixel power line VDDL may overlap with the power shorting bar 610 in at least a partial region. For example, the pixel power line VDDL and the power shorting bar 610 may have a stacked structure as shown in FIG8 . The power shorting bar 610 and the gate electrode GE (see FIG5 ) of the driving transistor DT (see FIG5 ) may be formed on the same layer and of the same material. Similarly, the pixel power line VDDL and the light blocking layer LS can be formed on the same layer using the same material (see FIG5 ). For example, a gate insulating layer 130 and a buffer layer 120 can be provided between the power shorting bar 610 and the pixel power line VDDL to insulate the power shorting bar 610 from the pixel power line VDDL.

[0144] When the power shorting bar 610 is configured as a planar electrode, the metal stress generated by the power shorting bar 610 increases, thus limiting the reduction in the thickness of the insulating layer between the power shorting bar 610 and the pixel power line VDDL. If the insulating layer between the power shorting bar 610 and the pixel power line VDDL is made thin, the surrounding insulating layer and the gap between the power shorting bar 610 and the pixel power line VDDL may be damaged by the metal stress. In the display panel 110 according to the exemplary embodiment of the present disclosure, the mesh structure of the power shorting bar 610 reduces the metal stress generated by the power shorting bar 610 and prevents damage caused by the metal stress. Furthermore, in the display panel 110 according to the exemplary embodiment of the present disclosure, the thickness of the insulating layer between the power shorting bar 610 and the pixel power line VDDL can be reduced, thereby reducing the overall thickness of the display panel 110.

[0145] Furthermore, in the display panel 110 according to the exemplary embodiment of the present disclosure, since the power shorting bar 610 has a mesh structure, the overlapping area between the power shorting bar 610 and the pixel power line VDDL can be reduced, thereby preventing static electricity explosion from occurring between the power shorting bar 610 and the pixel power line VDDL.

[0146] The bottleneck portion 620 can be disposed between the power shorting bar 610 and the second power pad PAD2 and can connect the power shorting bar 610 to the second power pad PAD2. The bottleneck portion 620 can contact the power shorting bar 610 on one side and the second power pad PAD2 on the other side. A plurality of bottleneck portions 620 can be provided, and the plurality of bottleneck portions 620 can be spaced apart from each other in the second direction (e.g., the X-axis direction).

[0147] Each of the plurality of bottleneck portions 620 may include an inflow portion 622 , which contacts the power shorting bar 610 , thereby allowing current to flow through the inflow portion 622 and a connection portion 624 connected to the second power pad PAD2 .

[0148] The inflow portion 622 may be connected to the power shorting bar 610 on one side. The inflow portion 622 may contact a portion of the plurality of first power lines 612, and current may flow in from some of the first power lines 612 in contact with the inflow portion 622. Furthermore, the inflow portion 622 may contact a portion of the uppermost second power line 614 among the plurality of second power lines 614, and current may flow in from the uppermost second power line 614 in contact with the inflow portion 622.

[0149] The inlet portion 622 may include a recessed portion 623 formed on at least one side of the inlet portion so as to be recessed toward the center line CL. The inlet portion 622 may include a recessed portion 623 disposed on at least one side of the inlet portion and located between the side surface contacting the power shorting bar 610 and the side surface contacting the connecting portion 624.

[0150] For example, the inflow portion 622 may include a first recessed portion 623a formed on the left edge of the inflow portion, recessed toward the centerline CL, and a second recessed portion 623b formed on the right edge of the inflow portion, recessed toward the centerline CL. The first recessed portion 623a and the second recessed portion 623b may be formed in a streamlined or curved circular shape. For example, the first recessed portion 623a and the second recessed portion 623b may have a semicircular shape.

[0151] Because the recess 623 is formed on at least one side of the inflow portion 622, the inflow portion 622 may include a first region A1 whose width gradually decreases from the side in contact with the power shorting bar 610 toward the second power pad PAD2. In an exemplary embodiment, the inflow portion 622 may further include a second region A2 whose width gradually increases from the first region A1 toward the second power pad PAD2.

[0152] In the display panel 110 according to an exemplary embodiment of the present disclosure, the width of the inflow portion 622 is not constant. The display panel 110 may include a first region A1 whose width gradually decreases from the side in contact with the power shorting bar 610 toward the second power pad PAD2. This allows the current flowing into the edge of the inflow portion 622 to be dispersed. For a more detailed description, as shown in FIG12 , the inflow portion 622 of the bottleneck portion 620 may have a constant width. That is, the inflow portion 622 of the bottleneck portion 620 may be in contact with the power shorting bar 610 in a vertical direction. For example, the inflow portion 622 of the bottleneck portion 620 may be perpendicular to the second power line 614 of the power shorting bar 610. For example, the current flowing into the inflow portion 622 may be concentrated at the edge of the inflow portion 622.

[0153] To provide an example, current flowing through the first power line 612a that does not contact the inflow portion 622 of the bottleneck portion 620 can flow along the path with the shortest distance to the second power pad PAD2. Therefore, current flowing through the first power line 612a that does not contact the inflow portion 622 of the bottleneck portion 620 can flow along the recess 623 or the edge of the inflow portion 622 toward the connection portion 624.

[0154] Furthermore, the current flowing through at least one of the first power lines 612b and 612c disposed in the edge region between the first power lines 612 in contact with the inlet portion 622 of the bottleneck portion 620 can flow in a direction that forms a straight line with respect to the first power lines 612b and 612c. Furthermore, because the inlet portion 622 is perpendicular to the power shorting bar 610, the first path, in which the current flows through the first power lines 612b and 612c to the inlet portion 622 in contact with the power shorting bar 610 and then along the edge of the inlet portion 622, can have the same distance as the second path, in which the current flows in a direction that forms a straight line with respect to the first power lines 612b and 612c. Therefore, a portion of the current flowing through the first power lines 612b and 612c disposed between the first power lines 612 in contact with the inlet portion 622 of the bottleneck portion 620 can flow along the second path, while another portion of the current can flow along the first path shown in FIG. 12 . Therefore, more current may be concentrated at the edge of the inflow portion 622 contacting the power shorting bar 610 (particularly the end of the inflow portion 622 contacting the power shorting bar 610) than at the center of the inflow portion 622, thereby increasing the temperature and damaging the inflow portion 622.

[0155] Furthermore, since the concave portion 623 having a streamlined or curved shape is formed in the inflow portion 622 of the bottleneck portion 620 , the display panel 110 according to the exemplary embodiment of the present invention can disperse current at the edge region of the inflow portion 622 .

[0156] To illustrate, current flowing through the first power line 612a, which is not in contact with the inflow portion 622 of the bottleneck portion 620, can flow along the path with the shortest distance to the second power pad PAD2, thereby flowing along the edge of the inflow portion 622 toward the connection portion 624. However, according to exemplary embodiments of the present disclosure, a curved recess 623 can be provided in the inflow portion 622. Therefore, the first path, in which the current flows through the first power lines 612b and 612c toward the inflow portion 622 in contact with the power shorting bar 610 and then along the edge of the inflow portion 622, is larger than the second path, in which the current flows in a direction that is straight relative to the first power lines 612b and 612c. Therefore, the current flowing through at least one of the first power lines 612b and 612c located in the edge region of the first power line 612 in contact with the inflow portion 622 of the bottleneck portion 620 can flow along the second path rather than the first path. Therefore, the current cannot be concentrated at the end of the side where the inflow portion 622 contacts the power shorting bar 610 and can be dispersed.

[0157] According to an exemplary embodiment of the present disclosure, a display device is provided, comprising: a display area in which a plurality of pixels are arranged to display an image; a non-display area disposed outside the display area, the non-display area including a bonding pad area; a power shorting bar disposed within the non-display area on one side of the display area; a power supply bonding pad area disposed within the bonding pad area; and a bottleneck portion connecting the power shorting bar to the power supply bonding pad. The power shorting bar has a mesh structure, wherein a plurality of first power lines extending along a first direction are interconnected with a plurality of second power lines extending along a second direction.

[0158] In the present disclosure, a power shorting bar can be formed in a mesh structure configured with multiple first power lines and multiple second power lines, and the widths of the multiple first power lines and the multiple second power lines can be designed differently, thereby reducing the current concentration in the edge area of the bottleneck portion.

[0159] Furthermore, in the present disclosure, compared to the case where the power shorting bar is configured as a planar electrode, metal stress can be reduced, thereby preventing damage caused by metal stress.

[0160] Furthermore, in the present disclosure, the thickness of the insulating layer between the power shorting bar and the pixel power line can be reduced, thereby also reducing the total thickness of the display panel.

[0161] In addition, in the present disclosure, the occurrence of static electricity explosion between the power short-circuit bar and the pixel power line can be prevented.

[0162] Furthermore, in the present disclosure, a concave portion having a streamlined or curved shape can be formed in the inlet portion of the bottleneck portion, thereby dispersing the current in the edge region of the inlet portion.

[0163] Furthermore, due to the reduced defect rate of the power shorting bar, the present disclosure can reduce manufacturing process costs, shorten manufacturing process time, and reduce production energy. Furthermore, the present disclosure can reduce greenhouse gas emissions caused by the manufacturing process, thereby implementing environmental, social, and governance (ESG) issues.

[0164] The aforementioned features, structures, and effects are included in at least one embodiment of this disclosure, but are not limited to just one embodiment. Furthermore, those skilled in the art may achieve the features, structures, and effects of at least one embodiment of this disclosure by combining or modifying other embodiments. Therefore, content related to such combinations and modifications should be construed as falling within the scope of this disclosure.

[0165] It is apparent to those skilled in the art that various modifications and variations of the present disclosure may be made without departing from the spirit or scope of the disclosure. Therefore, it is intended that the present disclosure cover modifications and variations of the present disclosure provided that such modifications and variations come within the scope of the appended patent claims and their equivalents.

[0166] These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and patent claims, but should be construed to encompass all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by what is disclosed.

[0167] 100: Display device 110: Display panel 111: first substrate 112: Second substrate 120: buffer layer 130: Gate insulation layer 140: first interlayer insulating layer 150: Second interlayer insulating layer 160: Planarization layer 165: Embankment 180: Encapsulation layer 190: Adhesive layer 205: Scan driver 210: Source driver integrated circuit 220: Flexible film 230: Circuit board 240: Timing controller 610: Power shorting bar 612, 612a, 612b, 612c: First power line 614: Second power line 620: Bottleneck 623: concave part 623a: first recess 623b: Second recess A1: First Area A2: Second Area G1: Group 1 G11: First subgroup G12: Second subgroup G13: The third subgroup G2: Group 2 DA: Display Area NDA: Non-display area TA: Second area / light-transmitting area NTA: First area / non-transparent area EA:Emitting Area NEA: Non-Emitting Area CF: Color filter BM: Black Matrix PA: Pad area PAD1: First power pad PAD2: Second power pad ACT: Active Layer GE: Gate Electrode SE: Source electrode DE: Drain electrode ED: Light-emitting device EVDD: First source voltage EVSS: Second source voltage VDDL: Pixel power line VSSL: common power line SL1: First signal line SL2: Second signal line SP1: First sub-pixel SP2: Second sub-pixel SP3: The third sub-pixel SP4: The fourth sub-pixel EL: light-emitting layer E1: First electrode / anode electrode E2: Second electrode / cathode electrode P: unit pixel SCANL: Scan line DL: Data Line LS: Light blocking layer CL: Center Line CC: Compensation circuit DT: driver transistor ST: Switching transistor Cst: capacitor W1: first width N1: first node Vdata: data voltage Scan: Scan signal

Claims

1. A display device comprising: a display area having a plurality of pixels for displaying an image; a non-display area disposed outside the display area, the non-display area including a pad area; a power shorting bar disposed on one side of the display area within the non-display area; a power pad located within the pad area; and a bottleneck portion for connecting the power shorting bar to the power pad, wherein the power shorting bar has a mesh structure in which a plurality of first power lines extending along a first direction are interconnected with a plurality of second power lines extending along a second direction, wherein the second power lines have different widths.

2. The display device as claimed in claim 1, wherein the width of the second power line that is a first separation distance from the bottleneck is less than the width of the second power line that is a second separation distance from the bottleneck, and the first separation distance is less than the second separation distance.

3. The display device as claimed in claim 1, wherein the second power lines have a gradually increasing width in the direction of increasing distance from the bottleneck.

4. The display device as claimed in claim 1, wherein the bottleneck portion is in contact with some of the first power lines and not in contact with the other first power lines.

5. The display device as claimed in claim 1, wherein at least some of the first power lines have different widths.

6. The display device as claimed in claim 1, wherein the first power lines are grouped into a first group and a second group, one end of the first group is in contact with the bottleneck, one end of the second group is not in contact with the bottleneck, and the width of each of the plurality of first power lines included in the second group is different from the width of at least one of the plurality of first power lines included in the first group.

7. The display device as claimed in claim 6, wherein the width of each of the first power lines included in the second group is smaller than the width of at least one of the first power lines included in the first group.

8. The display device as claimed in claim 6, wherein the first power lines included in the first group are grouped into a first subgroup disposed in a first region, a second subgroup disposed in a second region disposed on one side of the first region, and a third subgroup disposed in a third region disposed on the other side of the first region, wherein, The width of each of the plurality of first power lines included in the first subgroup is different from the width of each of the plurality of first power lines included in the second subgroup and the third subgroup.

9. The display device as claimed in claim 8, wherein the second subgroup includes the first power line disposed on the leftmost outer portion of the first power lines included in the first group, and the third subgroup includes the first power line disposed on the rightmost outer portion of the first power lines included in the first group.

10. The display device as claimed in claim 8, wherein the width of each of the first power lines included in the first subgroup is greater than the width of each of the first power lines included in the second subgroup and the third subgroup.

11. The display device as claimed in claim 8, wherein the width of each of the first power lines included in the second subgroup and the third subgroup is the same as the width of each of the first power lines included in the second group.

12. The display device as claimed in claim 1, wherein the bottleneck includes an inflow portion in contact with the power shorting bar, thereby allowing a current to flow in through the inflow portion.

13. The display device as claimed in claim 12, wherein the inflow portion is in contact with some of the first power lines, and a current flows in from the first power lines in contact with the inflow portion.

14. The display device as claimed in claim 12, wherein the inflow portion contacts a partial area of ​​an uppermost second power line of the second power lines, and a current flows in from the uppermost second power line that contacts the inflow portion.

15. The display device as claimed in claim 12, wherein the inflow portion includes a region whose width gradually decreases from one side in contact with the power shorting bar toward the power pad.

16. The display device as claimed in claim 12, wherein the inflow portion includes a recess formed recessedly on at least one side of the inflow portion facing a centerline of the bottleneck portion.

17. The display device as claimed in claim 16, wherein the recess includes a streamlined shape or a curved shape.

18. The display device as claimed in claim 1, further comprising a plurality of common power lines extending upward from the display area along the first direction to the non-display area, one end of each of the common power lines being connected to the power shorting bar.

19. The display device as claimed in claim 18, wherein the display area includes a plurality of light-transmitting areas for transmitting external light and a non-light-transmitting area between adjacent light-transmitting areas, and each of the common power lines is disposed in the non-light-transmitting area.

20. The display device as claimed in claim 19 further includes a light-emitting device comprising an anode electrode, a light-emitting layer and a cathode electrode, the light-emitting device being disposed in the non-transparent area, and each of the common power lines being configured to transmit a source voltage to the cathode electrode of the light-emitting device.

21. The display device as claimed in claim 18, wherein the common power lines are respectively connected to the first power lines of the power shorting bar.

22. The display device as claimed in claim 21, wherein the common power lines are disposed in a different layer from the first power lines of the power shorting bar, and wherein each of the common power lines is connected through a contact hole to a corresponding first power line of the first power lines of the power shorting bar.

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