Package structure including inactive element, assembly structure and method of manufacturing the same

Abstract

This disclosure provides a packaging structure, an assembly structure, and a method for fabricating the same. The packaging structure includes at least a semiconductor element, at least one inactive element, and an encapsulating colloid. The at least one inactive element is disposed around the at least one semiconductor element, including a main portion and at least one through-hole extending through the main portion. The encapsulating colloid encapsulates the at least one semiconductor element and the at least one inactive element. A first surface of the encapsulating colloid is substantially coplanar with a first surface of the at least one inactive element and a first surface of the at least one semiconductor element. A second surface of the encapsulating colloid is substantially coplanar with a second surface of the at least one inactive element and a second surface of the at least one semiconductor element.

Description

Technical Field

[0001] This application is a division of U.S. Application No. 113114118, filed April 16, 2024, which claims priority and benefits from U.S. Official Application No. 18 / 600,997, filed March 11, 2024, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a packaging structure, an assembly structure, and a method for fabricating the same. In particular, it relates to a packaging structure including at least one non-active component, an assembly structure including the packaging structure, and a method for fabricating the same. Prior Technology

[0003] Semiconductor electronic components are widely used in various electronic applications, and their size is constantly shrinking to meet current application demands. However, shrinking the size of semiconductor electronic components brings challenges that affect their final electronic properties, quality, cost, and yield. As semiconductor electronic components become smaller, they require multifunctionality and high-capacity data processing capabilities. Therefore, there is an increasing need to increase the integration of semiconductor components used in these electronic components. However, due to limitations in semiconductor integration technology, it is challenging to meet all required functions using only a single semiconductor wafer. To address this issue, semiconductor packaging has been developed, which involves incorporating multiple semiconductor wafers.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a packaging structure including a first molding structure, a first redistribution structure, and a second molding structure. The first molding structure has a first surface and a second surface opposite to the first surface, and includes at least one semiconductor element, at least one inactive element, and an encapsulant. The at least one inactive element is disposed around the at least one semiconductor element and includes a main portion and at least one via penetrating the main portion. The encapsulant encapsulates the at least one semiconductor element and the at least one inactive element. The first redistribution structure is disposed on the first surface of the first molding structure. The second redistribution structure is disposed on the second surface of the first molding structure and is electrically connected to the first redistribution structure through the at least one via of the at least one inactive element.

[0006] Another embodiment of this disclosure provides an assembly structure including a substrate, a first molding structure, a second molding structure, and an upper electronic component. The first molding structure is disposed above the substrate. The first molding structure includes at least one semiconductor element, at least one inactive element, and an encapsulating colloid encapsulating the at least one semiconductor element and the at least one inactive element. The second molding structure is disposed between the first molding structure and the substrate. The second molding structure includes at least one semiconductor element, at least one inactive element, and an encapsulating colloid encapsulating the at least one semiconductor element and the at least one inactive element. The upper electronic component is disposed above the first molding structure. The at least one inactive element of the first molding structure and the at least one inactive element of the second molding structure are configured to provide a vertical conductive path between the upper electronic component and the substrate.

[0007] Another embodiment of this disclosure provides a fabrication method. The fabrication method includes forming a first molded structure on a first carrier; disposing an upper electronic component on the first molded structure; removing the first carrier; forming a second molded structure on a second carrier; attaching the upper electronic component and the first molded structure to the second molded structure; and removing the second carrier.

[0008] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0009] A more complete understanding of this disclosure can be obtained by referring to the detailed description and the claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description. Figure 1 is a cross-sectional schematic diagram illustrating the assembly structure of some embodiments of this disclosure. Figure 2 is a partial schematic diagram, illustrating the upper part of the assembly structure in Figure 1. Figure 3 is an enlarged schematic diagram, illustrating area "A" in Figure 2. Figure 4 is a partial schematic diagram, illustrating the lower part of the assembly structure in Figure 1. Figure 5 is an enlarged schematic diagram, illustrating region "B" in Figure 4. Figure 6 is a top view schematic diagram, illustrating the first molded structure of the assembly structure in Figure 1. Figure 7 is a top view schematic diagram, illustrating the second molded structure of the assembly structure in Figure 1. Figure 8 is a top view schematic diagram illustrating the first molding structure of some embodiments disclosed herein. Figure 9 is a top view schematic diagram illustrating the second molding structure of some embodiments disclosed herein. Figure 10 is a top view schematic diagram illustrating a first molding structure of some embodiments disclosed herein. Figure 11 is a top view schematic diagram illustrating the second molding structure of some embodiments disclosed herein. Figure 12 is a cross-sectional schematic diagram illustrating the assembly structure of some embodiments of this disclosure. Figure 13 is a cross-sectional schematic diagram illustrating the assembly structure of some embodiments of this disclosure. Figures 14 to 25 are cross-sectional schematic diagrams illustrating various stages of a method for manufacturing an assembly structure according to some embodiments of this disclosure. Figure 26 is a flowchart illustrating the preparation method of the assembly structure of some embodiments disclosed herein. Implementation

[0010] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplification and clarity, and unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0011] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another. Therefore, without departing from the teachings of the progressive concept disclosed herein, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0012] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0013] Figure 1 is a cross-sectional schematic diagram illustrating an assembly structure 1 according to some embodiments of the present disclosure. Figure 2 is a partial schematic diagram illustrating the upper part of the assembly structure 1 of Figure 1. Figure 3 is an enlarged schematic diagram illustrating region "A" of Figure 2. Figure 4 is a partial schematic diagram illustrating the lower part of the assembly structure 1 of Figure 1. Figure 5 is an enlarged schematic diagram illustrating region "B" of Figure 4. In some embodiments, the assembly structure 1 may be a semiconductor electronic component, a semiconductor electronic structure, or a package structure. In some embodiments, the assembly structure 1 may include a package structure 10, a substrate 12, a plurality of bumps 14, and a plurality of external connectors 16.

[0014] The substrate 12 may be a semiconductor substrate and may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate 12 may include an insulator-on-semiconductor substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the substrate 12 may include organic materials, glass, ceramic materials, or the like. For example, the substrate 12 may include a cured photoimageable dielectric (PID) material, including epoxy resin or polyimide (PI) with a photoinitiator. For example, the substrate 12 may include a homogeneous material. For example, the material of substrate 12 may include epoxy FR5, FR4, bismaleimide triazine (BT), printed circuit board (PCB) material, prepreg (PP), Ajinomoto built-in film (ABF) or other suitable materials.

[0015] The substrate 12 may have a first surface 121 (e.g., an upper surface), a second surface 122 (e.g., a lower surface), and a side surface 123. The second surface 122 (e.g., the lower surface) may be opposite to the first surface 121 (e.g., the upper surface). The side surface 123 may extend between the first surface 121 (e.g., the upper surface) and the second surface 122 (e.g., the lower surface).

[0016] The package structure 10 may be disposed above the first surface 121 of the substrate 12 and may be attached to the first surface 121 of the substrate 12 via the bumps 14. An external connector 16 may be disposed on the second surface 122 of the substrate 12 to provide electrical connections to the substrate 12, such as I / O connections. Each external connector 16 may include a resolderable material, such as a solder ball.

[0017] The packaging structure 10 may include a first molding structure 5, a first redistribution structure 7, a second redistribution structure 8, a second molding structure 2, a third redistribution structure 4, and an electronic component 18.

[0018] A first molding structure 5 may be disposed above and electrically connected to a substrate 12. The first molding structure 5 may have a first surface 51 (e.g., an upper surface), a second surface 52 (e.g., a lower surface), and a side surface 53. The second surface 52 (e.g., the lower surface) may be opposite to the first surface 51 (e.g., the upper surface). The side surface 53 may extend between the first surface 51 (e.g., the upper surface) and the second surface 52 (e.g., the lower surface).

[0019] Referring to Figures 1 to 3, the first molding structure 5 may include at least one semiconductor element 50, at least one non-active element 6, and an encapsulating colloid 57. The semiconductor element 50 may include a semiconductor die or a wafer, such as a memory wafer (e.g., a dynamic random access memory (DRAM) wafer, a static random access memory (SRAM) wafer, etc.). The semiconductor element 50 may include a first semiconductor element 55 and a second semiconductor element 56 arranged side-by-side. In some embodiments, the size and function of the first semiconductor element 55 may be the same as those of the second semiconductor element 56. The structure of the first semiconductor element 55 may be the same as that of the second semiconductor element 56. Both the first semiconductor element 55 and the second semiconductor element 56 may be memory dies.

[0020] The first semiconductor element 55 may have a first surface 551 (e.g., an upper surface or an active surface), a second surface 552 (e.g., a lower surface or a back surface), and a side surface 553. The second surface 552 (e.g., the lower surface) may be opposite to the first surface 551 (e.g., the upper surface). The side surface 553 may extend between the first surface 551 (e.g., the upper surface) and the second surface 552 (e.g., the lower surface).

[0021] The first semiconductor element 55 may include a main portion 550 and an active circuit structure 554 disposed on an upper surface 5501 of the main portion 550. For example, a material of the main portion 550 may include, for example, silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials.

[0022] The active circuit structure 554 may include multiple dielectric layers, multiple circuit layers, and multiple solder pads 555. The dielectric layers may cover the circuit layers. The solder pads 555 may be electrically connected to the circuit layers and embedded in the dielectric layers. The solder pads 555 may be exposed from the first surface 551 of the first semiconductor element 55.

[0023] A passive element 6 may be disposed around a semiconductor element 50 (including, for example, a first semiconductor element 55 and a second semiconductor element 56). The passive element 6 may also be referred to as a "virtual die". The passive element 6 may include a first passive element 61 and a second passive element 62 disposed around the first semiconductor element 55 and the second semiconductor element 56. The structure of the first passive element 61 may be the same as or similar to the structure of the second passive element 62.

[0024] The first non-active element 61 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613, 614. The second surface 612 (e.g., the lower surface) may be opposite to the first surface 611 (e.g., the upper surface). The side surfaces 613, 614 may extend between the first surface 611 (e.g., the upper surface) and the second surface 612 (e.g., the lower surface).

[0025] The first non-active element 61 may include a main portion 610 and at least one through-hole 615 (or through-silicon via (TSV)) extending through the main portion 610. The main portion 610 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613, 614. The second surface 612 (e.g., the lower surface) may be opposite to the first surface 611 (e.g., the upper surface). The side surfaces 613, 614 may extend between the first surface 611 (e.g., the upper surface) and the second surface 612 (e.g., the lower surface). Therefore, the first surface 611, the second surface 612, and the side surfaces 613, 614 of the first non-active element 61 may be the first surface 611, the second surface 612, and the side surfaces 613, 614 of the main portion 610, respectively.

[0026] For example, the material of the main portion 610 may include silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the material of the main portion 550 of the first semiconductor element 55 may be the same as the material of the main portion 610 of the first non-active element 61.

[0027] The width W1 of the first semiconductor element 55 (or main portion 550) may be greater than the width W2 of the first non-active element 61 (or main portion 610). The thickness T1 of the main portion 550 of the first semiconductor element 55 may be less than the thickness T2 of the main portion 610 of the first non-active element 61.

[0028] Semiconductor element 50 (including, for example, first semiconductor element 55 and second semiconductor element 56) does not include a vertical conductive path in its main portion. That is, semiconductor element 50 (including, for example, first semiconductor element 55 and second semiconductor element 56) may not have a vertical conductive path to substrate 12. For example, first semiconductor element 55 does not include a vertical conductive path in its main portion 550.

[0029] The first non-active element 61 may include a plurality of through holes 615. A gap g1 may be formed between two adjacent through holes 615. Each through hole 615 may have a central axis 6153.

[0030] The through-hole 615 of the first non-active element 61 may have a first surface 6151 (e.g., an upper surface) and a second surface 6152 (e.g., a lower surface) opposite to the first surface 6151 (e.g., the upper surface). The first surface 6151 of the first through-hole 615 of the first non-active element 61 may be substantially coplanar with the first surface 611 of the first non-active element 61 and exposed from the first surface 611. The second surface 6152 of the through-hole 615 of the first non-active element 61 may be substantially coplanar with the second surface 612 of the first non-active element 61 and exposed from the second surface 612 of the first non-active element 61. That is, the through-hole 615 of the first non-active element 61 may extend from the first surface 611 of the main portion 610 to the second surface 612 of the main portion 610.

[0031] Therefore, the via 615 of the first non-active element 61 can provide a vertical conductive path extending to the main portion 610 of the first non-active element 61 and can be configured to transmit signals or power. Thus, the first redistribution structure 7 and the upper electronic element 18 can be electrically connected to the second redistribution structure 8 and the substrate 12 through the via 615 of the first non-active element 61, rather than through semiconductor elements 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56). It is not necessary to form a via in the main portion (e.g., the main portion 550) of the semiconductor elements 50 (e.g., the first semiconductor element 55 and the second semiconductor element 56).

[0032] In some embodiments, the non-active element 6 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active element 61 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 610. No horizontal conductive paths exist on either the first surface 611 or the second surface 612 of the main portion 610. The non-active element 6 includes only vertical conductive paths.

[0033] The encapsulant 57 can seal semiconductor element 50 (including, for example, first semiconductor element 55 and second semiconductor element 56) and inactive element 6 (including, for example, first inactive element 61 and second inactive element 62). For example, the encapsulant 57 can be disposed in a space 581 between the first semiconductor element 55 and the first inactive element 61, in a space 582 between the first semiconductor element 55 and the second semiconductor element 56, and in a space 583 between the second semiconductor element 56 and the second inactive element 62. A material of the encapsulant 57 may include a molding compound with or without fillers.

[0034] The encapsulating colloid 57 may have a first surface 571 (e.g., an upper surface), a second surface 572 (e.g., a lower surface), and a side surface 573. The second surface 572 (e.g., the lower surface) may be opposite to the first surface 571 (e.g., the upper surface). The side surface 573 may extend between the first surface 571 (e.g., the upper surface) and the second surface 572 (e.g., the lower surface).

[0035] The first surface 571 of the encapsulant 57 may be substantially coplanar or aligned with the first surface 611 of the first non-active element 61 and the first surface 551 of the first semiconductor element 55. Therefore, the first surface 51 of the first molded structure 5 may include the first surface 571 of the encapsulant 57, the first surface 611 of the first non-active element 61, and the first surface 551 of the first semiconductor element 55. Furthermore, the second surface 572 of the encapsulant 57 may be substantially coplanar or aligned with the second surface 612 of the first non-active element 61 and the second surface 552 of the first semiconductor element 55. Therefore, the second surface 52 of the first molded structure 5 may include the second surface 572 of the encapsulant 57, the second surface 612 of the first non-active element 61, and the second surface 552 of the first semiconductor element 55.

[0036] The first redistribution structure 7 can be disposed on the first surface 51 of the first molding structure 5 and electrically connected to the first surface 51. For example, the first redistribution structure 7 can be disposed on the first surface 571 of the encapsulating colloid 57, the first surface 611 of the first non-active element 61, and the first surface 551 of the first semiconductor element 55, and electrically connected to the through-hole 615 of the first semiconductor element 55 and the first non-active element 61.

[0037] The first redistribution structure 7 may be a fan-out structure. The first redistribution structure 7 may have a first surface 71 (e.g., an upper surface), a second surface 72 (e.g., a lower surface), and a side surface 73. The second surface 72 (e.g., the lower surface) may be opposite to the first surface 71 (e.g., the upper surface). The side surface 73 may extend between the first surface 71 (e.g., the upper surface) and the second surface 72 (e.g., the lower surface). The second surface 72 of the first redistribution structure 7 may directly contact the first surface 51 of the first molding structure 5.

[0038] The first redistribution structure 7 may include a plurality of dielectric layers 74, a plurality of circuit layers 75, a plurality of vias 76, and a plurality of solder pads 77. The dielectric layers 74 may include a cured photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) including a photoinitiator. The materials of these dielectric layers 74 may be the same as each other. In some embodiments, the material of the topmost dielectric layer 741 may differ from the materials of the other dielectric layers 74. The topmost dielectric layer 741 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. In some embodiments, the bottommost dielectric layer 742 may be omitted. The circuit layers 75 may be directly disposed on the first surface 51 of the first molded structure 5.

[0039] Circuit layer 75 may be covered by or embedded in dielectric layer 74. Circuit layer 75 may be a fan-out circuit layer. Through-hole 76 may be embedded in dielectric layer 74 and may connect two adjacent circuit layers 75. Through-hole 76 may taper towards the first molded structure 5. Pads 77 may be electrically connected to circuit layer 75 and embedded in dielectric layer 74 (e.g., topmost dielectric layer 741). Pads 77 may be exposed from the first surface 71 of the first redistribution structure 7. Each pad 77 may be a hybrid bond (HB) pad and may comprise Cu or Al.

[0040] The second redistribution structure 8 can be disposed on the second surface 52 of the first molding structure 5 and electrically connected to the second surface 52 of the first molding structure 5. For example, the second redistribution structure 8 can be disposed on the second surface 572 of the encapsulating colloid 57, the second surface 612 of the first non-active element 61, and the second surface 552 of the first semiconductor element 55, and electrically connected to the through-hole 615 of the first non-active element 61.

[0041] The second redistribution structure 8 can be a fan-out structure. The second redistribution structure 8 can have a first surface 81 (e.g., an upper surface), a second surface 82 (e.g., a lower surface), and a side surface 83. The second surface 82 (e.g., the lower surface) can be opposite to the first surface 81 (e.g., the upper surface). The side surface 83 can extend between the first surface 81 (e.g., the upper surface) and the second surface 82 (e.g., the lower surface). The first surface 81 of the second redistribution structure 8 can directly contact the second surface 52 of the first molding structure 5.

[0042] The second redistribution structure 8 may include a plurality of dielectric layers 84, a plurality of circuit layers 85, a plurality of vias 86, and a plurality of solder pads 87. The dielectric layers 84 may include a cured photoimageable dielectric (PID) material, such as epoxy resin or polyimide (PI) including a photoinitiator. The materials of these dielectric layers 84 may be the same as each other. In some embodiments, the material of the bottommost dielectric layer 841 may differ from the materials of the other dielectric layers 84. The bottommost dielectric layer 841 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. In some embodiments, the topmost dielectric layer 842 may be omitted. The circuit layers 85 may be directly disposed on the second surface 52 of the first molded structure 5.

[0043] Circuit layer 85 may be covered by or embedded in dielectric layer 84. Circuit layer 85 may be a fan-out circuit layer. Through-hole 86 may be embedded in dielectric layer 84 and may connect two adjacent circuit layers 85. Through-hole 86 may taper towards the first molded structure 5. Bond pads 77 may be electrically connected to circuit layer 75 and embedded in dielectric layer 84 (e.g., bottommost dielectric layer 841). Bond pads 87 may be exposed from the second surface 82 of the second redistribution structure 8. Each bond pad 87 may be a hybrid bond (HB) bond pad and may comprise Cu or Al.

[0044] The upper electronic component 18 may be disposed above and electrically connected to the first surface 71 of the first redistribution structure 7. The upper electronic component 18 may also be disposed on the first surface 51 of the first molding structure 5 (including, for example, the first surface 571 of the encapsulating colloid 57, the first surface 611 of the first non-active element 61 and the first surface 551 of the first semiconductor element 55).

[0045] The electronic component 18 may include a semiconductor die or a chip, such as a signal processing die (e.g., a digital signal processing (DSP) die), a logic die (e.g., an application processor (AP), a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a front-end chip (e.g., an analog front-end (AFE) die), or other active components.

[0046] The upper electronic component 18 may have a first surface 181 (e.g., an upper surface or a back surface), a second surface 182 (e.g., a lower surface or an active surface), and a side surface 183. The second surface 182 (e.g., a lower surface) may be opposite to the first surface 181 (e.g., an upper surface). The side surface 183 may extend between the first surface 181 (e.g., an upper surface) and the second surface 182 (e.g., a lower surface).

[0047] The electronic component 18 may include a main portion 180 and an active circuit structure 184 disposed on a lower surface 1801 of the main portion 180. For example, a material of the main portion 180 may include silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials.

[0048] The active circuit structure 184 may include multiple dielectric layers, multiple circuit layers, and multiple solder pads 185. The dielectric layers may cover the circuit layers. The solder pads 185 may be electrically connected to the circuit layers and embedded in the dielectric layers. The solder pads 185 may be exposed from the second surface 182 of the upper electronic component 18. The active circuit structure 184 may include a bottom dielectric layer surrounding the solder pads 185. The bottom dielectric layer may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. Each solder pad 185 may be a hybrid bonding (HB) pad and may include Cu or Al.

[0049] The upper electronic component 18 can be attached to and electrically connected to the first surface 71 of the first redistribution structure 7 via hybrid bonding. That is, the second surface 182 of the upper electronic component 18 can directly contact the first surface 71 of the first redistribution structure 7. Therefore, the active circuit structure 184 of the upper electronic component 18 can be directly attached to, connected to, and contact the topmost dielectric layer 741 of the first redistribution structure 7. The pads 185 of the upper electronic component 18 can be directly attached to, connected to, and contact the pads 77 of the first redistribution structure 7.

[0050] The size and function of the upper electronic component 18 may differ from the size and function of the semiconductor component 50 of the first molding structure 5 (e.g., including the first semiconductor component 55 and the second semiconductor component 56) and the size and function of the semiconductor component 20 of the second molding structure 2 (e.g., including the first semiconductor component 25 and the second semiconductor component 26).

[0051] The width W3 of the upper electronic component 18 can be substantially equal to the width W4 of the first molding structure 5 (or the width W4 of the encapsulant 57) and the width W4 of the second molding structure 2 (or the width W4 of the encapsulant 27). The side surface 183 of the upper electronic component 18 can be substantially aligned with the side surface 53 of the first molding structure 5 (or the side surface 573 of the encapsulant 57) and the side surface 23 of the second molding structure 2 (or the side surface 273 of the encapsulant 27). The upper electronic component 18 can be perpendicularly overlapped with the non-active components 6 (including, for example, the first non-active component 61 and the second non-active component 62).

[0052] Referring to Figures 1, 4, and 5, the second molding structure 2 can be disposed above and electrically connected to the substrate 12. The second molding structure 2 can be disposed below the first molding structure 5. The second molding structure 2 can have a first surface 21 (e.g., an upper surface), a second surface 22 (e.g., a lower surface), and a side surface 23. The second surface 22 (e.g., the lower surface) can be opposite to the first surface 21 (e.g., the upper surface). The side surface 23 can extend between the first surface 21 (e.g., the upper surface) and the second surface 22 (e.g., the lower surface).

[0053] The second molding structure 2 may include at least one semiconductor element 20, at least one non-active element 3, and an encapsulating colloid 27. The semiconductor element 20 may include a semiconductor die or a wafer, such as a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.). The semiconductor element 20 may include a first semiconductor element 25 and a second semiconductor element 26 arranged side-by-side. In some embodiments, the size and function of the first semiconductor element 25 may be the same as those of the second semiconductor element 26. Both the first semiconductor element 25 and the second semiconductor element 26 can be memory dies.

[0054] The first semiconductor element 25 may have a first surface 251 (e.g., an upper surface or an active surface), a second surface 252 (e.g., a lower surface or a back surface), and a side surface 253. The second surface 252 (e.g., the lower surface) may be opposite to the first surface 251 (e.g., the upper surface). The side surface 253 may extend between the first surface 251 (e.g., the upper surface) and the second surface 252 (e.g., the lower surface).

[0055] The first semiconductor element 25 may include a main portion 250 and an active circuit structure 254 disposed on an upper surface 2501 of the main portion 250. For example, a material of the main portion 250 may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials.

[0056] The active circuit structure 254 may include multiple dielectric layers, multiple circuit layers, and multiple solder pads 255. The dielectric layers may cover the circuit layers. The solder pads 255 may be electrically connected to the circuit layers and embedded in the dielectric layers. The solder pads 255 may be exposed from the first surface 251 of the first semiconductor element 25.

[0057] The passive element 3 may be disposed around the semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26). The passive element 3 may also be referred to as a "virtual die". The passive element 3 may include a first passive element 31 and a second passive element 32 disposed around the first semiconductor element 25 and the second semiconductor element 26. A structure of the first passive element 31 may be the same as or similar to a structure of the second passive element 32.

[0058] The first non-active element 31 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313, 314. The second surface 312 (e.g., the lower surface) may be opposite to the first surface 311 (e.g., the upper surface). The side surfaces 313, 314 may extend between the first surface 311 (e.g., the upper surface) and the second surface 312 (e.g., the lower surface).

[0059] The first non-active element 31 may include a main portion 310 and at least one through-hole 315 (or through-silicon via (TSV)) extending through the main portion 310. The main portion 310 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313, 314. The second surface 312 (e.g., the lower surface) may be opposite to the first surface 311 (e.g., the upper surface). The side surfaces 313, 314 may extend between the first surface 311 (e.g., the upper surface) and the second surface 312 (e.g., the lower surface). Therefore, the first surface 311, the second surface 312, and the side surfaces 313, 314 of the first non-active element 31 may be the first surface 311, the second surface 312, and the side surfaces 313, 314 of the main portion 310, respectively.

[0060] For example, a material of the main portion 310 may include silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the material of the main portion 250 of the first semiconductor element 25 may be the same as the material of the main portion 310 of the first non-active element 31.

[0061] A width W5 of the first semiconductor element 25 (or main portion 250) may be greater than a width W6 of the first inactive element 31 (or main portion 310). The width W6 of the first inactive element 31 (or main portion 310) of the second molding structure 2 may be equal to or different from the width W2 of the first inactive element 61 (or main portion 610) of the first molding structure 5. A thickness T3 of the main portion 250 of the first semiconductor element 25 may be less than a thickness T4 of the main portion 310 of the first inactive element 31. A thickness T4 of the main portion 310 of the first inactive element 31 of the second molding structure 2 may be equal to or different from the thickness T2 of the main portion 610 of the first inactive element 61 of the first molding structure 5.

[0062] Semiconductor element 20 (including, for example, first semiconductor element 25 and second semiconductor element 26) does not include a vertical conductive path in its main portion. That is, semiconductor element 20 (including, for example, first semiconductor element 25 and second semiconductor element 26) may not have a vertical conductive path to substrate 12. For example, first semiconductor element 25 does not include a vertical conductive path in its main portion 250.

[0063] The first non-active element 31 may include a plurality of through holes 315. A gap g2 may be formed between two adjacent through holes 315. Each through hole 315 may have a central axis 3153. In some embodiments, the gap g1 between two adjacent through holes 615 of the first molding structure 5 may be different from or smaller than the gap g2 between two adjacent through holes 315 of the second molding structure 2. In some embodiments, the central axis 6153 of one through hole 615 of the first molding structure 5 may be substantially aligned with the central axis 3153 of one through hole 315 of the second molding structure 2. In some embodiments, all central axes 6153 of all through holes 615 of the first molding structure 5 may be aligned or misaligned with all central axes 3153 of all through holes 315 of the second molding structure 2.

[0064] The through-hole 315 of the first non-active element 31 may have a first surface 3151 (e.g., an upper surface) and a second surface 3152 (e.g., a lower surface) opposite to the first surface 3151 (e.g., the upper surface). The first surface 3151 of the first through-hole 315 of the first non-active element 31 may be substantially coplanar with the first surface 311 of the first non-active element 31 and exposed from the first surface 311. The second surface 3152 of the through-hole 315 of the first non-active element 31 may be substantially coplanar with the second surface 312 of the first non-active element 31 and exposed from the second surface 312 of the first non-active element 31. That is, the through-hole 315 of the first non-active element 31 may extend from the first surface 311 of the main portion 310 to the second surface 312 of the main portion 310.

[0065] Therefore, the via 315 of the first non-active element 31 can provide a vertical conductive path extending through the main portion 310 of the first non-active element 31, and can be configured to transmit signals or power. Therefore, the third redistribution structure 4 can be electrically connected to the substrate 12 through the via 315 of the first non-active element 31 instead of through the semiconductor element 20 (including, for example, the first semiconductor element 25 and the second semiconductor element 26).

[0066] In some embodiments, the non-active element 3 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active element 31 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 310. No horizontal conductive paths exist on either the first surface 311 or the second surface 312 of the main portion 310. The non-active element 3 includes only vertical conductive paths.

[0067] The encapsulating colloid 27 can seal semiconductor elements 20 (including, for example, first semiconductor element 25 and second semiconductor element 26) and passive elements 3 (including, for example, first passive element 31 and second passive element 32). For example, the encapsulating colloid 27 can be disposed in space 281 between the first semiconductor element 25 and the first passive element 31, in space 282 between the first semiconductor element 25 and the second semiconductor element 26, and in space 283 between the second semiconductor element 26 and the second passive element 32. The material of the encapsulating colloid 27 can include molding compounds with or without fillers. A material of the encapsulating colloid 27 can include a molding compound with or without fillers.

[0068] The encapsulating colloid 27 may have a first surface 271 (e.g., an upper surface), a second surface 272 (e.g., a lower surface), and a side surface 273. The second surface 272 (e.g., the lower surface) may be opposite to the first surface 271 (e.g., the upper surface). The side surface 273 may extend between the first surface 271 (e.g., the upper surface) and the second surface 272 (e.g., the lower surface).

[0069] The first surface 271 of the encapsulant 27 may be substantially coplanar or aligned with the first surface 311 of the first non-active element 31 and the first surface 251 of the first semiconductor element 25. Therefore, the first surface 21 of the second molding structure 2 may include the first surface 271 of the encapsulant 27, the first surface 311 of the first non-active element 31, and the first surface 251 of the first semiconductor element 25. Furthermore, the second surface 272 of the encapsulant 27 may be substantially coplanar or aligned with the second surface 312 of the first non-active element 31 and the second surface 252 of the first semiconductor element 25. Therefore, the second surface 22 of the second molding structure 2 may include the second surface 272 of the encapsulant 27, the second surface 312 of the first non-active element 31, and the second surface 252 of the first semiconductor element 25.

[0070] The third redistribution structure 4 can be disposed on the first surface 21 of the second molding structure 2 and electrically connected to the first surface 21 of the second molding structure 2. For example, the third redistribution structure 4 can be disposed on the first surface 271 of the encapsulating colloid 27, the first surface 311 of the first non-active element 31, and the first surface 251 of the first semiconductor element 25, and electrically connected to the through-hole 315 of the first semiconductor element 25 and the first non-active element 31.

[0071] The third redistribution structure 4 can be a fan-out structure. The third redistribution structure 4 can have a first surface 41 (e.g., an upper surface), a second surface 42 (e.g., a lower surface), and a side surface 43. The second surface 42 (e.g., the lower surface) can be opposite to the first surface 41 (e.g., the upper surface). The side surface 43 can extend between the first surface 41 (e.g., the upper surface) and the second surface 42 (e.g., the lower surface). The second surface 42 of the third redistribution structure 4 can directly contact the first surface 21 of the second molding structure 2.

[0072] The third redistribution structure 4 may include multiple dielectric layers 44, multiple circuit layers 45, multiple vias 46, and multiple solder pads 47. The dielectric layers 44 may include cured photoimageable dielectric (PID) materials, such as epoxy resin or polyimide (PI) including photoinitiators. The materials of these dielectric layers 44 may be the same. In some embodiments, the material of the topmost dielectric layer 441 may differ from the materials of the other dielectric layers 44. The topmost dielectric layer 441 may be a hybrid bonding (HB) dielectric layer and may include SiO2, SiCN, and / or SiON. In some embodiments, the bottommost dielectric layer 442 may be omitted. The circuit layers 45 may be directly disposed on the first surface 21 of the second molded structure 2.

[0073] Circuit layer 45 may be covered by or embedded in dielectric layer 44. Circuit layer 45 may be a fan-out circuit layer. Through-hole 46 may be embedded in dielectric layer 44 and may connect two adjacent circuit layers 45. Through-hole 46 may taper towards the second molding structure 2. Pads 47 may be electrically connected to circuit layer 45 and embedded in dielectric layer 44 (e.g., the topmost dielectric layer 441). Pads 47 may be exposed from the first surface 41 of the third redistribution structure 4. Each pad 47 may be a hybrid bonding (HB) pad and may comprise Cu or Al.

[0074] The second redistribution structure 8 can be disposed above and electrically connected to the first surface 41 of the third redistribution structure 4. Therefore, the first redistribution structure 7 can be disposed between the first molding structure 5 and the upper electronic component 18. The second redistribution structure 8 can be disposed below the first molding structure 5. The third redistribution structure 4 can be disposed between the second redistribution structure 8 and the second molding structure 2.

[0075] The second redistribution structure 8 can be attached to and electrically connected to the first surface 41 of the third redistribution structure 4 via hybrid bonding. That is, the second surface 82 of the second redistribution structure 8 can directly contact the first surface 41 of the third redistribution structure 4. Therefore, the bottom dielectric layer 841 of the second redistribution structure 8 can be directly attached to, connected to, and contact the top dielectric layer 441 of the third redistribution structure 4. The solder pads 87 of the second redistribution structure 8 can be directly attached to, connected to, and directly contact the solder pads 47 of the third redistribution structure 4. Therefore, the first molding structure 5 can be electrically connected to the second molding structure 2 via hybrid bonding.

[0076] Bump 14 may be disposed on the second surface 22 of the second molding structure 2. For example, bump 14 may include a plurality of first bumps 141 and a plurality of second bumps 142. First bumps 141 may be disposed on the second surface 3152 (e.g., the lower surface) of the via 315. Therefore, first bumps 141 may physically and electrically connect the via 315 and the first surface 121 of the substrate 12. Second bumps 142 may be disposed on the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25). Therefore, second bumps 142 may connect the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25) and the first surface 121 of the substrate 12. Second bumps 142 may not have electronic functionality and may be dummy pads.

[0077] In some embodiments, the first bump 141 and the second bump 142 may be formed simultaneously during the manufacturing stage. In some embodiments, the first bump 141 and / or the second bump 142 may include a solderable material configured to control a gap between the second molded structure 2 and the substrate 12 to prevent the second molded structure 2 from tilting relative to the substrate 12. Additionally, a first gap g3 between two adjacent first bumps 141 may be smaller than a second gap g4 between two adjacent second bumps 142.

[0078] Figure 6 is a top view schematic diagram illustrating the first molded structure 5 of the assembly structure 1 in Figure 1. The first non-active element 61 may include multiple rows of through-holes 615, such as three rows of through-holes 615. The pads 555 of the first semiconductor element 55 may be configured in an array. The size and structure of the second semiconductor element 56 may be the same as those of the first semiconductor element 55. The size and structure of the second non-active element 62 may be the same as those of the first non-active element 61. The second non-active element 62 and the first non-active element 61 may be disposed on opposite sides of the second semiconductor element 56 and the first semiconductor element 55.

[0079] Figure 7 is a top view schematic diagram illustrating the second molded structure 2 of the assembly structure 1 in Figure 1. The first non-active element 31 may include multiple rows of through-holes 315, for example, two rows of through-holes 315. The pads 255 of the first semiconductor element 25 may be configured in an array. The size and structure of the second semiconductor element 26 may be the same as those of the first semiconductor element 25. The size and structure of the second non-active element 32 may be the same as those of the first non-active element 31. The second non-active element 32 and the first non-active element 31 may be disposed on opposite sides of the second semiconductor element 26 and the first semiconductor element 25.

[0080] In the embodiments shown in Figures 1 to 7, the passive elements 6 of the first molding structure 5 (including, for example, first passive element 61 and second passive element 62) are configured to provide a vertical conductive path between the upper electronic element 18 (or the first redistribution structure 7) and the second redistribution structure 8. The passive elements 3 of the second molding structure 2 (including, for example, first passive element 31 and second passive element 32) are configured to provide a vertical conductive path between the third redistribution structure 4 and the substrate 12. Therefore, the passive elements 6 of the first molding structure 5 (including, for example, first passive element 61 and second passive element 62) and the passive elements 3 of the second molding structure 2 (including, for example, first passive element 31 and second passive element 32) are configured to provide a vertical conductive path between the upper electronic element 18 and the substrate 12.

[0081] The upper electronic component 18 is not electrically connected to the substrate 12 through semiconductor elements 50 (e.g., first semiconductor element 55 and second semiconductor element 56) and semiconductor elements 20 (e.g., first semiconductor element 25 and second semiconductor element 26). It is not necessary to form a via in the main portion (e.g., main portion 550) of semiconductor elements 50 (e.g., first semiconductor element 55 and second semiconductor element 56). It is not necessary to form a via in the main portion (e.g., main portion 250) of semiconductor elements 20 (e.g., first semiconductor element 25 and second semiconductor element 26). Vertical conductive paths can be provided outside semiconductor elements 20 (e.g., first semiconductor element 25 and second semiconductor element 26) and semiconductor elements 50 (e.g., first semiconductor element 55 and second semiconductor element 56). Therefore, design flexibility is increased and manufacturing costs are reduced.

[0082] Furthermore, the active surface of semiconductor element 50 (e.g., the first surface 551 (or active surface) of the first semiconductor element 55) faces the active surface of upper electronic element 18 (e.g., the first surface 181 of upper electronic element 18). Therefore, upper electronic element 18 can quickly read from and / or write to semiconductor element 50 (e.g., the first semiconductor element 55). Thus, the performance of package structure 10 can be improved.

[0083] Figure 8 is a top view schematic diagram illustrating a first molding structure 5a of some embodiments disclosed herein. The first molding structure 5a may be similar to the first molding structure 5 of Figure 6, with the differences described below. The first molding structure 5a may further include a third inactive element 63 and a fourth inactive element 64. The third inactive element 63 and the fourth inactive element 64 may be disposed on opposite sides of the second semiconductor element 56 and the first semiconductor element 55. The dimensions and structure of the third inactive element 63 and the fourth inactive element 64 may be the same as or similar to the dimensions and structure of the first inactive element 61 and the second inactive element 62. The first inactive element 61, the second inactive element 62, the third inactive element 63, and the fourth inactive element 64 may surround the second semiconductor element 56 and the first semiconductor element 55.

[0084] Figure 9 is a top view schematic diagram illustrating a second molding structure 2a according to some embodiments of the present disclosure. The second molding structure 2a may be similar to the second molding structure 2 of Figure 7, with the differences described below. The first inactive element 31 and the second inactive element 32 may include three rows of through-holes 315. The second molding structure 2a may also include a third inactive element 33 and a fourth inactive element 34. The third inactive element 33 and the fourth inactive element 34 may be disposed on opposite sides of the second semiconductor element 26 and the first semiconductor element 25. The dimensions and structure of the third inactive element 33 and the fourth inactive element 34 may be the same as or similar to the dimensions and structure of the first inactive element 31 and the second inactive element 32. The first inactive element 31, the second inactive element 32, the third inactive element 33, and the fourth inactive element 34 may surround the second semiconductor element 26 and the first semiconductor element 25.

[0085] Figure 10 is a top view schematic diagram illustrating a first molding structure 5b of some embodiments disclosed herein. The first molding structure 5b can be similar to the first molding structure 5a of Figure 8, with the differences described below. From the top view, the dimensions of the first inactive element 61 can differ from the dimensions of the second inactive element 62b. For example, a length L1 of the first inactive element 61 can be greater than a length L2 of the second inactive element 62b. Furthermore, each of the third inactive element 63b and the fourth inactive element 64b can be L-shaped and can be disposed adjacent to a corner of the second semiconductor element 56 or around a corner of the second semiconductor element 56.

[0086] Figure 11 is a top view schematic diagram illustrating a second molding structure 2b of some embodiments disclosed herein. The second molding structure 2b can be similar to the second molding structure 2a of Figure 9, with the differences described below. From the top view, the dimensions of the first inactive element 31 can differ from the dimensions of the second inactive element 32b. For example, a length L3 of the first inactive element 31 can be greater than a length L4 of the second inactive element 32b. Furthermore, each of the third inactive element 33b and the fourth inactive element 34b can be L-shaped and can be disposed adjacent to a corner of the second semiconductor element 26 or around a corner of the second semiconductor element 26.

[0087] Figure 12 is a cross-sectional schematic diagram illustrating an assembly structure 1a of some embodiments disclosed herein. Except for the structure and dimensions of the non-active elements 3 (including, for example, the first non-active element 31 and the second non-active element 32) of the second molding structure 2, assembly structure 1a can be similar to assembly structure 1 of Figure 1. For example, the width W6 of the first non-active element 31 (or main portion 310) of the second molding structure 2 can be smaller than the width W2 of the first non-active element 31 (or main portion 310) of the first molding structure 5. All central axes 3153 of all through holes 315 of the second molding structure 2 can be aligned with the central axis 6153 of the corresponding through holes 615 of the first molding structure 5.

[0088] Figure 13 is a cross-sectional schematic diagram illustrating an assembly structure 1b of some embodiments disclosed herein. The assembly structure 1b can be similar to the assembly structure 1 of Figure 1, except for the structure of the package structure 10b. In the package structure 10b, the second surface 182 of the upper electronic component 18 does not contact the first surface 71 of the first redistribution structure 7. The second surface 182 of the upper electronic component 18 is separate from the first surface 71 of the first redistribution structure 7. The pads 185 of the upper electronic component 18 can be electrically connected to the pads 77 of the first redistribution structure 7 through a plurality of solder materials 191. The solder materials 191 may include a reflowable material such as AgSn. Therefore, the electrical connection between the upper electronic component 18 and the first redistribution structure 7 is not a hybrid bonding but a solder bonding. The pads 185 of the upper electronic component 18 and the pads 77 of the first redistribution structure 7 can be solder-bonded pads.

[0089] Furthermore, the second surface 82 of the second redistribution structure 8 does not contact the first surface 41 of the third redistribution structure 4. The second surface 82 of the second redistribution structure 8 is separate from the first surface 41 of the third redistribution structure 4. The solder pads 87 of the second redistribution structure 8 can be electrically connected to the solder pads 47 of the third redistribution structure 4 through a plurality of soldering materials 19. The soldering materials 19 may include a reflowable material such as AgSn. Therefore, the electrical connection between the second redistribution structure 8 and the third redistribution structure 4 is not a hybrid bonding but a solder bonding. The solder pads 87 of the second redistribution structure 8 and the solder pads 47 of the third redistribution structure 4 can be solder-bonded pads. Therefore, the first molded structure 5 can be electrically connected to the second molded structure 2 through the soldering materials 19.

[0090] Figures 14 to 25 are cross-sectional schematic diagrams illustrating various stages of a method for manufacturing and assembling structure 1 according to some embodiments of this disclosure.

[0091] Referring to Figures 14 and 15, a first molding structure 5 may be formed on a first carrier 90. Referring to Figure 14, at least one semiconductor element 50 and at least one passive element 6 may be disposed side-by-side on the first carrier 90. In some embodiments, the first carrier 90 may include a release layer 91 on one of its surfaces. The semiconductor element 50 and the passive element 6 may be disposed on the release layer 91. In some embodiments, monolithic semiconductor elements 50 (e.g., first semiconductor element 55 and second semiconductor element 56) and monolithic passive elements 6 (e.g., first passive element 61 and second passive element 62) may be reconstructed or reconfigured on the release layer 91 of the first carrier 90. In some embodiments, only known good grains, such as known good semiconductor elements 50 (e.g., first semiconductor element 55 and second semiconductor element 56) and known good passive elements 6 (e.g., first passive element 61 and second passive element 62), are used.

[0092] In some embodiments, the size and function of the first semiconductor element 55 may be the same as those of the second semiconductor element 56. Both the first semiconductor element 55 and the second semiconductor element 56 may be memory chips.

[0093] The first semiconductor element 55 may have a first surface 551 (e.g., an upper surface or an active surface), a second surface 552 (e.g., a lower surface or a back surface), and a side surface 553. The second surface 552 (e.g., the lower surface) may be opposite to the first surface 551 (e.g., the upper surface). The side surface 553 may extend between the first surface 551 (e.g., the upper surface) and the second surface 552 (e.g., the lower surface).

[0094] The first semiconductor element 55 may include a main portion 550 and an active circuit structure 554 disposed on an upper surface 5501 of the main portion 550. The active circuit structure 554 may include a plurality of dielectric layers, a plurality of circuit layers, and a plurality of solder pads 555. The dielectric layers may cover the circuit layers. The solder pads 555 may be electrically connected to the circuit layers and embedded in the dielectric layers. The solder pads 555 may be exposed from the first surface 551 of the first semiconductor element 55. The active circuit structure 554 and the solder pads 555 may face upward. The second surface 552 (e.g., the lower surface) of the first semiconductor element 55 may contact the release layer 91 of the first carrier 90.

[0095] The passive element 6 may include a first passive element 61 and a second passive element 62 disposed around the first semiconductor element 55 and the second semiconductor element 56. The structure of the first passive element 61 may be the same as or similar to the structure of the second passive element 62.

[0096] The first non-active element 61 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613, 614. The second surface 612 (e.g., the lower surface) may be opposite to the first surface 611 (e.g., the upper surface). The side surfaces 613, 614 may extend between the first surface 611 (e.g., the upper surface) and the second surface 612 (e.g., the lower surface).

[0097] A space 581 may be formed between the first semiconductor element 55 and the first inactive element 61. A space 582 may be formed between the first semiconductor element 55 and the second semiconductor element 56. A space 583 may be formed between the second semiconductor element 56 and the second inactive element 62.

[0098] The first non-active element 61 may include a main portion 610 and at least one through-hole 615 (or through-silicon via (TSV)) extending through the main portion 610. The main portion 610 may have a first surface 611 (e.g., an upper surface), a second surface 612 (e.g., a lower surface), and two side surfaces 613, 614. The second surface 612 (e.g., the lower surface) may be opposite to the first surface 611 (e.g., the upper surface). The side surfaces 613, 614 may extend between the first surface 611 (e.g., the upper surface) and the second surface 612 (e.g., the lower surface). Therefore, the first surface 611, the second surface 612, and the side surfaces 613, 614 of the first non-active element 61 may be the first surface 611, the second surface 612, and the side surfaces 613, 614 of the main portion 610, respectively.

[0099] Semiconductor element 50 (including, for example, a first semiconductor element 55 and a second semiconductor element 56) does not include a vertical conductive path in its main portion. For example, the first semiconductor element 55 does not include a vertical conductive path in its main portion 550.

[0100] The through-hole 615 of the first non-active element 61 may have a first surface 6151 (e.g., an upper surface) and a second surface 6152 (e.g., a lower surface) opposite to the first surface 6151 (e.g., the upper surface). The first surface 6151 of the first through-hole 615 of the first non-active element 61 may be substantially coplanar with the first surface 611 of the first non-active element 61 and exposed from the first surface 611. The second surface 6152 of the through-hole 615 of the first non-active element 61 may be substantially coplanar with the second surface 612 of the first non-active element 61 and exposed from the second surface 612 of the first non-active element 61.

[0101] In some embodiments, the non-active element 6 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active element 61 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 610. No horizontal conductive paths exist on either the first surface 611 or the second surface 612 of the main portion 610. The non-active element 6 includes only vertical conductive paths. The second surface 612 of the non-active element 6 can contact the release layer 91 of the first carrier 90.

[0102] Referring to Figure 15, an encapsulating colloid 57 can be formed on the release layer 91 of the first carrier 90 to seal the semiconductor element 50 (including, for example, the first semiconductor element 55 and the second semiconductor element 56) and the non-active element 6 (for example, the first non-active element 61 and the second non-active element 62). The encapsulating colloid 57 can be disposed in spaces 581, 582 and 583.

[0103] A polishing process can then be performed to form a first molding structure 5 on the first carrier 90. The first molding structure 5 may include a semiconductor element 50, a non-active element 6, and an encapsulating colloid 57. The first molding structure 5 may have a first surface 51 (e.g., an upper surface) and a second surface 52 (e.g., a lower surface) opposite to the first surface 51 (e.g., the upper surface).

[0104] The encapsulant 57 may have a first surface 571 (e.g., an upper surface) and a second surface 572 (e.g., a lower surface) opposite to the first surface 571 (e.g., the upper surface). The first surface 571 of the encapsulant 57 may be substantially coplanar or aligned with the first surface 611 of the first non-active element 61 and the first surface 551 of the first semiconductor element 55. Therefore, the first surface 51 of the first molding structure 5 may include the first surface 571 of the encapsulant 57, the first surface 611 of the first non-active element 61, and the first surface 551 of the first semiconductor element 55. Furthermore, the second surface 572 of the encapsulant 57 may be substantially coplanar or aligned with the second surface 612 of the first non-active element 61 and the second surface 552 of the first semiconductor element 55. Therefore, the second surface 52 of the first molding structure 5 may include the second surface 572 of the encapsulant 57, the second surface 612 of the first non-active element 61, and the second surface 552 of the first semiconductor element 55.

[0105] Referring to Figure 16, the first redistribution structure 7 can be formed or disposed on the first surface 51 of the first molding structure 5. For example, the first redistribution structure 7 can be formed or disposed on the first surface 571 of the encapsulating colloid 57, the first surface 611 of the first non-active element 61, and the first surface 551 of the first semiconductor element 55. The first redistribution structure 7 can be electrically connected to the through-hole 615 of the semiconductor element 50 (e.g., the first semiconductor element 55 and the second semiconductor element 56) and the non-active element 6 (e.g., the first non-active element 61 and the second non-active element 62).

[0106] The first redistribution structure 7 may be a fan-out structure. The first redistribution structure 7 may have a first surface 71 (e.g., an upper surface) and a second surface 72 (e.g., a lower surface) opposite to the first surface 71 (e.g., the upper surface). The second surface 72 of the first redistribution structure 7 may directly contact the first surface 51 of the first molding structure 5.

[0107] The first redistribution structure 7 may include a plurality of dielectric layers 74, a plurality of circuit layers 75, a plurality of vias 76, and a plurality of solder pads 77. The dielectric layers 74 may be made of the same material as each other. In some embodiments, the material of the topmost dielectric layer 741 may be different from the materials of the other dielectric layers 74. The topmost dielectric layer 741 may be a hybrid bonding (HB) dielectric layer. In some embodiments, the bottommost dielectric layer 742 may be omitted. The circuit layers 75 may be directly disposed on the first surface 51 of the first molded structure 5.

[0108] Circuit layer 75 may be covered by or embedded in dielectric layer 74. Circuit layer 75 may be a fan-out circuit layer. Through-hole 76 may be embedded in dielectric layer 74 and may connect two adjacent circuit layers 75. Through-hole 76 may taper towards the first molded structure 5. Pads 77 may be electrically connected to circuit layer 75 and embedded in dielectric layer 74 (e.g., topmost dielectric layer 741). Pads 77 may be exposed from the first surface 71 of the first redistribution structure 7. Each pad 77 may be a hybrid bonding (HB) pad.

[0109] Referring to Figure 17, the upper electronic component 18 can be disposed on and electrically connected to the first surface 71 of the first redistribution structure 7. The upper electronic component 18 can be wafer-type, panel-type, or chip-type. The upper electronic component 18 can have a first surface 181 (e.g., an upper surface or a back surface) and a second surface 182 (e.g., a lower surface or an active surface) opposite to the first surface 181 (e.g., the upper surface).

[0110] The upper electronic component 18 may include a main portion 180 and an active circuit structure 184 disposed on a lower surface 1801 of the main portion 180. The active circuit structure 184 may include multiple dielectric layers, multiple circuit layers, and multiple solder pads 185. The dielectric layers may cover the circuit layers. The solder pads 185 may be electrically connected to the circuit layers and embedded in the dielectric layers. The solder pads 185 may be exposed from a second surface 182 of the upper electronic component 18. The active circuit structure 184 may include a bottom dielectric layer surrounding the solder pads 185. The bottom dielectric layer may be a hybrid bonding (HB) dielectric layer. Each solder pad 185 may be a hybrid bonding (HB) solder pad.

[0111] The upper electronic component 18 can be attached to and electrically connected to the first surface 71 of the first redistribution structure 7 via hybrid bonding. That is, the second surface 182 of the upper electronic component 18 can directly contact the first surface 71 of the first redistribution structure 7. Therefore, the active circuit structure 184 of the upper electronic component 18 can be directly attached to, connected to, and contact the topmost dielectric layer 741 of the first redistribution structure 7. The pads 185 of the upper electronic component 18 can be directly attached to, connected to, and contact the pads 77 of the first redistribution structure 7.

[0112] Referring to Figure 18, the release layer 91 and the first carrier 90 can be removed from the first molding structure 5. Then, a polishing process can be performed on the second surface 52 of the first molding structure 5.

[0113] Referring to Figure 19, the second redistribution structure 8 can be formed or disposed on the second surface 52 of the first molding structure 5. For example, the second redistribution structure 8 can be formed or disposed on the second surface 572 of the encapsulating colloid 57, the second surface 612 of the first inactive element 61, and the second surface 552 of the first semiconductor element 55. The second redistribution structure 8 can be electrically connected to the through-hole 615 of the inactive element 6 (e.g., the first inactive element 61 and the second inactive element 62).

[0114] The second redistribution structure 8 can be a fan-out structure. The second redistribution structure 8 can have a first surface 81 (e.g., an upper surface) and a second surface 82 (e.g., a lower surface) opposite to the first surface 81 (e.g., the upper surface). The second surface 82 of the second redistribution structure 8 can directly contact the second surface 52 of the first molding structure 5.

[0115] The second redistribution structure 8 may include a plurality of dielectric layers 84, a plurality of circuit layers 85, a plurality of vias 86, and a plurality of solder pads 87. The dielectric layers 84 may be made of the same material as each other. In some embodiments, the material of the bottommost dielectric layer 841 may be different from the materials of the other dielectric layers 84. The bottommost dielectric layer 841 may be a hybrid bonding (HB) dielectric layer. In some embodiments, the topmost dielectric layer 842 may be omitted. The circuit layers 85 may be directly disposed on the second surface 52 of the first molded structure 5.

[0116] Circuit layer 85 may be covered by or embedded in dielectric layer 84. Circuit layer 85 may be a fan-out circuit layer. Through-hole 86 may be embedded in dielectric layer 84 and may connect two adjacent circuit layers 85. Through-hole 86 may taper towards the first molded structure 5. Bond pads 87 may be electrically connected to circuit layer 85 and embedded in dielectric layer 84 (e.g., bottom dielectric layer 841). Bond pads 87 may be exposed from the second surface 82 of the second redistribution structure 8. Each bond pad 87 may be a hybrid bonding (HB) bond pad.

[0117] Referring to Figures 20 and 21, a second molding structure 2 can be formed on a second carrier 92. Referring to Figure 20, at least one semiconductor element 20 and at least one passive element 3 can be disposed side-by-side on the second carrier 92. In some embodiments, the second carrier 92 may include a release layer 93 on its surface. The semiconductor element 20 and the passive element 3 can be disposed on the release layer 93. In some embodiments, monolithic semiconductor elements 20 (e.g., first semiconductor element 25 and second semiconductor element 26) and monolithic passive elements 3 (e.g., first passive element 31 and second passive element 32) can be reconstructed or reconfigured on the release layer 93 of the second carrier 92. In some embodiments, only known good grains are used, such as known good semiconductor elements 20 (e.g., first semiconductor element 25 and second semiconductor element 26) and known good passive elements 3 (e.g., first passive element 31 and second passive element 32).

[0118] The first semiconductor element 25 may have a first surface 251 (e.g., an upper surface or an active surface), a second surface 252 (e.g., a lower surface or a back surface), and a side surface 253. The second surface 252 (e.g., the lower surface) may be opposite to the first surface 251 (e.g., the upper surface). The side surface 253 may extend between the first surface 251 (e.g., the upper surface) and the second surface 252 (e.g., the lower surface).

[0119] The first semiconductor element 25 may include a main portion 250 and an active circuit structure 254 disposed on an upper surface 2501 of the main portion 250. The active circuit structure 254 may include a plurality of dielectric layers, a plurality of circuit layers, and a plurality of solder pads 255. The dielectric layers may cover the circuit layers. The solder pads 255 may be electrically connected to the circuit layers and embedded in the dielectric layers. The solder pads 255 may be exposed from the first surface 251 of the first semiconductor element 25. The active circuit structure 254 and the solder pads 255 may face upward. The second surface 252 (e.g., the lower surface) of the first semiconductor element 25 may contact the release layer 93 of the second carrier 92.

[0120] The passive element 3 may include a first passive element 31 and a second passive element 32 disposed around the first semiconductor element 25 and the second semiconductor element 26. The structure of the first passive element 31 may be the same as or similar to the structure of the second passive element 32.

[0121] The first non-active element 31 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313, 314. The second surface 312 (e.g., the lower surface) may be opposite to the first surface 311 (e.g., the upper surface). The side surfaces 313, 314 may extend between the first surface 311 (e.g., the upper surface) and the second surface 312 (e.g., the lower surface).

[0122] Space 281 may be formed between the first semiconductor element 25 and the first inactive element 31. Space 282 may be formed between the first semiconductor element 25 and the second semiconductor element 26. Space 283 may be formed between the second semiconductor element 26 and the second inactive element 32.

[0123] The first non-active element 31 may include a main portion 310 and at least one through-hole 315 (or through-silicon via (TSV)) extending through the main portion 310. The main portion 310 may have a first surface 311 (e.g., an upper surface), a second surface 312 (e.g., a lower surface), and two side surfaces 313, 314. The second surface 312 (e.g., the lower surface) may be opposite to the first surface 311 (e.g., the upper surface). The side surfaces 313, 314 may extend between the first surface 311 (e.g., the upper surface) and the second surface 312 (e.g., the lower surface). Therefore, the first surface 311, the second surface 312, and the side surfaces 313, 314 of the first non-active element 31 may be the first surface 311, the second surface 312, and the side surfaces 313, 314 of the main portion 310, respectively.

[0124] The through-hole 315 of the first non-active element 31 may have a first surface 3151 (e.g., an upper surface) and a second surface 3152 (e.g., a lower surface) opposite to the first surface 3151 (e.g., the upper surface). The first surface 3151 of the first through-hole 315 of the first non-active element 31 may be substantially coplanar with the first surface 311 of the first non-active element 31 and exposed from the first surface 311. The second surface 3152 of the through-hole 315 of the first non-active element 31 may be substantially coplanar with the second surface 312 of the first non-active element 31 and exposed from the second surface 312 of the first non-active element 31.

[0125] In some embodiments, the non-active element 3 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion. For example, the first non-active element 31 does not include a horizontal conductive path (e.g., a horizontal circuit layer) on its main portion 310. No horizontal conductive paths exist on either the first surface 311 or the second surface 312 of the main portion 310. The non-active element 3 includes only vertical conductive paths. The second surface 312 of the non-active element 3 can contact the release layer 93 of the second carrier 92.

[0126] Referring to Figure 21, an encapsulating colloid 27 can then be formed on the release layer 93 of the second carrier 92 to encapsulate the semiconductor element 20 (e.g., including the first semiconductor element 25 and the second semiconductor element 26) and the inactive element 3 (e.g., the first inactive element 31 and the second inactive element 32). The encapsulating colloid 27 can be disposed in spaces 281, 282, and 283.

[0127] Then, a polishing process can be performed to form a second molding structure 2 on the second carrier 92. The second molding structure 2 may include a semiconductor element 20, a non-active element 3, and an encapsulating colloid 27. The second molding structure 2 may have a first surface 21 (e.g., an upper surface) and a second surface 22 (e.g., a lower surface) opposite to the first surface 21 (e.g., the upper surface).

[0128] The encapsulant 27 may have a first surface 271 (e.g., an upper surface) and a second surface 272 (e.g., a lower surface) opposite to the first surface 271 (e.g., the upper surface). The first surface 271 of the encapsulant 27 may be substantially coplanar or aligned with the first surface 311 of the first non-active element 31 and the first surface 251 of the first semiconductor element 25. Therefore, the first surface 21 of the second molding structure 2 may include the first surface 271 of the encapsulant 27, the first surface 311 of the first non-active element 31, and the first surface 251 of the first semiconductor element 25. Furthermore, the second surface 272 of the encapsulant 27 may be substantially coplanar or aligned with the second surface 312 of the first non-active element 31 and the second surface 252 of the first semiconductor element 25. Therefore, the second surface 22 of the second molding structure 2 may include the second surface 272 of the encapsulant 27, the second surface 312 of the first non-active element 31, and the second surface 252 of the first semiconductor element 25.

[0129] Referring to Figure 22, a third redistribution structure 4 may be formed or disposed on the first surface 21 of the second molding structure 2. For example, the third redistribution structure 4 may be formed or disposed on the first surface 271 of the encapsulating colloid 27, the first surface 311 of the first inactive element 31, and the first surface 251 of the first semiconductor element 25. The third redistribution structure 4 may be electrically connected to the semiconductor element 20 (e.g., the first semiconductor element 25 and the second semiconductor element 26) through the through-holes 315 of the inactive elements 3 (e.g., the first inactive element 31 and the second inactive element 32).

[0130] The third redistribution structure 4 can be a fan-out structure. The third redistribution structure 4 can have a first surface 41 (e.g., an upper surface) and a second surface 42 (e.g., a lower surface) opposite to the first surface 41 (e.g., the upper surface). The second surface 42 of the third redistribution structure 4 can directly contact the first surface 21 of the second molding structure 2.

[0131] The third redistribution structure 4 may include multiple dielectric layers 44, multiple circuit layers 45, multiple vias 46, and multiple solder pads 47. The dielectric layers 44 may be made of the same material. In some embodiments, the material of the topmost dielectric layer 441 may differ from the materials of the other dielectric layers 44. The topmost dielectric layer 441 may be a hybrid bonding (HB) dielectric layer. In some embodiments, the bottommost dielectric layer 442 may be omitted. The circuit layers 45 may be directly disposed on the first surface 21 of the second molded structure 2.

[0132] Circuit layer 45 may be covered by or embedded in dielectric layer 44. Circuit layer 45 may be a fan-out circuit layer. Through-hole 46 may be embedded in dielectric layer 44 and may connect two adjacent circuit layers 45. Through-hole 46 may taper towards the second molding structure 2. Pads 47 may be electrically connected to circuit layer 45 and embedded in dielectric layer 44 (e.g., the topmost dielectric layer 441). Pads 47 may be exposed from the first surface 41 of the third redistribution structure 4. Each pad 47 may be a hybrid bonding (HB) pad.

[0133] Referring to Figure 23, the upper electronic component 18 and the first molding structure 5 can be attached to and electrically connected to the second molding structure 2 via a hybrid bonding process. That is, the second surface 82 of the second redistribution structure 8 can directly contact the first surface 41 of the third redistribution structure 4. Therefore, the pads 87 of the second redistribution structure 8 can be directly attached to, connected to, and can directly contact the pads 47 of the third redistribution structure 4.

[0134] Referring to Figure 24, the release layer 93 and the second carrier 92 can be removed from the second molding structure 2. Then, a polishing process can be performed on the second surface 22 of the second molding structure 2. Then, a plurality of bumps 14 can be formed or disposed on the second surface 22 of the second molding structure 2. For example, these bumps 14 may include a plurality of first bumps 141 and a plurality of second bumps 142. First bumps 141 can be formed or disposed on the second surface 3152 (e.g., the lower surface) of the via 315. Second bumps 142 can be formed or disposed on the second surface of the semiconductor element 20 (e.g., the second surface 252 of the first semiconductor element 25). In some embodiments, the first bumps 141 and the second bumps 142 can be formed simultaneously in the same stage.

[0135] Referring to Figure 25, the second molding structure 2, the third redistribution structure 4, the second redistribution structure 8, the first molding structure 5, the first redistribution structure 7, and the upper electronic component 18 can be cut to form the package structure 10. Then, bumps 14 (e.g., first bump 141 and second bumps) can be attached to the substrate 12. Therefore, the package structure 10 can be attached to the substrate 12 through the bumps 14 (e.g., first bump 141 and second bumps).

[0136] Then, multiple external connectors 16 can be formed or disposed on the second surface 122 of the substrate 12 to provide electrical connections to the substrate 12, such as I / O connections. Thus, the assembly structure 1 of FIG1 is obtained.

[0137] Figure 26 is a flowchart illustrating a method 900 for preparing the assembly structure 1 according to some embodiments of this disclosure.

[0138] In some embodiments, the preparation method 900 may include step S901, forming a first molded structure on a first carrier. For example, as shown in FIG15, a first molded structure 5 may be formed on a first carrier 90.

[0139] In some embodiments, the fabrication method 900 may include step S902, which involves disposing an electronic component on the first molding structure. For example, as shown in FIG17, an electronic component 18 may be disposed on the first molding structure 5.

[0140] In some embodiments, the preparation method 900 may include step S903, removing the first carrier. For example, as shown in FIG18, the first carrier 90 may be removed.

[0141] In some embodiments, the preparation method 900 may include step S904, forming a second molded structure on a second carrier. For example, as shown in FIG21, a second molded structure 2 may be formed on a second carrier 92.

[0142] In some embodiments, the fabrication method 900 may include step S905, attaching the upper electronic component and the first molding structure to the second molding structure. For example, as shown in FIG23, the upper electronic component 18 and the first molding structure 5 may be attached to the second molding structure 2.

[0143] In some embodiments, the preparation method 900 may include step S906, removing the second carrier. For example, as shown in FIG24, the second carrier 92 may be removed.

[0144] One embodiment of this disclosure provides a packaging structure including a first molding structure, a first redistribution structure, and a second molding structure. The first molding structure has a first surface and a second surface opposite to the first surface, and includes at least one semiconductor element, at least one inactive element, and an encapsulant. The at least one inactive element is disposed around the at least one semiconductor element and includes a main portion and at least one via penetrating the main portion. The encapsulant encapsulates the at least one semiconductor element and the at least one inactive element. The first redistribution structure is disposed on the first surface of the first molding structure. The second redistribution structure is disposed on the second surface of the first molding structure and is electrically connected to the first redistribution structure through the at least one via of the at least one inactive element.

[0145] Another embodiment of this disclosure provides an assembly structure including a substrate, a first molding structure, a second molding structure, and an upper electronic component. The first molding structure is disposed above the substrate. The first molding structure includes at least one semiconductor element, at least one inactive element, and an encapsulating colloid encapsulating the at least one semiconductor element and the at least one inactive element. The second molding structure is disposed between the first molding structure and the substrate. The second molding structure includes at least one semiconductor element, at least one inactive element, and an encapsulating colloid encapsulating the at least one semiconductor element and the at least one inactive element. The upper electronic component is disposed above the first molding structure. The at least one inactive element of the first molding structure and the at least one inactive element of the second molding structure are configured to provide a vertical conductive path between the upper electronic component and the substrate.

[0146] Another embodiment of this disclosure provides a fabrication method. The fabrication method includes forming a first molded structure on a first carrier; disposing an upper electronic component on the first molded structure; removing the first carrier; forming a second molded structure on a second carrier; attaching the upper electronic component and the first molded structure to the second molded structure; and removing the second carrier.

[0147] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0148] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0149] 1: Assembly Structure 1a: Assembly structure 1b: Assembly structure 2: Second molding structure 2a: Second molding structure 2b: Second molding structure 3: Non-active components 4: Third Redistribution Structure 5: First molding structure 5a: First molding structure 5b: First molding structure 6: Non-active components 7: First Redistribution Structure 8: Second Redistribution Structure 10: Packaging Structure 10b: Package structure 12: Base 14: Bumps 16: External connector 18: Electronic components 19: Welding materials 20: Semiconductor components 21: First Surface 22: Second Surface 23: Side surface 25: First semiconductor element 26: Second semiconductor element 27: Encapsulating colloid 31: First non-active element 32: Second non-active element 32b: Second non-active element 33: Third non-active element 33b: Third non-active element 34: Fourth Non-Active Component 34b: Fourth Non-Active Element 41: First Surface 42: Second surface 43: Side surface 44: Dielectric layer 45: Circuit Layer 46:Inner through hole 47: Solder pad 50: Semiconductor components 51: First Surface 52: Second Surface 53: Side surface 55: First semiconductor element 56: Second semiconductor element 57: Encapsulating colloid 61: First non-active element 62: Second non-active element 62b: Second non-active element 63: Third non-active element 63b: Third non-active element 64: Fourth Non-Active Component 64b: Fourth Non-Active Element 71: First Surface 72: Second Surface 73: Side surface 74: Dielectric layer 75: Circuit Layer 76:Inner through hole 77: Solder pad 81: First Surface 82: Second Surface 83: Side surface 84: Dielectric layer 85: Circuit Layer 86:Inner through hole 87: Solder pad 90: The First Carrier 91: Release layer 92: Second Carrier 93: Release layer 121: First Surface 122: Second Surface 123: Side surface 141: First bump 142: Second bump 180: Main Part 181: First Surface 182: Second Surface 183: Side surface 184: Active Circuit Structure 185: Solder pad 191: Welding materials 250: Main Part 251: First Surface 252: Second Surface 253: Side surface 254: Active circuit structure 255: Solder pad 271: First Surface 272: Second Surface 273: Side surface 281: Space 282: Space 283: Space 310: Main Part 311: First Surface 312: Second Surface 313: Side surface 314: Side surface 315: Through hole 441: Topmost dielectric layer 442: Bottom dielectric layer 550: Main Part 551: First Surface 552: Second Surface 553: Side surface 554: Active circuit structure 555: Solder pad 571: First Surface 572: Second Surface 573: Side surface 581: Space 582: Space 583: Space 610: Main Part 611: First Surface 612: Second Surface 613: Side surface 614: Side surface 615: Through hole 741: Topmost dielectric layer 742: Bottom dielectric layer 841: Bottom dielectric layer 842: Topmost dielectric layer 900: Preparation Method 1801: Lower surface 2501: Upper surface 3151: First Surface 3152: Second Surface 3153: Central axis 5501: Upper surface 6151: First Surface 6152: Second Surface 6153: Central axis g1: Gap g2: gap g3: First gap g4: Second gap L1: Length L2: Length L3: Length L4: Length S901: Steps S902: Steps S903: Steps S904: Steps S905: Steps S906: Steps T1: Thickness T2: Thickness T3: Thickness T4: Thickness W1: Width W2: Width W3: Width W4: Width W5: Width W6: Width

Claims

1. An assembly structure comprising: One base; A first molding structure disposed above the substrate, wherein the first molding structure includes at least one semiconductor element, at least one inactive element, and an encapsulating colloid encapsulating the at least one semiconductor element and the at least one inactive element; a second molding structure disposed between the first molding structure and the substrate, wherein the second molding structure includes at least one semiconductor element, at least one inactive element, and an encapsulating colloid encapsulating the at least one semiconductor element and the at least one inactive element; and an upper electronic element disposed above the first molding structure, wherein the at least one inactive element of the first molding structure and the at least one inactive element of the second molding structure are configured to provide a vertical conductive path between the upper electronic element and the substrate, wherein the at least one inactive element of the first molding structure includes a plurality of vias, and the at least one inactive element of the second molding structure includes a plurality of vias, wherein a central axis of one of the vias of the first molding structure is substantially aligned with a central axis of one of the vias of the second molding structure.

2. The assembly structure as claimed in claim 1, wherein the upper electronic component is electrically connected to the first molding structure via hybrid bonding, and the first molding structure is electrically connected to the second molding structure via hybrid bonding.

3. The assembly structure as claimed in claim 1, wherein the upper electronic component is electrically connected to the first molding structure via a plurality of solder materials, and the first molding structure is electrically connected to the second molding structure via the solder materials.

4. The assembly structure as claimed in claim 1, wherein the upper electronic component vertically overlaps the at least one non-active component of the first molding structure and the at least one non-active component of the second molding structure.

5. The assembly structure as claimed in claim 1, wherein the width of the upper electronic component is equal to the width of the first molding structure, and the width of the upper electronic component is equal to the width of the second molding structure.

6. The assembly structure as claimed in claim 1, wherein one side surface of the upper electronic component is aligned with one side surface of the first molding structure and one side surface of the second molding structure.

7. The assembly structure as claimed in claim 1, wherein the at least one non-active element of the first molding structure includes a main portion and at least one through-hole through the main portion, and a second surface of the encapsulating colloid of the first molding structure is coplanar with a second surface of the at least one non-active element of the first molding structure and a second surface of the at least one semiconductor element of the first molding structure.

8. The assembly structure as claimed in claim 1, wherein the at least one non-active element of the second molding structure includes a main portion and at least one through-hole through the main portion, and a second surface of the encapsulating colloid of the second molding structure is coplanar with a second surface of the at least one non-active element of the second molding structure and a second surface of the at least one semiconductor element of the second molding structure.

9. The assembly structure as described in claim 8, further comprising: At least one first protrusion connects the at least one through hole of the second molded structure to the substrate; And at least one second bump, connecting the at least one semiconductor element of the second molded structure to the substrate.

10. The assembly structure as described in claim 9, wherein the at least one first bump and the at least one second bump are formed synchronously.

11. The assembly structure as claimed in claim 9, wherein the at least one second bump includes a reflowable material for controlling a gap between the second molded structure and the substrate.

12. The assembly structure as claimed in claim 9, wherein the at least one first bump includes a plurality of first bumps, the at least one second bump includes a plurality of second bumps, and a first gap between two adjacent first bumps is smaller than a second gap between two adjacent second bumps.

13. The assembly structure as described in claim 1, further comprising: A first redistribution structure is disposed between the first molding structure and the upper electronic component; A second redistribution structure is disposed below the first molding structure; and a third redistribution structure is disposed between the second redistribution structure and the second molding structure.

14. The assembly structure as described in claim 13, wherein the first redistribution structure comprises: Multiple dielectric layers; A plurality of circuit layers covered by the dielectric layers; and a plurality of vias connecting adjacent circuit layers, wherein the vias taper toward the first molded structure.

15. The assembly structure as claimed in claim 13, wherein the upper electronic component is attached to the first redistribution structure via hybrid bonding, and the second redistribution structure is attached to the third redistribution structure via hybrid bonding.

16. The assembly structure as claimed in claim 1, wherein a gap between adjacent through holes in the first molding structure is different from a gap between adjacent through holes in the second molding structure.

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