Semiconductor device structure and methods of forming the same

Abstract

The embodiments disclosed herein provide a semiconductor device structure and a method for forming the same. The structure includes a source / drain region disposed on a substrate, an interlayer dielectric layer disposed on the source / drain region, a first conductive feature disposed on the source / drain region, a gate electrode layer disposed on the substrate, and a dielectric layer surrounding the first conductive feature. The dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature, and a second portion disposed between the first conductive feature and the gate electrode layer. At least a portion of the first portion has a first thickness, and the second portion has a second thickness substantially greater than the first thickness.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuits than the previous generation. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using the manufacturing process) decreases. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, it is necessary to improve the processing and manufacturing of ICs. [Summary of the Invention]

[0004] None

Implementation Method

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of elements and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," "above," "top," "top," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations illustrated in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0008] While the embodiments of this disclosure discuss nanostructured channel FETs, such as gate all-around (GAA) FETs, such as horizontal gate all-around (HGAA) FETs or vertical gate all-around (VGAA) FETs, certain implementations of this disclosure can be used in other processes and / or other devices, such as planar FETs, fin FETs, and other suitable devices. Other modifications that may be considered within the scope of this disclosure will be readily apparent to those skilled in the art. In the case of a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern these structures, including dual-patterning processes or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine lithography and self-alignment processes to allow the creation of patterns, for example, patterns with a pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern a GAA structure.

[0009] Figures 1 through 15B illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of this disclosure. It will be understood that additional operations may be provided before, during, and after the processes shown in Figures 1 through 15B, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limited and is interchangeable.

[0010] Figures 1 through 6 are perspective views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate, wherein an insulating layer (not shown) is disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0011] The substrate 101 may include various regions that are doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0012] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels, such as nanostructure channel FETs, in multi-gate devices. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some embodiments, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106 and 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0013] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0014] The first semiconductor layer 106 or a portion thereof may form nanostructure channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term nanostructure is used herein to refer to any material portion having nanoscale or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers both to elongated material portions with circular and substantially circular cross-sections, and to beam-shaped or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes around the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0015] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 may have a thickness ranging from about 2 nm to about 50 nm. As illustrated in Figure 1, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately for illustrative purposes and are not intended to limit the specific content disclosed in the claims. It is understood that any number of first semiconductor layers 106 and any number of second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0016] In Figure 2, the fin structure 112 is formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including lithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process may include the following steps: forming a photoresist layer (not shown) on the hard mask layer; exposing the photoresist layer to the pattern; performing a post-exposure baking process; and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam lithography process may be used to pattern the photoresist layer to form the mask element. The etching process forms trenches 114 in unprotected areas, extending through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, thereby leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or combinations thereof can be used to etch the trenches 114.

[0017] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching back, is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0018] In Figure 4, insulating material 118 is recessed to form isolation region 120. The recessed insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recessed insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108, which contacts the substrate portion 116 formed from substrate 101.

[0019] In Figure 5, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Then, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers of the gate spacers 138 and anisotropically etching the one or more layers. In some embodiments, gate spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. In some embodiments, while one sacrificial gate structure 130 is displayed, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0020] The sacrificial gate dielectric layer 132 may include one or more dielectric material layers, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include multiple layers, such as oxide layers and nitride layers. The gate spacer 138 may be made of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbide, SiOCN and / or combinations thereof.

[0021] A portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as a channel region of the semiconductor device structure 100.

[0022] In Figure 6, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and gate spacer 138 is recessed above, below, or on the top surface of the isolation region 120. The partial recess of the fin structure 112 can be achieved by an etching process, an isotropic or anisotropic etching process, and the etching process can be selective relative to one or more crystalline planes of the substrate 101. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0023] Figures 7A, 7B and 7C are cross-sectional side views of the semiconductor device structure 100 taken along lines AA, BB and CC of Figure 6, respectively.

[0024] Figures 8A, 8B, and 8C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. As shown in Figure 8A, the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally in the X direction. The removal of the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0025] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 may be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 may be formed by first forming a conformal dielectric layer, such as ALD, using a conformal deposition process, and then anisotropically etching to remove portions of the conformal dielectric layer other than the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers the spacers 144 along the X direction.

[0026] Figures 9A, 9B, and 9C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. As shown in Figures 9A and 9C, a source / drain (S / D) region 146 is formed from a substrate portion 116. The S / D region 146 may be grown vertically and horizontally to form facets that correspond to crystal planes of the material used for the substrate portion 116. In this disclosure, the terms source region and drain region are used interchangeably and have substantially the same structure. Furthermore, source / drain region may refer to source / drain individually or collectively, depending on the context. The S / D region 146 may consist of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET or one or more layers of Si, SiGe, and Ge for a p-channel FET. For p-channel FETs, p-type dopants, such as boron (B), may also be included in the S / D region 146. The S / D region 146 may be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0027] In some embodiments, the S / D region 146 is an n-type epitaxial material, and a dielectric layer 202 (Figure 13A) may be formed beneath the S / D region 146. The dielectric layer 202 may prevent current leakage via the substrate portion 116. The dielectric layer 202 may include any suitable dielectric material, such as SiN. The dielectric layer 202 may be formed by first forming a conformal layer on the semiconductor device structure 100, forming a mask on a portion of the conformal layer, and removing the exposed portion of the conformal layer. In some embodiments, as shown in Figure 13A, the dielectric layer 202 is formed beneath the S / D region 146 of the n-type epitaxial material, and not beneath the S / D region of the p-type epitaxial material.

[0028] Figures 10A, 10B, and 10C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. In Figures 10A, 10B, and 10C, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. CESL 162 may include oxygen-containing or nitrogen-containing materials, such as silicon nitride, carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, carbon oxide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Then, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 of the semiconductor device structure 100. Materials used for the ILD layer 164 may include compounds (including Si, O, C, and / or H), such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the ILD layer 164. The ILD layer 164 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the ILD layer 164 is formed, the semiconductor device structure 100 may undergo a thermal treatment to anneal the ILD layer 164.

[0029] After the ILD layer 164 is formed, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in Figures 10A and 10B.

[0030] Figures 11A, 11B, and 11C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. As shown in Figures 11A and 11B, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The sacrificial gate structure 130 and the semiconductor layer 108 are removed to form openings between the gate spacers 138 and between the first semiconductor layer 106. The ILD layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate layer 134 can be removed first by any suitable method, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 can be removed by any suitable method, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the sacrificial gate electrode layer 134, but without removing the gate spacer 138, the ILD layer 164, and the CESL 162.

[0031] A portion of the second semiconductor layer 108 may be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemical composition used in the selective wet etching process removes the SiGe without substantially affecting the Si, the dielectric material of the gate spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 may use a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant, such as a fluorine-based (e.g., F2) or chlorine-based gas (e.g., Cl2), or any suitable isotropic etchant.

[0032] After the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106) is formed, a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive materials, such as polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the ILD layer 164. Then, the gate dielectric layer 170 and gate electrode layer 172 formed on the ILD layer 164 are removed by means of, for example, CMP, until the top surface of the ILD layer 164 is exposed.

[0033] Figures 12A, 12B, and 12C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. As shown in Figures 12B and 12C, a cut-metal gate (CMG) process is performed. The CMG process divides the gate electrode layer 172 into multiple individually controllable segments. In some embodiments, an opening is formed in the gate electrode layer 172. The opening may extend into the S / D region, such as between adjacent S / D regions 146, as shown in Figure 12C. A dielectric material 176 is formed in the opening. The dielectric material 176 may be any suitable material, such as SiN. In some embodiments, a seam 178 is formed in the dielectric material 176 due to the high aspect ratio of the opening.

[0034] Figures 13A to 13F are cross-sectional side views of various manufacturing stages of the semiconductor device structure 100 taken along the CC line of Figure 6 according to some embodiments. For clarity, CESL 162 is omitted in Figures 13A to 13F. As shown in Figure 13A, an etch stop layer 204 and another ILD layer 206 (Figure 12A) are formed on the ILD layer 164, the dielectric material 176, and the gate structure 174. The etch stop layer 204 may include the same material as CESL 162, and the ILD layer 206 may include the same material as ILD layer 164. An opening 208 is then formed in the ILD layers 164, 206, etch stop layer 204, and CESL 162 to expose the S / D region 146. In some embodiments, a plurality of openings 208 are formed, some openings 208 each exposing two or more S / D regions 146, while some openings 208 each exposing a single S / D region 146, as shown in Figure 13A. In some embodiments, two or more S / D regions 146 of the n-type epitaxial material are exposed in a single opening 208, while a single S / D region 146 of the p-type epitaxial material is exposed in the opening 208. The openings 208 may have different sizes (i.e., critical sizes), such as about 20 nm to about 30 nm, about 40 nm to about 60 nm, or greater than 80 nm.

[0035] In some embodiments, a portion of the CESL 162 (Figure 12A) formed on the sidewall of the gate spacer 138 (Figure 12A) is removed during the formation of the opening 208. To improve the isolation between the subsequently formed conductive feature (230, Figure 14A) and the gate electrode layer 172 (Figure 14A), a dielectric layer 210 is formed in the opening 208, as shown in Figure 13B. The dielectric layer 210 may include any suitable dielectric material. In some embodiments, the dielectric layer 210 includes SiO2, SiOC, SiOCN, or SiN. The dielectric layer 210 may be formed by any suitable process. In some embodiments, the dielectric layer 210 is a conformal layer and is formed by ALD. An anisotropic etching process is then performed to remove the horizontal portion of the dielectric layer 210. After the anisotropic etching process, the dielectric layer 210 is disposed on the sidewall of the opening 208. In the XZ plane, dielectric layer 210 can be formed on the sidewalls of ILD layers 206 and 164, the sidewalls of etch stop layer 204, and the sidewalls of CESL 162, as shown in Figure 13C. In the YZ plane, dielectric layer 210 can also be formed on the sidewalls of gate spacer 138, the sidewalls of ILD layer 206, and the sidewalls of etch stop layer 204, as shown in Figures 14A and 14B. The portion of dielectric layer 210 disposed in the YZ plane is in contact with gate spacer 138 and adjacent to gate electrode layer 172. The portion of dielectric layer 210 disposed in the XZ plane is not disposed near conductive material. At the current manufacturing stage (i.e., after the anisotropic etching process), the thickness of the portion of dielectric layer 210 disposed in the XZ plane is substantially the same as the thickness of the portion of dielectric layer 210 disposed in the YZ plane.

[0036] As shown in Figure 13D, an oblique implantation process 212 is performed to implant material into a portion of the dielectric layer 210 disposed in the XZ plane. The oblique implantation process 212 implants material, such as Ge, Xe, Ar, Si, or other suitable material, into the portion of the dielectric layer 210 disposed in the XZ plane, while the portion of the dielectric layer 210 disposed in the YZ plane is substantially unaffected by the oblique implantation process 212. In some embodiments, the oblique implantation process 212 has an implantation energy ranging from about 0.3 keV to about 50 keV, an implantation dose ranging from about 5E13 atoms / cm² to about 1E16 atoms / cm², and a processing temperature ranging from about -100°C to about 500°C. To implant material into portions of the dielectric layer 210 disposed in the XZ plane, while avoiding implantation of the material into portions of the dielectric layer 210 disposed in the YZ plane, the oblique implantation process 212 has an oblique angle ranging from about 1 degree to about 60 degrees, such as from about 5 degrees to about 45 degrees. Furthermore, the substrate 101 does not rotate during the oblique implantation process 212.

[0037] In some embodiments, the tilt angle A of the oblique placement is relatively small, such as less than about 15 degrees, for example, about 5 degrees to about 10 degrees. Therefore, the portion of the dielectric layer 210 disposed in the XZ plane is placed with the material from bottom to top. In other words, the material can reach the bottom of the portion of the dielectric layer disposed in the XZ plane with a relatively small tilt angle A. In these embodiments, more material can be placed into two or more S / D regions 146 exposed in a single opening 208 compared to material placed into a single S / D region 146 exposed in a single opening 208. A larger opening 208 results in more material reaching the S / D region 146 located at the bottom of the larger opening 208. The size of the opening 208 (i.e., the critical size of the opening 208 in the Y direction) determines the size of the subsequently formed conductive feature 230 (Figure 13G) (i.e., the size of the conductive feature 230 in the Y direction). Therefore, in some embodiments, there is a direct relationship between the size of the conductive feature 230 and the concentration of the substance in the S / D region 146 electrically connected to the conductive feature 230. For example, the concentration of the substance in the two S / D regions 146 exposed to a single opening 208 is substantially greater than the concentration of the substance in the single S / D region 146 exposed to a single opening 208.

[0038] Figure 13D-1 illustrates the material concentration profiles in two source / drain regions 146 of a semiconductor device structure 100 according to some embodiments. In some embodiments, the material concentration in a first S / D region 146 (which may be one of two S / D regions 146 exposed to a single opening 208) has a first concentration profile 302, and the material concentration in a second S / D region 146 (which may be a single S / D region 146 exposed to a single opening 208) has a concentration profile 304. As shown in Figure 13D-1, the material concentration in the first S / D region 146 is substantially greater than the material concentration in the second S / D region 146. The two concentration profiles 302, 304 show a decrease in material concentration in a direction away from the top surface of the first and second S / D regions 146.

[0039] In some embodiments, the tilt angle A of the oblique placement is relatively large, such as greater than about 30 degrees, for example, about 40 degrees to about 60 degrees. Therefore, the portion of the dielectric layer 210 disposed in the larger opening 208 in the XZ plane has the material placed from bottom to top, while the portion of the dielectric layer 210 disposed in the smaller opening 208 in the XZ plane has the material placed at the top. In other words, the material cannot reach the bottom of the dielectric layer portions disposed in the smaller openings 208 in the XZ plane, which have a relatively large tilt angle A. In these embodiments, more of the dielectric layer 210 disposed in the XZ plane has the material placed in the larger opening 208, while only the top of the portion of the dielectric layer 210 disposed in the XZ plane has the material placed in the smaller opening 208. For example, in the smallest opening 208, the material is deposited on top of the dielectric layer 210 in the Z direction on the XZ plane, and in the largest opening 208, the material is deposited on the entire portion of the dielectric layer 210 in the Z direction on the XZ plane. The length of the top portion of the dielectric layer 210 with the material deposited in the Z direction can increase with the increase of the size of the opening 208.

[0040] The portion of the dielectric layer 210 in which the material is deposited (such as the top portion of the entire portion of the dielectric layer 210 disposed in the XZ plane) may have a material concentration range of about 0.5% to about 10%, while the portion of the dielectric layer 210 in which the material is not deposited (such as the portion of the dielectric layer 210 disposed in the YZ plane and the bottom portion of the portion of the dielectric layer 210 disposed in the XZ plane) may have a material concentration range of about 0.01% to about 0.1%.

[0041] In some embodiments, after the slanted implantation process, another implantation process is performed to implant a dopant in the S / D region 146. The dopant can be any suitable dopant, such as Ge. The implantation process may not have a slant angle, and the substrate 101 may be rotated during the implantation process. Therefore, the implantation process differs from the slanted implantation process.

[0042] As shown in Figure 13E, a cleaning process is performed on the semiconductor device structure 100. The cleaning process removes any residual etchant from the process to form openings 208 and a dielectric layer 210. In some embodiments, the portion of the dielectric layer 210 with the material deposited has a much higher etch rate than the portion of the dielectric layer 210 without the material deposited during the cleaning process. Therefore, the portion of the dielectric layer 210 with the material deposited is removed by the cleaning process. The cleaning process can be a wet etching process using diluted HF or a chemical oxide removal (COR) dry etching process. In some embodiments, the Ge material and the cleaning process are a wet cleaning process using diluted HF. Therefore, the thickness of the portion of the dielectric layer 210 with the material deposited is removed by the cleaning process exceeding 1 nm. As shown in Figure 13E, in some embodiments, a portion of the dielectric layer 210 disposed in the XZ plane has a thickness T1 that is substantially smaller than the thickness of the portion of the dielectric layer 210 disposed in the XZ plane prior to the cleaning process. The thickness T1 can be substantially uniform because the material is implanted throughout the entire portion of the dielectric layer 210 disposed in the Z direction of the XZ plane.

[0043] In some embodiments, the dielectric layer 210 portion disposed in the Z direction has a non-uniform thickness after the cleaning process. As shown in Figure 13F, the portion of the dielectric layer 210 disposed in the smaller opening 208 in the XZ plane includes a top portion having a thickness T1 and a bottom portion having a thickness T2 substantially greater than the thickness T1. As described above, in some embodiments, the bottom portion of the dielectric layer 210 portion disposed in the smaller opening 208 in the XZ plane is not deposited with the material. Therefore, the bottom portion of the dielectric layer 210 portion disposed in the smaller opening 208 in the XZ plane is substantially unaffected by the cleaning process, while the thickness of the top portion of the dielectric layer 210 portion disposed in the smaller opening 208 in the XZ plane is reduced due to the cleaning process. In some embodiments, since the material is deposited throughout the entire portion of the dielectric layer 210 disposed in the larger opening 208 in the XZ plane in the Z direction, the thickness of the dielectric layer 210 portion disposed in the larger opening 208 in the XZ plane is reduced to T1 due to the cleaning process. As described above, the size of the conductive feature 230 is determined by the size of the opening 208. In some embodiments, there is a directional relationship between the size of the conductive feature 230 and the ratio of the portion of the dielectric layer 210 having thickness T1 in the XZ plane to the portion of the dielectric layer 210 having thickness T2 in the XZ plane. For example, as shown in Figure 13F, in the smallest opening 208, the portion of the dielectric layer 210 having thickness T1 in the XZ plane to the portion of the dielectric layer 210 having thickness T2 in the XZ plane may have a first ratio. In an opening 208 larger than the smallest opening 208 (intermediate opening 208), due to the increase in the portion of the dielectric layer 210 having thickness T1 in the XZ plane, the portion of the dielectric layer 210 having thickness T1 in the XZ plane to the portion of the dielectric layer 210 having thickness T2 in the XZ plane may have a second ratio, which is greater than the first ratio. In the maximum opening 208, any portion of the dielectric layer 210 disposed in the XZ plane does not have a thickness T2, and the ratio of the portion of the dielectric layer 210 disposed in the XZ plane with a thickness T1 to the portion of the dielectric layer 210 disposed in the XZ plane with a thickness T2 is infinite.

[0044] Following the cleaning process, a silicon layer 214 is formed on each exposed S / D region 146, as shown in Figures 13E and 13F. The silicon layer 214 may comprise any suitable material, such as NiSi, TiSi, CoSi, RuSi, or wSi. The silicon layer 214 may be formed by any suitable process. In some embodiments, the silicon layer 214 is selectively formed on the S / D regions 146.

[0045] Figure 13F-1 is a top view of a dielectric layer 210 of a semiconductor device structure according to some embodiments. After a cleaning process, the dielectric layer 210 includes a first portion 210a having a thickness T1 and a second portion 210b having a second thickness T2 substantially greater than the thickness T1. The first portion 210a may be a portion disposed in the XZ plane, while the second portion 210b may be a portion disposed in the YZ plane. The first portion 210a is connected to the second portion 210b. As described above, the first portion 210a is deposited with the material, while the second portion 210b is not deposited with the material. Therefore, the cleaning process removes a portion of the first portion 210a, while the second portion 210b is substantially unaffected by the cleaning process. In some embodiments, the first portion 210a has a different thickness along the Z direction. For example, the bottom portion of the first portion 210a has a thickness T2 substantially greater than the thickness T1 of the top portion of the first portion 210a. In some embodiments, the difference between the thickness T2 and the thickness T1 is greater than 1 nm.

[0046] As shown in Figure 13G, a conductive feature 230 is formed in the opening 208. The conductive feature 230 may be conductive and may include a material having one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The conductive feature 230 may be formed by any suitable method, such as electrochemical plating (ECP) or PVD. A planarization operation, such as a CMP method, is performed to remove portions of the conductive feature 230 formed on the ILD layer 206. Referring again to Figure 13F-1, in some embodiments, a dielectric layer 210 surrounds the conductive feature 230.

[0047] Figures 14A and 14B are cross-sectional side views taken along lines AA and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. For clarity, elements such as the gate dielectric layer 170, silicon layer 214, and CESL 162 are omitted. As shown in Figure 14A, the conductive feature 230 and the gate electrode layer 172 are separated by the gate spacer 138 and the second portion 210b of the dielectric layer 210. The thickness of the second portion 210b of the dielectric layer 210 is substantially unaffected by the cleaning process. Therefore, the electrical isolation between the conductive feature 230 and the gate electrode layer 172 is improved. As shown in Figure 14B, the thickness of the first portion 210a of the dielectric layer 210 is reduced due to the cleaning process. Therefore, the process window for forming the conductive feature 240 (Figure 15B) is enlarged.

[0048] Figures 15A and 15B are cross-sectional side views taken along lines AA and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. For clarity, elements such as the gate dielectric layer 170, silicon layer 214, and CESL 162 are omitted. As shown in Figure 15A, an etch stop layer 216 is formed on the ILD layer 206, the dielectric layer 210, and the conductive feature 230, and a dielectric layer 218 is formed on the etch stop layer 216. The etch stop layer 216 may include the same material as the etch stop layer 204, and the dielectric layer 218 may include the same material as the ILD layer 206. The conductive feature 220 is formed in the dielectric layer 218, the etch stop layer 216, the ILD layer 206, and the etch stop layer 204 to be electrically connected to the gate electrode layer 172. As shown in Figures 15A and 15B, conductive feature 240 is formed in dielectric layer 218 and etch stop layer 216, and conductive feature 240 is electrically connected to conductive feature 230. In some embodiments, conductive feature 240 is in direct contact with conductive feature 230. As shown in Figure 15B, the process window for forming conductive feature 240 is enlarged due to the reduced thickness of the first portion 210a of dielectric layer 210. Furthermore, in some embodiments, conductive feature 240 is in contact with conductive feature 230 and the first portion 210a of dielectric layer 210, as shown in Figure 15B. Due to the smaller thickness T1 of the first portion 210a of dielectric layer 210, the contact resistance of conductive feature 240 is reduced.

[0049] Figures 16A to 16C are cross-sectional side views of various manufacturing stages of the semiconductor device structure 100 taken along the CC line of Figure 6 according to an alternative embodiment. In some embodiments, the angled placement process 212 is performed after the deposition of the dielectric layer 210 but before the anisotropic etching process to remove the horizontal portion of the dielectric layer 210. The angled placement process places the material into a portion of the dielectric layer 210 disposed in the XZ plane. In these embodiments, the material from the angled placement process 212 may not be placed into the S / D region 146. Similar to the process described in Figure 13D, the material may be placed into the top portion or the entire portion (or the first portion 210a) of the dielectric layer 210 disposed in the XZ plane, depending on the tilt angle A (Figure 13D).

[0050] As shown in Figure 16B, an anisotropic etching process is performed to remove the horizontal portion of the dielectric layer 210. The material in the portion of the dielectric layer 210 does not substantially affect the result of the anisotropic etching process. In other words, at the end of the anisotropic etching process, the thickness of the dielectric layer 210 can be substantially uniform.

[0051] As shown in Figure 16C, the processes of implantation, cleaning, and formation of silicon layer 214 are performed. Similar to the processes described in Figures 13E, 13F, and 13F-1, the thickness of dielectric layer 210 changes after the cleaning process. Then, the processes described in Figures 14A, 14B, 15A, and 15B are performed. By performing the oblique implantation process 212 prior to the anisotropic etching process, the material is not implanted into the S / D region 146.

[0052] Embodiments of this disclosure provide a semiconductor device structure 100, which includes a first portion 210a disposed on a first plane and a second portion 210b disposed on a second plane substantially perpendicular to the first plane, comprising a dielectric layer 210. The first portion 210a has a first thickness T1, and the second portion 210b has a second thickness T2 substantially greater than the first thickness T1. Some embodiments may achieve advantages. For example, as the thickness T2 increases, the electrical isolation between the conductive feature 230 and the gate electrode layer 172 is improved. As the thickness T1 decreases, the process window for forming the conductive feature 240 is enlarged.

[0053] An embodiment is a semiconductor device structure. The semiconductor device structure includes a source / drain region disposed on a substrate, an interlayer dielectric layer disposed on the source / drain region, a first conductive feature disposed on the source / drain region, a gate electrode layer disposed on the substrate, and a dielectric layer surrounding the first conductive feature. The dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature, and a second portion disposed between the first conductive feature and the gate electrode layer. At least a portion of the first portion has a first thickness, and the second portion has a second thickness substantially greater than the first thickness. In some embodiments, a difference between the first thickness and the second thickness is greater than about 1 nm. In some embodiments, the dielectric layer comprises SiO2, SiOC, SiOCN, or SiN. In some embodiments, the semiconductor device structure further includes a silicon layer disposed between the source / drain region and the first conductive feature. In some embodiments, the semiconductor device structure further includes a second conductive feature in contact with the first conductive feature and the first portion of the dielectric layer. In some embodiments, the semiconductor device structure further includes a plurality of semiconductor layers, wherein a gate electrode layer surrounds at least a portion of each of the plurality of semiconductor layers. In some embodiments, the first portion includes a top portion having a first thickness and a bottom portion having a third thickness substantially greater than the first thickness. In some embodiments, the third thickness is substantially the same as the second thickness.

[0054] Another embodiment is a semiconductor device structure. The semiconductor device structure includes first and second source / drain regions disposed on a substrate, each of the first and second source / drain regions containing a substance, the first source / drain region having a first concentration of the substance, and the second source / drain region having a second concentration of the substance substantially lower than the first concentration. The structure further includes a first conductive feature disposed on the first source / drain region, and the first conductive feature having a first size. The structure further includes a second conductive feature disposed on the second source / drain region, and the second conductive feature having a second size substantially smaller than the first size. In some embodiments, the semiconductor device structure further includes a dielectric layer surrounding the first conductive feature. In some embodiments, the dielectric layer includes a first portion and a second portion, wherein the first portion is connected and substantially perpendicular to the second portion. In some embodiments, the first portion has a first thickness, and the second portion has a second thickness substantially greater than the first thickness. In some embodiments, the first portion includes a top portion having a third thickness and a bottom portion having a fourth thickness substantially greater than the third thickness. In some embodiments, the substance comprises Xe or Ar.

[0055] Another embodiment provides a method for forming a semiconductor device structure. The method for forming a semiconductor device structure includes the following steps: forming a fin-shaped structure from a substrate; recessing a portion of the fin-shaped structure to expose a portion of the substrate; forming a source / drain region on the substrate portion; forming a gate electrode layer on the substrate; depositing an interlayer dielectric layer in the source / drain region; forming an opening in the interlayer dielectric layer to expose the source / drain region; and depositing a dielectric layer in the opening. The dielectric layer includes a first portion disposed in a first plane and a second portion disposed in a second plane substantially perpendicular to the first plane. The method further includes the following steps: performing an oblique placement process to place material into the dielectric layer, wherein the material concentration in the first portion of the dielectric layer is substantially greater than the material concentration in the second portion of the dielectric layer. The method further includes the following steps: performing a cleaning process to remove a portion of the first portion of the dielectric layer; and filling the opening with a conductive feature. In some embodiments, the method for forming a semiconductor device structure further includes the following step: removing a plurality of horizontal portions of the dielectric layer before performing the oblique placement process. In some embodiments, the method of forming a semiconductor device structure further includes the step of removing multiple horizontal portions of a dielectric layer after performing an oblique placement process, wherein a cleaning process is performed after the step of removing the multiple horizontal portions of the dielectric layer. In some embodiments, the cleaning process is a wet cleaning process using diluted HF. In some embodiments, the oblique placement process has an angle ranging from about 1 degree to about 60 degrees. In some embodiments, the material comprises Ge, Xe, Ar, or Si.

[0056] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The various aspects of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1 to 6 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 7A to 12A are cross-sectional side views of various manufacturing stages of a semiconductor device structure taken along line AA of Figure 6 according to some embodiments. Figures 7B to 12B are cross-sectional side views of various manufacturing stages of a semiconductor device structure taken along line BB of Figure 6 according to some embodiments. Figures 7C to 12C are cross-sectional side views of various manufacturing stages of a semiconductor device structure taken along line CC of Figure 6 according to some embodiments. Figures 13A to 13G are cross-sectional side views of various manufacturing stages of a semiconductor device structure taken along line CC of Figure 6 according to some embodiments. Figure 13D-1 illustrates the concentration profiles of the material in the two source / drain regions of a semiconductor device structure according to some embodiments. Figure 13F-1 is a top view of the dielectric layer of a semiconductor device structure according to some embodiments. Figures 14A and 14B are cross-sectional side views of one of the manufacturing stages of a semiconductor device structure taken along lines AA and CC of Figure 6, respectively, according to some embodiments. Figures 15A and 15B are cross-sectional side views of one of the manufacturing stages of a semiconductor device structure taken along lines AA and CC of Figure 6, respectively, according to some embodiments. Figures 16A to 16C are cross-sectional side views of the various manufacturing stages of a semiconductor device structure taken along line CC of Figure 6, according to some embodiments.

Claims

1. A semiconductor device structure comprising: a source / drain region disposed on a substrate; an interlayer dielectric layer disposed on the source / drain region; a first conductive feature disposed on the source / drain region; a gate electrode layer disposed on the substrate; and a dielectric layer surrounding the first conductive feature, wherein the dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, wherein at least a portion of the first portion has a first thickness, and the second portion has a second thickness substantially greater than the first thickness, and a biomass concentration in the first portion of the dielectric layer is greater than a biomass concentration in the second portion of the dielectric layer.

2. The semiconductor device structure as claimed in claim 1, wherein a difference between the first thickness and the second thickness is greater than about 1 nm.

3. The semiconductor device structure as claimed in claim 1, further comprising a plurality of semiconductor layers, wherein the gate electrode layer surrounds at least a portion of each of the semiconductor layers.

4. A semiconductor device structure comprising: first and second source / drain regions disposed on a substrate, wherein each of the first and second source / drain regions comprises a substance, the first source / drain region having a first concentration of the substance, and the second source / drain region having a second concentration of the substance, the second concentration of the substance being substantially lower than the first concentration of the substance; a gate electrode layer disposed on the substrate and located between the first source / drain region and the second source / drain region; a first conductive feature disposed on the first source / drain region, wherein the first conductive feature has a first size; a second conductive feature disposed on the second source / drain region, wherein the second conductive feature has a second size substantially smaller than the first size; and an inter-dielectric layer disposed on the first and second source / drain regions. A dielectric layer surrounding the first conductive feature, wherein the dielectric layer includes a first portion disposed between the interlayer dielectric layer and the first conductive feature and a second portion disposed between the first conductive feature and the gate electrode layer, wherein at least a portion of the first portion has a first thickness and the second portion has a second thickness substantially greater than the first thickness, and a phytochemical concentration of the second portion of the dielectric layer is greater than a phytochemical concentration of the first portion of the dielectric layer.

5. The semiconductor device structure as claimed in claim 4, wherein the first portion of the dielectric layer includes a top portion and a bottom portion, the top portion having a third thickness, and the bottom portion having a fourth thickness substantially greater than the third thickness.

6. The semiconductor device structure as claimed in claim 5, wherein the concentration of the plant material in the first portion of the dielectric layer ranges from about 0.01% to about 0.1%, and the concentration of the plant material in the second portion of the dielectric layer ranges from about 0.5% to about 10%.

7. The semiconductor device structure as described in claim 4, wherein the material comprises Xe or Ar.

8. A method for forming a semiconductor device structure, comprising the steps of: forming a fin-shaped structure from a substrate; recessing a portion of the fin-shaped structure to expose a substrate portion; forming a source / drain region in the substrate portion; forming a gate electrode layer on the substrate; depositing an interlayer dielectric layer on the source / drain region; forming an opening in the interlayer dielectric layer to expose the source / drain region; depositing a dielectric layer in the opening, wherein the dielectric layer includes a first portion disposed in a first plane and a second portion disposed in a second plane substantially perpendicular to the first plane; performing an oblique implantation process to implant a material into the dielectric layer, wherein the concentration of a material in the first portion of the dielectric layer is substantially greater than the concentration of a material in the second portion of the dielectric layer; A cleaning process is performed to remove a portion of the first portion of the dielectric layer; and the opening is filled with a conductive feature, wherein the first portion of the dielectric layer is disposed between the interlayer dielectric layer and the conductive feature, the second portion of the dielectric layer is disposed between the conductive feature and the gate electrode layer, wherein at least a portion of the first portion has a first thickness, and the second portion has a second thickness substantially greater than the first thickness, and a phytochemical concentration of the second portion of the dielectric layer is greater than a phytochemical concentration of the first portion of the dielectric layer.

9. The method as described in claim 8 further includes the step of removing a plurality of horizontal portions of the dielectric layer prior to performing the oblique implantation process.

10. The method as described in claim 8 further comprises the step of removing a plurality of horizontal portions of the dielectric layer after performing the oblique placement process, wherein the cleaning process is performed after the step of removing the horizontal portions of the dielectric layer.

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