Method of manufacturing semiconductor structure

Abstract

A method for manufacturing a semiconductor structure includes forming a plurality of bit line structures on a substrate; forming a dielectric layer on the substrate and between the bit line structures; forming a layer stack on the dielectric layer comprising a plasma-treated oxygen-rich antireflective layer and a silicon-rich antireflective layer disposed thereon; forming a patterned mask layer on the layer stack comprising mask features and openings, the openings having a first width smaller than the spacing between adjacent bit line structures. The method further includes trimming the patterned mask layer to enlarge the openings, such that the openings have a second width greater than the first width; after trimming the patterned mask layer, using the patterned mask layer as a mask patterned layer stack; and etching the substrate using the patterned layer stack as a hard mask to form contact holes between the bit line structures.

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a semiconductor structure. [Previous Technology]

[0002] Semiconductor devices are widely used in various electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductor layers, and semiconductor layers or materials on a semiconductor substrate, and then patterning these material layers using optical lithography to fabricate integrated circuits. With the development of semiconductor technology, the demand for high device density, high efficiency, and low manufacturing costs is increasing. Therefore, accurately controlling the yield of the optical lithography process across the entire wafer has become a challenge. [Summary of the Invention]

[0003] One embodiment of this disclosure provides a method for manufacturing a semiconductor structure, comprising forming a plurality of bit line structures on a substrate; forming a dielectric layer on the substrate and between the bit line structures; forming a layer stack on the dielectric layer, wherein the layer stack includes a plasma-treated oxygen-rich antireflective layer and a silicon-rich antireflective layer disposed on the plasma-treated oxygen-rich antireflective layer; forming a patterned mask layer on the layer stack, wherein the patterned mask layer includes masking features and an opening defined by the masking features, the opening having a first width, and the first width being smaller than the spacing between adjacent bit line structures. The method for manufacturing a semiconductor structure further includes trimming the patterned mask layer to enlarge the opening, such that the opening has a second width greater than the first width; after trimming the patterned mask layer, using the patterned mask layer as a mask patterned layer stack; and using the patterned layer stack as a hard mask, etching the substrate to form contact holes between the bit line structures.

[0004] In some embodiments, the step of trimming the patterned mask layer includes directional dry etching or tilt etching.

[0005] In some embodiments, the sidewalls with openings of a second width are not perpendicular to the top surface of the stacked layers.

[0006] In some embodiments, the second width of the opening gradually decreases from the top surface to the bottom surface of the masking feature.

[0007] In some embodiments, the second width of the opening decreases in a stepped manner from the top surface to the bottom surface of the masking feature.

[0008] In some embodiments, the second width is the same as the spacing between adjacent bit line structures.

[0009] In some embodiments, the step of forming a layer stack includes: forming a first layer containing oxygen on a dielectric layer; forming a second layer containing oxygen on the first layer; forming a third layer containing carbon on the second layer; forming an oxygen-rich antireflective layer on the third layer; plasma treating the oxygen-rich antireflective layer; and forming a silicon-rich antireflective layer on the plasma-treated oxygen-rich antireflective layer.

[0010] In some embodiments, plasma treatment includes using He and N2O as reaction gases.

[0011] In some embodiments, the power of the plasma treatment is between 800W and 1000W.

[0012] In some embodiments, the step of forming a layer stack includes forming an underlayer containing photoresist on a silicon-rich antireflective layer, wherein a patterned mask layer is formed on the underlayer.

[0013] In some embodiments, the oxygen-rich antireflective layer is formed in a first deposition chamber, and the silicon-rich antireflective layer is formed in a second deposition chamber.

[0014] In some embodiments, plasma treatment is performed in a first deposition chamber.

[0015] In some embodiments, the oxygen-rich antireflective layer and the silicon-rich antireflective layer are formed in the same plasma-enhanced chemical vapor deposition chamber.

[0016] In some embodiments, the plasma treatment is performed in the same plasma-enhanced chemical vapor deposition chamber.

[0017] In some embodiments, the method of manufacturing the semiconductor structure further includes forming capacitive contacts in the contact holes.

[0018] Another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, comprising forming a plurality of bit line structures on a substrate; forming a dielectric layer on the substrate and between the bit line structures; depositing an oxygen-rich antireflective layer on the dielectric layer; performing plasma treatment on the oxygen-rich antireflective layer, the plasma treatment comprising using He and N2O as reaction gases, and the power of the plasma treatment being between 800W and 1000W; and forming a silicon-rich antireflective layer on the plasma-treated oxygen-rich antireflective layer.

[0019] In some embodiments, the oxygen-rich antireflective layer is formed in a first deposition chamber, and the silicon-rich antireflective layer is formed in a second deposition chamber.

[0020] In some embodiments, plasma treatment is performed in a first deposition chamber.

[0021] In some embodiments, the oxygen-rich antireflective layer and the silicon-rich antireflective layer are formed in the same plasma-enhanced chemical vapor deposition chamber.

[0022] In some embodiments, the plasma treatment is performed in the same plasma-enhanced chemical vapor deposition chamber.

[0023] Some embodiments of the semiconductor structure manufacturing method disclosed herein improve the quality of the hard mask by performing plasma treatment on the oxygen-rich antireflective layer before depositing the silicon-rich antireflective layer.

Implementation Method

[0025] Several embodiments of this disclosure will be disclosed below with reference to the drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, these practical details are not necessary in some embodiments of this disclosure. In addition, for the sake of simplicity, some conventional structures and elements will be shown in the drawings in a simple schematic manner, and in all drawings, the same reference numerals will be used to denote the same or similar elements. And, where feasible, features of different embodiments can be applied interchangeably.

[0026] The terms “include,” “including,” “have,” and similar words used in this document are open-ended terms, meaning that they include but are not limited to these terms.

[0027] The embodiments disclosed herein provide multiple operation steps. The order of some or all of these operation steps described herein does not imply that these operation steps can only be performed in such an order. If it is beneficial to this disclosure, the order of these operation steps may also be adjusted. In addition, these operation steps may be omitted depending on the embodiment, and additional operation steps may be added to these operation steps depending on the embodiment.

[0028] Referring to Figures 1 to 11, Figures 1 to 11 are cross-sectional views of different steps in a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure. Referring to Figure 1, the method for manufacturing a semiconductor structure begins in step S10, where at least one bit line contact 110 is formed on a substrate 102.

[0029] The substrate 102 may include a plurality of isolation regions 104 and a plurality of active regions 106. The substrate 102 may be, for example, a silicon substrate (such as a monocrystalline silicon substrate, a polycrystalline silicon substrate, or an amorphous silicon substrate). Optionally, the substrate 102 may be a silicon substrate doped with other semiconductor elements, such as germanium. In some embodiments, the substrate 102 may include a semiconductor alloy, such as SiGe, SiGeC, GaInP, etc. In some embodiments, the substrate 102 may include a semiconductor compound, such as GaAs, SiC, InP, InAs, etc. In addition, in some embodiments, the substrate 102 may include a silicon-on-insulator structure. The active regions 106 may be doped regions in the substrate 102, and the active regions 106 are isolated from each other by isolation regions 104.

[0030] The isolation region 104 can be manufactured using a shallow trench isolation technique. The isolation region 104 may comprise, for example, a material comprising at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation region 104 may comprise a single-layer dielectric layer, a double-layer dielectric layer, or a multi-layer dielectric layer. For example, the isolation region 104 may be a double-layer structure comprising silicon oxide and silicon nitride. For example, the isolation region 104 may be a triple-layer structure comprising silicon oxide, silicon nitride, and silicon oxynitride.

[0031] An isolation layer 108 is formed on a substrate 102 and covers the upper surfaces of the isolation region 104 and the active region 106 of the substrate 102. The isolation layer 108 includes at least one opening to expose at least one of the active regions 106 of the substrate 102. The opening is further filled with a conductive material to form a bit line contact 110. In some embodiments, the bit line contact 110 is electrically connected to the corresponding active region 106, and a portion of the active region 106 serves as the source of a transistor.

[0032] A plurality of bit lines 120 protrude from the substrate 102. In some embodiments, the bit lines 120 may be arranged regularly on the substrate 102 at the same spacing. The bit lines 120 comprise two portions disposed along the vertical direction (i.e., along the Z direction) of the substrate 102. In some embodiments, the bit lines 120 comprise a conductor layer 122 located in the lower half and an insulating capping layer 124 located in the upper half.

[0033] The steps of fabricating the conductor layer 122 and the insulating capping layer 124 include forming a conductive material layer and an insulating capping layer on the substrate 102, wherein the insulating capping layer is formed on the conductive material layer. In some embodiments, the insulating capping layer and the conductive material layer are simultaneously etched to form the conductor layer 122 and the insulating capping layer 124. In this way, the plurality of bit lines 120 including the conductor layer 122 and the insulating capping layer 124 can be separated in a first direction (such as the X direction), and the plurality of bit lines 120 are arranged in parallel in a second direction (such as the Y direction).

[0034] In some embodiments, the conductor layer 122 comprises at least one conductive material, such as a doped semiconductor, a metal, a conductive metal nitride, a metal silicate, etc. In some embodiments, the conductor layer 122 may be a stacked structure. For example, the conductor layer 122 may be a stack comprising doped semiconductors, metals, conductive metal nitrides, such as W, WN, and / or TiN, etc. The conductor layer 122 is electrically connected to the bit line contact 110.

[0035] In some embodiments, the insulating cap layer 124 comprises silicon nitride. The vertical length of the insulating cap layer 124 (i.e., the length along the Z direction) may be greater than the vertical length of the conductor layer 122.

[0036] Referring to Figure 2, the semiconductor structure manufacturing method proceeds to step S12, where the spacer layer 130 is disposed along the sidewall of the bit line 120. The spacer layer 130 can be a single-layer structure or a multi-layer structure. In some embodiments, the spacer layer 130 may comprise silicon nitride, silicon oxide, or a combination thereof. In some embodiments, the spacer layer 130 may comprise a sacrificial layer, which can be removed in a subsequent process to form an air gap in the spacer layer 130. In some embodiments, the spacer layer 130 can be fabricated using any suitable process, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.

[0037] Referring to Figure 3, the semiconductor structure manufacturing method proceeds to step S14, where a dielectric layer 140 is formed between adjacent bit lines 120 and spacer layers 130. In some embodiments, the bit lines 120 and the spacer layers 130 thereon may also be referred to as a bit line structure. The dielectric layer 140 is disposed on the substrate 102 and located in the space between the bit lines 120. The dielectric layer 140 may contain, for example, silicon nitride, silicon dioxide, or a combination thereof. In some embodiments, the dielectric layer 140 is deposited through a deposition process with good filling capability, such as a flowable chemical vapor deposition process. Optionally, a planarization process may be performed such that the top surface of the dielectric layer 140 is coplanar with the top surface of the spacer layers 130 on the bit lines 120.

[0038] Referring to Figure 4, the semiconductor structure manufacturing method proceeds to step S16, where a bottom segment of the layer stack 150 is formed on the dielectric layer 140. The layer stack 150 includes a material used as a hard mask layer. In some embodiments, the layer stack 150 includes a first layer 151 on the dielectric layer 140, a second layer 152 on the first layer 151, a third layer 153 on the second layer 152, and a fourth layer 154 on the third layer 153. The first layer 151 to the fourth layer 154 may be dielectric materials.

[0039] In some embodiments, the first layer 151 and the second layer 152 are oxides, and the first layer 151 and the second layer 152 are made of different materials and / or processes. For example, the first layer 151 may be a hydrogen silsesquioxane (HSQ) or a methyl silsesquioxane (MSQ), and may be formed using a spin-on-dielectric (SOD) process. The second layer 152 may be tetraethyl orthosilicate (TES), and may be formed using a deposition process.

[0040] The third layer 153 may be a layer comprising carbon, hydrogen, and oxygen. In some embodiments, the third layer 153 may be a layer comprising carbon, hydrogen, and fluorine. In some embodiments, the third layer 153 may be a carbon film. The term "carbon film" is used herein to describe a material whose mass is primarily carbon, whose structure is primarily defined by carbon atoms, or whose physical and chemical properties are dominated by its carbon content. The term "carbon film" refers to materials that do not include simple mixtures or compounds comprising carbon, such as dielectric materials, such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polycrystalline silicon.

[0041] The fourth layer 154 is an anti-reflective layer. In some embodiments, the fourth layer 154 comprises an inorganic material, such as silicon oxynitride. More specifically, the fourth layer 154 is an oxygen-rich silicon oxynitride layer, wherein the oxygen atom percentage of the fourth layer 154 is between 30% and 50%.

[0042] Referring to Figure 5, the semiconductor structure manufacturing method proceeds to step S18, where a plasma treatment is performed on the fourth layer 154. The plasma treatment is performed to improve the surface roughness of the fourth layer 154 and / or the adhesion between the fourth layer 154 and an overlying layer (not shown). The plasma treatment includes the use of He and N₂O as reaction gases, and the power of the plasma treatment is between 800W and 1000W. If the power of the plasma treatment is less than 800W, it does not significantly help improve the surface roughness of the fourth layer 154. For example, if the power of the plasma treatment increases from 560W to 1000W, the surface roughness of the fourth layer 154 will improve from about 0.475nm to about 0.375nm, and the number of failed wafers per batch will decrease from 10 to 7. However, if the power of the plasma treatment is greater than 1000W, it may cause undesirable damage to the fourth layer 154, and the process time and cost will also increase.

[0043] Referring to Figure 6, the semiconductor structure manufacturing method proceeds to step S20, where the top segment of the layer stack 150 is further formed on the fourth layer 154. The layer stack 150 further includes a fifth layer 155 disposed on the fourth layer 154, and a sixth layer 156 disposed on the fifth layer 155.

[0044] In some embodiments, the fifth layer 155 is an anti-reflective layer. In some embodiments, the fifth layer 155 comprises an inorganic material, such as silicon oxynitride. More specifically, the fifth layer 155 is a silicon-rich silicon oxynitride layer, wherein the silicon atom percentage of the fifth layer 155 is approximately 60%. In other words, the fourth layer 154 together with the fifth layer 155 can be considered as a bilayer anti-reflective layer. The silicon atom percentage in the fifth layer 155 is higher than that in the fourth layer 154, and the oxygen atom percentage in the fourth layer 154 is higher than that in the fifth layer 155.

[0045] After plasma treatment of the fourth layer 154, the surface roughness of the fourth layer 154 is improved, and the adhesion between the fourth layer 154 and the fifth layer 155 is also enhanced. Therefore, in subsequent processes, the potential peeling problem between the interface of the fourth layer 154 and the fifth layer 155 can be avoided.

[0046] In some embodiments, the sixth layer 156 is an underlayer containing an organic material such as a polymer. In some embodiments, the sixth layer 156 is coated on the fifth layer 155, and the thickness T1 of the sixth layer 156 is greater than the sum of the thickness T2 of the fourth layer 154 and the thickness T3 of the fifth layer 155.

[0047] Referring to Figure 7, the semiconductor structure fabrication method proceeds to step S22, where a patterned mask layer 160 is formed on the layer stack 150. The patterned mask layer 160 includes at least one mask feature 162 and a plurality of openings OP1 defined by the mask feature 162. In some embodiments, the material of the patterned mask layer 160 includes photoresist, and the mask feature 162 and the openings OP1 are defined by a photolithography process. In some embodiments, the location of the openings OP1 corresponds to the location of contact holes located between bit line structures, wherein the bit line structures include bit lines 120 and spacer layers 130, and other areas besides the contact holes are covered by the mask feature 162. Therefore, the sixth layer 156 can be used to protect the layers below it and can serve as an etch stop layer.

[0048] Adjacent bit line structures, including bit lines 120 and spacer layers 130, are defined with a spacing p1 between them. More specifically, the spacing P1 is the distance measured along the X direction between the outer surfaces of two opposite portions of the spacer layer 130. Each opening OP1 has a width W11. The width W11 of each opening OP1 is smaller than the spacing P1 between adjacent bit line structures. In some embodiments, the sidewall of each opening OP1 is substantially perpendicular to the top surface of the sixth layer 156.

[0049] Referring to Figure 8A, the semiconductor structure manufacturing method proceeds to step S24, where a trimming process is performed on the patterned mask layer 160 to enlarge the openings OP1. In some embodiments, the trimming process may be etching or other suitable processes. After the trimming process is completed, each opening OP1 has a width W12, which is larger than the width W11 before trimming. After the trimming process, the width W12 of each opening OP1 is substantially the same as the spacing P1 between adjacent bit line structures.

[0050] In some embodiments, the trimming process is a directional dry etching or a tilting etching, such that after the trimming process, the sidewalls of each opening OP1 are not perpendicular to the top surface of the sixth layer 156. For example, each opening OP1 has a width W12 defined by the top surface 163 of the masking feature 162 and a width W13 defined by the bottom surface 164 of the masking feature 162. The width W12 is greater than the width W13, and the width W12 is substantially the same as the spacing P1 between adjacent bit line structures. In some embodiments, the width of each opening OP1 gradually decreases from W12 to W13. In other embodiments, the width of each opening OP1 decreases in a stepped manner from W12 to W13.

[0051] Because the patterned mask layer 160 is patterned and trimmed, the outline of the mask feature 162 is difficult to control. The stress and heat accumulated during the patterning and trimming processes will accumulate in the layer stack 150. By performing plasma processing on the fourth layer 154, the problem of peeling between the fourth layer 154 and the fifth layer 155 can be avoided, thereby improving the quality of the hard mask formed by the layer stack 150.

[0052] Referring to Figure 9, the semiconductor structure fabrication method proceeds to step S26, where a mask feature 162 (see Figure 8A or Figure 8B) is used as a mask to pattern the layer stack 150. An opening OP1 (see Figure 8A or Figure 8B) is deepened to form an opening OP2 surrounded by the layer stack 150. This patterned layer stack 150 can be considered as a hard mask during subsequent etching of contact holes. A portion of the top surface of the dielectric layer 140 is exposed through opening OP2 after the layer stack 150 is patterned. In some embodiments, the mask feature 162 may be consumed during patterning. In other embodiments, the mask feature 162 may be removed after patterning.

[0053] Referring to Figure 10, the semiconductor structure manufacturing method proceeds to step S28, where a plurality of contact holes 170 are formed between adjacent bit line structures. The contact holes 170 are formed by etching using a patterned layer stack 150 (see Figure 9) as a hard mask. By performing plasma treatment on the fourth layer 154, the adhesion of the layer stack 150 can be improved, thus reducing the peeling problem between the double anti-reflective layers, i.e., the fourth layer 154 and the fifth layer 155. Therefore, the precision of fabricating the contact holes 170 can be improved accordingly.

[0054] The portions of the dielectric layer 140, the isolation layer 108, and the substrate 102 not covered by the patterned layer stack 150 are removed. The portion of the substrate 102 to be removed includes the isolation region 104 and the active region 106 of the removed portion, such that each contact hole 170 has a recessed bottom surface below the bit line 120. In some embodiments, the patterned layer stack 150 may be consumed during the formation of the contact hole 170. In other embodiments, the patterned layer stack 150 may be removed after the contact hole 170 has been formed.

[0055] Referring to Figure 11, the semiconductor structure manufacturing method proceeds to step S30, where a plurality of capacitor contacts 180 are formed in contact holes 170. The formation of the capacitor contacts 180 includes depositing conductive material to fill the contact holes 170, and performing an etch-back process to recess the conductive material in the contact holes 170. In some embodiments, the material of the capacitor contacts 180 comprises a metal, such as tungsten or an aluminum-copper alloy. In some embodiments, the material of the capacitor contacts 180 comprises a metal nitride, such as titanium nitride. The capacitor contacts 180 may be further connected to a capacitor, hence the capacitor contacts 180 are also referred to as capacitor contacts.

[0056] Referring to Figure 12, it is a schematic flowchart of forming a double-layer anti-reflection layer in a semiconductor structure according to some embodiments of the present disclosure. The schematic flowchart of forming a double-layer anti-reflection layer in a semiconductor structure begins at block B01 and includes placing a wafer in a first deposition chamber. The wafer may include a substrate, bit line structures on the substrate, a dielectric layer covering the bit line structures, and a bottom segment of the layer stack on the dielectric layer.

[0057] The schematic flow for forming a double-layer antireflective layer in a semiconductor structure proceeds to block B02, where the first deposition chamber is adjusted to a stable state. This adjustment includes adjusting the temperature and pressure of the first deposition chamber to the desired levels. In block B03, an oxygen-rich antireflective layer, such as an oxygen-rich oxide nitride layer, is deposited on the wafer. The deposition step used to deposit the oxygen-rich antireflective layer can be plasma-enhanced chemical vapor deposition (PECVD). The gas used in PECVD includes a nitrogen-containing gas, such as SiH₄ / N₂O. The oxygen atom percentage of the oxygen-rich antireflective layer is between 30% and 50%.

[0058] In block B04, a clean gas, such as nitrogen or an inert gas, is introduced into the first deposition chamber. Then, the clean gas is extracted in block B05 to complete the cleaning process of the first deposition chamber.

[0059] In block B06, the oxygen-enriched antireflective layer is subjected to plasma treatment. The plasma treatment is performed to improve the surface roughness of the oxygen-enriched antireflective layer. The plasma treatment involves using He and N₂O as reactant gases, and the power of the plasma treatment is between 800W and 1000W. If the power of the plasma treatment is less than 800W, it does not significantly improve the surface roughness of the oxygen-enriched antireflective layer. If the power of the plasma treatment is greater than 1000W, it may cause undesirable damage to the oxygen-enriched antireflective layer, and the process time and cost will also increase.

[0060] After the plasma treatment of the oxygen-rich anti-reflective layer is completed, the process continues to block B07, where a clean gas, such as nitrogen or an inert gas, is introduced into the first deposition chamber. Then, the clean gas is extracted in block B08 to complete the wafer cleaning process.

[0061] Next, block B09 includes moving the wafer from the first deposition chamber to the second deposition chamber. In block B10, the second deposition chamber is adjusted to a stable state, wherein the step of adjusting the second deposition chamber includes adjusting the temperature and pressure of the second deposition chamber to a desired temperature and pressure. In block B11, a silicon-rich antireflective layer, such as a silicon-rich oxide nitride layer, is deposited on the oxygen-rich antireflective layer on the wafer. In some embodiments, the deposition step used to deposit the silicon-rich antireflective layer may be plasma-enhanced chemical vapor deposition. The gas used in plasma-enhanced chemical vapor deposition includes a nitrogen-containing gas, such as SiH4 / N2O. The silicon atomic percentage of the silicon-rich antireflective layer is approximately 60%. In other embodiments, the deposition step used to deposit the silicon-rich antireflective layer may not be limited to plasma-enhanced chemical vapor deposition.

[0062] After the silicon-rich anti-reflection layer is deposited, the process enters block B12, where a clean gas, such as nitrogen or an inert gas, is introduced into the second deposition chamber. Then, the clean gas is extracted in block B13 to complete the cleaning process of the second deposition chamber.

[0063] The oxygen-rich antireflective layer and the silicon-rich antireflective layer are deposited in the first deposition chamber and the second deposition chamber, respectively. Therefore, the plasma-treated double-layer antireflective layer can be considered as an ex-situ deposition. That is, the selection of the first and second deposition chambers can be more flexible. Additionally, plasma-treating the oxygen-rich antireflective layer before depositing the silicon-rich antireflective layer can enhance the adhesion between the silicon-rich antireflective layer and the oxygen-rich antireflective layer.

[0064] Referring to Figure 13, it is a schematic flowchart of forming a double antireflective layer in a semiconductor structure according to some other embodiments of the present disclosure. The schematic flowchart of forming a double antireflective layer in a semiconductor structure begins at block B21 and includes placing a wafer in a plasma-enhanced chemical vapor deposition chamber. The wafer may include a substrate, bit line structures on the substrate, a dielectric layer covering the bit line structures, and a bottom segment of the layer stack on the dielectric layer.

[0065] The schematic flow for forming a double-layer antireflective layer in a semiconductor structure proceeds to block B22, where the plasma-enhanced chemical vapor deposition (PECVD) chamber is adjusted to a stable state. This adjustment includes adjusting the temperature and pressure of the PECVD chamber to the desired levels. In block B23, an oxygen-rich antireflective layer, such as an oxygen-rich oxide nitride layer, is deposited on the wafer. The deposition step used to deposit the oxygen-rich antireflective layer can be plasma-enhanced chemical vapor deposition. The gas used in the plasma-enhanced chemical vapor deposition includes a nitrogen-containing gas, such as SiH₄ / N₂O. The oxygen atom percentage of the oxygen-rich antireflective layer is between 30% and 50%.

[0066] In block B24, a clean gas, such as nitrogen or an inert gas, is introduced into the plasma-enhanced chemical vapor deposition chamber. Then, the clean gas is extracted in block B25 to complete the cleaning process of the plasma-enhanced chemical vapor deposition chamber.

[0067] In block B26, the oxygen-enriched antireflective layer is subjected to plasma treatment. The plasma treatment is performed to improve the surface roughness of the oxygen-enriched antireflective layer. The plasma treatment involves using He and N₂O as reactant gases, and the power of the plasma treatment is between 800W and 1000W. If the power of the plasma treatment is less than 800W, it does not significantly improve the surface roughness of the oxygen-enriched antireflective layer. If the power of the plasma treatment is greater than 1000W, it may cause undesirable damage to the oxygen-enriched antireflective layer, and the process time and cost will also increase.

[0068] After the plasma treatment of the oxygen-rich anti-reflective layer is completed, the process continues to block B27, where a clean gas, such as nitrogen or an inert gas, is introduced into the plasma-enhanced chemical vapor deposition chamber. Then, the clean gas is extracted in block B28 to complete the wafer cleaning process.

[0069] Next, block B29 includes adjusting the plasma-enhanced chemical vapor deposition chamber to a stable state, wherein the step of adjusting the plasma-enhanced chemical vapor deposition chamber includes adjusting the temperature and pressure of the plasma-enhanced chemical vapor deposition chamber to a desired temperature and pressure. In block B30, a silicon-rich antireflective layer, such as a silicon-rich oxide nitride layer, is deposited on an oxygen-rich antireflective layer on the wafer. In some embodiments, the gas used in the plasma-enhanced chemical vapor deposition includes a nitrogen-containing gas, such as SiH4 / N2O. The silicon atomic percentage of the silicon-rich antireflective layer is approximately 60%.

[0070] After the silicon-rich anti-reflection layer is deposited, the process enters block B31, where a clean gas, such as nitrogen or an inert gas, is introduced into the plasma-enhanced chemical vapor deposition chamber. Then, the clean gas is extracted in block B32 to complete the cleaning process of the plasma-enhanced chemical vapor deposition chamber.

[0071] The oxygen-rich antireflective layer and the silicon-rich antireflective layer are deposited in the same plasma-enhanced chemical vapor deposition chamber, eliminating the need to transfer the wafer between chambers. Therefore, the plasma-treated double antireflective layer can be considered as an in-situ deposition. The time required for deposition and plasma treatment of the double antireflective layer can be significantly reduced.

[0072] Compared to the off-site process, the off-site process processes 109.6 wafers per hour with a surface roughness of 0.475µm for the oxygen-rich antireflective layer, while the on-site process processes 117.4 wafers per hour with a surface roughness of 0.375nm for the oxygen-rich antireflective layer. Therefore, by performing plasma treatment on the oxygen-rich antireflective layer in situ before depositing the silicon-rich antireflective layer, the adhesion between the interface of the oxygen-rich antireflective layer and the silicon-rich antireflective layer, as well as the wafer yield, can be improved.

[0073] Although this disclosure has been disclosed above with reference to embodiments, it is not intended to limit this disclosure. Anyone skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0024] To make the objectives, features, advantages, and embodiments of this disclosure more apparent and understandable, the detailed description of the accompanying drawings is as follows: Figures 1 to 11 are cross-sectional views of different steps in a method for manufacturing a semiconductor structure according to some embodiments of this disclosure. Figure 12 is a schematic flowchart of forming a double-layer anti-reflection layer in a semiconductor structure according to some embodiments of this disclosure. Figure 13 is a schematic flowchart of forming a double-layer anti-reflection layer in a semiconductor structure according to some other embodiments of this disclosure. [Biomaterial Storage]

[0075] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a semiconductor structure, comprising: forming a plurality of bit line structures on a substrate; forming a dielectric layer on the substrate and between the bit line structures; forming a stack on the dielectric layer, wherein the stack includes a plasma-treated oxygen-rich antireflective layer and a silicon-rich antireflective layer disposed on the plasma-treated oxygen-rich antireflective layer; forming a patterned mask layer on the stack, wherein the patterned mask layer includes a mask feature and an opening defined by the mask feature, the opening having a first width, and the first width being smaller than a spacing between adjacent bit line structures; trimming the patterned mask layer to enlarge the opening, such that the opening has a second width greater than the first width; after trimming the patterned mask layer, patterning the stack using the patterned mask layer as a mask; and etching the substrate using the patterned stack as a hard mask to form a contact hole between the bit line structures.

2. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the step of trimming the patterned mask layer includes a directional dry etching or a tilt etching.

3. A method of manufacturing a semiconductor structure as claimed in claim 2, wherein the sidewall of the opening having the second width is not perpendicular to the top surface of the stacked layers.

4. A method of manufacturing a semiconductor structure as claimed in claim 3, wherein the second width of the opening gradually decreases from the top surface to the bottom surface of the mask feature.

5. A method of manufacturing a semiconductor structure as claimed in claim 3, wherein the second width of the opening decreases in a stepped manner from the top surface to the bottom surface of the mask feature.

6. A method of manufacturing a semiconductor structure as claimed in claim 1, wherein the second width is the same as the spacing between adjacent bit line structures.

7. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the step of forming the layer stack comprises: forming a first layer containing oxygen on the dielectric layer; forming a second layer containing oxygen on the first layer; forming a third layer containing carbon on the second layer; forming an oxygen-rich antireflective layer on the third layer; performing a plasma treatment on the oxygen-rich antireflective layer; and forming the silicon-rich antireflective layer on the plasma-treated oxygen-rich antireflective layer.

8. A method for manufacturing a semiconductor structure as claimed in claim 7, wherein the plasma process includes using He and N2O as reaction gases.

9. A method for manufacturing a semiconductor structure as described in claim 7, wherein the power of the plasma treatment is between 800W and 1000W.

10. A method of manufacturing a semiconductor structure as claimed in claim 7, wherein the step of forming the layer stack comprises: forming an underlayer including photoresist on the silicon-rich antireflective layer, wherein the patterned mask layer is formed on the underlayer.

11. A method for manufacturing a semiconductor structure as claimed in claim 7, wherein the oxygen-rich antireflective layer is formed in a first deposition chamber and the silicon-rich antireflective layer is formed in a second deposition chamber.

12. A method for manufacturing a semiconductor structure as claimed in claim 11, wherein the plasma treatment is performed in the first deposition chamber.

13. A method for manufacturing a semiconductor structure as claimed in claim 7, wherein the oxygen-rich antireflective layer and the silicon-rich antireflective layer are formed in the same plasma-enhanced chemical vapor deposition chamber.

14. A method for manufacturing a semiconductor structure as claimed in claim 13, wherein the plasma treatment is performed in the same plasma-enhanced chemical vapor deposition chamber.

15. The method of manufacturing a semiconductor structure as described in claim 1 further includes forming a capacitive contact in the contact hole.

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