Memory device and manufacturing method thereof

Abstract

A method for manufacturing a memory device includes the following steps: forming a bit line structure above a substrate; conformally forming a first spacer layer above the bit line structure; performing a surface treatment on the upper portion of the first spacer layer, wherein after the surface treatment, the oxygen concentration in the upper portion of the first spacer layer is higher than the oxygen concentration in the lower portion of the first spacer layer; removing the upper portion of the first spacer layer; forming a contact structure adjacent to the bit line structure; and forming a landing pad above the contact structure and the bit line structure.

Description

[Technical Field]

[0001] This disclosure relates to a memory device and a method for manufacturing the same. [Previous Technology]

[0002] A typical dynamic random access memory (DRAM) cell combines a capacitor and a transistor, where the capacitor temporarily stores data based on its charging state. Bit lines are electrically connected to either the source or drain region of the transistor, and word lines are electrically connected to the gate region of the transistor. As semiconductor dimensions shrink and density increases, the aspect ratio of the semiconductor structure increases, which makes it difficult to achieve satisfactory interstitial filling performance. [Summary of the Invention]

[0003] Some embodiments of this disclosure provide a method for manufacturing a memory device, including the following steps: forming a bit line structure above a substrate; conformally forming a first spacer layer above the bit line structure; performing a surface treatment on the upper part of the first spacer layer, wherein after the surface treatment, the oxygen concentration in the upper part of the first spacer layer is higher than the oxygen concentration in the lower part of the first spacer layer; removing the upper part of the first spacer layer; forming a contact structure adjacent to the bit line structure; and forming a landing pad above the contact structure and the bit line structure.

[0004] In some embodiments, the surface treatment step includes the following steps: performing oxygen-containing plasma treatment or hydrogen-containing plasma treatment on the upper part of the first spacer layer.

[0005] In some embodiments, after surface treatment, the silicon concentration at the upper part of the first spacer layer is lower than the silicon concentration at the lower part of the first spacer layer.

[0006] In some embodiments, the surface treatment is performed at an angle.

[0007] In some embodiments, the manufacturing method further includes the following steps: after surface treatment, conformally forming a second spacer layer over a first spacer layer; forming a photoresist layer covering the lower part of the second spacer layer, wherein the upper part of the second spacer layer is exposed by the photoresist layer; and removing the upper part of the second spacer layer.

[0008] In some embodiments, the upper portion of the second spacer layer and the upper portion of the first spacer layer are removed simultaneously.

[0009] In some embodiments, the manufacturing method further includes the following steps: after removing the upper portion of the first spacer layer and the upper portion of the second spacer layer, a third spacer layer is conformally formed above the bit line structure and the second spacer layer, wherein the upper portion of the third spacer layer is in contact with the bit line structure.

[0010] In some embodiments, the second spacer layer is sandwiched between the lower part of the third spacer layer and the first spacer layer.

[0011] In some embodiments, the landing pad is separated from the first spacer layer.

[0012] In some embodiments, the bottom of the landing pad is higher than the top of the first spacer layer.

[0013] Some embodiments disclosed herein provide a memory device including a bitline structure, bitline spacers, and a landing pad. The bitline spacers are disposed along the sidewall of the bitline structure and include a first spacer layer, a second spacer layer, and a third spacer layer. The first spacer layer contacts the lower portion of the sidewall of the bitline structure, the second spacer layer is disposed along the sidewall of the first spacer layer, and the third spacer layer is disposed along the sidewall of the second spacer layer, wherein the third spacer layer extends to the upper portion of the sidewall of the bitline structure. The landing pad is located above the bitline structure.

[0014] In some embodiments, the third spacer layer is in contact with the top of the first spacer layer.

[0015] In some embodiments, the interface between the first spacer layer and the bit line structure is aligned with the interface between the third spacer layer and the bit line structure.

[0016] In some embodiments, the top of the first spacer layer is substantially flush with the top of the second spacer layer.

[0017] In some embodiments, the landing pad is separated from the first spacer layer.

[0018] In some embodiments, the bottom surface of the landing pad is higher than the top of the first spacer layer.

[0019] In some embodiments, the top of the first spacer layer is below the top surface of the bit line structure.

[0020] In some embodiments, the third spacer layer overlaps perpendicularly with the first spacer layer.

[0021] In some embodiments, the third spacer layer has a portion that is vertically located between the landing pad and the first spacer layer.

[0022] In some embodiments, the first spacer layer and the third spacer layer are made of different materials.

[0023] It should be understood that the foregoing general description and the following detailed description are described by example and are intended to provide further explanation of the content disclosed in the claim.

Implementation Method

[0025] Figure 1 illustrates a circuit diagram of a memory device. Referring to Figure 1, a memory device (e.g., dynamic random access memory (DRAM)) may include a plurality of memory cells MC. A typical DRAM memory cell combines a capacitor CA and a transistor TR, wherein the capacitor CA temporarily stores data based on the charging state of the capacitor CA. The capacitor CA is electrically connected to the source / drain region of the transistor TR, the bit line BL is electrically connected to another source / drain region of the transistor TR, and the word line WL is electrically connected to the gate region of the transistor TR. In this disclosure, we focus on the manufacturing process of the bit lines and capacitors. The manufacturing process of the word lines and transistors will not be mentioned in this disclosure.

[0026] Figure 2 is a top view illustrating a method of manufacturing a memory device according to some embodiments of this disclosure. The memory device includes an active region AA, a word line WL, and a bit line structure 110. The word line WL is located above the active region AA, and the bit line structure 110 is located above the word line WL. The word line WL and the bit line structure 110 are along different directions. For example, the longitudinal direction of the word line WL is perpendicular to the longitudinal direction of the bit line structure 110. The word line WL divides each active region AA into three regions. The regions at both ends of the active region AA are connected to capacitors, and the middle region is connected to the bit line structure 110.

[0027] Figures 3 to 11 illustrate cross-sectional views taken along line A-A' of the memory device in Figure 2. Note that character lines WL are not shown in Figures 3 to 11. Referring to Figure 3, a substrate 100 is provided. An isolation structure 102 is formed in the substrate 100 and defines the active region AA in Figure 2 of the substrate 100. A dielectric layer 106 is formed over the substrate 100 and the isolation structure 102. A recess R1 may be formed in the substrate 100 and the isolation structure 102 not covered by the dielectric layer 106. The substrate 100 may be made of a semiconductor, such as silicon. The isolation structure 102 may be made of silicon oxide, silicon nitride, etc. The dielectric layer 106 may be made of silicon oxide, silicon nitride, etc.

[0028] Subsequently, bit line contacts 108 and bit line structures 110 are formed over the substrate 100 and the dielectric layer 106. The bit line structures 110 are located over the bit line contacts 108, and each bit line structure 110 includes a conductive layer 112, a conductive layer 114 above the conductive layer 112, and a capping layer 116 above the conductive layer 114. The bit line contacts 108 and bit line structures 110 can be formed, for example, by sequentially forming a conductive material layer and a capping material layer over the substrate 100. Subsequently, the conductive material layer and the capping material layer are patterned into the bit line contacts 108 and the bit line structures 110 including the conductive layer 112, the conductive layer 114, and the capping layer 116. Adjacent bit line structures 110 define trenches T1. In some embodiments, the width of the trenches T1 is between 30 nanometers and 50 nanometers. In some embodiments, the width of the bit line structures 110 is between 8 nanometers and 12 nanometers. In some embodiments, the bitline contact 108 may be made of polysilicon. The conductive layer 112 may be made of a metal nitride, such as titanium nitride. The conductive layer 114 may be made of a metal, such as tungsten. The capping layer 116 may be made of a dielectric material, such as silicon nitride. In some embodiments, a portion of the bitline structure 110 may be formed in a recess R1.

[0029] Referring to Figure 4, a spacer layer 122, an etch stop layer 124, and a fill layer 126 are sequentially formed over a substrate 100, an isolation structure 102, a dielectric layer 106, and a bit line structure 110. Specifically, the spacer layer 122 is conformally formed over the bit line structure 110 and is lined within a groove R1. Subsequently, the spacer layer 122 is surface-treated so that the exterior of the spacer layer 122 is transformed into an etch stop layer 124. Subsequently, a fill layer 126 is conformally formed over the etch stop layer 124. The fill layer 126 is thicker than the spacer layer 122 and the etch stop layer 124, and the fill layer 126 fills the groove R1. The spacer layer 122, the etch stop layer 124, and the fill layer 126 are all made of a dielectric material. In some embodiments, the spacer layer 122 and the fill layer 126 are made of silicon nitride, and the etch stop layer 124 is made of silicon oxide. In some other embodiments, the spacer layer 122 is made of a low-k material, such as SiC, SiCO, or SiCN, and the etch stop layer 124 may be omitted. In some embodiments, the thickness of the spacer layer 122 is between 4 nanometers and 6 nanometers.

[0030] Referring to Figure 5, an etching process is performed to remove a portion of the etch stop layer 124 and fill layer 126 above the dielectric layer 106. After the etching process is completed, a portion of the etch stop layer 124 and fill layer 126 remains in the groove R1. The etch stop layer 124 protects the spacer layer 122 from being etched by the etching process; therefore, the spacer layer 122 remains after the etching process is completed. In some embodiments, the etching process may be a wet etching process using hot phosphoric acid as the etchant.

[0031] Referring to Figures 6 and 7, the upper portion of the spacer layer 122 undergoes surface treatment to alter its properties. Specifically, the surface treatment may be oxygen-containing plasma treatment, hydrogen-containing plasma treatment, oxygen-containing implantation process, or hydrogen-containing implantation process, and the surface treatment is performed at an inclined angle. That is, the incident direction of the implantation material or plasma may be inclined to the normal of the substrate 100. In some embodiments, the inclination angle may be approximately 25° to 45°. In some embodiments, surface treatment may be performed first in the first direction D1 of Figure 6, and then in the second direction D2 of Figure 7. Since the depth-to-width ratio of the trenches T1 between the bit line structures 110 is large, the surface treatment has little effect on the properties of the lower portion of the spacer layer 122. After the surface treatment is completed, the oxygen concentration in the upper portion of the spacer layer 122 is higher than that in the lower portion of the spacer layer 122, and the silicon concentration in the upper portion of the spacer layer 122 is lower than that in the lower portion of the spacer layer 122. In some other embodiments, when the spacer layer 122 is a carbon-containing layer, after the surface treatment is completed, the carbon concentration in the upper part of the spacer layer 122 is lower than the carbon concentration in the lower part of the spacer layer 122. Therefore, after the surface treatment is completed, the properties of the upper part and the lower part of the spacer layer 122 are different.

[0032] Referring to Figure 8, after surface treatment, a spacer layer 128 is conformally formed over the spacer layer 122. The spacer layer 128 is made of a dielectric material that is different from the material of the spacer layer 122. In some embodiments, the spacer layer 128 is made of silicon oxide. In some embodiments, the thickness of the spacer layer 128 is between 4 nanometers and 6 nanometers.

[0033] Referring to Figure 9, the photoresist layer PR is formed above the spacer layer 128 and overfills the trench T1 between the bit line structures 110. Then, the photoresist layer PR is etched back so that the photoresist layer PR covers the lower part of the spacer layer 128. The upper part of the spacer layer 128 is exposed by the photoresist layer PR.

[0034] Referring to Figure 10, an etching process is performed to remove the upper portion of spacer layer 128 and the upper portion of spacer layer 122. The photoresist layer PR does not cover the upper portion of spacer layer 128 and the upper portion of spacer layer 122, therefore it can be etched using a suitable etching process. The etching process exhibits etching selectivity between oxide-based materials and other materials. In some embodiments, the etching process in Figure 10 etches silicon oxide faster than it etches other materials (such as silicon nitride). In some embodiments, the higher the oxygen concentration of spacer layer 122, the faster the etching process removes spacer layer 122; the lower the silicon concentration of spacer layer 122, the faster the etching process removes spacer layer 122; and the lower the carbon concentration of spacer layer 122, the faster the etching process removes spacer layer 122. Because the upper portion of spacer layer 122 is treated to have a higher oxygen concentration, the properties of the upper portion of spacer layer 122 are similar to those of silicon oxide. Therefore, when removing the upper part of spacer layer 128, the upper part of spacer layer 122 is also easily removed. Because the upper part of spacer layer 122 is removed, the opening of trench T1 widens, thus reducing the aspect ratio of trench T1. After the etching process is complete, the top of spacer layer 122 is lower than the top surface of bitline structure 110. After the etching process is complete, the top of spacer layer 122 is substantially flush with the top of spacer layer 128. After removing the upper parts of spacer layer 122 and spacer layer 128, the photoresist layer PR is stripped.

[0035] Referring to Figure 11, after removing the upper portion of spacer layer 122 and the upper portion of spacer layer 128, spacer layer 129 is conformally formed above bit line structure 110 and spacer layer 128. The upper portion of spacer layer 129 contacts the capping layer 116 of bit line structure 110. Spacer layer 128 is sandwiched between the lower portion of spacer layer 129 and spacer layer 122. The interface between spacer layer 122 and bit line structure 110 is aligned with the interface between spacer layer 129 and bit line structure 110. Spacer layer 129 is made of a dielectric material, such as silicon nitride. In some embodiments, spacer layer 122 and spacer layer 129 are made of the same material; for example, both spacer layer 122 and spacer layer 129 are made of silicon nitride. In some other embodiments, spacer layers 122 and 129 are made of different materials; for example, spacer layer 122 is made of a high-k dielectric material, and spacer layer 129 is made of silicon nitride. Spacer layer 122 is completely covered and protected by spacer layer 129. In embodiments where spacer layer 122 is made of a low-k material, spacer layer 122 is prone to oxidation and easily removed in subsequent processes, which would result in connections between conductive layer 114 and components formed in subsequent processes. Therefore, in this disclosure, spacer layer 122, covered by spacer layer 129, is not removed in subsequent processes. In some embodiments, the thickness of spacer layer 122 is between 4 nanometers and 6 nanometers. In some embodiments, spacer layers 122, 128, and 129 may be collectively referred to as bit line spacers.

[0036] Figure 12 illustrates a top view of a memory device in some embodiments of this disclosure. Figures 13 and 14 illustrate cross-sectional views taken along lines A-A' and B-B' of the memory device in Figure 12, respectively. Note that only the bit line structure 110 and the sacrificial layer 130 are shown in Figure 12, and other components are omitted. Referring to Figures 12, 13, and 14, the sacrificial layer 130 is formed over the substrate 100, the bit line structure 110, and overfills the trench T1. In some embodiments, the sacrificial layer 130 may be formed by spin-coating dielectric coating. Due to the removal of the upper portion of the spacer layer 122, the opening of the trench T1 is widened, resulting in better gap-filling performance of the sacrificial layer 130.

[0037] Subsequently, a planarization process is performed to remove excess portions of the sacrificial layer 130 until the top of the bitline structure 110 is exposed. Then, the sacrificial layer 130 is patterned such that it covers a portion of the substrate 100 (as shown in Figure 13), while not covering another portion (as shown in Figure 14). The spacer layer 129 completely covers the spacer layer 122. Therefore, even if the spacer layer 122 is oxidized in the previous stage, the spacer layer 129 prevents the patterning process of the sacrificial layer 130 from removing the spacer layer 122. Material formed in subsequent processes will not contact the bitline structure 110. After patterning the sacrificial layer 130, the top of the bitline structure 110 is partially etched, and the tops of the bitline structures 110 not adjacent to the sacrificial layer 130 become curved. The tops of the bitline structures 110 not adjacent to the sacrificial layer 130 are lower than the tops of the bitline structures 110 adjacent to the sacrificial layer 130. Partially removing the bit line structure 110 can reduce the aspect ratio of the trench T1 between the bit line structures 110, thereby reducing the difficulty of filling material in subsequent processes. The sacrificial layer 130 is made of a dielectric material that is different from the material of the spacer layer 129. In some embodiments, the sacrificial layer 130 may be made of silicon oxide.

[0038] Figure 15 illustrates a top view of a memory device in some embodiments of this disclosure. Figures 16 and 17 illustrate cross-sectional views taken along lines A-A' and B-B' of the memory device in Figure 15, respectively. Note that only the bit line structure 110, the sacrificial layer 130, and the isolation layer 140 are shown in Figure 15, and other elements are omitted. Referring to Figures 15, 16, and 17, the isolation layer 140 overfills the trench T1 and is formed above the bit line structure 110. In some embodiments, the isolation layer 140 may be formed by low-pressure chemical vapor deposition (LPCVD). Due to the removal of the upper portion of the spacer layer 122, the opening of the trench T1 is widened, resulting in better gap-filling performance of the isolation layer 140.

[0039] Subsequently, a planarization process is performed to remove excess portions of the isolation layer 140 until the top of the bit line structure 110 is exposed. Since the top of the bit line structure 110 not adjacent to the sacrificial layer 130 is lower than the top of the bit line structure 110 adjacent to the sacrificial layer 130, the top of the bit line structure 110 not adjacent to the sacrificial layer 130 is still covered by the isolation layer 140. The isolation layer 140 is made of a dielectric material different from the material of the sacrificial layer 130. In some embodiments, the isolation layer 140 may be made of silicon nitride.

[0040] Figure 18 illustrates a top view of a memory device in some embodiments of this disclosure. Figures 19 and 21 illustrate cross-sectional views taken along line A-A' of the memory device in Figure 18, and Figure 20 illustrates a cross-sectional view taken along line B-B' of the memory device in Figure 18. Note that only the bit line structure 110 and the isolation layer 140 are shown in Figure 18, and other components are omitted. Referring to Figures 18, 19, and 20, an etching process can be performed to remove the sacrificial layer 130. Since the material of the sacrificial layer 130 is different from the materials of the spacer layer 129 and the isolation layer 140, a suitable etching process can be selected to remove the sacrificial layer 130 without substantially removing the spacer layer 129 and the isolation layer 140. Adjacent isolation layers 140 define trenches T2.

[0041] Referring to Figure 21, an etching process is performed to etch away a portion of the spacer layers 128 and 129 in trench T2, forming a groove R2 exposing the substrate 100. The spacer layer 122, the etch stop layer 124, and the fill layer 126 in groove R1 (see Figure 3) are also partially etched. The remaining portions of the spacer layers 128 and 129 covered by the isolation layer 140 are not etched.

[0042] Figure 22 illustrates a top view of a memory device in some embodiments of this disclosure. Figure 23 illustrates a cross-sectional view taken along line A-A' of the memory device in Figure 22. Note that only the bit line structure 110, the isolation layer 140, and the contact structure 150 are shown in Figure 22, and other elements are omitted. Referring to Figures 22 and 23, the contact structure 150 is formed near the bit line structure 110 and in a trench T2. Specifically, the contact structure 150 is formed by sequentially forming a conductive layer 152, a conductive layer 154, and a conductive layer 156 in the trench T2. In some embodiments, the conductive layer 152 may be made of doped polysilicon, the conductive layer 154 may be made of a metal silicide (such as CoSi), and the conductive layer 156 may be made of a metal (such as tungsten). Subsequently, a landing pad 160 is formed above and in contact with the bit line structure 110 and the contact structure 150, and is spaced apart from the spacer layers 122 and 128. The bottom surface of the landing pad 160 is higher than the top surface of the spacer layer 122. In some embodiments, the landing pad 160 may be made of a metal (such as tungsten). The conductive layer 152 of the contact structure 150 contacts the substrate 100, and the contact structure 150 and the landing pad 160 provide a connection between the substrate 100 and a subsequently formed capacitor.

[0043] Subsequently, a groove is formed through the landing pad 160, and an isolation structure 170 is formed in the groove. The bottom of the isolation structure 170 contacts the cover layer 116, spacer layers 122, 128, 129, and contact structure 150 of the bit line structure 110. The isolation structure 170 is used to isolate adjacent landing pads 160. After the isolation structure 170 is formed, a capacitor (not shown) is formed above the landing pad 160.

[0044] The resulting memory device is illustrated in Figure 23. The memory device includes a bitline structure 110, bitline spacers, and a landing pad 160. The bitline spacers are disposed along the sidewall of the bitline structure 110 and include spacer layers 122, 128, and 129. Spacer layer 122 contacts the lower portion of the sidewall of the bitline structure 110. Spacer layer 128 is disposed along the sidewall of spacer layer 122. Spacer layer 129 is disposed along the sidewall of spacer layer 128 and extends to the upper portion of the sidewall of the bitline structure 110. Spacer layer 129 contacts the top end of spacer layer 122. The landing pad 160 is located above the bitline structure 110. Spacer layer 129 overlaps spacer layer 122 perpendicularly, and spacer layer 129 has a portion perpendicularly located between the landing pad 160 and spacer layer 122.

[0045] As described above, this disclosure is used to reduce the aspect ratio of the trenches between the bit line structures 110. Therefore, it is easier to fill the trenches between the bit line structures 110 with material. Specifically, the aspect ratio of the trenches between the bit line structures 110 can be reduced by surface treating the spacer layer 122, which is made of silicon nitride or a low-k material, along the sidewalls of the bit line structures 110. Therefore, the upper portion of the spacer layer 122 has a higher oxygen concentration. The upper portion of the spacer layer 122 can be removed by an etching process for removing the spacer layer 128 made of silicon oxide, and the width of the trenches between the bit line structures 110 can be widened to reduce the aspect ratio.

[0046] Although this disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the description of the embodiments contained herein.

[0047] Those skilled in the art will understand that various modifications and changes can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In summary, this disclosure is intended to cover modifications and changes to this disclosure, provided that such modifications and changes fall within the scope of the invention application. [Simplified Explanation of the Diagram]

[0024] This disclosure can be more fully understood by reading the following detailed description of embodiments in conjunction with the accompanying drawings: Figure 1 illustrates a circuit diagram of a memory device. Figure 2 illustrates a top view of a method of manufacturing a memory device according to some embodiments of this disclosure. Figures 3 to 11 illustrate cross-sectional views taken along line A-A' of the memory device in Figure 2. Figure 12 illustrates a top view of a memory device according to some embodiments of this disclosure. Figures 13 and 14 illustrate cross-sectional views taken along lines A-A' and B-B' of the memory device in Figure 12, respectively. Figure 15 illustrates a top view of a memory device according to some embodiments of this disclosure. Figures 16 and 17 illustrate cross-sectional views taken along lines A-A' and B-B' of the memory device in Figure 15, respectively. Figure 18 illustrates a top view of a memory device according to some embodiments of this disclosure. Figure 19 illustrates a cross-sectional view taken along line A-A' of the memory device in Figure 18. Figure 20 illustrates a cross-sectional view taken along line B-B' of the memory device in Figure 18. Figure 21 illustrates a cross-sectional view taken along line A-A' of the memory device in Figure 18. Figure 22 illustrates a top view of the memory device in some embodiments of this disclosure. Figure 23 illustrates a cross-sectional view taken along line A-A' of the memory device in Figure 22. [Biomaterial Storage]

[0049] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a memory device, comprising the following steps: forming a bit line structure above a substrate; conformally forming a first spacer layer above the bit line structure; performing a surface treatment on an upper portion of the first spacer layer, wherein after the surface treatment, the oxygen concentration at the upper portion of the first spacer layer is higher than the oxygen concentration at the lower portion of the first spacer layer; removing the upper portion of the first spacer layer; forming a contact structure adjacent to the bit line structure; and forming a landing pad above the contact structure and the bit line structure.

2. The manufacturing method as claimed in claim 1, wherein the step of performing the surface treatment comprises the following steps: performing an oxygen-containing plasma treatment or a hydrogen-containing plasma treatment on the upper portion of the first spacer layer.

3. The manufacturing method as claimed in claim 1, wherein after the surface treatment, the silicon concentration of the upper portion of the first spacer layer is lower than the silicon concentration of the lower portion of the first spacer layer.

4. The manufacturing method as claimed in claim 1, wherein the surface treatment is performed at an inclined angle.

5. The manufacturing method as claimed in claim 1 further comprises the following steps: after performing the surface treatment, conformally forming a second spacer layer over the first spacer layer; forming a photoresist layer covering a lower portion of the second spacer layer, wherein the upper portion of the second spacer layer is exposed by the photoresist layer; and removing the upper portion of the second spacer layer.

6. The manufacturing method as claimed in claim 5, wherein the upper portion of the second spacer layer and the upper portion of the first spacer layer are removed simultaneously.

7. The manufacturing method as claimed in claim 5 further comprises the following steps: after removing the upper portion of the first spacer layer and the upper portion of the second spacer layer, a third spacer layer is conformally formed above the bit line structure and the second spacer layer, wherein an upper portion of the third spacer layer is in contact with the bit line structure.

8. The manufacturing method as claimed in claim 7, wherein the second spacer layer is sandwiched between a lower portion of the third spacer layer and the first spacer layer.

9. The manufacturing method as claimed in claim 1, wherein the landing pad is separated from the first spacer layer.

10. The manufacturing method as claimed in claim 1, wherein a bottom of the landing pad is higher than a top of the first spacer layer.

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