Memory system, storage apparatus, and control method

Abstract

A memory system and control method are provided that can suppress temperature rise and performance degradation. The memory system comprises: non-volatile memory, which has a non-volatile memory area and is capable of reading and writing data to the memory area; and a controller, which includes: a host interface circuit, which receives external command information from a host device, containing commands to read and write data to the non-volatile memory; a memory interface circuit, which communicates with the non-volatile memory; a command information processing unit, which generates internal command information to execute commands to the non-volatile memory based on the external command information, and sends the internal command information to the non-volatile memory through the memory interface circuit; and a delay circuit control unit, which controls a delay circuit that delays the execution of commands based on the relationship between the amount of data read and written from the non-volatile memory and a first threshold value within a unit of time.

Description

[Technical Field]

[0001] This embodiment relates to a memory system, a memory device, and a control method. [Previous Technology]

[0002] Memory devices with non-volatile memory, such as Universal Flash Memory (UFS), eMMC, and solid-state drives (SSD), are well known.

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2017 / 0300263 [Patent Document 2] U.S. Patent Application Publication No. 2023 / 0367378 [Patent Document 3] U.S. Patent Application Publication No. 2023 / 0035828 [Summary of the Invention]

[0004] According to this embodiment, a memory system and control method capable of suppressing temperature rise and performance degradation are provided.

[0005] The memory system disclosed herein includes: a non-volatile memory having a non-volatile memory region and capable of reading and writing data in the aforementioned memory region; and a controller comprising: a host interface circuit that receives external command information from a host device, including an instruction to cause the aforementioned non-volatile memory to read and write the aforementioned data; a memory interface circuit that communicates with the aforementioned non-volatile memory; an instruction information processing unit that generates internal instruction information based on the external instruction information to cause the aforementioned non-volatile memory to execute the aforementioned instruction, and sends the aforementioned internal instruction information to the aforementioned non-volatile memory through the aforementioned memory interface circuit; and a delay circuit control unit that controls a delay circuit that delays the execution of the aforementioned instruction based on the relationship between the amount of data read and written by the aforementioned non-volatile memory and a first threshold value within a unit of time.

Implementation Method

[0007] Hereinafter, the present embodiment will be described with reference to the attached drawings. In order to facilitate the understanding of the explanation, the same component symbols will be added to the same components as much as possible in each drawing, and repeated explanations will be omitted.

[0008] Figure 1 is a functional block diagram of the memory system 101 of this embodiment. The memory system 101 (one example of a "memory device") includes non-volatile memory 10 (one example of "memory") and a controller 20.

[0009] The controller 20 includes an internal logic unit 21 (an example of a "control unit"), a bus 22, volatile memory 23, a host interface (I / F) circuit 24, a memory interface (I / F) circuit 25, a timer 26, and a delay circuit 27. Specifically, the controller 20 is a controller chip.

[0010] The memory system 101 may also be a UFS device based on the UFS (Universal Flash Storage) specification (e.g., JESD220F). The UFS specification is a specification for NAND flash memory suitable for digital cameras, smartphones and home appliances, and is developed by JEDEC (Joint Electron Device Engineering Councils).

[0011] The non-volatile memory 10 includes a non-volatile memory region 11 and a temperature sensor 12. Specifically, the non-volatile memory 10 is a memory chip. The memory region 11 in the non-volatile memory 10 is, for example, a memory cell array. The data stored in the memory region 11 is retained even when no power is supplied.

[0012] In this embodiment, the non-volatile memory 10 is a semiconductor memory. Specifically, the non-volatile memory 10 is a NAND flash memory.

[0013] In addition, the non-volatile memory 10 may also be MRAM (Magnetoresistive Random Access Memory), PRAM (Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory) or FeRAM (Ferroelectric Random Access Memory).

[0014] The non-volatile memory 10 is capable of reading and writing data to the memory area 11. Specifically, the non-volatile memory 10 may include, for example, a controller (an example of a "memory control unit").

[0015] The non-volatile memory 10 is configured to perform data writing and data reading operations in specific write units in accordance with internal command information received from the controller 20.

[0016] Furthermore, the non-volatile memory 10 is configured to delete data in deletion units comprising multiple write units. For example, when the non-volatile memory 10 is a NAND flash memory, the non-volatile memory 10 is configured to perform write and read operations in page units, and to delete data in block units composed of multiple pages.

[0017] In detail, the non-volatile memory 10, in addition to the memory area 11, also includes an interface circuit (input / output circuit) for exchanging information with the controller 20, a sensing amplifier for reading information stored in the memory cell array and sending written information to the memory cell array, a data register for storing data or other information received by the interface circuit from the controller 20 or data or other information read from the memory cell array using the sensing amplifier, a state register for storing the state of the non-volatile memory 10, and a physical address (physical address) received by the interface circuit from the controller 20. Address registers, row decoders and column decoders for accessing specific memory cells based on physical address information stored in the address registers, instruction registers for storing command information received by the interface circuit from the controller 20, and sequencers for controlling, writing, reading, and deleting operations on devices such as sense amplifiers, data registers, status registers, row decoders, and column decoders based on various command information stored in the instruction registers.

[0018] Temperature sensor 12 acquires temperature information representing the temperature of memory system 101. In this embodiment, temperature sensor 12 is a sensor circuit formed at the non-volatile memory 10. The sensor circuit is formed near the circuitry of memory region 11. Temperature sensor 12 acquires temperature information representing the temperature of non-volatile memory 10.

[0019] Furthermore, the temperature sensor 12 is not limited to being formed at the non-volatile memory 10. For example, it may also be formed at the controller 20, or disposed near the non-volatile memory 10 or the controller 20. Also, the temperature sensor 12 may be disposed at other locations besides those described above, and obtain temperature information representing the temperature of the memory system 101 or the non-volatile memory 10 by correction based on a specific correction coefficient. The temperature sensor 12 may, for example, be a thermocouple, or a semiconductor temperature sensor that uses the electrical characteristics of a semiconductor whose band gap changes in response to temperature variations to measure temperature.

[0020] The host device 111 sends external command information containing commands that cause the non-volatile memory 10 to read or write data to the memory system 101. Specifically, the commands that cause the non-volatile memory 10 to read or write data are external read commands or external write commands.

[0021] External read command is a command used to read out the read object data from the data stored in the non-volatile memory 10.

[0022] In detail, the external read command includes the logical address of the object data to be read and the capacity of the object data to be read.

[0023] If the memory system 101 receives an external read command, it retrieves the read target data from the non-volatile memory 10 according to the external read command. Then, the memory system 101 sends the retrieved read target data and the response information representing the completion of the external read command to the host device 111.

[0024] External write command is a command used to write data (hereinafter referred to as write target data) to non-volatile memory 10.

[0025] In detail, an external write command includes the logical address of the object to be written and the capacity of the object to be written. The external write command may also include the object to be written, or may be accompanied by the object to be written.

[0026] If the memory system 101 receives an external write command, it follows the external write command to make the non-volatile memory 10 remember the write target data. Then, the memory system 101 sends a response message representing the completion of the external write command to the host device 111.

[0027] Host device 111, for example, is a UFS host based on the UFS specification (e.g., JESD220F). Specifically, host device 111 is a personal computer and a portable information terminal, etc.

[0028] The controller 20 at the memory system 101 controls the operation of the non-volatile memory 10, which includes data writing and data reading operations.

[0029] At the controller 20, the internal logic unit 21, the volatile memory 23, the host interface circuit 24, the memory interface circuit 25, and the timer 26 are interconnected via the bus 22.

[0030] The host interface circuit 24 is the front end of the controller 20 and connects the host device 111 and the controller 20 communicatively.

[0031] The host interface circuit 24 receives external read commands and external write commands and write object data from the host device 111.

[0032] The host interface circuit 24, for example, performs sequential communication with the host device 111. The host interface circuit 24 converts the sequential data received from the host device into parallel data and outputs it to the bus 22.

[0033] Furthermore, the host interface circuit 24, for example, converts the parallel data received from the bus 22 into sequential data and sends it to the host device 111.

[0034] For example, when the memory system 101 is a UFS device, the host interface circuit 24 has a transport layer using the MIPI UniPro (Mobile Industry Processor Interface Unified Protocol) based on the MIPI UniPro™ specification and a MIPI M-PHY physical layer based on the MIPI M-PHY™ specification. The host interface circuit 24 has a physical configuration for transmitting and receiving signals with reference to clock signals, power supply voltage, etc., "DIN, DIN_c, which are differential signal pairs and are information (data) received from the host device 111" and "DOUT, DOUT_c, which are information (data) sent to the host device 111".

[0035] The memory interface circuit 25 is located at the rear end of the controller 20 and communicatively connects the non-volatile memory 10 to the controller 20. The memory interface circuit 25, for example, is configured according to the ONFI standard or the Toggle standard.

[0036] Volatile memory 23 is a volatile memory device. Specifically, volatile memory 23 is SRAM (Static Random Access Memory). Alternatively, volatile memory 23 can also be DRAM (Dynamic Random Access Memory) located outside the controller 20. Volatile memory 23 serves as a buffer for temporarily storing various commands and data.

[0037] The internal logic unit 21 is, for example, a CPU (Central Processing Unit). The internal logic unit 21 operates as a processing unit that processes commands from the host device 111 by running firmware (an example of a computer program).

[0038] The firmware, for example, is stored in non-volatile memory 10. The firmware is transferred from non-volatile memory 10 to volatile memory 23. The internal logic unit 21 implements the firmware stored in volatile memory 23.

[0039] During firmware execution, the internal logic unit 21 stores the necessary data for firmware execution in the volatile memory 23. The internal logic unit 21 reads the necessary commands and data for firmware execution from the volatile memory 23 and performs calculations according to the content of the processing commands. At this time, the internal logic unit 21 may generate new data necessary for firmware execution and store it in the volatile memory 23.

[0040] The internal logic unit 21 is a functional block and includes an operation mode selection unit 28, a data acquisition unit 29, a temperature information acquisition unit 30, a transmission and reception information processing unit 31 (an example of a "command information processing unit"), and a delay circuit control unit 32.

[0041] The transmission and reception information processing unit 31 at the internal logic unit 21 generates internal command information corresponding to external command information. Specifically, the internal command information includes internal read commands and internal write commands corresponding to external read commands and external write commands, respectively. The internal read commands and internal write commands are internal instructions that can be executed by the non-volatile memory 10.

[0042] The receiving information processing unit 31, for example, temporarily stores the external read command, external write command and write object data output by the host interface circuit 24 to the bus 22 in the volatile memory 23.

[0043] The transmission and reception information processing unit 31 manages the logical addresses and physical addresses of the non-volatile memory 10. Specifically, the transmission and reception information processing unit 31 manages the logical-physical translation table that represents the correspondence between the logical addresses and physical addresses of the memory regions 11 in the non-volatile memory 10.

[0044] The logic-physical conversion table, for example, is stored in memory region 11 and transferred to volatile memory 23 when the firmware is executed.

[0045] If the external read command output to the bus 22 by the host interface circuit 24 is stored in the volatile memory 23, the internal read command is generated based on the external read command and the logic-physical translation table.

[0046] In detail, the transmitting and receiving information processing unit 31, for example, converts the logical address contained in the external read command into a physical address based on a logical-physical translation table. The transmitting and receiving information processing unit 31 generates an internal read command containing the physical address and the capacity of the read object data, and stores the internal read command as data to be sent to the non-volatile memory 10 (hereinafter, there will be a case called waiting data) in the volatile memory 23.

[0047] Furthermore, if the receiving information processing unit 31 stores the external write command and write object data output to the bus 22 by the host interface circuit 24 in the volatile memory 23, it performs the following processing.

[0048] That is, the receiving information processing unit 31 generates internal write commands based on external write commands and logical-physical translation tables.

[0049] In detail, the transmitting and receiving information processing unit 31, for example, converts the logical address contained in the external write command into a physical address based on a logical-physical translation table. The transmitting and receiving information processing unit 31 generates an internal write command containing the physical address and the capacity of the write object data.

[0050] Furthermore, the receiving information processing unit 31 converts the data to be written into a form suitable for storage in non-volatile memory 10.

[0051] The transmission and reception information processing unit 31 stores the internal write command and the write object data that becomes the object of the internal write command in the volatile memory 23 as data to be transmitted.

[0052] The memory interface circuit 25 transmits internal command information to the non-volatile memory 10. Specifically, the memory interface circuit 25 transmits internal read commands, internal write commands, and write object data to the non-volatile memory 10.

[0053] In this embodiment, the memory interface circuit 25 communicates in parallel with the non-volatile memory 10, for example. The memory interface circuit 25 receives pending data stored in the volatile memory 23 through the bus 22 and transmits the received pending data to the memory interface circuit 25.

[0054] Here, the data awaiting transmission is stored in the volatile memory 23 by means of a cue data structure. That is, the internal read commands, internal write commands, and write object data stored in the volatile memory 23 are transmitted to the non-volatile memory 10 through the memory interface circuit 25 in the order in which they are stored in the volatile memory 23.

[0055] The delay circuit 27 performs thermal thottling processing to delay the execution of internal read commands and internal write commands caused by the non-volatile memory 10 (hereinafter, this will be referred to as the execution of commands caused by the non-volatile memory 10). In this embodiment, the delay circuit 27 is provided at the memory interface circuit 25.

[0056] In this embodiment, the delay circuit 27 is configured to prevent internal command information from being sent from the memory interface circuit 25 to the non-volatile memory 10 during a specific delay period, thereby performing temperature control frequency modulation processing.

[0057] In other words, the delay circuit 27 delays the timing of "the memory interface circuit 25 sending internal read commands, internal write commands, and write object data to the non-volatile memory 10".

[0058] In detail, the delay circuit 27 includes, for example, a timer. The time measured by the timer, i.e., the delay time, is set by the internal logic unit 21. The memory interface circuit 25, when the timer of the delay circuit 27 starts operating, does not receive the pending data stored in the volatile memory 23 until the timer completes.

[0059] That is, during the period when the delay circuit 27 is operating, the pending data stored in the volatile memory 23 will not be transmitted from the memory interface circuit 25 to the non-volatile memory 10, and the pending data generated by the transmit / receive information processing unit 31 will be stacked in the transmission queue of the volatile memory 23. Furthermore, a delay time is added between the transmission intervals of two consecutively transmitted pending data.

[0060] In addition, the delay circuit 27 may be, for example, a circuit that "stores the data to be sent until a specific time (a specific number of counts) has elapsed", or it may be a configuration in which multiple flip-flop circuits with a specific delay amount are connected in series.

[0061] The timer 26 is controlled by the internal logic unit 21 and measures a unit of time. The unit of time can be of any length.

[0062] In detail, if the timer 26 is set by the internal logic unit 21, it measures the time from the set timing. If the timer 26 makes the measured time consistent with the unit time, it notifies the internal logic unit 21 of the timer's completion.

[0063] The non-volatile memory 10 performs a data read operation when it receives an internal read command from the controller 20. In detail, the non-volatile memory 10 reads the data to be read from a portion of the memory region 11 represented by the physical address contained in the internal read command, and sends the data to the memory interface circuit 25.

[0064] Furthermore, the non-volatile memory 10 performs data writing operations when receiving internal write commands and write target data. In detail, the non-volatile memory 10 writes the write target data to a portion of the memory region 11 represented by the physical address contained in the internal write command, in accordance with the internal write command.

[0065] Figure 2 is a state transition diagram showing the operating mode of the memory system 101. Referring to Figures 1 and 2, the operating mode selection unit 28 at the internal logic unit 21 sets the operating mode of the memory system 101 to one of the following: normal mode M1, high temperature mode M2, and performance suppression mode M3.

[0066] The temperature information acquisition unit 30 repeatedly acquires temperature information from the temperature sensor 12 and outputs it to the operation mode selection unit 28. In this embodiment, the temperature information acquisition unit 30 repeatedly acquires temperature information, for example, at a cycle corresponding to the operation mode set by the operation mode selection unit 28. The cycle for acquiring temperature information may be the same in each operation mode of the memory system 101, or it may be partially or completely different.

[0067] Specifically, the temperature information acquisition unit 30 monitors the operation of the operation mode selection unit 28, and when the operation mode selection unit 28 sets the mode to normal mode M1, high temperature mode M2, or performance suppression mode M3, the period is set to N milliseconds, M milliseconds, and M milliseconds, respectively. Here, N is larger than M.

[0068] The data acquisition unit 29 repeatedly performs the process of acquiring the "data that has been read and written by the non-volatile memory 10 during a unit time period (hereinafter, it will be referred to as the unit time I / O data)", and outputs the acquired unit time I / O data to the operation mode selection unit 28.

[0069] In this embodiment, the data acquisition unit 29 monitors the operation of the operation mode selection unit 28, and acquires I / O data per unit time when the operation mode selection unit 28 sets the mode to high temperature mode M2 ​​or performance suppression mode M3. The unit time can be any time. The data acquisition unit 29 can set the unit time to a static, fixed time, or it can be set to a dynamically changing time.

[0070] In detail, the data acquisition unit 29 sets a unit time for the timer 26 and performs the following summation process until a completion notification is received from the timer 26.

[0071] That is, the data acquisition unit 29, for example, acquires the capacity of the read object data contained in the external read command or the internal read command each time an internal read command is generated based on an external read command. The data acquisition unit 29 acquires "the amount of data read by the non-volatile memory 10 in a unit of time (hereinafter, it will be referred to as the amount of data read per unit time)" by summing up the acquired capacities.

[0072] Furthermore, the data acquisition unit 29, for example, acquires the capacity of the write object data contained in the external write command or the internal write command each time an internal write command is generated based on an external write command. The data acquisition unit 29 acquires "the amount of data written to the non-volatile memory 10 within a unit time period (hereinafter, there will be a case referred to as the amount of data written per unit time)" by summing up the acquired capacities.

[0073] The data acquisition unit 29 acquires the unit-time I / O data by summing the acquired unit-time read data and unit-time write data, and outputs the unit-time I / O data to the operation mode selection unit 28. The data acquisition unit 29 repeatedly performs the unit-time I / O data acquisition process when the operation mode is high temperature mode M2 ​​or performance suppression mode M3.

[0074] [Normal Mode M1] Normal mode M1 is the operating mode in which the memory system 101 operates in accordance with external read commands and external write commands from the host device 111.

[0075] The operation mode selection unit 28 is, for example, set to normal mode M1 as the initial value of the operation mode. In normal mode M1, the operation mode selection unit 28 performs a temperature comparison process by comparing the temperature Tc represented by the temperature information with the threshold value Tth (an example of the "second threshold value") each time temperature information is periodically received from the temperature information acquisition unit 30.

[0076] The operation mode selection unit 28, when the operation mode is normal mode M1, if the temperature Tc becomes higher than the threshold value Tth, changes the operation mode from normal mode M1 to high temperature mode M2. The threshold value Tth can be, for example, a specific value selected from a temperature range of 80 to 95 degrees.

[0077] On the other hand, when the operation mode is normal mode M1, the operation mode 28 maintains normal mode M1 when the temperature Tc is below the threshold value Tth.

[0078] [High Temperature Mode M2] High Temperature Mode M2 ​​is an operation mode that further monitors the amount of I / O data per unit time compared to the normal mode M1.

[0079] In the high temperature mode M2, the operation mode selection unit 28 performs the temperature comparison processing described above, and each time the unit time I / O data is repeatedly received from the data acquisition unit 29, it performs data capacity comparison processing that compares the unit time I / O data with the threshold value Dth ("the first threshold value").

[0080] The operation mode selection unit 28, when the operation mode is high temperature mode M2 ​​and the temperature Tc is above the threshold value Tth, maintains the operation mode as high temperature mode M2 ​​when the I / O data volume per unit time (i.e., Σ(Data size)) is below the threshold value Dth. The threshold value Dth can be, for example, a specific value selected from 2000 to 3500 MiB.

[0081] Furthermore, in the case where the operation mode is high temperature mode M2 ​​and the temperature Tc is above the threshold value Tth, if Σ(Data size) becomes larger than the threshold value Dth, the operation mode is changed from high temperature mode M2 ​​to performance suppression mode M3.

[0082] On the other hand, when the operation mode is high temperature mode M2, if the temperature Tc becomes lower than the threshold value Tth, the operation mode of the operation mode 28 is changed from high temperature mode M2 ​​to normal mode M1.

[0083] [Performance Suppression Mode M3] Performance Suppression Mode M3 is an operating mode that further utilizes the delay circuit 27 to perform temperature-controlled frequency modulation processing compared to High Temperature Mode M2.

[0084] The operation mode selection unit 28 performs the above-mentioned temperature comparison processing and data capacity comparison processing in performance suppression mode M3.

[0085] When the operation mode selection unit 28 is in the case that the operation mode is the performance suppression mode M3 and the temperature Tc is above the threshold value Tth, when the Σ(Data size) is above the threshold value Dth, the operation mode is maintained in the performance suppression mode M3.

[0086] On the other hand, when the operation mode is performance suppression mode M3 and the temperature Tc is above the threshold value Tth, if Σ(Data size) becomes lower than the threshold value Dth, the operation mode is changed from performance suppression mode M3 to high temperature mode M2.

[0087] Furthermore, in the case where the operation mode is performance suppression mode M3, if the temperature Tc becomes lower than the critical value Tth, the operation mode is changed from performance suppression mode M3 to normal mode M1.

[0088] The delay circuit control unit 32 controls the delay circuit 27 based on the relationship between the amount of I / O data per unit time and the threshold value Dth.

[0089] Specifically, the delay circuit control unit 32, for example, delays the execution of commands caused by the non-volatile memory 10 for the delay circuit 27 when the temperature is above the threshold value Tth and the amount of I / O data per unit time is above the threshold value Dth.

[0090] More specifically, the delay circuit control unit 32, for example, in the case where the delay circuit 27 is controlled to delay the execution of commands caused by the non-volatile memory 10, if the temperature Tc is above the threshold value Tth and the amount of I / O data per unit time becomes greater than the threshold value Dth, then the delay circuit 27 is started to undergo temperature control frequency modulation processing.

[0091] In this embodiment, the delay circuit control unit 32 monitors the operation of the operation mode selection unit 28, and when the performance suppression mode M3 is set by the operation mode selection unit 28, the delay circuit 27 is activated by setting a delay time for the timer included in the delay circuit 27.

[0092] On the other hand, when the delay circuit control unit 32 is set to normal mode M1 or high temperature mode M2 ​​by the operation mode selection unit 28, the delay circuit 27 is stopped.

[0093] In performance suppression mode M3, if the delay circuit 27 is activated, the data stored in volatile memory 23 that is waiting to be sent will not be sent to non-volatile memory 10 during the period from the start of its operation until the delay time has elapsed.

[0094] That is, the time from when the host interface circuit 24 receives external command information until the memory interface circuit 25 sends the corresponding internal command information to the non-volatile memory 10 is longer when the delay circuit control unit 32 delays the execution of the command caused by the non-volatile memory 10 through the delay circuit 27 than when the delay circuit control unit 32 does not delay the execution of the command caused by the non-volatile memory 10 through the delay circuit 27.

[0095] [Action] Figure 3 is a sequence diagram showing the internal processing actions of the memory system 101 when the memory system 101 receives an external read command from the host device 111 in normal mode M1.

[0096] Referring to Figures 1 and 3, the host device 111 sends an external read command to the memory system 101.

[0097] External read command, more specifically, is an external sequential read command or an external random read command. Internal read command, more specifically, is an internal sequential read command or an internal random read command. The internal sequential read command and the internal random read command are respectively obtained based on the external sequential read command and the external random read command.

[0098] External sequential read commands and internal sequential read commands are commands used to read data stored in each of the non-volatile memory 10 from each of the regions having a plurality of consecutive addresses in memory region 11 in address order. Here, the address refers to a logical address and a physical address, respectively, in the external sequential read command and the internal sequential read command.

[0099] External random access commands and internal random access commands are commands used to read data stored in non-volatile memory 10 from regions having multiple non-contiguous addresses within memory region 11. Here, the address refers to a logical address and a physical address, respectively, in external random access commands and internal random access commands.

[0100] Also, although not illustrated, the external write command, more specifically, is an external sequential write command or an external random write command. The internal write command, more specifically, is an internal sequential write command or an internal random write command. The internal sequential write command and the internal random write command are respectively derived from the external sequential write command and the external random write command.

[0101] External sequential write commands and internal sequential write commands are commands used to write data of each write target to the non-volatile memory 10 in address order for each region having a contiguous plurality of addresses in the memory region 11. Here, the address refers to a logical address and a physical address, respectively, in the external sequential write command and the internal sequential write command.

[0102] External random write command and internal random write command are commands used to write data to each write target in memory region 11 for each region having a plurality of non-contiguous addresses. Here, the address refers to the logical address and the physical address in the external random write command and the internal random write command, respectively.

[0103] The operating mode of the internal logic unit 21 at the controller 20 is set to normal mode M1. If the internal logic unit 21 receives an external read command through the host interface circuit 24, it generates an internal read command corresponding to the external read command.

[0104] The internal logic unit 21 sends the generated internal read command to the non-volatile memory 10 through the memory interface circuit 25.

[0105] Non-volatile memory 10, if it receives an internal read command, will obtain the read object data according to the internal read command and send the read object data to the controller 20.

[0106] The memory interface circuit 25, if receiving object data from non-volatile memory 10, outputs the read object data to the internal logic unit 21 through bus 22. In addition, the read object data can also be temporarily buffered at volatile memory 23.

[0107] The internal logic unit 21, if receiving read object data from the memory interface circuit 25, converts the data unit of the read object data into a data unit managed by the host device 111. Furthermore, the internal logic unit 21 generates response information indicating that an external read command has been completed.

[0108] The internal logic unit 21 outputs the read object data and response information to the host interface circuit 24 via the bus 22. In addition, the read object data and response information can also be temporarily buffered in the volatile memory 23.

[0109] If the host interface circuit 24 receives read object data and response information from the internal logic unit 21, it will send the read object data and response information to the host device 111.

[0110] Figure 4 is a sequence diagram showing the internal processing actions of the memory system 101 when the memory system 101 receives multiple external read commands from the host device 111 in high temperature mode M2.

[0111] Referring to Figures 1 and 4, the host device 111 repeatedly sends external read commands to the memory system 101.

[0112] The memory system 101, for example, has more than two QDs (Que Depths), so the host device 111 is able to send one or more external read commands to the memory system 101 from the time the first external read command is sent until the response information of the command is received.

[0113] Specifically, for example, when the QD of the memory system 101 is 8, the host device 111 is able to send the second to the eighth external read commands to the memory system 101 from the time the first external read command is sent until the response information is received.

[0114] The operating mode of the internal logic unit 21 at the controller 20 is set to high temperature mode M2. The internal logic unit 21 repeatedly receives external read commands through the host interface circuit 24.

[0115] The internal logic unit 21 generates an internal read command corresponding to the external read command each time an external read command is received, and sends the generated internal read command to the non-volatile memory 10 through the memory interface circuit 25.

[0116] Furthermore, the internal logic unit 21, for example, sets a unit time for the timer 26 at time t1 and measures the amount of I / O data per unit time until a completion notification is received from the timer 26.

[0117] Non-volatile memory 10, if receiving an internal read command, retrieves the read object data according to the internal read command and sends the read object data to controller 20. In the example shown in Figure 4, the capacity of the read object data is 4KB (kilobyte).

[0118] The memory interface circuit 25 outputs the read object data to the internal logic unit 21 through the bus 22 each time it receives and reads object data from the non-volatile memory 10.

[0119] The internal logic unit 21 converts the data unit of the read object data into the data unit managed by the host device 111 each time it receives read object data from the memory interface circuit 25, and generates response information.

[0120] The internal logic unit 21 reads the object data and response information and outputs it to the host interface circuit 24 through the bus 22.

[0121] Also, if the internal logic unit 21 receives a completion notification from the timer 26 at time t2, it compares the measured I / O data per unit time with the threshold value Dth.

[0122] In the example shown in Figure 4, since the amount of I / O data per unit time (e.g., 12KB) is below the threshold value Dth, the operating mode of the memory system 101 is maintained in high-temperature mode M2. Therefore, since the memory system 101 keeps the delay circuit 27 in a stopped state, the timing of the transmission of each internal read command is not delayed.

[0123] The host interface circuit 24 sends the read object data and response information to the host device 111 each time it receives read object data and response information from the internal logic unit 21.

[0124] Figure 5 is a sequence diagram showing the internal processing actions of the memory system 101 when the memory system 101 receives multiple external read commands from the host device 111 when the operating mode changes from high temperature mode M2 ​​to performance suppression mode M3.

[0125] Referring to Figures 1 and 5, the host device 111 sends an external sequential read (SeqR) command to the memory system 101.

[0126] The operating mode of the internal logic unit 21 at the controller 20 is set to high temperature mode M2. The internal logic unit 21 receives external SeqR commands through the host interface circuit 24.

[0127] If the internal logic unit 21 receives an external SeqR command, it generates multiple internal read commands based on the external SeqR command to read data stored in each of the regions having a plurality of consecutive physical addresses from the non-volatile memory 10 in address order. In the example shown in FIG5, the internal logic unit 21 generates four internal read commands.

[0128] The internal logic unit 21 sends the four generated internal read commands to the non-volatile memory 10 repeatedly through the memory interface circuit 25.

[0129] Furthermore, the internal logic unit 21, for example, sets a unit time for the timer 26 at time t1 and measures the amount of I / O data per unit time until a completion notification is received from the timer 26.

[0130] Non-volatile memory 10, if receiving an internal read command, retrieves the read object data according to the internal read command and sends the read object data to controller 20. In the example shown in Figure 5, the capacity of the read object data is 4KB (kilobyte).

[0131] The memory interface circuit 25 outputs the read object data to the internal logic unit 21 through the bus 22 each time it receives and reads object data from the non-volatile memory 10.

[0132] The internal logic unit 21 converts the data unit of the read object data into the data unit managed by the host device 111 each time it receives read object data from the memory interface circuit 25.

[0133] Furthermore, the internal logic unit 21 generates a response message if it confirms that it has received the four read object data obtained by the four internal read commands.

[0134] The internal logic unit 21 repeatedly outputs the read object data of the four objects to the host interface circuit 24 through the bus 22. Then, the internal logic unit 21 outputs the response information to the host interface circuit 24 through the bus 22.

[0135] Also, if the internal logic unit 21 receives a completion notification from the timer 26 at time t2, it compares the measured I / O data per unit time with the threshold value Dth.

[0136] In the example shown in Figure 5, since the amount of I / O data per unit time (e.g., 2500-4000 MB / s) is larger than the threshold value Dth, the internal logic unit 21 changes the operating mode from high temperature mode M2 ​​to performance suppression mode M3. After that, the internal logic unit 21 activates the delay circuit 27.

[0137] Thus, from the start of operation of the delay circuit 27 until the delay time DT1 has elapsed, the data waiting to be sent will not be sent from the memory interface circuit 25 through the delay circuit 27.

[0138] Specifically, the internal read command Read2, which corresponds to the "external read command Read1 sent from the host device 111 following the external SeqR command", is a waiting data that will not be sent to the non-volatile memory 10 before time t2. Therefore, after a delay time DT1, it is sent from the memory interface circuit 25 to the non-volatile memory 10.

[0139] The host interface circuit 24 sends the read object data to the host device 111 each time it receives read object data from the internal logic unit 21. Furthermore, if the host interface circuit 24 receives response information from the internal logic unit 21, it sends the response information to the host device 111.

[0140] [Topic] Figure 6 is an example illustrating the change in power consumption relative to performance for memory system 101. The vertical axis represents power consumption in "W". The horizontal axis represents performance in "MiB / s". Performance, for example, is the amount of I / O data per unit time.

[0141] Figure 7 is an example illustrating the change in temperature Tc of memory system 101 relative to power consumption. The vertical axis represents temperature Tc in °C, and the horizontal axis represents power consumption in W.

[0142] As shown in Figures 6 and 7, the power consumption is roughly proportional to the amount of I / O data per unit time. Also, the temperature Tc is roughly proportional to the power consumption. Therefore, the temperature Tc increases in response to the amount of I / O data per unit time.

[0143] When external random read commands and external random write commands are executed, time is required for the conversion from logical address to physical address based on the logical-physical translation table. Therefore, the amount of I / O data per unit time when external random read commands and external random write commands are executed is smaller than the amount of I / O data per unit time when external sequential read commands and external sequential write commands are executed.

[0144] In the comparative example memory system, when the temperature Tc rises, performance suppression is implemented regardless of the amount of I / O data per unit time. This performance suppression may be, for example, a frequency division of the internal frequency or an individual setting of the delay amount for each command.

[0145] Therefore, even for external random read commands and external random write commands with smaller I / O data per unit time and smaller impact on heat generation, a delay will be set, and the processing time of these commands will also be longer.

[0146] Furthermore, in the memory system of the comparative example, in order to minimize the impact caused by performance suppression, a significant performance suppression is implemented only after the temperature Tc reaches a high temperature. Therefore, after the performance suppression is implemented, the operation of the host device 111 becomes slow.

[0147] Figure 8 is a graph illustrating one example of the temperature variation over time when performance suppression is implemented in a prior art memory system. The vertical axis represents temperature Tc in °C, and the horizontal axis represents time in seconds.

[0148] Table 1 shows the simulation results of the memory system performance under normal conditions and under performance suppression conditions.

[0149] As shown in Figure 8 and Table 1, in the prior art memory system, it is configured to "implement performance suppression that reduces performance by 90% if the temperature Tc exceeds 110°C".

[0150] After the temperature Tc exceeds 110°C, a significant performance suppression is implemented, and the amount of I / O data per unit time is also significantly reduced. However, even so, the temperature Tc does not decrease but is maintained at 114°C.

[0151] [Threshold Value Tth] Figure 9 is a graph showing one example of the time variation of temperature Tc when the threshold value Tth is set to 90°C and 100°C in memory system 101. The vertical axis represents temperature in "°C". The horizontal axis represents time.

[0152] Figure 10 is a diagram illustrating one example of the temperature variation of leakage current. The vertical axis represents leakage current in mA. The vertical axis also represents temperature in °C. Here, leakage current is the constantly flowing current. Leakage current is calculated by subtracting the operating current generated by reading and writing data within the memory system 101 from the current flowing in the circuitry contained within the memory system 101.

[0153] As shown in Figures 9 and 10, the curve Cr represents the time change of temperature Tc when the memory system 101 is continuously operated at 100% performance.

[0154] Curves C90 and C100 illustrate the time-varying temperature Tc when the threshold value Tth is set to 90°C and 100°C respectively, and the memory system 101 operates continuously at 100% performance. In this example, when the temperature Tc exceeds the threshold value Tth, the performance of the memory system 101 becomes 82% due to the temperature-controlled frequency modulation processing caused by the delay circuit 27.

[0155] Here, 100% performance, for example, is the amount of I / O data per unit time of the memory system 101 when the delay circuit 27 is not subjected to temperature-controlled frequency modulation processing, but the waiting data is stacked in the signal queue of the volatile memory 23, and external sequential read commands or external sequential write commands are repeatedly sent to the memory system 101 from the host device 111.

[0156] 82% performance, for example, is the performance of “the delay circuit 27 performing temperature-controlled frequency modulation processing in a manner that would make the I / O data volume per unit time 100%”.

[0157] The temperature Tf1 reached when the critical limit Tth is 90°C is reduced by about 12°C compared to the temperature Tfr reached when the delay circuit 27 is not subjected to temperature control frequency modulation.

[0158] On the other hand, when the critical limit Tth is 100°C, the temperature Tf2 is only reduced by about 4°C compared to the temperature Tfr.

[0159] The reason why "even if the same temperature control frequency adjustment process is performed, there will be differences in the temperature reached" is based on the following reasons.

[0160] That is, the leakage current at memory system 101 will increase exponentially with respect to temperature (see Figure 10).

[0161] Therefore, the heat generated by leakage current at temperature Tf2 is significantly greater than the heat generated by leakage current at temperature Tf1. Thus, even with the same temperature control frequency modulation process, the temperature drop from the temperature Tfr reached when the threshold value Tth is 100°C is smaller than the temperature drop from the temperature Tfr reached when the threshold value Tth is 90°C.

[0162] The inventor noticed that "when the temperature is close to or reaches the temperature Tfr, even if strong temperature control frequency modulation is performed, the effect of temperature reduction is still insufficient due to leakage current" and thought of the structure of "performing temperature control frequency modulation from an earlier timing".

[0163] Figure 11 is a diagram showing one example of the temperature changes of the memory system 101 when the memory system 101 is operating at 100% and 90% of its performance. In addition, the vertical axis and the horizontal axis represent temperature and time, respectively.

[0164] As shown in Figures 1, 10 and 11, the threshold value Tth is the temperature below which the memory system 101 continues to operate when the non-volatile memory 10 reads and writes data to each region of memory region 11 that has a plurality of consecutive physical addresses, and the execution of commands caused by the non-volatile memory 10 is delayed by the delay circuit 27.

[0165] In detail, curves C1 and C2 show the time change of temperature Tc when the memory system 101 at room temperature (about 25°C) operates continuously at 100% and 90% performance, respectively.

[0166] 90% performance, for example, is the performance of “the delay circuit 27 performing temperature-controlled frequency modulation processing in a manner that would make the I / O data volume per unit time 100%”.

[0167] When the memory system 101 operates continuously at 100% performance, the temperature Tc reaches the peak temperature Tf (100). When the memory system 101 operates continuously at 90% performance, the temperature Tc reaches Tf (90). Here, the peak temperature Tf (90) is lower than the peak temperature Tf (100).

[0168] The inventors have focused on the fact that "for example, when the reached temperature Tf(90) is set as the reference temperature, by performing temperature control frequency modulation processing earlier than the time sequence when the temperature Tc becomes above the reached temperature Tf(90), it is possible to reduce the adverse effects of heat generation caused by leakage current".

[0169] The critical limit value Tth is, for example, reaching a temperature below Tf (90). In this embodiment, the critical limit value Dth is reaching a temperature of Tf (90).

[0170] Even if the delay circuit 27 performs temperature control frequency modulation in a way that achieves 90% performance when the temperature Tc is at the temperature Tf (100), it is difficult to make the temperature Tc drop continuously until it reaches the temperature Tf (90).

[0171] This is because the leakage current at memory system 101 increases exponentially with respect to temperature. Therefore, when temperature Tc is at temperature Tf(100), the temperature Tc is difficult to decrease due to the heat generated by the leakage current.

[0172] On the other hand, although it is also possible to consider the method of “operating the memory system 101 with 90% performance from the start of the operation of the memory system 101”, the amount of I / O data per unit time will be lower, and therefore the time required for read and write processing will be longer, which is not ideal.

[0173] By setting the threshold value Tth to the temperature Tf (90), the upper limit of temperature Tc can be set to be close to the temperature Tf (90). Furthermore, when temperature Tc is below the threshold value Tth (that is, the temperature Tf (90)), the memory system 101 can operate at 100% performance, thus suppressing the situation where "the time required for read and write processing increases".

[0174] [Critical Limit Value Dth] The critical limit value Dth is smaller than the amount of I / O data per unit time when the non-volatile memory 10 reads and writes data to each region of memory region 11 which has a plurality of consecutive physical addresses, and larger than the amount of I / O data per unit time when the non-volatile memory 10 reads and writes data to each region of memory region 11 which has a plurality of non-consecutive physical addresses.

[0175] Specifically, the threshold value Dth is, for example, smaller than the amount of I / O data per unit time when "an external sequential read command is repeatedly received from the host device 111 at the memory system 101 in a manner that would cause the pending data to be stacked in the signal queue of the volatile memory 23 (hereinafter, there will be a situation called continuous sequential read operations)".

[0176] In addition, the threshold value Dth may be smaller than the amount of I / O data per unit time when "an external sequential write command is repeatedly received from the host device 111 at the memory system 101 in a manner that would cause the pending data to be stacked in the signal queue of the volatile memory 23 (hereinafter, there will be a situation called continuous sequential write operation)".

[0177] Furthermore, the threshold value Dth, for example, is greater than the amount of I / O data per unit time when "an external random read command is repeatedly received from the host device 111 at the memory system 101 in a manner that would cause the pending data to be stacked in the data queue of the volatile memory 23 (hereinafter, there will be a situation called continuous random read operations)".

[0178] In addition, the threshold value Dth may be, for example, larger than the amount of I / O data per unit time when "an external random write command is repeatedly received from the host device 111 at the memory system 101 in a manner that would cause the pending send data to be stacked in the send queue of volatile memory 23 (hereinafter, there will be a situation called continuous random write operation)".

[0179] In the following cases, there may be situations where sequential read operations and sequential write operations are collectively referred to as sequential R / W operations. There may also be situations where sequential random read operations and sequential random write operations are collectively referred to as sequential random R / W operations.

[0180] Table 2 shows the simulation results of the memory system 101 when the operation mode is normal mode M1 and when Tc > Tth.

[0181] As shown in Table 2, this simulation was performed under the following conditions. That is, the performance corresponding to external sequential read commands and external sequential write commands (hereinafter referred to as sequential performance), that is, the amount of I / O data per unit time, is the performance when "the amount of data read and written by these commands is 4 GiB, and the QD and chunk size are 8 and 512KB respectively".

[0182] The performance corresponding to external random read commands and external random write commands (hereinafter, there will be a situation referred to as random performance) is the performance when "the amount of data read and written by these commands is 4 GiB, and the QD, chunk size and number of consecutive instructions are 32, 3KB and 24576 respectively".

[0183] The 400 KIOPs of "random performance in normal mode M1" is equivalent to 1600 MiB / s. For example, if the threshold value Dth is set to 3000 MiB / s, even if external random read or write commands are repeatedly received, the operating mode can be maintained as normal mode M1 or high temperature mode M2.

[0184] On the other hand, when an external sequential read command or an external sequential write command is repeatedly received, the system can switch the operation mode to performance suppression mode M3.

[0185] Power consumption is slightly proportional to performance (see Figure 6). Therefore, the power consumption when repeatedly receiving external random read commands or external random write commands is about 38% of the power consumption when repeatedly receiving external sequential read commands or external sequential write commands.

[0186] That is, at memory system 101, when the heat generated by repeated reception is a small external random read command or external random write command, since no temperature control frequency adjustment is performed, it is possible to suppress the situation where the time required for read and write processing increases.

[0187] Figure 12 is a diagram showing one example of the time variation of the operating current Icc when the memory system 101 performs continuous sequential read operations.

[0188] The vertical and horizontal axes in graphs S1 and S3 respectively represent the operating current Icc and time. Graphs S1 and S3 show the time variation of the operating current Icc under normal mode M1 and performance suppression mode M3, respectively.

[0189] Herein, the operating current Icc is the result of the measurement of the current consumed at the VCC power supply that supplies power to the memory system 101.

[0190] As shown in Figure 12, in performance suppression mode M3, since the performance (i.e., the amount of I / O data per unit time) is reduced, the power consumption is also reduced. Therefore, the operating current Icc in performance suppression mode M3 is lower than the operating current Icc in normal mode M1.

[0191] Figure 13 is a diagram showing one example of the time variation of the operating current Icc when the memory system of the comparative example performs continuous sequential read operations.

[0192] Charts Sr1 and Sr3 respectively show the time variation of the operating current Icc under normal conditions and under the condition of performance suppression. In addition, the interpretation method of charts Sr1 and Sr3 is the same as that of charts S1 and S3.

[0193] As shown in Figure 13, the operating current Icc when performance suppression is implemented is the same as that of the memory system 101 shown in Figure 12, but is lower than the operating current Icc under normal conditions.

[0194] Figure 14 is a diagram showing one example of the time variation of the operating current Icc when the memory system of the comparative example performs continuous random read operations.

[0195] Charts Rr1 and Rr3 respectively show the time variation of the operating current Icc under normal conditions and under the condition of performance suppression. In addition, the interpretation method of charts Rr1 and Rr3 is the same as that of charts S1 and S3.

[0196] As shown in Figure 14, the operating current Icc when performance suppression is implemented is the same as that of the memory system in the comparative example shown in Figure 13, which is lower than the operating current Icc under normal conditions.

[0197] This is because, in the memory system of the comparative example, since performance suppression is implemented regardless of the amount of I / O data per unit time as described above, even for external random read commands that have a small impact on heat generation, a delay is set.

[0198] Figure 15 is a diagram showing one example of the time variation of the operating current Icc when the memory system 101 performs continuous random read operations.

[0199] Charts R1 and R3 show the time variation of the operating current Icc under normal mode M1 and high temperature mode M2, respectively. The interpretation method of charts R1 and R3 is the same as that of charts S1 and S3.

[0200] As shown in Figure 15, when continuous random read operations are performed at memory system 101, the operating mode does not transition to performance suppression mode M3 because the amount of I / O data per unit time is smaller than the threshold value Dth. Therefore, the power consumption in normal mode M1 and high-temperature mode M2 ​​is slightly the same, and thus, the operating current Icc in high-temperature mode M2 ​​is slightly the same as the operating current Icc in normal mode M1.

[0201] Furthermore, when the performance suppression mode M3 is set via the operation mode selection unit 28, the delay circuit control unit 32 can cause the delay circuit 27 to operate once or multiple times. When the delay circuit 27 operates multiple times, the delay circuit control unit 32, for example, operates the delay circuit 27 at each of the internal read commands and internal write commands. Also, the delay circuit control unit 32, for example, can also operate the delay circuit 27 each time the data acquisition unit 29 acquires a unit time I / O data amount. Alternatively, the delay circuit control unit 32, for example, can also operate the delay circuit 27 each time the data acquisition unit 29 acquires a specific number of unit time I / O data amounts.

[0202] Furthermore, although the description pertains to the configuration where the delay circuit 27 is located at the memory interface circuit 25, it is not limited thereto. The delay circuit 27 may also be located at the internal logic unit 21 or the non-volatile memory 10. When the delay circuit 27 is located at the internal logic unit 21, the delay circuit 27, for example, delays the generation of internal read commands and internal write commands caused by the internal logic unit 21 by a specific delay time. Similarly, when the delay circuit 27 is located at the non-volatile memory 10, the delay circuit 27, for example, delays the generation of internal read commands and internal write commands caused by the internal logic unit 21 by a specific delay time.

[0203] Furthermore, although the explanation was given regarding the condition of transitioning from the normal mode M1 to the high-temperature mode M2 ​​as "the temperature Tc is higher than the critical limit Tth", it is not limited to this. The condition of transitioning from the normal mode M1 to the high-temperature mode M2 ​​may also be "the temperature Tc is above the critical limit Tth".

[0204] Furthermore, although the explanation focuses on the condition that "when the temperature Tc is above the critical limit Tth, Σ(Data size) is greater than the critical limit Dth" as the condition for transitioning from high-temperature mode M2 ​​to performance suppression mode M3, it is not limited to this. The condition that "when the temperature Tc is above the critical limit Tth, Σ(Data size) is above the critical limit Dth" can also be used as the condition for transitioning from high-temperature mode M2 ​​to performance suppression mode M3.

[0205] Furthermore, although the explanation was given regarding the condition of transitioning from performance suppression mode M3 to high temperature mode M2 ​​as "temperature Tc is above the critical limit Tth and Σ(Data size) is lower than the critical limit Dth", it is not limited to this. The condition of transitioning from performance suppression mode M3 to high temperature mode M2 ​​may also be "temperature Tc is above the critical limit Tth and Σ(Data size) is below the critical limit Dth".

[0206] Furthermore, although the explanation was given regarding the condition of transitioning from performance suppression mode M3 or high temperature mode M2 ​​to normal mode M1 when "temperature Tc is lower than the critical limit value Tth", it is not limited to this. It is also possible to use the condition of transitioning from performance suppression mode M3 or high temperature mode M2 ​​to normal mode M1 when "temperature Tc is below the critical limit value Tth".

[0207] Furthermore, although the description pertains to the configuration in which "the operation mode selection unit 28 compares the amount of I / O data per unit time with the threshold value Dth, and sets the operation mode to high-temperature mode M2 ​​or performance suppression mode M3 based on the comparison result," it is not limited to this configuration. The configuration in which "the operation mode selection unit 28 compares the amount of data read per unit time with the threshold value Dth, and sets the operation mode to high-temperature mode M2 ​​or performance suppression mode M3 based on the comparison result" can also be used. Since the power consumption of reading data from the non-volatile memory 10 is greater than the power consumption of writing data to the non-volatile memory 10, even with this configuration, sufficient effectiveness can be achieved. Furthermore, the configuration in which "the operation mode selection unit 28 compares the amount of data written per unit time with the threshold value Dth, and sets the operation mode to high-temperature mode M2 ​​or performance suppression mode M3 based on the comparison result" can also be used.

[0208] (a) A memory device comprising: a non-volatile memory having a non-volatile memory region and capable of reading and writing data in the aforementioned memory region; a host interface circuit that receives from a host device an external command information containing a command to cause the aforementioned non-volatile memory to read and write the aforementioned data; a memory interface circuit that sends internal command information corresponding to the aforementioned external command information to the aforementioned non-volatile memory; and a delay circuit that delays the execution of the aforementioned command caused by the aforementioned non-volatile memory when the amount of data read and written by the aforementioned non-volatile memory in a unit time period is greater than or equal to a first threshold value.

[0209] (b) A memory device comprising: a non-volatile memory having a non-volatile memory region and capable of reading and writing data in the aforementioned memory region; a host interface circuit that receives from a host device an external command information containing a command to cause the aforementioned non-volatile memory to read the aforementioned data; a memory interface circuit that sends internal command information corresponding to the aforementioned external command information to the aforementioned non-volatile memory; and a delay circuit that delays the execution of the aforementioned command caused by the aforementioned non-volatile memory when the amount of data read by the aforementioned non-volatile memory in a unit time period is greater than or equal to a first threshold value.

[0210] (c) A memory device comprising: a non-volatile memory having a non-volatile memory region and capable of reading and writing data in the aforementioned memory region; a host interface circuit that receives from a host device an external command information containing a command to write the aforementioned data to the aforementioned non-volatile memory; a memory interface circuit that sends internal command information corresponding to the aforementioned external command information to the aforementioned non-volatile memory; and a delay circuit that delays the execution of the aforementioned command caused by the aforementioned non-volatile memory when the amount of data written to the aforementioned non-volatile memory in a unit time period is greater than or equal to a first threshold value.

[0211] The above description refers to specific examples. However, this disclosure is not limited to these specific examples. Even if the practitioner makes appropriate design changes to these specific examples, as long as they possess the features of this disclosure, they are included within the scope of this disclosure. The elements, configurations, conditions, shapes, etc., of the aforementioned specific examples are not limited to those shown, and can be appropriately changed. The elements of the aforementioned specific examples can be appropriately combined and changed as long as they do not create technical contradictions. [Simplified Explanation of the Diagram]

[0006] [Figure 1] is a functional block diagram of the memory system 101 of this embodiment. [Figure 2] is a state transition diagram showing the operating modes of the memory system 101. [Figure 3] is a sequence diagram showing the internal processing actions of the memory system 101 when it receives an external read command from the host device 111 in normal mode M1. [Figure 4] is a sequence diagram showing the internal processing actions of the memory system 101 when it receives multiple external read commands from the host device 111 in high-temperature mode M2. [Figure 5] is a sequence diagram showing the internal processing actions of the memory system 101 when it receives multiple external read commands from the host device 111 in the case where the operating mode changes from high-temperature mode M2 ​​to performance suppression mode M3. [Figure 6] is a diagram illustrating one example of the change in power consumption relative to performance of memory system 101. [Figure 7] is a diagram illustrating one example of the change in temperature Tc of memory system 101 relative to power consumption. [Figure 8] is a diagram illustrating one example of the time-varying temperature when performance suppression is implemented in a prior art memory system. [Figure 9] is a diagram illustrating one example of the time-varying temperature Tc when the threshold value Tth in memory system 101 is set to 90°C and 100°C. [Figure 10] is a diagram illustrating one example of the temperature variation of leakage current. [Figure 11] is a diagram illustrating one example of the temperature variations of memory system 101 when memory system 101 operates at 100% and 90% performance. [Figure 12] is a diagram showing one example of the time variation of the operating current Icc when the memory system 101 performs continuous sequential read operations. [Figure 13] is a diagram showing one example of the time variation of the operating current Icc when the memory system of the comparative example performs continuous sequential read operations. [Figure 14] is a diagram showing one example of the time variation of the operating current Icc when the memory system of the comparative example performs continuous random read operations. [Figure 15] is a diagram showing one example of the time variation of the operating current Icc when the memory system 101 performs continuous random read operations.

Claims

1. A memory system comprising: a non-volatile memory having a non-volatile memory region and capable of reading and writing data in the memory region; and a controller comprising: a host interface circuit that receives external command information from a host device, including a command to cause the non-volatile memory to read and write the aforementioned data; a memory interface circuit that communicates with the non-volatile memory; a command information processing unit that generates internal command information based on the external command information to cause the non-volatile memory to execute the aforementioned command, and sends the internal command information to the non-volatile memory via the memory interface circuit; and a delay circuit control unit that controls a delay circuit that delays the execution of the aforementioned command based on the relationship between the amount of data read and written by the non-volatile memory and a first threshold value within a unit time period.

2. The memory system as described in claim 1, wherein, The aforementioned delay circuit control unit delays the execution of the aforementioned command for the aforementioned delay circuit when the aforementioned data amount is above the aforementioned first threshold value.

3. The memory system as described in claim 2, wherein, The aforementioned memory system further includes: a temperature sensor that acquires temperature information representing the temperature of the aforementioned memory system; and a delay circuit control unit that delays the execution of the aforementioned command for the aforementioned delay circuit when the aforementioned temperature is above a second threshold and the aforementioned data amount is above the aforementioned first threshold.

4. The memory system described in any of claims 1 to 3, wherein, The aforementioned delay circuit delays the execution of the aforementioned command by configuring it so that the aforementioned internal command information is not sent to the aforementioned non-volatile memory during a specific delay period.

5. The memory system as described in claim 1, wherein, The aforementioned first threshold value is smaller than the amount of data when the aforementioned non-volatile memory reads and writes the aforementioned data to regions in the aforementioned memory region that each has a plurality of consecutive addresses, and larger than the amount of data when the aforementioned non-volatile memory reads and writes the aforementioned data to regions in the aforementioned memory region that each has a plurality of non-consecutive addresses.

6. The memory system as described in claim 3, wherein, The aforementioned second threshold is the temperature below which the memory system continues to operate when the aforementioned non-volatile memory reads and writes the aforementioned data to each region having a plurality of consecutive addresses in the aforementioned memory region, and the execution of the aforementioned command is delayed by the aforementioned delay circuit.

7. The memory system as described in claim 2, wherein, The time from when the host interface circuit receives the external command information until the memory interface circuit sends the internal command information is longer when the delay circuit control unit delays the execution of the command due to the delay circuit, compared to when the delay circuit control unit does not delay the execution of the command due to the delay circuit.

8. A memory device comprising: a non-volatile memory having a non-volatile memory region and capable of reading and writing data in the memory region; a host interface circuit that receives from a host device external command information containing a command to read and write the data in the non-volatile memory; a memory interface circuit that sends internal command information corresponding to the external command information to the non-volatile memory; and a delay circuit that delays the execution of the aforementioned command caused by the non-volatile memory when the amount of data read and written by the non-volatile memory in a unit time period is greater than or equal to a first threshold value.

9. A control method for a memory system, the memory system comprising: a non-volatile memory having a non-volatile memory region and capable of reading and writing data in the memory region; and a controller communicating with the non-volatile memory, the control method comprising: receiving from a host device external command information containing a command to cause the non-volatile memory to read and write the aforementioned data; generating internal command information based on the external command information to cause the non-volatile memory to execute the aforementioned command; sending the internal command information to the non-volatile memory; and controlling a delay circuit that delays the execution of the aforementioned command based on the relationship between the amount of data read and written by the non-volatile memory and a first threshold value within a unit time period.

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