Semiconductor device and semiconductor structure

Abstract

A semiconductor device includes a substrate, a circuit layer, a dielectric layer, a wiring layer, a metal buffer layer, and metal bonding pads. The circuit layer is disposed on the upper surface of the substrate. The dielectric layer is disposed on the upper surface of the circuit layer. The wiring layer is disposed on the upper surface of the circuit layer and is located within the dielectric layer. The metal buffer layer is disposed on the upper surface of the wiring layer and is located within the dielectric layer. The metal bonding pads are disposed on the upper surface of the metal buffer layer. This invention further provides a semiconductor structure.

Description

Technical Field

[0001] This case relates to a design for preventing the breakage of a metal bonding pad used for wire bonding connections, and in particular to a semiconductor device and semiconductor structure with a metal buffer layer. Prior Technology

[0002] With advancements in semiconductor manufacturing technology, electronic products are trending towards thinner, lighter, and smaller designs, leading to increasingly higher demands on semiconductor packaging. Currently, the most common packaging architectures in the semiconductor industry primarily employ one-metal processes and wire-bonding packaging technology.

[0003] In packaging architectures employing single-layer metal and wire bonding processes, the single-layer metal used for wire bonding (e.g., aluminum) is prone to cracking or deformation due to the wire bonding process. Especially when components operate at high temperatures or after prolonged use, the single-layer metal material (e.g., aluminum) is susceptible to structural damage due to thermal stress and mechanical stress generated by the wire bonding. These cracks or deformations not only affect the conductivity and stability of the components but may also cause the failure of the entire package structure. Summary of the Invention

[0004] In some embodiments, a semiconductor device includes a substrate, a circuit layer, a dielectric layer, a wiring layer, a metal buffer layer, and metal bonding pads. The circuit layer is disposed on the upper surface of the substrate. The dielectric layer is disposed on the upper surface of the circuit layer. The wiring layer is disposed on the upper surface of the circuit layer and is located within the dielectric layer. The metal buffer layer is disposed on the upper surface of the wiring layer and is located within the dielectric layer. The metal bonding pads are disposed on the upper surface of the metal buffer layer.

[0005] In some embodiments, the routing layer includes multiple vertical traces, and the metal buffer layer is connected to the circuit layer via the multiple vertical traces.

[0006] In some embodiments, each vertical trace is connected to the input or output of a circuit layer.

[0007] In some embodiments, the routing layer further comprises multiple horizontal traces.

[0008] In some embodiments, at least one horizontal trace passes between two adjacent vertical traces.

[0009] In some embodiments, at least one horizontal trace is connected to the power supply terminal of the circuit layer.

[0010] In some embodiments, at least one horizontal trace is connected to the ground terminal of the circuit layer.

[0011] In some embodiments, the semiconductor device further includes a passivation layer. The passivation layer is formed on the dielectric layer and includes openings. The openings correspond to metal wire bonding pads.

[0012] In some embodiments, the metal bonding pad is made of aluminum.

[0013] In some embodiments, the size of the metal buffer layer is the same as the size of the metal bonding pad.

[0014] In some embodiments, a semiconductor structure includes a semiconductor device as described in any of the above embodiments and a plurality of wires. The plurality of wires are wire-bonded to the metal wire bonding pad of the semiconductor device as described in any of the above embodiments.

[0015] In some embodiments, multiple wires are connected to the central region of the metal bonding pad corresponding to the opening.

[0016] In some embodiments, the metal bonding pad corresponding to the opening area includes multiple corner areas. Multiple wires are evenly bonded to each corner area.

[0017] The following detailed description of the features and advantages of this invention is sufficient to enable anyone skilled in the art to understand the technical content of this invention and implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the relevant purpose and advantages of this invention. Simple Explanation of the Diagram

[0018] Figure 1 is a cross-sectional schematic diagram of one embodiment of a semiconductor device. Figure 2 is a top view of one embodiment of the wiring layer. Figure 3 is a cross-sectional schematic diagram of one embodiment of a semiconductor structure. Figure 4A is a schematic diagram of one embodiment of the metal bonding pad corresponding to the opening area. Figure 4B is a schematic diagram of another embodiment of the metal bonding pad corresponding to the area of ​​the opening. Implementation

[0019] Figure 1 is a schematic cross-sectional view of one embodiment of semiconductor device 1. Referring to Figure 1, semiconductor device 1 includes a substrate 10, a circuit layer 11, a dielectric layer 12, a wiring layer 13, a metal buffer layer 14, and metal bonding pads 15. The circuit layer 11 is disposed on the upper surface of the substrate 10. The dielectric layer 12 is disposed on the upper surface of the circuit layer 11. The wiring layer 13 is disposed on the upper surface of the circuit layer 11 and located within the dielectric layer 12. The metal buffer layer 14 is disposed on the upper surface of the wiring layer 13 and located within the dielectric layer 12. The metal bonding pads 15 are disposed on the upper surface of the metal buffer layer 14.

[0020] In some embodiments, the metal buffer layer 14 may be, but is not limited to, a via.

[0021] In some embodiments, the metal bonding pad 15 may be made of, but is not limited to, aluminum. In some embodiments, the metal buffer layer 14 may be made of, but is not limited to, copper.

[0022] In some embodiments, the metal buffer layer 14 can provide more support for the metal bonding pad 15, thereby reducing the stress borne by the metal bonding pad 15. Specifically, since the metal buffer layer 14 is disposed on the lower surface of the metal bonding pad 15, it can provide a larger support area for the metal bonding pad 15, allowing the mechanical stress experienced by the metal bonding pad 15 due to bonding to be more evenly distributed in the structure composed of the metal buffer layer 14 and the metal bonding pad 15. This avoids the concentration of mechanical stress in the metal bonding pad 15, thus improving the distribution of mechanical stress in the structure composed of the metal buffer layer 14 and the metal bonding pad 15. Furthermore, the metal buffer layer 14 can increase the support strength of the structure composed of the metal buffer layer 14 and the metal bonding pad 15, reducing the possibility of deformation and displacement of the metal bonding pad 15, thereby improving the stability of the structure. Furthermore, the metal buffer layer 14 provides a better heat dissipation path for the metal bonding pad 15, reduces the generation of local hot spots on the metal bonding pad 15, and reduces the stress on the metal bonding pad 15 caused by thermal expansion and contraction, thereby alleviating the thermal stress on the metal bonding pad 15. That is, in some embodiments, the semiconductor device 1 has better structural integrity, higher reliability, and longer service life due to the provision of the metal buffer layer 14.

[0023] In some embodiments, the size of the metal buffer layer 14 is the same as the size of the metal bonding pad 15. However, this is not a limitation, and in some embodiments, the size of the metal buffer layer 14 is larger than the size of the metal bonding pad 15.

[0024] When the size of the metal buffer layer 14 is the same as or larger than the size of the metal bonding pad 15, the contact area between the metal buffer layer 14 and the metal bonding pad 15 is large. This larger contact area reduces the contact resistance between the metal buffer layer 14 and the metal bonding pad 15, and the cross-sectional area through which current flows also increases, thereby reducing the overall resistance of the semiconductor device 1. Furthermore, the metal buffer layer 14, with its larger contact area with the metal bonding pad 15, provides a larger and more uniform conductive path, avoiding hot spots caused by current concentration in small areas, reducing the problem of excessively high local current density, and thus reducing electromagnetic interference and thermal effects caused by high current density and improving the electromagnetic compatibility (EMC) of the semiconductor device 1. In some embodiments, the semiconductor device 1 can further exhibit better electrical performance, lower operating temperature, and lower IREM (Internal Resistance and Electromagnetic Effects) due to the provision of the metal buffer layer 14.

[0025] Because the metal buffer layer 14 provides sufficient mechanical support and stress dispersion, the wiring layer 13 can be safely positioned at the bottom of the metal buffer layer 14 without the risk of being crushed or affected by the metal bonding pad 15, which may crack or deform. As described above, when external forces (such as stress during the bonding process) are applied to the metal bonding pad 15, these stresses are first uniformly absorbed and dispersed by the metal buffer layer 14, significantly reducing the stress transmitted to the wiring layer 13, thereby effectively preventing the wiring layer 13 from being damaged or crushed by external forces.

[0026] In the prior art, due to the lack of a support structure like the metal buffer layer 14, the metal bonding pad is prone to cracking or deformation due to stress concentration when subjected to mechanical stress during the bonding process, which in turn damages the routing layer located below it. Therefore, in the prior art, the routing layer cannot be placed below the metal bonding pad, which severely limits the flexibility and reliability of the structural design. However, the present invention provides effective support and stress dispersion by setting the metal buffer layer 14 below the metal bonding pad 15, allowing the routing layer 13 to be safely placed below the metal buffer layer 14, successfully overcoming the defect of the prior art that cannot set the routing layer.

[0027] Since the wiring layer 13 can be safely disposed below the metal buffer layer 14, the semiconductor device 1 has more vertical and horizontal wiring space and conductive path options, thereby increasing the wiring flexibility of the semiconductor device 1. In some embodiments, the wiring layer 13 includes a plurality of vertical traces 131. The metal buffer layer 14 is connected to the circuit layer 11 via the plurality of vertical traces 131. In some embodiments, each vertical trace 131 is connected to an input or output terminal of the circuit layer 11.

[0028] In some embodiments, the wiring layer 13 further includes a plurality of horizontal traces 132. In FIG. 1, the plurality of horizontal traces 132 includes a plurality of horizontal traces 1321 and a plurality of horizontal traces 1322. The plurality of horizontal traces 1321 are not directly connected to the circuit layer 11 shown in FIG. 1, but are connected to the circuit layer 11 of the semiconductor device 1 not shown in this cross-sectional view; in other words, the plurality of horizontal traces 1321 are simply horizontal traces 132 passing through the cross-section of the semiconductor device 1 shown in this figure. In contrast, the plurality of horizontal traces 1322 are horizontal traces 132 directly connected to the circuit layer 11 of the cross-section of the semiconductor device 1 shown in FIG. 1.

[0029] In some embodiments, at least one horizontal trace 132 is connected to the power supply terminal of circuit layer 11. In some embodiments, at least one horizontal trace 132 is connected to the ground terminal of circuit layer 11. In some embodiments, when multiple horizontal traces 1321 are connected to the power supply terminal of circuit layer 11, multiple horizontal traces 1322 are connected to the ground terminal of circuit layer 11. In some embodiments, when multiple horizontal traces 1321 are connected to the ground terminal of circuit layer 11, multiple horizontal traces 1322 are connected to the power supply terminal of circuit layer 11. That is, in some embodiments, multiple horizontal traces 1321 and multiple horizontal traces 1322 are connected to different terminals of circuit layer 11.

[0030] Figure 2 is a top view of one embodiment of the routing layer 13. The routing layer 13 in Figure 2 corresponds to the routing layer 13 in Figure 1. Please refer to Figures 1 and 2. In some embodiments, at least one horizontal trace 132 passes between two adjacent vertical traces 131. In some embodiments, a plurality of horizontal traces 1321 extend horizontally in the same direction because they are connected to the same end of the circuit layer 11. In some embodiments, a plurality of horizontal traces 1322 extend horizontally in the same direction because they are connected to the same end of the circuit layer 11. In some embodiments, since the plurality of horizontal traces 1321 and the plurality of horizontal traces 1322 are connected to different ends of the circuit layer 11, the plurality of horizontal traces 1321 and the plurality of horizontal traces 1322 extend horizontally in different directions.

[0031] Through the arrangement of trace layer 13, semiconductor device 1 has greater wiring flexibility. Semiconductor device 1 can achieve vertical and horizontal signal transmission in the same area through vertical traces 131 and horizontal traces 132, thereby realizing multi-path signal transmission, reducing the wiring complexity of semiconductor device 1, and solving the wiring congestion problem in high-density circuits. Furthermore, vertical traces 131 and horizontal traces 132 can achieve the shortest path signal transmission, reducing additional parasitic capacitance and resistance in signal transmission. A shorter signal transmission path means reduced time delay, and delay is a major performance bottleneck in high-speed circuits. Reducing delay directly improves the circuit's response speed, enabling semiconductor device 1 to support higher frequency signal transmission. That is, in some embodiments, semiconductor device 1 has better design flexibility and better electrical performance due to the arrangement of trace layer 13.

[0032] In some embodiments, the semiconductor device 1 further includes a passivation layer 16. The passivation layer 16 is formed on the dielectric layer 12 and includes an opening 161. The opening 161 corresponds to the metal bonding pad 15.

[0033] Figure 3 is a schematic cross-sectional view of one embodiment of the semiconductor structure 2. Please refer to Figure 3. The semiconductor structure 2 includes a semiconductor device 1 as shown in Figure 1 and a plurality of wires 20. The plurality of wires 20 are wire-bonded to a metal wire bonding pad 15.

[0034] Figure 4A is a schematic diagram of one embodiment of the metal bonding pad 15 corresponding to region 151 of opening 161. Please refer to Figures 3 and 4A. In some embodiments, multiple wires 20 are bonded together in the central region 152 of region 151 of metal bonding pad 15 corresponding to opening 161. In Figure 4A, the stress generated by the bonding of multiple wires 20 is applied to metal bonding pad 15 in a single-point manner. In other words, the stress generated by the bonding of multiple wires 20 is concentrated at a single point. This concentrated pressure may generate greater stress on metal bonding pad 15, thereby increasing the risk of metal bonding pad 15 cracking or deforming.

[0035] Figure 4B is a schematic diagram of another embodiment of the metal bonding pad 15 corresponding to the region 151 of the opening 161. In some embodiments, the region 151 of the metal bonding pad 15 corresponding to the opening 161 includes multiple corner regions 153. In some embodiments, multiple wires 20 are evenly wire-connected to each corner region 153. In Figure 4B, the stress generated by the multiple wires 20 due to the wire connection is applied to the metal bonding pad 15 in a multi-point manner. In other words, the stress generated by the multiple wires 20 due to the wire connection is distributed across multiple points. This distributed pressure application can reduce the pressure intensity of each corner region 153, thereby reducing the risk of breakage or deformation of the metal bonding pad 15. That is, in some embodiments, the way the semiconductor structure 2 is evenly wire-connected to each corner region 153 through multiple wires 20 can give the metal bonding pad 15 better reliability and durability.

[0036] In summary, in some embodiments, the semiconductor device 1 exhibits better structural integrity, higher reliability, longer lifespan, better electrical performance, lower operating temperature, and lower IREM due to the metal buffer layer 14. Furthermore, in some embodiments, the semiconductor device 1 exhibits better design flexibility and better electrical performance due to the wiring layer 13.

[0037] Although the technical content of this case has been disclosed above with reference to preferred embodiments, it is not intended to limit this case. Any modifications and refinements made by those skilled in the art without departing from the spirit of this case should be included within the scope of this case. Therefore, the scope of protection of this case shall be determined by the appended claims.

[0038] 1: Semiconductor devices 10:Substrate 11: Circuit Layer 12: Dielectric layer 13: Wiring Layer 14: Metal buffer layer 15: Metal wire bonding pad 16: Passivation layer 131: Vertical routing 132, 1321, 1322: Horizontal routing 161: Opening 20: Wire 151: Region 152: Central Area 153: Corner Area 2: Semiconductor Structure

Claims

1. A semiconductor device comprising: a substrate; a circuit layer disposed on an upper surface of the substrate; a dielectric layer disposed on the upper surface of the circuit layer; a wiring layer disposed on the upper surface of the circuit layer and located in the dielectric layer; a metal buffer layer disposed on the upper surface of the wiring layer and located in the dielectric layer; and a metal bonding pad disposed on the upper surface of the metal buffer layer.

2. The semiconductor device of claim 1, wherein the wiring layer includes a plurality of vertical traces, and the metal buffer layer is connected to the circuit layer via the vertical traces.

3. The semiconductor device as claimed in claim 2, wherein each of the vertical traces is connected to an input or output terminal of the circuit layer.

4. The semiconductor device as claimed in claim 2, wherein the wiring layer further comprises a plurality of horizontal wirings.

5. The semiconductor device as claimed in claim 4, wherein at least one of the horizontal traces passes between two adjacent vertical traces.

6. The semiconductor device as claimed in claim 4, wherein at least one of the horizontal traces is connected to the power supply terminal of the circuit layer.

7. The semiconductor device as claimed in claim 4, wherein at least one of the horizontal traces is connected to the ground terminal of the circuit layer.

8. The semiconductor device of claim 1 further includes a passivation layer formed on the dielectric layer and including an opening corresponding to the metal wire bonding pad.

9. The semiconductor device as claimed in claim 1, wherein the metal wire bonding pad is made of aluminum.

10. A semiconductor structure comprising: a semiconductor device as described in any one of claims 1 to 9; and a plurality of wires wire-bonded to the metal wire bonding pad of the semiconductor device.

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