Semiconductor device and method for fabricating the same

Abstract

A method of manufacturing a semiconductor device includes: forming a dummy channel structure; forming a gate electrode surrounding the dummy channel structure; forming a word line surrounding the gate electrode; removing the dummy channel structure to form an opening; forming a gate dielectric layer in the opening; and forming a channel structure in the opening.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Prior Technology

[0002] Dynamic random-access memory (DRAM) is a type of random-access semiconductor memory that stores each bit of data in a storage cell. DRAM is known for its high speed, high density, and scalability. However, as DRAM production scales up, its manufacturing becomes more challenging and more prone to defects. These defects can lead to device errors and / or malfunctions. For example, the gate structure may not effectively control the channel structure. Therefore, there is a need for an efficient semiconductor device apparatus and its manufacturing method. Summary of the Invention

[0003] The embodiments disclosed herein provide a method for manufacturing a semiconductor device, comprising: forming a dummy channel structure; forming a gate electrode surrounding the dummy channel structure; forming a word line surrounding the gate electrode; removing the dummy channel structure to form an opening; forming a gate dielectric layer in the opening; and forming a channel structure in the opening.

[0004] In some embodiments, the dummy channel structure overlaps with a capacitor.

[0005] In some embodiments, a dielectric layer is formed on the capacitor, wherein a dummy channel structure is formed on the dielectric layer.

[0006] In some embodiments, the opening exposes the capacitor.

[0007] In some embodiments, the gate dielectric layer extends vertically from the capacitor and along one sidewall of the opening.

[0008] In some embodiments, the method further includes etching back the gate electrode such that a top surface of the gate electrode is lower than a top surface of the dummy channel structure.

[0009] In some embodiments, a top surface of the character line is lower than a top surface of the gate electrode.

[0010] In some embodiments, forming a character line includes: forming a character line material surrounding a dummy channel structure; forming a hard mask structure over the character line material; and etching the character line material through the hard mask structure to form the character line.

[0011] In some embodiments, the hard mask structure overlaps with the dummy channel structure.

[0012] In some embodiments, a spacer is also included forming along one sidewall of the hard mask structure before etching the character line material.

[0013] A semiconductor device includes: a capacitor; a channel structure extending vertically from a top surface of the capacitor; a gate dielectric layer surrounding the channel structure; a gate electrode surrounding the gate dielectric layer; and a word line surrounding the gate electrode.

[0014] In some embodiments, the gate dielectric layer has a linear cross-sectional profile.

[0015] In some embodiments, the gate dielectric layer extends vertically from the top surface of the capacitor.

[0016] In some embodiments, a bottom surface of the gate dielectric layer is lower than a bottom surface of the gate electrode.

[0017] In some embodiments, a top surface of the gate dielectric layer is higher than a top surface of the gate electrode.

[0018] In some embodiments, a dielectric layer is further included that contacts one sidewall of the gate dielectric layer.

[0019] In some embodiments, the channel structure is made of an oxide semiconductor material.

[0020] In some embodiments, the channel structure is made of indium gallium zinc oxide (IGZO).

[0021] In some embodiments, the gate electrode has an annular top profile.

[0022] In some embodiments, the character line has a strip-shaped top profile. Simple Explanation of the Diagram

[0023] When read with reference to the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a schematic diagram of a memory array according to an embodiment of this disclosure. Figure 2 is a schematic diagram of a memory cell according to an embodiment of this disclosure. Figure 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figures 4A to 21B are schematic diagrams of different steps in a method for manufacturing a semiconductor device according to embodiments of this disclosure. Figures 22A to 23B are schematic diagrams of different steps in a method for manufacturing a semiconductor device according to embodiments of this disclosure. Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0026] As used herein, "approximately," "about," "roughly," or "substantially" can generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms "approximately," "about," "roughly," or "substantially" can be inferred. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and can decrease or vary as integrated circuits shrink in size.

[0027] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit this disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including," when used in this specification, designate the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence of said features, integrals, steps, operations, elements, and / or components.

[0028] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized exemplary embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations due to manufacturing processes. For example, an injection area illustrated as rectangular will typically have circular or curved features and / or an injection concentration gradient at its edges, rather than a binary variation from the injection area to the non-injection area. Similarly, a buried area formed through injection can result in some injection in the area between the buried area and the surface through which injection is carried out. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device and are not intended to limit the scope of this disclosure.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0030] The exemplary embodiments will now be explained in detail with reference to the accompanying drawings.

[0031] Figure 1 is a schematic diagram of a memory array according to a partial embodiment of this disclosure. In some embodiments, the memory array 10 includes a plurality of memory cells 11 arranged in a rectangular matrix. Figure 1 shows a simple example of a 4×4 cell matrix. Other memory matrices may have thousands of cells in height and width. In some embodiments, the memory array 10 may be dynamic random-access memory (DRAM).

[0032] Each row of memory cells 11 is connected by word lines 20, and each column of memory cells 11 is connected by bit lines 30. The word lines 20 can extend horizontally. The word lines 20 are parallel to each other. Furthermore, the word lines 20 can be spaced apart from each other at substantially equal intervals.

[0033] On the other hand, bit lines 30 can extend vertically. Similar to word lines 20, bit lines 30 are parallel to each other and can be spaced apart from each other at substantially equal intervals.

[0034] Figure 2 is a schematic diagram of a memory cell according to a partial embodiment of this disclosure. Specifically, Figure 2 is a close-up view of Figure 1. In some embodiments, the memory cell 11 includes a transistor 11T and a storage capacitor 11C electrically connected to the transistor 11T. In some embodiments, the transistor 11T is an NMOS transistor and is configured to control the channel to the memory cell 11 by turning the gate of the transistor 11T on or off.

[0035] In some embodiments, the storage capacitor 11C is configured to store information based on the state of the charge stored therein. A storage capacitor 11C in an empty state (i.e., not charged) is represented as a logic value of 0. A storage capacitor 11C in a fully charged state is represented as a logic value of 1. The memory cell 11 uses the two extreme charge states stored in the storage capacitor 11C to store one bit of data. In some embodiments, a word line 20 connected to the access transistor 11T is used to control the gate of the access transistor 11T by applying a voltage to the gate of the access transistor 11T. In some embodiments, a bit line 30 is perpendicular to the arrangement of the word line 20 and is also connected to the access transistor 11T. When the gate of the access transistor 11T is turned on, the access transistor 11T connects the storage capacitor 11C to the bit line 30, such that the logic value stored in the storage capacitor 11C is read on the bit line 30.

[0036] Figure 3 is a flowchart of a method for manufacturing a semiconductor device according to a partial embodiment of the present disclosure. Figures 4A to 21B are schematic diagrams of different steps of the method for manufacturing a semiconductor device according to a partial embodiment of the present disclosure. Specifically, Figures 4A to 21A are cross-sectional views along line A-A' of the top view of Figures 4B to 21B.

[0037] The manufacturing method M50 in Figure 3 can be applied to a semiconductor device. The semiconductor device and manufacturing method M50 will be discussed together with Figures 4A to 21B. As shown in Figure 3, the manufacturing method M50 may include the following operations S100, S200, S300, S400, S500, S600, S700, S800, S900, S1000, S1100, S1200, S1300, S1400, S1500, S1600, S1700, and S1800.

[0038] This document provides various operations of the embodiments. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. Alternative orderings will be understood to benefit from this description. Furthermore, it should be understood that not all operations must exist in every embodiment provided herein. Moreover, it should be understood that not all operations are necessary in some embodiments.

[0039] Method M50 begins with operation S100, forming capacitors in the first and second dielectric layers, and depositing third and fourth dielectric layers on the capacitors. Referring to Figures 4A and 4B, the first dielectric layer 100 and the second dielectric layer 200 are sequentially deposited on a substrate (not shown), and a plurality of capacitors 300 are formed in the first dielectric layer 100 and the second dielectric layer 200. Then, the third dielectric layer 400 and the fourth dielectric layer 500 are sequentially deposited on the second dielectric layer 200, covering the capacitors 300.

[0040] In some embodiments, a first dielectric layer 100 is deposited on a substrate (not shown). In some embodiments, the first dielectric layer 100 is configured to provide electrical isolation between capacitors 300 formed in subsequent steps. The first dielectric layer 100 is made of a dielectric material. In some embodiments, the first dielectric layer 100 is made of silicon oxide (such as SiO2).

[0041] The first dielectric layer 100 can be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD) or other suitable deposition processes.

[0042] In some embodiments, a second dielectric layer 200 is deposited on a first dielectric layer 100. In some embodiments, the second dielectric layer 200 is configured to provide electrical isolation between capacitors 300 formed in subsequent steps. The second dielectric layer 200 is made of a dielectric material. In some embodiments, the first dielectric layer 100 and the second dielectric layer 200 are made of different dielectric materials. In some embodiments, the second dielectric layer 200 is made of silicon nitride (SiN).

[0043] The second dielectric layer 200 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the second dielectric layer 200 can be less than the vertical thickness of the first dielectric layer 100.

[0044] In some embodiments, the first dielectric layer 100 and the second dielectric layer 200 may be patterned to form openings. A mask pattern (not shown) may be formed on the second dielectric layer 200. Subsequently, the first dielectric layer 100 and the second dielectric layer 200 are etched through the mask pattern to form openings. In some embodiments, after etching, groups of the first dielectric layer 100 and the second dielectric layer 200 may be separated from each other through openings, wherein each opening extends vertically from an underlying structure in the substrate (not shown) and is parallel to each other. In some embodiments, the openings may be arranged horizontally at substantially equal intervals.

[0045] Next, capacitors 300 can be formed into the openings. In other words, capacitors 300 replace each opening. In some embodiments, capacitors 300 are parallel to each other and can be arranged regularly at substantially equal intervals.

[0046] The capacitor 300 may include a bottom electrode, a capacitor dielectric layer above the bottom electrode, and a top electrode above the capacitor dielectric layer. In some embodiments, the bottom electrode and the top electrode of the capacitor 300 may include a conductive material. In some embodiments, the bottom electrode and the top electrode may include a metal. In some embodiments, the bottom electrode and the top electrode may include titanium nitride (TiN). In some embodiments, the capacitor dielectric layer of the capacitor 300 may include a dielectric material. The bottom electrode, the capacitor dielectric layer, and the top electrode of the capacitor 300 may be deposited sequentially using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0047] The capacitor 300 can be planarized to make it flush with the second dielectric layer 200. With its surface lowered, the capacitor 300 and the second dielectric layer 200 are coplanar, thus sharing the same top surface. That is, the top surface of the capacitor 300 and the top surface of the second dielectric layer 200 can be connected to each other. A chemical mechanical polishing (CMP) process can be used for the planarization process. The CMP process can be stopped when the second dielectric layer 200 is exposed.

[0048] Next, a third dielectric layer 400 may be deposited on the capacitor 300 and the second dielectric layer 200. In some embodiments, the third dielectric layer 400 covers the capacitor 300. The third dielectric layer 400 is configured to provide electrical isolation between conductive structures (e.g., word lines) to be formed in subsequent steps. In some embodiments, a portion of the third dielectric layer 400 also serves as a sacrificial structure for conductive structures (e.g., channels) to be formed in subsequent steps.

[0049] The third dielectric layer 400 is made of a dielectric material. In some embodiments, the third dielectric layer 400 and the first dielectric layer 100 are made of the same material. In some embodiments, the third dielectric layer 400 is made of silicon dioxide (SiO2). The third dielectric layer 400 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD or other suitable deposition processes.

[0050] In some embodiments, a fourth dielectric layer 500 is deposited on top of a third dielectric layer 400. The fourth dielectric layer 500 is made of a dielectric material. In some embodiments, the fourth dielectric layer 500 and the second dielectric layer 200 are made of the same material. In some embodiments, the fourth dielectric layer 500 is made of silicon nitride (SiN). The fourth dielectric layer 500 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the fourth dielectric layer 500 can be greater than the vertical thickness of the third dielectric layer 400.

[0051] Method M50 proceeds to operation S200, where the fourth dielectric layer is patterned to define a dummy channel structure. Referring to Figures 5A and 5B, the fourth dielectric layer 500 can be patterned to define the dummy channel structure 502. A mask pattern (not shown) can be formed on the fourth dielectric layer 500. Subsequently, the fourth dielectric layer 500 is etched through the mask pattern.

[0052] In some embodiments, operation S200 may include photolithography. In some embodiments, a mask pattern is formed on a fourth dielectric layer 500 directly above the capacitor 300. Therefore, the portion of the fourth dielectric layer 500 overlapping with the capacitor 300 may not be etched during the etching process, and a dummy channel structure 502 may be defined after the etching process.

[0053] In some embodiments, each dummy channel structure 502 may overlap with a corresponding capacitor 300. In some embodiments, the dummy channel structure 502 is configured to act as a placeholder for a channel structure to be formed in a subsequent step.

[0054] Method M50 proceeds to operation S300, where a pad layer is deposited on the dummy channel structure and the third dielectric layer. Referring to Figures 6A and 6B, a pad layer 600 is deposited on the dummy channel structure 502 and the third dielectric layer 400.

[0055] In some embodiments, the padding layer 600 extends from the top surface of the third dielectric layer 400 to the dummy channel structure 502 and covers the top and sidewalls of the dummy channel structure 502.

[0056] The liner layer 600 may be made of a dielectric material. In some embodiments, the liner layer 600 is made of the same material as the third dielectric layer 400 or the first dielectric layer 100. In some embodiments, the liner layer 600 is made of silicon dioxide (SiO2). The liner layer 600 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD or other suitable deposition processes.

[0057] Method M50 proceeds to operation S400, where gate electrode material is deposited on the liner layer. Referring to Figures 7A and 7B, gate electrode material 700 is deposited on the liner layer 600. In some embodiments, the gate electrode material 700 extends from the top surface of the liner layer 600 and covers the liner layer 600.

[0058] The gate electrode material 700 may be made of a conductive material. In some embodiments, the gate electrode material 700 may include a metal. In some embodiments, the gate electrode material 700 may include titanium nitride (TiN). The gate electrode material 700 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0059] Method M50 proceeds to operation S500, where word line material is deposited on the gate electrode material. Referring to Figures 8A and 8B, word line material 800 is deposited on the gate electrode material 700.

[0060] The character line material 800 can be made of a conductive material. In some embodiments, the character line material 800 may include a metal. In some embodiments, the character line material 800 may include tungsten (W). The character line material 800 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0061] In some embodiments, a planarization process can be performed on the character line material 800 to expose the top surface of the gate electrode material 700. The planarized character line material 800 and the gate electrode material 700 are coplanar and therefore share the same top surface. That is, the top surfaces of the character line material 800 and the gate electrode material 700 can be connected to each other. A chemical mechanical polishing (CMP) process can be used for the planarization process.

[0062] Method M50 proceeds to operation S600, where the character line material is etched back. Referring to Figures 9A and 9B, the character line material 800 is etched back to reduce the top surface of the character line material 800. As a result, portions of the gate electrode material 700 and the dummy channel structure 502 can protrude from the etched top surface of the character line material 800.

[0063] Method M50 proceeds to operation S700, where a hard mask structure is deposited on the character line material. Referring to Figures 10A and 10B, a hard mask structure 900 is deposited on the exposed portions of the character line material 800 and the gate electrode material 700.

[0064] In some embodiments, the hard mask structure 900 may include a first hard mask layer 901, a second hard mask layer 902, and a third hard mask layer 903. The first hard mask layer 901, the second hard mask layer 902, and the third hard mask layer 903 may be deposited sequentially using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0065] In some embodiments, a first hard masking layer 901 is deposited on the character line material 800 and covers the exposed portion of the gate electrode material 700. In some embodiments, the first hard masking layer 901 may be an underlayer film.

[0066] In some embodiments, a second hard masking layer 902 is deposited on a first hard masking layer 901. In some embodiments, the second hard masking layer 902 is made of a dielectric material. In some embodiments, the second hard masking layer 902 may include carbon. In some embodiments, the second hard masking layer 902 may include amorphous carbon (α-carbon).

[0067] In some embodiments, a third hard mask layer 903 is deposited on the second hard mask layer 902. In some embodiments, the third hard mask layer 903 may be a dielectric anti-reflection coating (DARC) layer. In some embodiments, the third hard mask layer 903 may include silicon. In some embodiments, the third hard mask layer 903 may be silicon oxynitride (SiO₂xN₂y) or any suitable anti-reflective material layer. In some embodiments, the third hard mask layer 903 is configured to reduce reflectivity during photoresist patterning. Additionally, an organic anti-reflective coating (not shown) may be selectively used over the third hard mask layer 903 to enhance photoresist performance.

[0068] Method M50 proceeds to operation S800, where a patterned photoresist is formed on the hard mask structure. Referring to Figures 11A and 11B, a patterned photoresist 1000 is formed on the hard mask structure 900. A photoresist material layer (not shown) can be formed on the hard mask structure 900 using a suitable deposition process (such as spin coating). The photoresist material layer is then exposed to a light source through a photomask (not shown) with a specific pattern. In some embodiments, regions of the photoresist material layer become soluble upon exposure to light. As a result, the exposed regions of the photoresist material layer can be washed away to define the patterned photoresist 1000.

[0069] In some embodiments, the patterned photoresist 1000 may be located above the hard mask structure 900 above the dummy channel structure 502. The patterned photoresist 1000 is configured to act as an etch protector for the lower hard mask structure 900 above the dummy channel structure 502 in subsequent etching processes.

[0070] In some embodiments, the patterned photoresist 1000 may also be located above the hard mask structure 900 above the character line material 800. The patterned photoresist 1000 is also configured to act as an etch protector for the lower hard mask structure 900 above the character line material 800 in subsequent etching processes.

[0071] Method M50 proceeds to operation S900, where a hard mask structure is etched through photoresist. Referring to Figures 12A and 12B, the hard mask structure 900 is etched through photoresist 1000. In some embodiments, the hard mask structure 900 above the dummy channel structure 502 and the character line material 800 can be protected from the effects of the etching process by the photoresist 1000.

[0072] In some embodiments, the etching process is configured to etch the hard mask structure 900 and may leave other exposed materials (e.g., gate electrode material 700 and word line material 800) with little or no etching. In some embodiments, the etching process may include certain etchants for etching the hard mask structure 900, such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), or oxygen (O2).

[0073] In some embodiments, the photoresist 1000 may be removed after the etching process. In some embodiments, the removal of the photoresist 1000 includes a liquid resist stripper (not shown) that chemically alters the photoresist 1000 so that it no longer adheres to the hard mask structure 900.

[0074] In some embodiments, the removal of photoresist 1000 exposes a third hard mask layer 903. In some embodiments, the third hard mask layer 903 may be removed during or after the removal of photoresist 1000, exposing a second hard mask layer 902. In some embodiments, the remaining hard mask structure 900 includes a first hard mask layer 901 and a second hard mask layer 902.

[0075] In method M50, operation S1000 is performed, where spacers are formed along the hard shield structure and the gate electrode material. Referring to Figures 13A and 13B, a plurality of spacers 1100 are formed along the sidewalls of the hard shield structure 900 and the sidewalls of the gate electrode material 700.

[0076] In some embodiments, spacer 1100 is made of a dielectric material. In some embodiments, spacer 1100 is made of the same material as liner 600, third dielectric layer 400, or first dielectric layer 100. In some embodiments, spacer 1100 is made of silicon dioxide (SiO2).

[0077] In some embodiments, a spacer capping layer (not shown) may be formed over an underlying structure (e.g., hard mask structure 900, gate electrode material 700, and word line material 800). The spacer capping layer may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The spacer capping layer is then subjected to an anisotropic etching process to remove the horizontal portions of the spacer capping layer, leaving only the vertical portions. The remaining vertical portions are referred to as spacers 1100.

[0078] Method M50 proceeds to operation S1100, where character line material is etched through the spacer and hard mask structure. Referring to Figures 14A and 14B, character line material 800 is etched using spacer 1100 and hard mask structure 900 as an etching mask to form a plurality of character lines 802. In some embodiments, character lines 802 have a striped top profile.

[0079] Method M50 proceeds to operation S1200 by removing the hard mask structure. Referring to Figures 15A and 15B, the hard mask structure 900 and spacers 1100 are removed along the sidewalls of the hard mask structure 900. In some embodiments, a suitable etching process can be used to remove the hard mask structure 900. As a result, portions of the word lines 802 can be exposed. As shown in the top view of Figure 15B, each word line 802 can extend along a first direction and can connect to the gate electrodes 702 in the same column along the first direction. The word lines 802 are arranged along a second direction perpendicular to the first direction and can be parallel to each other.

[0080] Method M50 proceeds to operation S1300 via the etch-back gate electrode. Referring to Figures 16A and 16B, a portion of the etch-back gate electrode 702 is shown. Specifically, the top horizontal portion and the upper vertical portion of the etch-back gate electrode 702 are shown.

[0081] In some embodiments, the etching process of operation S1300 is configured to etch the material of the gate electrode 702 until the pad layer 600 is exposed. In some embodiments, the etching process of operation S1300 may also remove a small portion of the spacer 1100.

[0082] In some embodiments, after the etching process of operation S1300, the gate electrode 702 has an annular top profile. In some embodiments, the top surface of the gate electrode 702 is at a higher level than the top surface of the character line 802 and lower than the top surface of the dummy channel structure 502.

[0083] Method M50 proceeds to operation S1400 by refilling the fifth dielectric layer. Referring to Figures 17A and 17B, the fifth dielectric layer 1200 is deposited and refilled on top of the liner layer 600, spacer 1100, gate electrode 702, dummy channel structure 502, and word line 802.

[0084] In some embodiments, the fifth dielectric layer 1200 is made of a dielectric material. In some embodiments, the fifth dielectric layer 1200 is made of the same material as the spacer 1100, the pad layer 600, the third dielectric layer 400, or the first dielectric layer 100. In some embodiments, the fifth dielectric layer 1200 is made of silicon dioxide (SiO2).

[0085] In some embodiments, the fifth dielectric layer 1200 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The fifth dielectric layer 1200 may then be planarized (e.g., CMP process) to remove excess portions of the fifth dielectric layer 1200 on top of the dummy channel structure 502, thereby making the fifth dielectric layer 1200 flush with the dummy channel structure 502. In some embodiments, the planarization process may be stopped when the dummy channel structure 502 is exposed.

[0086] Method M50 proceeds to operation S1500 by removing the dummy channel structure. Referring to Figures 18A and 18B, the dummy channel structure 502 is removed and an opening 1300 is formed in each gate electrode 702.

[0087] In some embodiments, an etching process is performed to remove the dummy channel structure 502. In some embodiments, the etching process is a wet immersion process. In some embodiments, the etching process is configured to remove material from the dummy channel structure 502. In some embodiments, the etching process may also remove the padding layer 600. In some embodiments, an opening 1300 is formed to replace the dummy channel structure 502.

[0088] Method M50 proceeds to operation S1600 by removing the third dielectric layer. Referring to Figures 19A and 19B, a portion of the third dielectric layer 400 on top of the capacitor 300 is removed.

[0089] In some embodiments, an etching process is performed to remove the third dielectric layer 400 on top of the capacitor 300. In some embodiments, the top surface of the capacitor 300 is exposed in the opening 1300.

[0090] In some embodiments, the fifth dielectric layer 1200 may also be etched during an etching process. In other words, the etching process removes a portion of the fifth dielectric layer 1200. In some embodiments, the etching process may remove a portion of the fifth dielectric layer 1200, but leave a small portion of the fifth dielectric layer 1200 on the gate electrode 702 intact. In other words, the etching process does not expose the gate electrode 702.

[0091] In step M50, operation S1700 is performed, where a gate dielectric layer is formed on the sidewall of the opening. Referring to Figures 20A and 20B, a gate dielectric layer 1400 is formed on the sidewall of the opening 1300. Specifically, the gate dielectric layer 1400 extends upward from the capacitor 300 and along the sidewall of the opening 1300.

[0092] In some embodiments, the gate dielectric layer 1400 is made of a dielectric material. In some embodiments, the gate dielectric layer 1400 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. In some embodiments, the gate dielectric layer 1400 is configured to electrically separate the gate electrode 702 and the conductive structure (e.g., channel structure) to be formed in subsequent steps.

[0093] In some embodiments, a gate dielectric capping layer (not shown) may be formed over an underlying structure (e.g., a fifth dielectric layer 1200 and a capacitor 300). The gate dielectric capping layer may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. An etching process is then performed on the gate dielectric capping layer to remove the horizontal portion of the gate dielectric capping layer, leaving only the vertical portion of the gate dielectric capping layer retained along the sidewalls of the opening 1300. The remaining vertical portion is referred to as the gate dielectric layer 1400.

[0094] In some embodiments, the top of the gate dielectric layer 1400 may be substantially flush with the top surface of the fifth dielectric layer 1200. In some embodiments, the top surface of the gate dielectric layer 1400 is higher than the top surface of the gate electrode 702.

[0095] In some embodiments, the bottom surface of the gate dielectric layer 1400 is lower than the bottom surface of the gate electrode 702. In some embodiments, the gate dielectric layer 1400 extends vertically from the top surface of the capacitor 300. In some embodiments, the gate dielectric layer 1400 has a linear cross-sectional profile. In some embodiments, the fifth dielectric layer 1200 contacts the sidewall of the gate dielectric layer 1400.

[0096] Method M50 proceeds to operation S1800, forming a channel structure in the opening. Referring to Figures 21A and 21B, a channel structure 1500 is formed in the opening 1300. Specifically, the channel structure 1500 is formed on the capacitor 300 and surrounded by a gate dielectric layer 1400.

[0097] In some embodiments, a channel layer (not shown) may be formed over an underlying structure (e.g., a fifth dielectric layer 1200, a gate dielectric layer 1400, and a capacitor 300). The channel layer may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. Planarization (e.g., CMP) may then be performed on the channel layer to remove excess portion of the channel layer on top of the fifth dielectric layer 1200 and to flush the channel layer with the fifth dielectric layer 1200. In some embodiments, planarization may be stopped when the fifth dielectric layer 1200 is exposed. The remaining portion of the channel layer is referred to as channel structure 1500.

[0098] In some embodiments, the channel structure 1500 extends vertically from the capacitor 300. In some embodiments, the channel structure 1500 has a vertical length substantially the same as that of the gate dielectric layer 1400. In some embodiments, the channel structure 1500 may be electrically connected to the underlying capacitor 300. In some embodiments, a bitline structure (not shown) may be located above the channel structure 1500.

[0099] In some embodiments, channel structure 1500 may include an oxide semiconductor (OS) material. In some embodiments, channel structure 1500 may include indium gallium zinc oxide (IGZO). In some embodiments, channel structure 1500 may include a stacked nanowire structure configured to allow current to flow out of plane (e.g., vertically). Vertical channel structure 1500 can increase the storage cell density in semiconductor device 50.

[0100] In some embodiments, the channel structure 1500 may be covered by the gate electrode 702 through the gate dielectric layer 1400. In other words, the gate electrode 702, the gate dielectric layer 1400, and the channel structure 1500 may form a ring gate (GAA) configuration. Because it is fully gated, the channel structure 1500 has maximized the contact surface and therefore maximizes the current flowing through the gate dielectric layer 1400 and the gate electrode 702. Therefore, compared to a planar channel structure, the gate electrode 702 can have higher switching speeds and better control of the ring gate channel structure 1500.

[0101] Figures 22A to 23B are schematic diagrams illustrating different steps of a method for manufacturing a semiconductor device according to embodiments of this disclosure. Referring to Figures 22A and 22B, which are similar to Figures 18A and 18B, the embodiments in Figures 22A and 22B differ from those in Figures 18A and 18B in that, in the embodiments of Figures 22A and 22B, an etching process is performed to remove both the dummy channel structure 502 and a portion of the gate electrode 702 to expose the sidewalls of the word line 802.

[0102] In some embodiments, the exposed character line 802 can be used as a gate electrode to control the channel structure to be formed in subsequent processes. In some embodiments, an opening 1300 is formed to replace the removed portions of the dummy channel structure 502 and the gate electrode 702.

[0103] The structures in Figures 22A and 22B can undergo the same process as discussed in Figures 19A and 21B, with the resulting structures shown in Figures 23A and 23B. In the embodiments of Figures 23A and 23B, the channel structure 1500 can extend vertically from the capacitor 300.

[0104] In some embodiments, the gate dielectric layer 1400 may extend vertically from the second dielectric layer 200. In some embodiments, the gate dielectric layer 1400 may contact the sidewalls of the spacer 1100, the sidewalls of the word line 802, and the sidewalls of the gate electrode 702. In some embodiments, the top surface of the gate dielectric layer 1400 may be higher than the top surface of the word line 802. In some embodiments, the gate electrode 702 may extend from the bottom surface of the word line 802. In some embodiments, the word line 802 may be used as a gate electrode to control the channel structure 1500.

[0105] In summary, this invention provides a method for manufacturing a vertical ring gate structure, which facilitates component miniaturization. Furthermore, this disclosure provides a method for forming a channel structure by creating a dummy channel structure and then replacing the dummy channel structure with a channel structure. Therefore, the channel structure can be formed in a self-aligned manner and can achieve a good shape, thereby improving device performance.

[0106] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0107] 10: Memory Array 11: Memory Unit 11C: Storage capacitor 11T: Access Transistor 20: Character Line 30: Bit line 100: First dielectric layer 200: Second dielectric layer 300: Capacitor 400: Third dielectric layer 500: Fourth dielectric layer 502: Virtual channel structure 600: Padding layer 700: Gate electrode material 702: Gate electrode 800: Character Line Material 802: Character Line 900: Hard mask structure 901: First hard mask layer 902: Second hard mask layer 903: Third hard mask layer 1000: Optical Resist 1100: Spacer 1200: Fifth dielectric layer 1300: Opening 1400: Gate dielectric layer 1500: Channel Structure M50: Method S100: Operation S200: Operation S300: Operation S400: Operation S500: Operation S600: Operation S700: Operation S800: Operation S900: Operation S1000: Operation S1100: Operation S1200: Operation S1300: Operation S1400: Operation S1500: Operation S1600: Operation S1700: Operation S1800: Operation

[0108] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor device, comprising: This creates a virtual channel structure; A gate electrode is formed around the dummy channel structure, wherein the gate electrode has an annular top profile; A word line is formed around the gate electrode; the dummy channel structure is removed to form an opening; a gate dielectric layer is formed in the opening; and a channel structure is formed in the opening.

2. The method as described in claim 1, wherein the dummy channel structure overlaps with a capacitor.

3. The method as described in claim 2 further includes forming a dielectric layer on the capacitor, wherein the dummy channel structure is formed on the dielectric layer.

4. The method as described in claim 2, wherein the opening exposes the capacitor.

5. The method as described in claim 2, wherein the gate dielectric layer extends vertically from the capacitor and along one sidewall of the opening.

6. The method as described in claim 1 further comprises etching back the gate electrode such that a top surface of the gate electrode is lower than a top surface of the dummy channel structure.

7. The method as described in claim 1, wherein a top surface of the character line is lower than a top surface of the gate electrode.

8. The method as described in claim 1, wherein forming the character line comprises: forming a character line material surrounding the dummy channel structure; forming a hard mask structure over the character line material; and etching the character line material through the hard mask structure to form the character line.

9. The method as described in claim 8, wherein the hard mask structure overlaps with the dummy channel structure.

10. The method as described in claim 8 further includes forming a spacer along one sidewall of the hard mask structure before etching the character line material.

11. A semiconductor device, comprising: A capacitor; A channel structure extends vertically from one of the top surfaces of the capacitor; A gate dielectric layer surrounds the channel structure; A gate electrode surrounding the gate dielectric layer, wherein the gate electrode has an annular top profile; and a word line surrounding the gate electrode.

12. The semiconductor device as claimed in claim 11, wherein the gate dielectric layer has a linear cross-sectional profile.

13. The semiconductor device as claimed in claim 11, wherein the gate dielectric layer extends perpendicularly from the top surface of the capacitor.

14. The semiconductor device as claimed in claim 11, wherein a bottom surface of the gate dielectric layer is lower than a bottom surface of the gate electrode.

15. The semiconductor device as claimed in claim 11, wherein a top surface of the gate dielectric layer is higher than a top surface of the gate electrode.

16. The semiconductor device as claimed in claim 11 further includes a dielectric layer in contact with a sidewall of the gate dielectric layer.

17. The semiconductor device as claimed in claim 11, wherein the channel structure is made of a material of oxide semiconductor.

18. The semiconductor device as claimed in claim 17, wherein the channel structure is made of indium gallium zinc oxide (IGZO).

19. The semiconductor device as claimed in claim 11, wherein the character line has a strip-shaped top profile.

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