Semiconductor device structure and methods of forming the same

Abstract

The embodiments disclosed herein provide a semiconductor device structure. The semiconductor device structure includes a device layer having a first side and a second side opposite to the first side, and a first interconnect structure disposed above the first side of the device layer. The first interconnect structure includes a first interconnect level layer and a second interconnect level layer disposed above the first interconnect level layer, wherein the second interconnect level layer includes a vertical array of a plurality of memory cell devices. The semiconductor device structure further includes a third interconnect level layer disposed above the second interconnect level layer.

Description

Technical Field

[0001] none Prior Technology

[0002] As the semiconductor industry develops to the nanometer technology process node in pursuit of higher device density and performance, there is a growing desire to integrate multifunctional logic circuits and non-volatile memory circuits onto a single chip. Due to the continuous reduction in device feature size, there is a need in the art for a semiconductor device structure capable of achieving these characteristics with high integration density. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The embodiments disclosed herein can be better understood through the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, according to standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased. Figure 1A illustrates an exemplary circuit diagram of a ferroelectric random access memory (RAM) circuit of the 1-transistor (1T) type according to some embodiments; Figure 1B illustrates a memory device array employing a plurality of 1T-type FeRAM circuits as shown in Figure 1A; Figures 2A to 2C are vertical cross-sectional views of exemplary semiconductor device structures according to some embodiments of the present disclosure; Figure 3A is a vertical cross-sectional view of an exemplary semiconductor device structure taken along plane AA of Figure 3C; Figure 3B is a vertical cross-sectional view of an exemplary semiconductor device structure taken along plane BB of Figure 3C; Figure 3C is a horizontal cross-sectional view of an exemplary semiconductor device structure according to some embodiments of the present disclosure; Figure 4A is a vertical cross-sectional view of an exemplary semiconductor device structure taken along plane AA of Figure 4C; Figure 4B is a vertical cross-sectional view of an exemplary semiconductor device structure taken along plane BB of Figure 4C; Figure 4C is a horizontal cross-sectional view of an exemplary semiconductor device structure according to some embodiments of the present disclosure; Figures 5 through 17 are vertical cross-sectional views of exemplary semiconductor device structures during various stages of manufacturing according to some embodiments of this disclosure; Figure 18 illustrates a schematic diagram of the layout design according to the embodiment in Figure 17; Figure 19 illustrates a schematic diagram of a layout design according to some embodiments of this disclosure; Figure 20 illustrates a vertical cross-sectional view of an exemplary semiconductor device structure according to some embodiments; Figures 21 through 28 are cross-sectional side views of various stages of manufacturing an exemplary semiconductor device structure according to some embodiments of the present disclosure; Figure 29 illustrates a cross-sectional side view of an exemplary semiconductor device structure according to some embodiments of the present disclosure; Figure 30 illustrates a cross-sectional side view of an exemplary semiconductor device structure according to some embodiments of the present disclosure; and Figure 30-1 illustrates an enlarged view of a portion of the semiconductor device structure shown in Figure 30 according to some embodiments of the present disclosure. Implementation

[0005] The following disclosure provides many different embodiments or examples of configurations to implement different features of the target. Specific examples of the components and settings are described below to simplify this disclosure. Of course, these are merely exemplary and are not intended to limit this disclosure. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may further include embodiments where an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Additionally, the reference numerals and / or letters in the figures may be repeated in various examples. Such repetition is for simplicity and clarity and is not in itself intended to limit the relationship between the various embodiments and / or configurations described.

[0006] Furthermore, this disclosure may use spatially relative terms such as "below," "under," "lower part," "above," "on," "above," "top," "upper part," etc. For ease of description, this disclosure may use these terms to describe the relationship between one element or feature and another element or feature in the accompanying drawings. In addition to the orientations depicted in the drawings, spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and therefore the spatially relative descriptive terms used in this disclosure may be interpreted accordingly.

[0007] The various embodiments disclosed herein relate to semiconductor device structures having memory cell arrays processed in a back-end-of-line (BEOL) architecture to improve device density and performance. Non-volatile memory technologies may include, for example, ferroelectric random-access memory (FeRAM), resistive random-access memory (RRAM or ReRAM), magnetoresistive random-access memory (MRAM), and phase-change memory (PCM). FeRAM devices are promising candidates for next-generation non-volatile memory technologies due to their fast write / read speeds, small size, low power consumption, and low manufacturing cost.

[0008] Figure 1A illustrates an exemplary circuit diagram of a 1-transistor (1T) type FeRAM circuit according to some embodiments. The 1T FeRAM circuit can be used as a capacitor or charge storage memory device to implement various embodiments of this disclosure. As shown in Figure 1A, the FeRAM circuit typically includes word lines (WL), bit lines (BL), source lines (SL), and a memory transistor (MT) having a gate (G) coupled to the word lines, a drain (D) coupled to the bit lines, and a source (S) coupled to the source lines (which may be grounded). Figure 1B illustrates an array of memory devices employing a plurality of 1T type FeRAM circuits as shown in Figure 1A. The select gate (SG) of the plurality of FeRAM circuits in a column is operatively coupled to the word lines WL1, WL2, ... and the control gate line. The plurality of FeRAM circuits in a row are operatively coupled to the bit lines BL1, BL2, ... and the source line. The gate can be controlled by a first voltage from the bit line, the drain can be controlled by a second voltage from the bit line, and the source can be controlled by a third voltage from the source line. In some embodiments, the source is grounded. In some embodiments, the drain is grounded.

[0009] As explained in more detail below, the FeRAM circuit can be configured as a vertical gate-all-around (GAA) transistor structure with the channel region completely surrounded by the gate (vertically positioned between the top source / drain components and the bottom source / drain components). A ferroelectric material layer can be disposed between the gate and the channel region. The ferroelectric material can maintain polarization without an external electric field. The polarization in the ferroelectric material exhibits a hysteresis effect, allowing data bits to be encoded with the polarization direction within the ferroelectric material. The polarization of the ferroelectric material can alter the threshold voltage of the FeRAM circuit by detecting changes in the gate threshold voltage. For example, when an external electric field is applied to the dielectric, the dipoles tend to align with the direction of the electric field due to minute changes in atomic positions and variations in the electron charge distribution within the ferroelectric material. After the charge is removed, the dipoles remain polarized. In a 1T FeRAM, the remaining polarization state affects the gate threshold voltage Vt, and when a voltage is applied, the current value changes according to the remaining polarization state, thereby storing / reading binary "0" and "1" data.

[0010] Figure 2A is a vertical cross-sectional view of an exemplary semiconductor device structure 100 after forming a complementary metal-oxide-semiconductor (CMOS) transistor, embedding a metal interconnect structure in a dielectric material layer, and forming a dielectric material layer with a connection-via-level, according to some embodiments of this disclosure. The exemplary semiconductor device structure 100 includes a substrate 8 containing a semiconductor material layer 10. The substrate 8 may include a bulk semiconductor substrate, such as a silicon substrate, wherein the semiconductor material layer 10 extends continuously from the top surface of the substrate 8 to the bottom surface of the substrate 8; or include an on-insulator semiconductor layer with the semiconductor material layer 10 as a top semiconductor layer covering a buried insulating layer. A shallow trench isolation structure 12 including a dielectric material (e.g., silicon oxide) may be formed in the upper portion of the substrate 8. Appropriately doped semiconductor wells (e.g., p-type and n-type wells) may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 12. Logic devices (e.g., CMOS transistors) may be formed above the top surface of the substrate 8. Each logic device may include source / drain regions 14, semiconductor channels 15 (including surface portions of substrate 8 extending between source / drain regions 14), and gate structures 20. Depending on the context, source / drain regions may refer individually or collectively to a source or a drain. In this disclosure, source and drain are used interchangeably and their structures are substantially the same. Each gate structure 20 may include a gate dielectric 22, a gate electrode strip 24, a gate cover dielectric 28, and a dielectric gate spacer 26. Optionally, source / drain metal-semiconductor alloy regions 18 may be formed on each source / drain region 14. Although planar field-effect transistors (FETs) are illustrated, some embodiments of this disclosure are also applicable to logic elements using other types of FET devices, such as three-dimensional fin FETs (FinFETs), gate-all-around (GAA) transistor devices (e.g., horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs), vertical FETs, forked FETs, or complementary FETs (CFETs). It will be understood by those skilled in the art that other modifications made through some embodiments of this disclosure are considered to be within the scope of this disclosure.

[0011] An exemplary semiconductor device structure 100 may include a memory array region 50 and a peripheral region 52, wherein an array of memory elements will subsequently be formed in the memory array region 50, and logic devices supporting the operation of the memory device array may be formed in the peripheral region 52. In one embodiment, the devices (e.g., field-effect transistors) in the memory array region 50 may include bottom electrode access transistors that provide access to the bottom electrodes of subsequently formed memory cells. In this process step, top electrode access transistors that provide access to the top electrodes of subsequently formed memory cells may be formed in the peripheral region 52. The devices (e.g., field-effect transistors) in the peripheral region 52 may provide functionality that may be needed to operate the subsequently formed memory cell array. Specifically, the devices in the peripheral region 52 may be configured to control programming operations, erase operations, and sensing (read) operations of the memory cell array. For example, the devices in the peripheral region 52 may include sensing circuitry and / or top electrode biasing circuitry. The devices formed on the top surface of the substrate 8 may include CMOS transistors and optional additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuit 75.

[0012] Subsequently, a plurality of interconnect level structures can be formed, referred to as lower interconnect level layers (L0, L1, L2). The lower interconnect level layers (L0, L1, L2) may include interconnect level layer L0, first interconnect level layer L1, and second interconnect level layer L2. The dielectric material layer may include, for example, a contact layer dielectric material layer 31A, a first metal-wire-layer dielectric material layer 31B, and a second metal-wire-layer dielectric material layer 32. The plurality of metal interconnect structures are then formed on the substrate 8 and the device (e.g., a field-effect transistor) to embed the device within the dielectric material layer. Various metal interconnect structures may include a device contact via structure 41V formed in the contact-layer dielectric material layer 31A (interconnect level layer L0) and contacting the corresponding component of the CMOS circuit 75, a first metal line structure 41L formed in the first metal-line-layer dielectric material layer 31B (interconnect level layer L1), a first metal via structure 42V formed in the lower part of the second metal-line-layer dielectric material layer 32, and a second metal line structure 42L formed in the upper part of the second metal-line-layer dielectric material layer 32 (interconnect level layer L2).

[0013] Each dielectric layer (31A, 31B, and 32) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each metal interconnect structure (41V, 41L, 42V, and 42L) may include at least one conductive material, which may be a combination of a metal pad layer (e.g., a metal nitride or metal carbide) and a metal filler material. Each metal pad layer may include TiN, TaN, WN, TiC, TaC, and WC, while each metal filler portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the disclosed intended scope may also be used. In one embodiment, the first metal via structure 42V and the second metal wire structure 42L may be formed as an integrated wire and via structure via a dual damascene process.

[0014] The dielectric material layers (31A, 31B, and 32) can be located at a lower level relative to the memory cell array to be subsequently formed. Therefore, the dielectric material layers (31A, 31B, and 32) are referred to in this disclosure as lower dielectric material layers, i.e., dielectric material layers located at a lower level relative to the subsequently formed memory cell array. The metal interconnect structures (41V, 41L, 42V, and 42L) are referred to in this disclosure as lower metal interconnect structures. A subset of the metal interconnect structures (41V, 41L, 42V, and 42L) includes lower metal lines (e.g., a third metal line structure 42L) embedded in the lower dielectric material layers, and the lower metal lines have a top surface located within a horizontal plane including the topmost surface of the lower dielectric material layer. Generally, the total number of metal line layers in the lower dielectric material layers (31A, 31B, and 32) can be between 1 and 5.

[0015] The exemplary semiconductor device structure 100 may include various device regions, and the device regions may include a memory array region 50, in which at least one non-volatile memory cell array may subsequently be formed. For example, the at least one non-volatile memory cell array may include ferroelectric random access memory (FeRAM), resistive random access memory (RRAM or ReRAM), magnetic / magnetoresistive random access memory (MRAM), and phase-change memory (PCM) devices, etc. The exemplary semiconductor device structure 100 may also include a peripheral logic region 52, in which electrical connections between each non-volatile memory cell array and peripheral circuitry including field-effect transistors may subsequently be formed. The regions of the memory array region 50 and the logic region 52 may be configured to form various means of peripheral circuitry.

[0016] In Figure 2B, an array 95 of non-volatile memory cells and / or ferroelectric memory cell devices is formed in the memory array region 50 above the second interconnect layer L2. The details of the structure and fabrication steps of the non-volatile ferroelectric memory cell array 95 will be described in detail below. A third interconnect dielectric material layer 33 may be formed during the formation of the array 95 of non-volatile ferroelectric memory cells. The collection of all structures formed in the layer of the array 95 of non-volatile memory cells and / or ferroelectric memory cell devices is hereby referred to as the third interconnect layer L3.

[0017] In Figure 2C, a third interconnect level metal interconnect structure (43V, 43L) can be formed in the third interconnect level dielectric material layer 33. The third interconnect level metal interconnect structure (43V, 43L) may include a second metal via structure 43V and a third metal line 43L. Subsequently, additional interconnect level layers can be formed, and are referred to in this disclosure as upper interconnect level layers (L4, L5, L6, L7). For example, the upper interconnect level layers (L4, L5, L6, L7) may include a fourth interconnect level layer L4, a fifth interconnect level layer L5, a sixth interconnect level layer L6, and a seventh interconnect level layer L7. The fourth interconnect level layer L4 may include a fourth interconnect level dielectric material layer 34 (in which a fourth interconnect level metal interconnect structure (44V, 44L) is formed), and the fourth interconnect level metal interconnect structure includes a third metal via structure 44V and a fourth metal line 44L. The fifth interconnect layer L5 may include a fifth interconnect dielectric material layer 35 (in which a fifth interconnect metal interconnect structure (45V, 45L) is formed), and the fifth interconnect metal interconnect structure includes a fourth metal via structure 45V and a fifth metal line 45L. The sixth interconnect layer L6 may include a sixth interconnect dielectric material layer 36 (in which a sixth interconnect metal interconnect structure (46V, 46L) is formed), and the sixth interconnect metal interconnect structure includes a fifth metal via structure 46V and a fifth metal line 46L. The seventh interconnect layer L7 may include a seventh interconnect dielectric material layer 37 (in which a seventh interconnect metal interconnect structure (47V, 47L) is formed), and the seventh interconnect metal interconnect structure includes a sixth metal via structure 47V and a sixth metal line 47L. Metal bonding pad 47B can be configured to be solder bonded (using C4 ball bonding or wire bonding), or C4 ball bonding or wire bonding fusion or hybrid bonding processes (e.g., insulator to insulator, metal to metal or insulator to metal bonding).

[0018] Each interconnect-level dielectric layer can be referred to as an interconnect-level dielectric (ILD) layer 30 (i.e., 31A, 31B, 32, 33, 34, 35, 36, and 37). Each interconnect-level metal interconnect structure can be referred to as a metal interconnect structure 40. Each consecutive combination of metal via structures and overlying metal lines located in the same interconnect level (L2 to L7) can be sequentially formed into two interconnect levels. Different structures can be formed by using two single damascene processes, or a single structure can be formed simultaneously by using a dual damascene process. Each metal interconnect structure 40 (i.e., 41V, 41L, 42V, 42L, 43V, 43L, 44V, 44L, 45V, 45L, 46V, 46L, 47V, and 47B) may include a corresponding metal pad (e.g., a layer of TiN, TaN, or WN) and a corresponding metal filler material (e.g., W, Cu, Co, Mo, Ru, other elemental metals, or alloys or combinations thereof). Various etch-stop dielectric material layers and dielectric capping layers can be inserted between vertically adjacent pairs of ILD layers 30, or can be incorporated into one or more ILD layers 30.

[0019] While one embodiment of this disclosure employs an array 95 of nonvolatile memory cells and / or ferroelectric memory cell devices formed as a component of a third interconnect layer L3, in other embodiments of this disclosure, it is explicitly contemplated that the array 95 of nonvolatile memory cells and / or ferroelectric memory cell devices can be formed as a component of any other interconnect layer (e.g., L1-L7). Furthermore, while this disclosure is described in one embodiment by way of forming a set of eight interconnect layers, it is explicitly contemplated that embodiments using different numbers of interconnect layers are possible. Moreover, some embodiments of this disclosure explicitly contemplate embodiments in which two or more arrays 95 of nonvolatile memory cells and / or ferroelectric memory cell devices can be provided in a plurality of interconnect layers within the memory array region 50. Furthermore, while one embodiment of this disclosure describes an array 95 of non-volatile memory cells and / or ferroelectric memory cell devices that can be formed in a single interconnect layer, in other embodiments of this disclosure, it is explicitly contemplated that an array 95 of non-volatile memory cells and / or ferroelectric memory cell devices can be formed over two vertically adjacent interconnect layers.

[0020] Figure 3C is a horizontal cross-sectional view of an exemplary semiconductor device structure 200 after etching and patterning metal line trenches in a first dielectric material layer according to an embodiment of the present disclosure. Figure 3A is a vertical cross-sectional view of the exemplary semiconductor device structure 200 taken along plane BB of Figure 3C. Figure 3B is a vertical cross-sectional view of the exemplary semiconductor device structure 200 taken along plane AA of Figure 3C. The exemplary semiconductor device structure 200 may be fabricated to include a plurality of vertical gate full-loop devices, each of which may be configured as a capacitor or charge storage memory device. Referring to Figures 3A through 3C, a first dielectric material layer 120 may be deposited on a substrate 110. The substrate 110 may be any suitable substrate, such as a semiconductor device substrate. In other embodiments, the substrate 110 may be a second or third interconnect dielectric material 32, 33, as shown in Figure 2C. In some embodiments, the substrate 110 may be the substrate 2101 discussed in Figures 21 through 28 described later. The first dielectric layer 120 may include dielectric materials such as silicon oxide (SiO2), undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. The first dielectric layer 120 may be deposited or grown over the ILD layer 30 using any of a plurality of suitable deposition processes. A photoresist layer (not shown) may be applied over the first dielectric layer 120 and may be patterned to form trenches 121 in regions of the first dielectric layer 120 where metal lines will subsequently form. For example, the photoresist pattern may be formed by depositing photoresist and then patterning the deposited photoresist using photolithography. The patterned photoresist may cover portions of the first dielectric layer 120 to protect these portions during a subsequent etching process. An etching process is then performed to form the metal line trenches 121 in the first dielectric layer 120. For example, wet etching, dry etching, or a combination thereof may be used to etch the first dielectric layer 120. In one embodiment, each metal trench 121 may be located in the upper portion of the first dielectric material layer 120. The metal trenches 121 may extend laterally along a first horizontal direction hd1 and may be laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The photoresist can then be removed by, for example, ashing or chemical processing.

[0021] Figure 4C is a horizontal cross-sectional view of an exemplary semiconductor device structure 200 after depositing and planarizing conductive metal material in a metal wire trench to form a metal wire, according to an embodiment of the present disclosure. Figure 4A is a vertical cross-sectional view of the exemplary semiconductor device structure 200 taken along plane AA of Figure 4C. Figure 4B is a vertical cross-sectional view of the exemplary semiconductor device structure 200 taken along plane BB of Figure 4C. Referring to Figures 4A to 4C, a metal wire 122 can be formed in the metal wire trench 121. An electrically conductive material can be deposited over a first dielectric material layer 120 to fill the metal wire trench 121. The metal wire 122 can be formed of an electrically conductive metal material, such as copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, or alloys thereof. The metal line 122 can be formed by depositing a conductive material layer through any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), plasma-enhanced CVD (PECVD), or sputtering.

[0022] Then, a planarization process, such as chemical mechanical polishing (CMP), can be performed to remove excess electrically conductive metal material from the surface of the first dielectric layer 120 and to make the top surface of the metal line 122 coplanar with the top surface of the first dielectric layer 120. In one embodiment, each metal line 122 may be located in the upper part of the first dielectric layer 120. The metal lines 122 may extend laterally along a first horizontal direction hd1 and may be laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In some embodiments, one or more metal lines 122 may be grounded. When the substrate 2101 is configured as the substrate 2101 of Figures 21 to 28, the metal line 122 may be a conductive member 2198 connected to a conductive member 2197 configured as a power rail.

[0023] Figures 5 through 17 are vertical cross-sectional views of an exemplary semiconductor device structure 200 during various manufacturing stages according to some embodiments of the present disclosure, along a second horizontal direction hd2 (i.e., plane BB). In Figure 5, after the metal line 122 is formed, a first electrode layer 142L and a semiconductor channel material layer 140L are sequentially deposited over the metal line 122 and the substrate 110. The first electrode layer 142L may be patterned to form a bottom electrode. The bottom electrode may be configured as a source / drain electrode of a transistor or an electrode of a capacitor (e.g., a vertical GAA capacitor device), or configured as a charge storage memory device (e.g., a FeRAM memory cell). The first electrode layer 142L may be formed of an electrically conductive material, such as copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, or alloys thereof. The first electrode layer 142L may be formed by any suitable process, such as ALD, PVD, or electroplating. In one example, the first electrode layer 142L is titanium nitride formed through an ALD process.

[0024] The semiconductor channel material layer 140L may comprise polycrystalline silicon, amorphous silicon, or semiconductor oxides, such as InGaZnO (IGZO), indium tin oxide (ITO), InWO, InZnO, InSnO, GaOx, or InOx. In one embodiment, the semiconductor channel material layer 140L is formed of IGZO. Depending on the application requirements, the IGZO may be intrinsic or may contain dopants. The semiconductor material layer 140L is surrounded by a ferroelectric dielectric layer (e.g., ferroelectric dielectric layer 130L shown in Figure 8) and a gate electrode layer (e.g., electrode material layer 160L shown in Figure 8) to form a ferroelectric memory cell. The semiconductor material layer 140L may be deposited using any suitable deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, PECVD, or sputtering processes.

[0025] In Figure 6, the semiconductor channel material layer 140L and the first electrode layer 142L are patterned to form the semiconductor channel 140 and the bottom electrode 142. A mask layer (not shown) (e.g., photoresist) of a two-dimensional array can be deposited over the semiconductor channel material layer 140L and the first electrode layer 142L. A photolithography process is performed to transfer the pattern over the mask layer. Then, a portion of the semiconductor channel material layer 140L and the first electrode layer 142L is selectively removed by an etching process. By etching the unmasked portions of the semiconductor channel material layer 140L and the first electrode layer 142L, the semiconductor channel material layer 140L and the first electrode layer 142L are patterned to form a two-dimensional array of semiconductor channels 140 and bottom electrodes 142. Thus, each column of semiconductor channels 140 and bottom electrodes 142 is formed over the corresponding metal line 122.

[0026] The resulting semiconductor channel 140 and bottom electrode 142 can be in the form of an upright pillar, a continuously arranged column, nanowires, or a quadrilateral shape. As shown, the semiconductor channel 140 and bottom electrode 142 can be vertically aligned relative to the first dielectric material layer 120. In other words, the long axis of each semiconductor channel 140 and bottom electrode 142 can be perpendicular to the extended plane of the first dielectric material 120 and / or the underlying semiconductor substrate. After forming the semiconductor channel 140 and bottom electrode 142, the masking layer can be removed by ashing or any suitable process.

[0027] In Figure 7, a first etch stop layer 143 is selectively formed on the exposed surface of the first dielectric material 120. The first etch stop layer 143 may comprise a material different from the first dielectric material 120, and therefore, the first etch stop layer 143 has a different etching effect than the first dielectric material 120. In some embodiments, the first etch stop layer 143 is made of a dielectric material, such as oxides, nitrides, metal oxides, metal nitrides, or combinations thereof. Suitable materials for the first etch stop layer 143 may include, but are not limited to, silicon nitride, silicon carbide, oxygen-doped silicon carbide (ODC), silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, and aluminum oxide. Since both the first etch stop layer 143 and the first dielectric material 120 comprise dielectric materials, rather than semiconductor or metallic materials not used in the semiconductor channel 140 and the bottom electrode 142, the first etch stop layer 143 may be selectively formed on the first dielectric material 120. The first etch stop layer 143 may be a single layer or a multilayer structure comprising two or more layers of dielectric material as disclosed herein. In an exemplary embodiment, the first etch stop layer 143 is silicon oxynitride. The first etch stop layer 143 may be formed by any suitable process, such as CVD, ALD, PVD, PEALD, or PECVD. The first etch stop layer 143 may be deposited to a height such that the top surface of the first etch stop layer 143 is slightly higher than the interface height defined by the semiconductor channel 140 and the bottom electrode 142.

[0028] In Figure 8, the ferroelectric dielectric layer 130L and the electrode material layer 160L are sequentially formed above the two-dimensional array of the first etch stop layer 143 and the semiconductor channel 140. The ferroelectric dielectric layer 130L can be formed from any suitable ferroelectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), aluminum scandium nitride (AlScN), lead zirconium oxide (PbZrO3), Pb[ZrxTi1-x]O3, (0≤x≤1) (PZT), BaTiO3, PbTiO3, PbNb2O6, LiNbO3, LiTaO3, polyvinylidene fluoride (PVDF), potassium dihydrogen phosphate (KDP), PbMg1 / 3Nb2 / 3O3 (PMN), PbSc1 / 2Tal / Materials such as 2O3PbSc1 / 2Tal / 2O3 (PST), SrBi2Ta2O9 (SBT), Bil / 2Na1 / 2TiO3Bil / 2Nal / 2TiO3, or combinations thereof, can be used. Other dielectric materials, such as silicon oxide or high-k dielectric materials (e.g., materials with a dielectric constant greater than 3.9), can also be used. Suitable high-k dielectric materials include, but are not limited to, silicon nitride, hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (Hf0.5Zr0.5O2) (HZO), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), and hafnium dioxide-aluminum oxide (HfO2-Al2O3). In one example embodiment, the ferroelectric dielectric layer 130L is HZO. The ferroelectric dielectric layer 130L can be deposited through conformal deposition, such as ALD process or any suitable deposition process.

[0029] In Figure 9, portions of the ferroelectric dielectric layer 130L and electrode material layer 160L are patterned. An etch mask material (e.g., photoresist 177) of a two-dimensional array can be applied over the corresponding columns of electrode material layers 160L covering the semiconductor channels 140. The pattern can be transferred over the photoresist 177 by performing a lithography process. When the two-dimensional array of photoresist 177 is used as an etch mask to remove the unmasked portions of the ferroelectric dielectric layer 130L and electrode material layer 160L, the remaining portions of the ferroelectric dielectric layer 130L and electrode material layer 160L can be patterned to form a conformal layer structure surrounding each semiconductor channel 140. A portion of the first etch stop layer 143, the ferroelectric dielectric layer 130L, and the electrode material layer 160L are exposed.

[0030] In Figure 10, photoresist 177 is removed, and a first dielectric layer 170 is deposited on the exposed surfaces of the electrode material layer 160L, the ferroelectric dielectric layer 130L, and the first etch stop layer 143. The photoresist 177 can be removed by ashing or any suitable process. When the photoresist 177 is removed, portions of the electrode material layer 160L and the ferroelectric dielectric layer 130L may remain at the corners of the semiconductor channel 140 and the first etch stop layer 143, forming a footing extending laterally from the electrode material layer 160L and the ferroelectric dielectric layer 130L deposited on the sidewalls of the semiconductor channel 140. The first dielectric layer 170 may be formed of silicon oxide or any suitable dielectric material. In some embodiments, the first dielectric layer 170 is formed of the same material configured to form the first dielectric material layer 120. The first dielectric layer 170 can be deposited using any suitable deposition technique (e.g., CVD or PECVD), and the height of the first dielectric layer 170 is higher than the top surface of the electrode material layer 160L. After the first dielectric layer 170 is formed, a CMP process is performed to planarize the upper surface of the first dielectric layer 170. The CMP process can be performed until the electrode material layer 160L is exposed.

[0031] In Figure 11, an etch-back process is performed to remove a portion of the first dielectric layer 170. The etch-back process can be dry etching, wet etching, or a combination thereof. The etch-back process is a selective etching process, and the etch-back process removes the first dielectric layer 170 but does not remove the electrode material layer 160L. The etch-back process can be performed such that the top surface of the first dielectric layer 170 is slightly higher than the height above the bases of the electrode material layer 160L and the ferroelectric dielectric layer 130L (e.g., the electrode material layer 160L extends laterally from the electrode material layer 160L and the ferroelectric dielectric layer 130L deposited on the sidewalls of the semiconductor channel 140).

[0032] Following the etch-back process, a metal layer 171 is formed on the exposed surfaces of the first dielectric layer 170 and the electrode material layer 160L. The metal layer 171 is configured as a word line for a FeRAM memory cell. The metal layer 171 may comprise one or more layers of electrically conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. In one embodiment, the metal layer 171 is tungsten. The metal layer 171 may be formed using CVD, ALD, electroplating, or other suitable deposition techniques.

[0033] Then, the metal layer 171 is recessed through an etch-back process (e.g., dry etching, wet etching, or a combination thereof). The etch-back process can be performed such that the top surface of the metal layer 171 is lower than the top surface of the semiconductor channel 140. The etch-back process is a selective etching process that removes the metal layer 171 but not the electrode material layer 160L.

[0034] In Figure 12, an etch-back process is performed to remove portions of the electrode material layer 160L and the ferroelectric dielectric layer 130L. The etch-back process can be a selective etching process, removing the electrode material layer 160L and the ferroelectric dielectric layer 130L without substantially affecting the semiconductor channel 140 and the metal layer 171. The etch-back process can include isotropic etching processes (e.g., wet etching processes) or anisotropic etching processes (e.g., reactive ion etching processes). The etch-back process can be performed until the top surfaces of the electrode material layer 160L and the ferroelectric dielectric layer 130L are substantially coplanar with the top surface of the metal layer 171. After the etch-back process, the height of the top surface of the semiconductor channel 140 is higher than the top surfaces of the electrode material layer 160L, the ferroelectric dielectric layer 130L, and the metal layer 171. The recessed depth of the electrode material layer 160L and the ferroelectric dielectric layer 130L causes the metal layer 171 to surround the semiconductor channel 140 (e.g., columnar semiconductor channel 140).

[0035] In Figure 13, a second etch stop layer 145 is deposited on the exposed surfaces of the semiconductor channel 140, electrode material layer 160L, ferroelectric dielectric layer 130L, and metal layer 171. The deposition height of the second etch stop layer 145 can be greater than the top surface of the semiconductor channel 140. The second etch stop layer 145 may include the same material as the first etch stop layer 143 and can be formed in the same manner as the first etch stop layer 143. Subsequently, a CMP process is performed to planarize the upper surface of the second etch stop layer 145. The CMP process can be performed until the semiconductor channel 140 is exposed.

[0036] In Figure 14, a second electrode layer 147 is selectively formed on the semiconductor channel 140. The second electrode layer 147 can be deposited first in a capping manner and then patterned to form the top electrode. Similarly, the top electrode can be configured as a source / drain electrode of a transistor or an electrode of a capacitor (e.g., a vertical GAA capacitor device), and can be configured as a charge storage memory device (e.g., a FeRAM memory cell). The second electrode layer 147 can include the same material as the first electrode layer 142L and can be deposited in the same manner as the first electrode layer 142L. In one embodiment, the second electrode layer 147 is titanium nitride formed through an ALD process.

[0037] In Figure 15, a second dielectric layer 172 is formed on the exposed surfaces of the second etch stop layer 145 and the second electrode layer 147. The second dielectric layer 172 may comprise the same material as the first dielectric layer 170 and may be formed in the same manner as the first dielectric layer 170. During the deposition of the second dielectric layer 172, the second electrode layer 147 is embedded within the second dielectric layer 172.

[0038] In Figure 16, an opening 173 is formed in the second dielectric layer 172, and the opening 173 extends through the second dielectric layer 172. The opening 173 is configured to be filled with a conductive material to form a conductive component within the opening 173. The opening 173 can be formed by any suitable process, such as one or more etching processes. In some embodiments, the opening 173 can be obtained by a dual damascene process. Each opening 173 may include a trench opening extending laterally along a first horizontal direction hd1 in the upper portion of the second dielectric layer 172. Each opening 173 may further include a via opening formed perpendicularly through the second dielectric layer 172 to expose a portion of the second electrode layer 147.

[0039] In Figure 17, an electrically conductive material is formed in the opening 173 to form a conductive component 175. Suitable conductive materials may include, but are not limited to, copper, aluminum, zirconium, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, ruthenium, palladium, platinum, cobalt, nickel, iridium, or alloys thereof. The conductive component 175 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The opening 173 and the top surface of the second dielectric layer 172 are filled with the electrically conductive material. Excess conductive material may be removed from the top surface of the second dielectric layer 172 by a CMP process. The conductive component 175 filling the corresponding trench opening in the second dielectric layer 172 may be configured as an effective bit line. Each conductive component 175 is formed in the second electrode layer 147, and each conductive component 175 is in direct contact with the top surface of the corresponding column of the semiconductor channel 140. Therefore, conductive components 175 are formed above a two-dimensional array of semiconductor channels 140, wherein each conductive component 175 is formed directly above the top surface of the columnar semiconductor channels 140 of the corresponding column.

[0040] Therefore, each semiconductor channel 140 is disposed between a first electrode layer 142 (e.g., source) and a second electrode layer 147 (e.g., drain). The second electrode layer 147 is electrically connected to a conductive component 175 (e.g., bit line). The semiconductor channel 140 is surrounded by a metal layer 171 (e.g., word line), an electrode material layer 160L, and a ferroelectric dielectric layer 130L, wherein the ferroelectric dielectric layer 130L is disposed between the semiconductor channel 140 and the electrode material layer 160L and is in contact with the semiconductor channel 140 and the electrode material layer 160L. The semiconductor channel 140, the first electrode layer 142, the second electrode layer 147, the ferroelectric dielectric layer 130L, the electrode material layer 160L, and the metal layer 171 can be collectively referred to as a vertical gate all-around (GAA) device structure 180. The channel region (vertically disposed between the top source / drain component and the bottom source / drain component) is surrounded by the ferroelectric material layer. The device structure 180 forms a 1-transistor (1T) FeRAM circuit that can be configured as a capacitor or memory device. The vertical GAA device structure 180 provides a large effective area for the capacitor or memory device and increases the charge storage capacity. In addition, the use of a high-k dielectric material (e.g., hafnium zirconium oxide (HZO)) as the ferroelectric material provides high ferroelectric polarization to further enhance the charge storage capacity.

[0041] In some embodiments, the individual memory cell devices are electrically connected to form an array of memory cell devices, configured to increase charge storage capacity. The array of memory cell devices may be located in a memory array region within an interconnect structure, such as the memory array region 50 above the second interconnect layer L2 shown in Figures 2B and 2C. Since the 1T GAA FeRAM device array is positioned between BEOL metal wirings in the interconnect structure away from the front-end transistor devices, additional space can be provided for complex front-end transistor devices, thereby improving the overall structure performance.

[0042] Figure 18 illustrates a schematic diagram of a layout design 1800 according to an embodiment of Figure 17. Figure 17 illustrates a vertical cross-sectional view of a portion of an exemplary semiconductor device structure 200 taken along plane CC shown in Figure 18. As shown, a first group of memory cell devices 151 (e.g., a vertical GAA device structure 180) is disposed in a first row extending along a first direction, and a second group of memory cell devices 153 (e.g., a vertical GAA device structure 180) is disposed in a second row extending along the first direction, wherein the second group of memory cell devices 153 is separate from the first group of memory cell devices 151. A first bit line (BL1) (e.g., a conductive component 175) is coupled to the first group of memory cell devices 151 and extends along the first direction, and a second bit line (BL2) is coupled to the second group of memory cell devices 153 and extends along the first direction. The first character line (WL1) (e.g., metal layer 171) is configured to extend along a second direction different from the first direction, and the second character line (WL2) (e.g., metal layer 171) is configured to extend along the second direction.

[0043] The first word line (WL1) and the second word line (WL2) may be disposed in the first interconnect dielectric layer. The first word line (BL1) and the second word line (BL2) may be disposed in the second interconnect dielectric layer above the first interconnect dielectric layer. The first word line (WL1) surrounds the first memory cell device 180 in the first group of memory cell devices 151 and the first memory cell device 180 in the second group of memory cell devices 153. The second word line (WL2) surrounds the second memory cell device 180 in the first group of memory cell devices 151 and the second memory cell device 180 in the second group of memory cell devices 153. In some embodiments, the first line (BL1) and the second word line (BL2) and the first word line (WL1) and the second word line (WL2) are formed such that at least the first word line (BL1) extends along a first direction perpendicular to the second direction of the first word line (WL1). That is, the intersection angle "θ1" between the first character line (BL1) and the first character line (WL1) is approximately 90 degrees.

[0044] Figure 19 illustrates a schematic diagram of a layout design 1900 according to an alternative embodiment. The embodiment in Figure 19 is substantially the same as the embodiment in Figure 18, except that the first bit line (BL1) and the second bit line (BL2) are formed to be non-perpendicular to the first word line (WL1) and the second word line (WL2), and at least the intersection angle "θ2" formed between the first bit line (BL1) and the first word line (WL1) is greater than or less than 90 degrees. The embodiments shown in Figures 18 and 19 can be applied to various embodiments of this disclosure, wherein Figure 19 illustrates a first group of memory cell devices 155 and a second group of memory cell devices 157.

[0045] In some embodiments, the memory unit devices of the third group (not shown) and the memory unit devices of the fourth group (not shown) may be disposed below the memory unit devices of the first group and the memory unit devices of the second group, respectively, and aligned with the memory unit devices of the first group and the memory unit devices of the second group. The memory unit devices of the first group and the third group, as well as the memory unit devices of the second group and the fourth group, may each be disposed in a manner similar to that shown in Figure 20, which will be described in detail below.

[0046] Figure 20 illustrates a vertical cross-sectional view of an exemplary semiconductor device structure 300 according to some embodiments. The exemplary semiconductor device structure 300 includes two memory cell devices 302, 304 that are vertically stacked and connected. The memory cell devices 302, 304 may be 1T FeRAM circuits (e.g., GAA device structure 180 of Figure 17) and are electrically connected to increase charge storage capacity. In one embodiment, a first electrode layer 142 of the memory cell device 302 contacts a conductive component 175 of the memory cell device 304, which serves as a bit line. The metal line 122 of the memory cell device 304 and the conductive component 175 of the memory cell device 302 may be grounded. Although two memory cell devices 302, 304 are shown, three or more memory cell devices may be vertically stacked to form an array of memory cell devices. In any case, the exemplary semiconductor device structure 300 or the array of memory cell devices may be disposed in the memory array region (e.g., the memory array region 50 above the second interconnect layer L2 shown in Figures 2B and 2C) between BEOL metal wirings or in the interconnect structure.

[0047] Figures 21 through 28 are cross-sectional side views of various stages of fabricating an exemplary semiconductor device structure 400 according to some embodiments of the present disclosure, wherein figures 21 through 28 illustrate the X and Z directions for reference. In this embodiment, an array of memory cell devices is disposed in a back-side interconnect structure to increase device density and thus improve charge storage capacity. In Figure 21, a front-side interconnect structure 2250 is formed over the device layer 2200. The front-side interconnect structure 2250 includes various conductive components, such as a plurality of first conductive components 2204 and a plurality of second conductive components 2206, and an intermetallic dielectric (IMD) layer 2202 to separate and isolate the various conductive components 2204, 2206. In some embodiments, the plurality of first conductive components 2204 are conductive components, and the plurality of second conductive components 2206 are conductive vias. The front interconnect structure 2250 includes multiple layers of conductive components 2204, and the conductive components 2204 are disposed in each layer to provide an electrical path to the device layer 2200 below.

[0048] Device layer 2200 may include substrate 2101 on which various devices, such as transistors, diodes, image sensors, resistors, capacitors, inductors, memory cells, or combinations thereof, may be formed. In some embodiments, device layer 2200 includes at least one or more logic devices 2201, which may be planar field-effect transistors (FETs), three-dimensional fin FETs (FinFETs), gate-all-around (GAA) devices (e.g., horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs), vertical FETs, forked FETs or complementary FETs (CFETs), multi-bridge channel (MBC) transistors, or any transistor with a channel-surrounded gate electrode. Each logic device 2201 includes an S / D (source / drain) region 2124 and a gate 2138 (disposed between the S / D region 2124 as a source region and the S / D region 2124 as a drain region). Conductive component 2206 provides vertical electrical wiring from device layer 2200 to conductive component 2204 between conductive components 2204. For example, the bottom conductive component 2206 of the front interconnect structure 2250 may be electrically connected to conductive contacts (not shown) located above S / D area 2124 and gate 2138.

[0049] In Figure 22, device layer 2200 and front-side interconnect structure 2250 are bonded to carrier substrate 2182. Carrier substrate 2182 is configured to provide mechanical support for semiconductor device structure 400 to facilitate subsequent back-side processing of substrate 2101. Carrier substrate 2182 may include a redistribution layer (RDL) 2183 formed on one side of carrier substrate 2182. RDL 2183 may include one or more dielectric layers (not shown), wherein conductive elements 2252 are disposed in one or more dielectric layers. Conductive elements 2252 may include wires / traces configured as conductive components 2204, 2206 in front-side interconnect structure 2250. In one exemplary embodiment shown in Figure 22, the front interconnect structure 2250 is bonded to the RDL 2183 of the carrier substrate 2182 via, for example, insulator-to-insulator bonding (e.g., dielectric layer of the RDL 2183 of the front interconnect structure 2250 to the IMD layer 2202) and via a hybrid bonding technique via metal-to-metal bonding (e.g., conductive element 2252 of the RDL 2183 to conductive component 2204 of the front interconnect structure 2250). Additionally or optionally, the front interconnect structure 2250 and the RDL 2183 of the carrier substrate 2182 may be bonded together via a bonding layer.

[0050] In Figure 23, the flip semiconductor device structure 400 is arranged such that the carrier substrate 2182 is disposed at the bottom, while the back side of the substrate 2101 faces upward.

[0051] In Figure 24, a thinning process can be performed on the back side of substrate 2101. The thinning process can be performed using any suitable technique (e.g., grinding, polishing, and / or chemical etching). For example, a significant amount of substrate material can be removed from the back side of substrate 2101 using a mechanical grinding process. Then, an etching chemical process can be applied to further thin the back side of substrate 2101. In some embodiments, the thinning process can be performed until a portion of the source / drain region 2124 is exposed. In some embodiments, the thinning process can be performed until the entire substrate 2101 is removed.

[0052] In Figure 25, a dielectric material layer 2190 is formed above the back side of the substrate 2101, and a conductive component 2198 is formed within the dielectric material layer 2190. The conductive component 2198 may be a conductive via for connecting the S / D region 2124. The dielectric material layer 2190 may be patterned using a lithography process and one or more etching processes to form openings that expose the source / drain regions 2124 and a portion of the substrate 2101 (if present). After forming the openings, a conductive material is formed in the openings and above the top surface of the dielectric material layer 2190. A planarization process is performed to expose the dielectric material layer 2190 to form the conductive component 2198 within the dielectric material layer 2190. The dielectric material layer 2190 may include the same material as the IMD layer 2202. The conductive component 2198 may be made of a metal or metal nitride such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, or Ni. The conductive component 2198 can be formed by any suitable process, such as PVD, electroplating, or any suitable deposition technique. Although not shown, a silicon layer can be selectively formed between the conductive component 2198 and the S / D region 2124. In this embodiment, the silicon layer may comprise a metal or metal alloy, and the metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof.

[0053] In Figure 26, after forming the conductive component 2198, an ILD layer 2185 is formed on the dielectric material layer 2190 and the conductive component 2198. Then, one or more conductive components 2197 are formed in the ILD layer 2185. The dielectric material layer 2190 and the ILD layer 2185 may be interconnect level layers disposed in a back-side interconnect structure. The conductive component 2197 is electrically connected to the S / D region 2124 through the conductive component 2198 and the silicon layer. The conductive component 2197 may be configured as a power rail connected to a power source (not shown). In some embodiments, the conductive component 2197 is part of a power rail. In some embodiments, a second ILD layer and a second conductive component formed in the second ILD layer may be further provided above the dielectric material layer 2190 and the conductive component 2198. Depending on the layout design, additional ILD layers and conductive components may be formed above the dielectric material layer 2190 and the conductive component 2198. The dielectric layer 2190 and conductive components 2198 provide power to various devices in different regions of the semiconductor device structure 400. In this embodiment, at least one or more conductive components (e.g., conductive component 2197) may be electrically connected to an array of memory cells in the subsequently formed memory device layer 2194, and at least one or more conductive components (e.g., conductive component 2197) may be electrically connected to logic devices subsequently formed in the peripheral area. Depending on the conductivity type of the transistor device (e.g., logic device 2201), a positive voltage (VDD) or a negative voltage (VSS) (i.e., ground voltage or zero voltage) may be fed to the power supply connected to the power rail. Connecting the power supply from the back side of the semiconductor device structure 400 to the conductive components 2197 (e.g., the power rail) allows various devices to be powered directly from the back side power supply, thereby enhancing device performance, saving a large amount of wiring resources configured on the front side of the device, reducing BEOL process complexity, and preventing abnormal electrical misconnection problems.

[0054] In Figure 27, a memory device layer 2194 is formed above the ILD layer 2185 and conductive components 2197. The memory device layer 2194 may include an interconnect dielectric material layer 2133, an array 2195 of non-volatile memory cells formed in the interconnect dielectric material layer 2133, and conductive components 2186 and 2188. Conductive component 2186 may be a conductive via, and conductive component 2188 may be a conductive line. In some embodiments, the memory device layer 2194 (or the interconnect dielectric material layer 2133) may be configured as one of the interconnect-level dielectric layers. In some embodiments, conductive components 2186 and 2188 may be replaced by via structures, such as through-oxide-via (TOV), through-insulator-via (TIV), etc. The non-volatile memory cell array 2195 may include a plurality of 1T FeRAM circuits, such as the GAA device structure 180 shown in Figure 17, or a plurality of semiconductor device structures 300 shown in Figure 20. The memory device layer 2194 may be formed in a manner similar to that described in Figures 5 to 17 above. Other non-volatile memory devices are also contemplated, such as resistive random access memory (RRAM or ReRAM), magnetoresistive random access memory (MRAM), or phase-change memory (PCM).

[0055] In Figure 28, a back interconnect structure 2196, similar to the front interconnect structure 2250, is formed on the memory device layer 2194. The back interconnect structure 2196 includes a plurality of inter-metal dielectric layers 2274 and conductive components 2276, 2278 formed in each inter-metal dielectric layer 2274. The back interconnect structure 2196 can be configured to provide power and / or additional signal connections to various devices in the memory device layer 2194 and the device layer 2200. In some embodiments, the back interconnect structure 2196 and the front interconnect structure 2250 can share the same power supply.

[0056] Therefore, the array 2195 of non-volatile memory cells is embedded in the back-side interconnect structure 2196, which is located away from the device layer 2200. This allows for more wiring space on the front side of the device layer 2200, and in fact, various devices can be directly powered by the back-side power supply, saving wiring resources used on the front side of the device and reducing the complexity of the front-side BEOL process without causing abnormal electrical misconnection problems. Therefore, device performance is improved.

[0057] Various manufacturing processes can be further performed on the semiconductor device structure 400. For example, after forming the back interconnect structure 2196, a redistribution layer (not shown) can be provided on the back interconnect structure 2196, which may include one or more contact pads formed in one or more passivation layers. The redistribution layer is reconfigured to flip the wiring of wafer bonding or other suitable packaging techniques, thereby integrating the semiconductor device structure 400 onto a board (e.g., a printed circuit board).

[0058] Figure 29 illustrates a cross-sectional side view of an exemplary semiconductor device structure 500 according to some embodiments of the present disclosure. Semiconductor device structure 500 is substantially the same as semiconductor device structure 400, except that an array 2193 of non-volatile memory cells is further provided in the front interconnect structure 2250. Similarly, the array 2193 of non-volatile memory cells may include a plurality of 1T FeRAM circuits, such as the GAA device structure 180 shown in Figure 17, or a plurality of semiconductor device structures 300 shown in Figure 20. The array 2193 of non-volatile memory cells may be formed in a manner similar to that described in Figures 5 through 17. The array 2193 of non-volatile memory cells and the array 2195 of non-volatile memory cells can be the same and can be selected from various non-volatile memory devices, such as ferroelectric random access memory (FeRAM), resistive random access memory (RRAM or ReRAM), magnetoresistive random access memory (MRAM), and phase-change memory (PCM). In some embodiments, the array 2193 of non-volatile memory cells is a vertical GAA structure, and the array 2195 of non-volatile memory cells is a non-vertical GAA structure. In some embodiments, the array 2193 of non-volatile memory cells is a non-vertical GAA structure, and the array 2195 of non-volatile memory cells is a vertical GAA structure. In some embodiments, the array 2193 of non-volatile memory cells may use a different memory device than the array 2195 of non-volatile memory cells.

[0059] Figure 30 illustrates a cross-sectional side view of an exemplary semiconductor device structure 600 according to some embodiments of the present disclosure. Semiconductor device structure 600 is substantially the same as semiconductor device structure 400, except that device layer 2200 is replaced by device layer 2300. Figure 30-1 illustrates an enlarged view of a portion 2305 of the semiconductor device structure 600 shown in Figure 30 according to some embodiments of the present disclosure. In Figure 30-1, device layer 2300 generally includes a substrate 2301 and one or more nanostructured transistors 2303 disposed in the substrate 2301. The term "nanostructure" is configured in this disclosure to refer to a portion of any material having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, and includes beam-shaped or rod-shaped material portions, such as cylindrical or substantially rectangular cross-sections. Nanostructured transistors can be referred to as nanowire / nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor with a gate electrode layer surrounded by channels.

[0060] In embodiments where the nanostructure transistor 2303 is a GAA transistor, the nanostructure transistor 2303 may include a gate structure 2340 and epitaxial source / drain (S / D) components 2342, 2343, and 2344 disposed on opposite sides of the gate structure 2340. A first semiconductor layer 2350 and a second semiconductor layer 2352, configured to define the channel region of the nanostructure transistor, are respectively disposed between and in contact with the epitaxial S / D components 2342, 2343, and 2344. Each gate structure 2340 includes a gate spacer 2358 formed on the sidewall of the gate structure 2340, an interface layer (IL) 2360 formed around the surface of each semiconductor layer of the stacked semiconductor layers 2350, 2352, a high-k (HK) dielectric layer 2362 formed around each semiconductor layer of the stacked semiconductor layers 2350, 2352, and a gate electrode layer 2364 formed on the HK dielectric layer 2362 surrounding each semiconductor layer of the stacked semiconductor layers 2350, 2352. An inner spacer 2366 is formed between the gate electrode layer 2364 and the epitaxial S / D components 2342, 2343, 2344.

[0061] S / D contact 2348 is disposed on a first side (e.g., front side) of device layer 2300. S / D contact 2348 is separated from epitaxial S / D component 2342 by silicon layer 2349. Silicon layer 2349 may be made of metal or metal alloy. Interlayer dielectric (ILD) layer 2368 is disposed on the first side of device layer 2300 and is separated from epitaxial S / D components 2343, 2344 by contact etch stop layer (CESL) 2370. Part of the surface of S / D contact 2348, gate spacer 2358, HK dielectric layer 2362, gate electrode layer 2364, ILD layer 2368 and CESL 2370 are substantially coplanar and in contact with front interconnect structure 2202.

[0062] The front interconnect structure 2202 may include a plurality of conductive lines 2204 and conductive vias 2206 formed in the IMD layer 2202, as shown in Figure 30. Conductive components (e.g., back power rails) 2198 are formed on a second side (e.g., the back side) of the device layer 2300 opposite to the first side. The conductive components 2198 may be formed after the front interconnect structure 2250 is formed on the first side. In some embodiments, after temporarily attaching the carrier substrate 2182 to the front interconnect structure 2250 and flipping the carrier substrate 2182, a thinning process is performed to remove a portion of the substrate 2301. Then, a hard mask (not shown) may be formed on a portion of the substrate 2301 above the epitaxial S / D component (e.g., epitaxial S / D component 2343) to connect the conductive components (e.g., back power rails) 2198. Then, portions of the substrate 2301 not covered by the hard mask are removed to form openings exposing epitaxial source / drain (S / D) components (e.g., epitaxial S / D components 2342, 2344), which may be epitaxial drain components. A pad 2347 is formed on the exposed epitaxial drain components. The pad 2347 may be formed of nitrides or metal nitrides, such as SiN, TaN, TiN, WN, or MoN. Subsequently, a dielectric material 2190 is formed on the pad 2347 to fill the openings, wherein the dielectric material 2190 may be any suitable dielectric material, such as an oxide. Then, the remaining portion of the substrate 2301 that is not covered by the hard mask is removed to form an opening that exposes the epitaxial S / D components (e.g., epitaxial S / D component 2343) that were previously protected by the hard mask, such that a plurality of epitaxial source components (e.g., epitaxial S / D component 2343) are exposed through the opening, and a plurality of epitaxial drain components (e.g., epitaxial S / D components 2342, 2344) are disposed below the dielectric material 2372.

[0063] A backside silica layer 2345 made of metal or metal alloy can be selectively formed on the exposed epitaxial source component (e.g., epitaxial S / D component 2343). Subsequently, electrically conductive components are formed in openings in the silica layer 2345, thereby forming conductive components (e.g., backside power rails) 2198 of the device layer 2300. After forming the conductive components (e.g., backside power rails) 2198, a planarization process (e.g., CMP) is performed on the backside of the device layer 2300, such that the exposed surfaces of the conductive components 2198, the pads 2347, and the dielectric material 2190 are substantially coplanar. After CMP, an ILD layer 2185 is formed on the dielectric material layer 2190 and the conductive components 2198. Then, one or more conductive components 2197 are formed in the ILD layer 2185.

[0064] Therefore, the epitaxial source components (e.g., epitaxial S / D components 2343) are connected to conductive components (e.g., rear power rails) 2198 disposed on the back side of the device layer 2300, and can be directly powered by a positive voltage (VDD) or a negative voltage (VSS) (i.e., ground voltage or zero voltage), while the epitaxial drain components (e.g., epitaxial S / D components 2342, 2344) are connected to power rails (not shown) disposed on the front side of the device layer 2300. The rear power rails (e.g., conductive components 2198) save a significant amount of wiring resources used on the front side of the device layer 2300, reduce the complexity of the BEOL process, and prevent abnormal electrical misconnection problems. Furthermore, since power can be provided through both the back and front sides of the device layer 2300, the power consumption of the semiconductor device structure 600 and the memory device layer 2194 formed on the device layer 2300 can be reduced.

[0065] The various embodiments disclosed herein relate to semiconductor device structures having an array of memory cell devices disposed in a back-end process (BEOL) structure to improve device density and performance. Each memory cell device may be a vertical all-ring gate (GAA) device structure, wherein the channel region is surrounded by a layer of ferroelectric material (e.g., FeRAM memory cell). The vertical GAA device structure provides a large effective area for capacitors or memory devices and increases charge storage capacity. Furthermore, since the array of memory cell devices is disposed between BEOL metal wirings in the interconnect structure away from the front-end transistor device, additional space can be provided for complex front-end transistor devices, thereby improving the overall structure performance. In some embodiments, the array of memory cell devices is disposed between the back power rail and the back interconnect structure, configured to increase charge storage capacity while providing increased wiring space on the front side of the device layer.

[0066] One embodiment is a semiconductor device structure. The semiconductor device structure includes a device layer having a first side and a second side opposite to the first side, and a first interconnect structure disposed above the first side of the device layer. The first interconnect structure includes a first interconnect level layer and a second interconnect level layer disposed above the first interconnect level layer, wherein the second interconnect level layer includes an array of vertical memory cell devices. This semiconductor device structure further includes a third interconnect level layer disposed above the second interconnect level layer.

[0067] Another embodiment is a semiconductor device structure. This semiconductor device structure includes a device layer having a first side and a second side opposite to the first side, a first interconnect structure disposed adjacent to the first side of the device layer, and a memory device layer disposed above the second side of the device layer. The memory device layer includes a plurality of memory cell devices in a first group disposed in a first row extending along a first direction, wherein each memory cell device has a channel region surrounded by a first ferroelectric material layer and vertically disposed. The memory device layer further includes bit lines coupled to the first group of memory cell devices and extending along the first direction. The semiconductor device structure further includes a second interconnect structure disposed above the memory device layer.

[0068] Another embodiment is a method of forming a semiconductor device structure. The method includes providing a first interconnect structure over a first side of a device layer, wherein the device layer has a substrate comprising one or more logic devices; attaching the first interconnect structure to a carrier substrate; flipping the carrier substrate such that a second side of the device layer faces upward to expose a back side of the substrate; removing a portion of the substrate from the back side; and forming a dielectric material layer over the back side of the substrate, wherein the dielectric material layer includes power rails coupled to a power source. The method further includes forming a memory device layer over the dielectric material layer, wherein the memory device layer includes an array of a vertically oriented plurality of memory cell devices. This method also includes providing a second interconnect structure over the memory device layer.

[0069] The foregoing outlines the features of various embodiments, enabling those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that they can simply use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

[0070] 8, 110, 2101, 2301:Substrate 10: Semiconductor material layer 12: Shallow trench isolation structure 14: Source / Drain Region 15: Semiconductor Channel 18: Source / Drain Metal-Semiconductor Alloy Region 20: Gate structure 22: Gate dielectric 24: Gate electrode bar 26: Dielectric gate spacer 28: Gate-covered dielectric 30, 33, 34, 35, 36, 37: Interconnect-level dielectric layer / ILD layer / Interconnect-level dielectric material / Interconnect-level dielectric material layer 31A, 31B, 32: Dielectric material layer / interconnect-level dielectric layer / ILD layer / interconnect-level dielectric material 40, 41V, 42V, 43V, 44V, 45V, 46V, 47V, 47B: Metal interconnect structure / metal wire structure 41L, 42L, 43L, 44L, 45L, 46L: Metal interconnect structure / metal wire structure / metal wire 50: Memory Array Area 52: Surrounding Area / Surrounding Logical Area 75: CMOS Circuit 95, 2193, 2195: Array 100, 200, 300, 400, 500, 600: Semiconductor device structures 120: Dielectric material layer / Dielectric material 121: Trench 122: Metal wire 130L: Ferroelectric dielectric layer 140: Semiconductor Channel 140L: Semiconductor Channel Material Layer / Semiconductor Material Layer 142: Bottom Electrode / Electrode Layer 142L, 147: Electrode layers 143, 145: Etching stop layer 151, 153, 155, 157: Memory unit devices 160L: Electrode material layer 170, 172: Dielectric layer 171: Metal layer 173: Opening 175, 2186, 2188, 2197, 2198, 2276, 2278: Conductive components 177: Photoresist 180: Device Structure / Memory Unit Device 302, 304: Memory unit devices 1800, 1900: Layout Design 2124: S / D region / source / drain region 2133: Interconnect dielectric material layer 2138, G: Gate 2182: Carrier substrate 2183: Rerouting Layer / RDL 2185: ILD layer 2190, 2372: Dielectric material layer / dielectric material 2194: Memory Device Layer 2196: Backside interconnect structure 2200, 2300: Device layer 2201: Logic Device 2202: IMD Layer / Interconnection Structure 2204: Conductive wire / conductive component 2206: Conductive via / Conductive component 2274: Intermetallic Dielectric Layer 2250: Interconnection Structure 2252: Conductive element 2303: Nanostructured Transistor 2305: Part 2340: Gate structure 2342, 2343, 2344: Epitaxial source / drain components / epitaxy S / D components 2343: Epitaxial Source Electrode Component 2345, 2349: Silicone layers 2347: Padding 2348: S / D Contact 2350, 2352: Semiconductor layers 2358: Gate spacer 2360: Interface Layer / IL Layer 2362: Dielectric layer 2364: Gate electrode layer 2366: Inner spacer 2368: Interlayer dielectric layer / ILD layer 2370: Contact Etching Stop Layer / CESL AA, BB, CC: Plane BL, BL1, BL2: Bit lines D: Jiji hd1: First horizontal direction hd2: Second horizontal direction MT: Memory Transistor L0, L1, L2, L3, L4, L5, L6, L7: Interconnection layer S: Source SG: Select Gate SL: Source Line WL, WL1, WL2: Character lines X, Z: Direction θ1, θ2: Cross angles

[0071] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device structure, comprising: A device layer having a first side and a second side opposite to the first side; A first interconnect structure is disposed above the first side of the device layer, and the first interconnect structure includes: a first interconnect level layer; A second interconnect layer is disposed above the first interconnect layer, wherein the second interconnect layer includes an array of vertically arranged memory cell devices; and a third interconnect layer is disposed above the second interconnect layer; a dielectric material layer is disposed above the second side of the device layer, wherein the dielectric material layer includes a power rail coupled to a power source; and a memory device layer is disposed above the dielectric material layer, wherein the memory device layer includes an array of vertically arranged memory cell devices.

2. The semiconductor device structure as claimed in claim 1, wherein each memory cell device is electrically connected to a bit line, and each memory cell device is surrounded by a word line, and the bit line extends along a first direction that is perpendicular to or not perpendicular to a second direction of the word line.

3. The semiconductor device structure as claimed in claim 1, wherein each memory cell device is a gate-to-ring transistor structure having a channel region surrounded by a ferroelectric material layer, and the channel region is vertically disposed between a top source / drain component and a bottom source / drain component.

4. The semiconductor device structure as claimed in claim 3, wherein the array of the memory cell devices includes at least two gate-to-ring transistor structures stacked vertically.

5. The semiconductor device structure as described in claim 1, further comprising: A second interconnection structure is disposed above the second side of the device layer.

6. A semiconductor device structure, comprising: A device layer having a first side and a second side opposite to the first side; A first interconnect structure is disposed adjacent to the first side of the device layer; a dielectric material layer is disposed above the second side of the device layer, wherein the dielectric material layer includes a power rail coupled to a power source. A memory device layer is disposed above the dielectric material layer, and the memory device layer includes: a plurality of memory cell devices in a first group disposed in a first row extending along a first direction, wherein each memory cell device has a channel area surrounded by a first ferroelectric material layer and vertically disposed thereon; And a bit line, coupled to the memory cell devices of the first group and extending along the first direction; and a second interconnect structure disposed above the memory device layer.

7. The semiconductor device structure as described in claim 6, further comprising: A single character line is set to extend along a second direction that is different from the first direction.

8. The semiconductor device structure as described in claim 7, wherein the first direction is not perpendicular to the second direction.

9. The semiconductor device structure as described in claim 6, further comprising: A second group of a plurality of memory cell devices is disposed in the first row extending along the first direction, wherein each memory cell device in the second group has a channel region surrounded by a second ferroelectric material layer and vertically disposed therein, and at least one of the memory cell devices in the first group and at least one of the memory cell devices in the second group are vertically stacked and connected to each other.

10. A method for forming a semiconductor device structure, comprising: A first interconnect structure is provided above a first side of a device layer, wherein the device layer has a substrate comprising one or more logic devices; The first interconnect structure is attached to a carrier substrate; The carrier substrate is flipped so that a second side of the device layer faces upward to expose a back side of the substrate; a portion of the substrate is removed from the back side; a dielectric material layer is formed above the back side of the substrate, wherein the dielectric material layer includes a power rail coupled to a power source; a memory device layer is formed above the dielectric material layer, wherein the memory device layer includes an array of vertically oriented plurality of memory cell devices; and a second interconnect structure is provided above the memory device layer.

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