Semiconductor device and forming method thereof

Abstract

This disclosure provides a method for forming a semiconductor device, including forming an interconnect die, the interconnect die including a plurality of through-holes partially extending through a semiconductor substrate, an interconnect structure located on the semiconductor substrate, and a plurality of die connection elements located on the interconnect structure. A protective layer is applied to the die connection elements, and then the protective layer is patterned to form a plurality of protective overlays around the die connection elements. An encapsulation material is formed over and around the interconnect die and the protective overlays. A first planarization process is performed to make the encapsulation material, the protective overlays, and the die connection elements level. A first redistribution structure is formed over the die connection elements, and the first redistribution structure is electrically connected to the die connection elements.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for forming the same. Prior Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (such as transistors, diodes, resistors, and capacitors). In most cases, this integration density is increased by progressively shrinking the smallest feature size, allowing more components to be integrated into a given area. With the increasing demand for miniaturized electronic devices, the need for smaller semiconductor dies and more innovative packaging technologies has also arisen. Summary of the Invention

[0003] This disclosure provides a method for forming a semiconductor device, including forming an interconnect die, the interconnect die including a plurality of through-holes partially extending through a semiconductor substrate, an interconnect structure located on the semiconductor substrate, and a plurality of die connection elements located on the interconnect structure. A protective layer is applied to the die connection elements, and then the protective layer is patterned to form a plurality of protective overlays around the die connection elements. An encapsulation material is formed above and around the interconnect die and the protective overlays. A first planarization process is performed to make the encapsulation material, the protective overlays, and the die connection elements level. A first redistribution structure is formed above the die connection elements, and the first redistribution structure is electrically connected to the die connection elements.

[0004] This disclosure provides a method for forming a semiconductor device, including forming interconnect dies. Forming the interconnect dies includes: forming through-holes partially through a substrate; forming an interconnect structure above the substrate; forming a first die connection element and a second die connection element above the interconnect structure; forming a first dielectric coating above the first die connection element; and forming a second dielectric coating on the second die connection element. The method further includes attaching the interconnect dies above a carrier substrate; forming an encapsulation material above and around the interconnect dies; planarizing the encapsulation material to expose the first die connection element and the second die connection element; forming a first redistribution structure above the encapsulation material, the first die connection element, and the second die connection element; and attaching an integrated circuit die above the first redistribution structure.

[0005] This disclosure provides a semiconductor device including a back-side redistribution structure disposed above a packaging substrate, a packaging material disposed above the back-side redistribution structure, a front-side redistribution structure disposed above the packaging material, a through-hole embedded in the packaging material and electrically coupled to the front-side redistribution structure, and an interconnect die embedded in the packaging material. The interconnect die includes a semiconductor substrate, an interconnect structure disposed above the semiconductor substrate, a first die connection element disposed above the interconnect structure and electrically connected to the front-side redistribution structure, and a first dielectric coating layer directly between the first die connection element and the packaging material, wherein the first lateral thickness of the first dielectric coating layer is smaller than the first lateral diameter of the first die connection element. Simple Explanation of the Diagram

[0006] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, many features are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly demonstrate the features of this disclosure. Figure 1 is a cross-sectional view of an integrated circuit die. Figures 2A to 2B are cross-sectional views of grain stacking. Figures 3A to 5C are intermediate stage views of manufacturing interconnect grains according to various embodiments. Figures 6 through 14 are intermediate stage views of manufacturing an integrated circuit package according to various embodiments. Figures 15A to 15C are cross-sectional views of interconnect grains according to various embodiments. Figures 16A and 16B are cross-sectional views of interconnect grains according to various embodiments. Figures 17A to 17C are cross-sectional views of interconnect grains according to various embodiments. Implementation

[0007] The following discloses many different embodiments or examples to implement different features of the provided object. Specific examples of elements and their arrangements are described below to illustrate this disclosure. These embodiments are merely illustrative and do not limit the scope of this disclosure. For example, the specification mentions that a first feature is formed on a second feature, which includes embodiments where the first and second feature are in direct contact, and also includes embodiments where there are other features between the first and second feature, i.e., the first and second feature are not in direct contact. Furthermore, repeated reference numerals or designations may be used in different embodiments; these repetitions are only for the purpose of clearly describing this disclosure and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0008] Furthermore, spatially related terms may be used, such as "below," "lower," "above," "higher," and similar terms. These spatially related terms are used to facilitate the description of the relationship between one or more elements or features in the illustration and another element or feature(s). These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the illustration. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially related adjectives used will also be interpreted according to the orientation after the turn.

[0009] According to various embodiments, the interposer of the integrated circuit package includes a molding compound located between two redistribution structures. Interconnect dies and vias are disposed in the molding compound and embedded within the interposer. These interconnect dies are manufactured at the wafer level and may include die connection elements providing electrical connections to the redistribution structures. A protective layer is formed over and around the die connection elements and patterned as an independent protective overlay for one or more die connection elements. Therefore, the protective overlay provides protection benefits for the die connection elements while reducing warpage of the interconnect dies, thereby improving the quality of the integrated circuit package in subsequent steps. Specifically, the interconnect dies can be monolithically formed from the wafer and attached to a carrier substrate. A molding material is formed over and around the interconnect dies, and a first redistribution structure is formed over the interconnect dies. Subsequently, the integrated circuit dies are attached to the first redistribution structure, and the carrier substrate is removed to form a second redistribution structure on the opposite side of the interconnect dies.

[0010] Figure 1 is a cross-sectional view of the integrated circuit die 50. Multiple integrated circuit dies 50 will be packaged in subsequent processes to form an integrated circuit package. Each integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC) die, microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or a combination thereof. Integrated circuit dies 50 can be formed in a wafer, which includes different die regions that are monolithized in subsequent steps to form multiple integrated circuit dies 50. An integrated circuit die 50 includes a semiconductor substrate 52, an interconnect structure 54, die connection elements 56, and a dielectric layer 58.

[0011] Semiconductor substrate 52 may be an active layer of a silicon substrate (doped or undoped) or a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may also include other semiconductor materials, such as germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide), or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Semiconductor substrate 52 has active surfaces (e.g., the upward-facing surface in Figure 1) and inactive surfaces (e.g., the downward-facing surface in Figure 1). Devices (not shown separately) are located on the active surfaces of semiconductor substrate 52. These devices may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. Inactive surfaces may not have devices.

[0012] Interconnect structures 54 are located on the active surface of semiconductor substrate 52 and are used to electrically connect devices on semiconductor substrate 52 to each other to form integrated circuits. Interconnect structures 54 may include one or more dielectric layers and corresponding metallization layers within the dielectric layers. Acceptable dielectric layer materials include oxides (e.g., silicon oxide or aluminum oxide), nitrides (e.g., silicon nitride), combinations thereof (e.g., silicon oxynitride), or similar materials. Other dielectric materials may also be used, such as polymers (e.g., polymers based on polybenzoxazole (PBO), polyimide, benzocyclobuten (BCB), etc.). Metallization layers may include conductive vias and / or conductive lines to interconnect devices on semiconductor substrate 52. Metallization layers may be made of conductive materials, such as metals (e.g., copper, cobalt, aluminum, gold, or combinations thereof). The metallization layers of interconnect structures 54 may be formed by damascene processes, such as single damascene processes, dual damascene processes, or similar processes.

[0013] Die connection element 56 is located on the front side 50F of integrated circuit die 50. Die connection element 56 can be a conductive pillar, conductive pad, or similar structure for connection to the outside. Die connection element 56 is located within and / or on the interconnect structure 54. For example, die connection element 56 can be part of the upper metal layer of the interconnect structure 54. Die connection element 56 can be formed from metal (such as copper, aluminum, or similar materials) and can be formed by processes such as electroplating.

[0014] Optionally, during the fabrication of the integrated circuit die 50, a solder area (not shown separately) may be placed on the die connection element 56. The solder area can be used for chip probe (CP) testing of the integrated circuit die 50. For example, the solder area may be a solder ball, solder bump, or similar structure used to connect the chip probe to the die connection element 56. The chip probe test can be used to detect whether the integrated circuit die 50 is a known good die (KGD). Therefore, only integrated circuit dies 50 that are known good dies will undergo subsequent processing and packaging, while dies that fail the chip probe test will not be packaged. The solder area can be removed after testing.

[0015] Dielectric layer 58 is located on the front side 50F of integrated circuit die 50. Dielectric layer 58 is located within and / or on the interconnect structure 54. For example, dielectric layer 58 may be the top dielectric layer of interconnect structure 54. Dielectric layer 58 laterally encapsulates die connection element 56. Dielectric layer 58 may be an oxide, nitride, polymer, or a combination thereof, and may be fabricated by processes such as spin coating, lamination, chemical vapor deposition (CVD). The front surfaces of die connection element 56 and dielectric layer 58 may be substantially coplanar on the front side 50F of integrated circuit die 50 (within the range of process variations).

[0016] Figures 2A and 2B are cross-sectional views of die stacks 60A and 60B, respectively. Die stacks 60A and 60B may each have a single function (e.g., a logic device, a memory die, etc.) or multiple functions. In some embodiments, die stack 60A is a logic device, such as a system-on-integrated-chip (SoIC) device, while die stack 60B is a memory device, such as a high bandwidth memory (HBM) device.

[0017] As shown in Figure 2A, the die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die, and the second integrated circuit die 50B is an interface die. The interface die connects the logic die to the memory die and translates instructions between the logic die and the memory die. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded with their active surfaces facing each other (e.g., "face-to-face" bonding). A conductive via 62 may be formed through one of the integrated circuit dies 50 to establish an external connection with the die stack 60A. The conductive via 62 may be a through-substrate via (TSV), such as a through-silicon via or a similar structure. In the illustrated embodiment, the conductive via 62 is formed within the second integrated circuit die 50B (e.g., the interface die). The conductive via 62 passes through the semiconductor substrate 52 of the integrated circuit die 50 and is physically and electrically connected to the metal layer of the interconnect structure 54.

[0018] As shown in Figure 2B, the die stack 60B is a stacked device comprising multiple semiconductor substrates 52. For example, the die stack 60B may be a memory device comprising multiple memory chips, such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, or a similar device. Each semiconductor substrate 52 may or may not have a separate interconnect structure 54. The semiconductor substrates 52 are interconnected via conductive vias 62 (such as TSVs).

[0019] Figures 3 through 12 illustrate intermediate stage views of manufacturing the integrated circuit package 200 (see Figures 10 through 12), according to some embodiments. Figures 3A through 5B illustrate intermediate stage views of manufacturing the interconnect die 110. Package region 100P is illustrated, and the integrated circuit package 200 is formed within package region 100P. Although only a single package region 100P is illustrated, it should be understood that multiple package regions 100P can be formed. Intermediate wafer 100 is formed, and the intermediate wafer 100 includes an intermediate layer 240 located within package region 100P. Integrated circuit device 202 is attached to intermediate layer 240. Intermediate layer 240 may include interconnect dies 110 for providing interconnects (e.g., electrical coupling) to integrated circuit device 202 within package region 100P. Furthermore, package substrate 220 may be attached to intermediate layer 240. A single-piece packaging region 100P is formed to create an integrated circuit package 200, including a package substrate 220 and a single-piece portion (e.g., an interposer layer 240) of an intermediate wafer 100. In one embodiment, the integrated circuit package 200 is a chip-on-wafer-on-substrate (CoWoS®) package, such as a CoWoS-L package, but it should be understood that this embodiment can be applied to other three-dimensional integrated circuit (3DIC) packages.

[0020] In Figures 3A to 3C, interconnect grains 110 are formed according to various embodiments. Figure 3A shows a cross-sectional side view of the wafer-level interconnect grain 110. Figure 3B shows an enlarged cross-sectional side view of the interconnect grain 110. Figure 3C shows an exemplary plan view (e.g., a top view) of a region of the interconnect grain 110.

[0021] For example, the interconnect die 110 will then be monolithized and integrated into the interposer 240 and the integrated circuit package 200 (see Figure 6). Each interconnect die 110 can be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, or a similar structure. The interconnect die 110 can be a bridging die.

[0022] Each interconnect die 110 includes a substrate 112, on which conductive features are formed. The substrate 112 may include a semiconductor substrate, one or more dielectric layers, or similar structures. Furthermore, each interconnect die 110 may include through-substrate vias (TSVs) 114 extending into or through the substrate 112 and connected to the conductive features of the interconnect die 110. In the illustrated embodiment, the substrate 112 initially covers the through-substrate vias 114 on the back side of the interconnect die 110. In another embodiment, the through-substrate vias 114 are exposed on the back side of the interconnect die 110. The interconnect die 110 further includes die connection elements 116 disposed on the front side of the interconnect die 110, some of which are electrically connected to the back side of the interconnect die 110 through the through-substrate vias 114. The through-substrate vias 114 may be small vias, for example, smaller than the size of via 106.

[0023] In some embodiments, the interconnect die 110 may include a bridging die 118. The bridging die 118 may be a metal layer formed within and / or on the substrate 112 for connecting integrated circuit devices (described later). The bridging die 118 may include interconnects, redistribution lines, or similar structures. The bridging die 118 is located in front of the interconnect die 110. Therefore, the interconnect die 110 can be used to directly connect and enable communication between integrated circuit devices. In this embodiment, the interconnect die 110 may be placed in regions between subsequently attached integrated circuit devices such that each interconnect die 110 is covered by multiple overlapping integrated circuit devices. In some embodiments, the interconnect die 110 may also include passive and / or active devices. In some embodiments, the interconnect die 110 substantially does not include active or passive devices. Interconnect die 110 can be placed on carrier substrate 102 with bridging die 118 facing away from carrier substrate 102 (e.g. towards an integrated circuit device subsequently attached).

[0024] In some embodiments, the substrate 112 of the interconnect die 110 may have a height H1 ranging from 40 µm to 160 µm. Furthermore, the edges of the interconnect die 110 may have the same or different lengths E1 (e.g., extending between the dicing regions 110S), ranging from 5 mm to 32 mm, and the diagonal length E2 ranging from 7 mm to 46 mm. Additionally, the total area of ​​the interconnect die 110 (e.g., the die size defined by the dicing regions 110S) may range from 20 mm² to 270 mm². However, the interconnect die 110 may have any suitable size.

[0025] Furthermore, the die interconnect element 116 may have a lateral diameter D1 ranging from 25µm to 35µm. The spacing P1 of the die interconnect element 116 may be greater than or equal to 35µm. For example, the spacing P1 may be at least 40% to 50% larger than the diameter D1. Although the die interconnect element 116 is schematically elliptical (e.g., circular), the die interconnect element 116 may include any suitable shape, such as rectangular (e.g., square), and may have rounded or sharp corners. The arrangement density of the die interconnect element 116 (see Figure 3C) may occupy 2.5% to 40% of the total area of ​​the interconnect die 110.

[0026] In Figures 4A through 4C, according to various embodiments, a protective layer 120 is formed on and around the die interconnect element 116. Figure 4A illustrates a cross-sectional side view of the wafer-level interconnect die 110. Figure 4B illustrates an enlarged cross-sectional side view of the interconnect die 110. Figure 4C illustrates an exemplary plan view (e.g., a top cross-sectional view) of the interconnect die 110 including the die interconnect element 116.

[0027] For example, the protective layer 120 is made of a polymer, which may be a photosensitive material, such as a polymer based on polyimide, PBO, BCB, or similar materials, and can be patterned by photolithography (see Figures 5A to 5C). The protective layer 120 can be applied by processes such as spin coating, lamination, chemical vapor deposition (CVD), or combinations thereof. In various embodiments, the protective layer 120 is a dielectric layer that provides protection (e.g., oxidation and / or diffusion resistance) and insulation for underlying features (e.g., die interconnect elements 116). Furthermore, the protective layer 120 provides additional stability to the die interconnect elements 116 and enhances the structural strength of the interconnect grains 110.

[0028] In Figures 5A through 5C, according to various embodiments, the protective layer 120 is patterned to form a protective overlay 122 surrounding the die connection element 116. In various embodiments, the protective overlay 122 is a dielectric overlay designed to provide protection, insulation, and additional structural integrity for the features underneath. Figure 5A illustrates a cross-sectional side view of the wafer-level interconnect die 110. Figure 5B illustrates an enlarged cross-sectional side view of the interconnect die 110. Figure 5C illustrates an exemplary plan view (e.g., a top cross-sectional view) of the interconnect die 110 including the die connection element 116.

[0029] For example, patterning can be performed using any acceptable process, such as first exposing the protective layer 120 (e.g., made of a photosensitive material) by a mask. The protective layer 120 can then be developed by rinsing the structure with an aqueous alkaline solution or other suitable developer after exposure. The remaining portion of the protective layer 120 can be cured to form a protective coating 122. It should be noted that the protective coating 122 can be considered as part of the interconnect grains 110.

[0030] According to some embodiments, the curing process may cause the protective overlay 122 to shrink by up to 30%. This shrinkage may cause stress and warping of the interconnect die 110. In particular, this shrinkage may create stress within the interconnect die 110 and cause warping during this stage and / or subsequent steps in the fabrication of the integrated circuit package 200. However, converting the protective layer 120 into a smaller protective overlay 122 can reduce many of the effects of shrinkage. As discussed in more detail below, the thickness and profile of the protective overlay 122 can be selected to achieve this benefit while maintaining the protection, insulation, and structural support advantages associated with the die connection element 116.

[0031] In some embodiments, there is a one-to-one correspondence between the die-connecting elements 116 and the protective coatings 122, with each protective coating 122 covering an individual die-connecting element 116. After patterning (e.g., curing), the lateral thickness T1 of each protective coating 122 along the height of the sidewall of the die-connecting element 116 can range from 10 µm to 30 µm. For example, the thickness T1 can be approximately 30% to 100% of the diameter D1 of the corresponding die-connecting element 116 (e.g., the thickness T1 can be less than or equal to the diameter D1). Specifically, a thickness T1 greater than 10 µm (or approximately 30% of the corresponding diameter D1) ensures that the die-connecting element 116 is adequately protected, insulated, and reinforced. Furthermore, a thickness T1 less than 30 µm (or approximately 100% of the corresponding diameter D1) reduces some of the effects caused by thermal expansion mismatch between the protective coating 122 and adjacent features. For example, using less protective coating 122 material can reduce stress in the interconnect grains 110, thereby reducing warpage and preventing other problems such as peeling during the manufacturing process of the integrated circuit package 200. In fact, stress accumulation and warpage can be prevented or reduced during the curing process of the protective coating 122.

[0032] Furthermore, the dimensions and other parameters selected to protect the coating 122 also achieved similar benefits in subsequent steps, which will be discussed in detail below and described in conjunction with Figures 15A to 17C.

[0033] In Figure 6, according to various embodiments, through-holes 106 are formed on a carrier substrate 102, and interconnect dies 110 are attached to the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or a similar material. The carrier substrate 102 may be a wafer, allowing multiple packages to be formed simultaneously on the carrier substrate 102. A release layer 104 may be formed on the carrier substrate 102 before forming and attaching the through-holes 106 and interconnect dies 110.

[0034] The release layer 104 can be made of a polymer-based material and can be removed from the overlying structure together with the carrier substrate 102 in a subsequent step. In some embodiments, the release layer 104 is a heat-release material based on epoxy resin that loses its adhesiveness upon heating (e.g., a light-to-heat-conversion (LTHC) release coating). In other embodiments, the release layer 104 can be an ultraviolet (UV) adhesive that loses its adhesiveness upon exposure to UV light. The release layer 104 can be applied and cured in liquid form and can be a laminate or similar structure laminated onto the carrier substrate 102. The top surface of the release layer 104 can be uniform in height and can have a high degree of flatness.

[0035] A perforation 106 is formed on the release layer 104. Although three perforations 106 are shown in the cross-sectional view, it should be understood that any number of perforations 106 can be formed, and other perforations 106 may be located in other cross-sections. As an example of forming the perforation 106, a seed layer (not shown separately) is first formed on the release layer 104. In some embodiments, the seed layer is a metal layer, which may be a single layer or a multilayer composite layer composed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer thereon. The seed layer can be formed by a deposition process, such as physical vapor deposition (PVD) or a similar process. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by methods such as spin coating and can be patterned by illumination. The pattern of the photoresist corresponds to the perforation 106. The patterning forms openings in the photoresist, exposing the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed seed layer. The conductive material can be formed through processes such as plating (e.g., electroless plating or electroplating from the seed layer). The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and the portion of the seed layer not covered by the conductive material are then removed. The photoresist can be removed through an acceptable ashing or stripping process (e.g., using oxygen plasma). Once the photoresist is removed, the exposed portion of the seed layer can be removed through an acceptable etching process (e.g., wet etching or dry etching). The remaining seed layer and conductive material form the via 106.

[0036] Single interconnect dies 110 are placed on release layer 104, laterally adjacent to via 106. After splitting, interconnect dies 110 can be placed on release layer 104 using, for example, a pick-and-place tool. Interconnect dies 110 will be used for direct communication between integrated circuit devices (described later) within integrated circuit package 200. In some embodiments, interconnect dies 110 are attached after via 106 is formed; however, these steps can be performed in reverse order. In the illustrated cross-section, two interconnect dies 110 are attached within package region 100P. It should be understood that any number of interconnect dies 110 can be attached within each package region 100P.

[0037] In Figure 7, encapsulation material 128 is formed around each component. Once formed, encapsulation material 128 laterally covers the interconnect die 110 and the through-hole 106. Encapsulation material 128 can be a molding compound, epoxy resin, or a similar material. Encapsulation material 128 can be applied by compression molding, transfer molding, or similar processes, and encapsulation material 128 can be formed on the carrier substrate 102 such that the interconnect die 110 and / or the through-hole 106 are embedded in or covered by encapsulation material 128. For example, a portion of encapsulation material 128 can be located above the top surface of the through-hole 106 and the protective capping layer 122. Encapsulation material 128 can fill the gap regions between the components. Encapsulation material 128 can be applied in a liquid or semi-liquid form and then cured. It should be noted that the protective capping layer 122 continues to protect the die connection elements 116 of the interconnect die 110 during the application of encapsulation material 128. As shown in the figure, the die connection element 116, the protective coating 122, and the encapsulation material 128 together form a sandwich structure.

[0038] In Figure 8, a removal process can be selectively performed on the package material 128 to expose the interconnect die 110 and the via 106. The removal process can remove material from the package material 128, the protective coating 122 of the interconnect die 110, and / or the via 106 until the die connection element 116 and the via 106 are exposed. The removal process may include, for example, a planarization process such as chemical-mechanical polishing (CMP), a polishing process, or a combination thereof. After the planarization process, the front surfaces of the package material 128, the interconnect die 110 (e.g., die connection element 116 and protective coating 122), and the via 106 may be substantially coplanar (within process variation). If the via 106 and the die connection element 116 have been exposed, the planarization process can be omitted. After the removal process, the via 106 passes through the package material 128. Therefore, the perforation 106 can also be called through-mold vias (TMVs).

[0039] In Figure 9, a front redistribution structure 130 is formed on the front surface of the encapsulation material 128, the interconnect die 110 (e.g., die connection element 116 and protective capping layer 122), and the through-hole 106. The front redistribution structure 130 includes a dielectric layer 132 and metallization layers 134 (sometimes referred to as redistribution layers or redistribution lines) located between the dielectric layers 132. Therefore, the metallization layers 134 in the front redistribution structure 130 are electrically connected to each other through corresponding dielectric layers 132. The metallization layers 134 of the front redistribution structure 130 are electrically connected to the through-hole 106 and the interconnect die 110 (e.g., die connection element 116).

[0040] In some embodiments, the dielectric layer 132 is made of a polymer, which may be a photosensitive material, such as a polymer based on PBO, polyimide, BCB, or similar materials, and may be patterned using a photomask. In other embodiments, the dielectric layer 132 is made of a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), or similar materials. The dielectric layer 132 may be formed by processes such as spin coating, lamination, chemical vapor deposition, or combinations thereof. After the dielectric layer 132 is formed, it may be patterned to expose underlying conductive features, such as a portion of the through-hole 106, the die connection element 116, and / or the metallization layer 134. Patterning may be performed by any acceptable process, such as exposing the dielectric layer 132 when it is made of a photosensitive material, or etching it using methods such as anisotropic etching. If the dielectric layer 132 is made of a photosensitive material, it may be developed after exposure.

[0041] The metallization layer 134 includes conductive vias and / or conductive lines. The conductive vias pass through the corresponding dielectric layer 132, while the conductive lines extend along the corresponding dielectric layer 132. As an example of forming the metallization layer 134, a seed layer (not shown separately) is first formed on the corresponding underlying feature. For example, the seed layer can be formed on the corresponding dielectric layer 132 and within any of its openings. In some embodiments, the seed layer is a metal layer, which can be a single layer or a multilayer composite layer composed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer thereon. The seed layer can be formed by a deposition process, such as physical vapor deposition (PVD) or a similar process. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by methods such as spin coating and can be patterned by illumination. The pattern of the photoresist corresponds to the metallization layer 134. The patterning forms openings in the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed seed layer. The conductive material can be formed by processes such as plating (e.g., electroless plating or electroplating from the seed layer). The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. Then, the photoresist and the portion of the seed layer not covered by the conductive material are removed. The photoresist can be removed by an acceptable ablation or stripping process (e.g., using oxygen plasma). Once the photoresist is removed, the exposed portion of the seed layer can be removed by an acceptable etching process (e.g., wet etching or dry etching). The remaining seed layer and conductive material form the metallization layer 134 of the pre-redistribution structure 130.

[0042] The front redistribution structure 130 is illustrated as an example. By repeating the above steps, more or fewer dielectric layers 132 and metallization layers 134 can be formed as needed.

[0043] Other variations of the front redistribution structure 130 are also under consideration. For example, a portion of the dielectric layer 132 may be made of an encapsulation material (such as a molding compound, epoxy resin, or similar material). A metallization layer 134 may be formed by plating conductive vias from conductive lines. The dielectric layer 132 may be formed by encapsulating the metallization layer 134. The dielectric layer 132 may employ any desired material stacking structure.

[0044] Under-bump metals (UBMs) 136 can be formed through the top dielectric layer 132 of the front redistribution structure 130. The under-bump metals 136 are physically and electrically connected to the top metallization layer 134 of the front redistribution structure 130. The under-bump metals 136 include conductive vias and conductive bumps. The conductive vias pass through the top dielectric layer 132, while the conductive bumps extend along the top dielectric layer 132. The under-bump metals 136 may be made of the same material as the metallization layer 134. In some embodiments, the dimensions of the under-bump metals 136 differ from those of the metallization layer 134.

[0045] In Figure 10, integrated circuit devices 202 are attached to the front redistribution structure 130 (e.g., under-bump metal 136). Multiple integrated circuit devices 202 are positioned adjacent to each other within package region 100P. Within each package region 100P, the integrated circuit devices 202 may include logic devices 202A and memory devices 202B. Although only one logic device 202A is shown in the cross-sectional view, it should be understood that multiple logic devices 202A can be attached. Logic devices 202A and memory devices 202B may be manufactured using the same technology node process or different technology node processes. For example, logic device 202A may be formed using a more advanced process node, while memory device 202B may use an older process node.

[0046] Each of the logic devices 202A may be a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, or a similar device. The logic device 202A may be an integrated circuit die (similar to integrated circuit die 50 described in Figure 1) or a die stack (similar to die stack 60A described in Figure 2A). In some embodiments, the logic device 202A is a system-on-a-chip (SoC) die. In other embodiments, the logic device 202A is a die stack of a system-on-a-chip (SoIC) device.

[0047] Each memory device 202B may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high-bandwidth memory (HBM) module, or a similar device. The memory device 202B may be an integrated circuit die (similar to the integrated circuit die 50 described in Figure 1) or a die stack (similar to the die stack 60B described in Figure 2B). In some embodiments, the memory device 202B is a die stack, such as a high-bandwidth memory (HBM) device.

[0048] In the illustrated embodiment, the integrated circuit device 202 is attached to the front redistribution structure 130 via solder joints (e.g., conductive connection element 204). The conductive connection element 204 may be made of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connection element 204 is first formed with a layer of solder, for example by vapor deposition, electroplating, printing, solder transfer, solder ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the conductive connection element 204 into the desired bump shape. Attaching the integrated circuit device 202 to the front redistribution structure 130 may include placing the integrated circuit device 202 on the front redistribution structure 130 and reflowing the conductive connection element 204. For example, a pick-and-place tool may be used to place the integrated circuit device 202 on the front redistribution structure 130. After reflow, the conductive connection element 204 attaches the die connection element 206 on the front side of the integrated circuit device 202 to the under-bump metal 136 of the front redistribution structure 130, thereby achieving an electrical connection between the front redistribution structure 130 and the integrated circuit device 202. Therefore, the front redistribution structure 130 and the interconnect die 110 electrically connect the integrated circuit device 202 to each other (e.g., electrically couple memory device 202B to logic device 202A). In another embodiment, the integrated circuit device 202 is attached to the front redistribution structure 130 by direct bonding and using the die connection element 206.

[0049] In Figure 11, an underfill element 210 can be formed around the conductive connection element 204 and between the front redistribution structure 130 and the integrated circuit device 202. The underfill element 210 can reduce stress and protect the contacts formed by the backflow of the conductive connection element 204. The underfill element 210 can be made of an underfill material, such as a molding compound, epoxy resin, or similar material. The underfill element 210 can be formed by a capillary flow process after the integrated circuit device 202 is attached to the front redistribution structure 130, or it can be formed by a suitable deposition method before the integrated circuit device 202 is attached to the front redistribution structure 130. The underfill element 210 can be applied in a liquid or semi-liquid form and then cured.

[0050] Encapsulation material 212 is formed around each component. After forming, encapsulation material 212 laterally covers the underfill element 210 (if present) and the integrated circuit device 202. Encapsulation material 212 may be a molding compound, epoxy resin, or similar material. Encapsulation material 212 can be applied by compression molding, transfer molding, or similar processes and can be formed on the front redistribution structure 130, so that the integrated circuit device 202 is embedded or covered. Encapsulation material 212 may also fill the gap area between the underfill element 210 (if present) and / or the integrated circuit device 202. Encapsulation material 212 can be applied in liquid or semi-liquid form and then cured.

[0051] A removal process can be selectively performed on the package material 212 to expose the integrated circuit device 202. The removal process may include, for example, chemical mechanical polishing (CMP), polishing, or similar processes. After the planarization process, the top surfaces of the package material 212 and the integrated circuit device 202 may be substantially coplanar (within the range of process variations). If the integrated circuit device 202 has already been exposed, the planarization process can be omitted.

[0052] In Figure 12, a debonding process is performed on the carrier substrate to separate (or "debond") the carrier substrate 102 from the back surface of the interposer wafer 100. According to some embodiments, the debonding process includes projecting light (e.g., laser light or ultraviolet light) onto a release layer 104, causing the release layer 104 to decompose under photothermal effects, thereby removing the carrier substrate 102. The interposer wafer 100 is then flipped, ready for subsequent processing on its back side. The interposer wafer 100 may be placed on tape, a carrier substrate, or other suitable support structure (not shown separately) for subsequent processing.

[0053] Next, a removal process can be performed on the substrate 112 and the encapsulation material 128 to expose the vias 106 and 114. The removal process can remove material from the encapsulation material 128, the interconnect die 110 (e.g., substrate 112 and substrate vias 114), and / or the vias 106 until the substrate vias 114 and 106 are exposed. The removal process may include, for example, chemical mechanical polishing (CMP), a polishing process, or a similar process. After the planarization process, the back surfaces of the encapsulation material 128, the interconnect die 110 (e.g., substrate 112 and substrate vias 114), and the vias 106 may be substantially coplanar (within the range of process variations).

[0054] Several advantages are derived from forming the protective capping layer 122 (see Figures 4A through 5C) during the removal process. As previously described, the protective capping layer 122 has a specific dimensional design that reduces stress and warpage in the interconnect die 110. By preventing or reducing such warpage, the removal process can be performed more efficiently to expose the substrate vias 114. Furthermore, since almost all substrate vias 114 can be exposed during the removal process (e.g., within specified process parameters such as duration, rotational speed, and abrasion), the yield of the removal process is also higher. This avoids certain defects, such as substrate via blind defects (TSVs), where some substrate vias 114 are not exposed after the removal process (e.g., still covered by the substrate 112).

[0055] In Figure 13, a back-side redistribution structure 150 is formed on the back-side surfaces of the packaging material 128, the interconnect die 110 (e.g., substrate 112 and substrate through-hole 114), and the through-hole 106. The back-side redistribution structure 150 includes a dielectric layer 152 and metallization layers 154 (sometimes referred to as redistribution layers or redistribution lines) located between the dielectric layers 152. Therefore, the metallization layers 154 in the back-side redistribution structure 150 are electrically connected to each other through corresponding dielectric layers 152. The metallization layers 154 of the back-side redistribution structure 150 are electrically connected to the through-hole 106 and the interconnect die 110 (e.g., substrate through-hole 114). Therefore, the back-side redistribution structure 150 is electrically connected to the front-side redistribution structure 130 through an intermediate wafer 100 (e.g., through-hole 106 and interconnect die 110).

[0056] In some embodiments, dielectric layer 152 is made of a polymer, which may be a photosensitive material that can be patterned by photolithography, such as a polymer based on PBO, polyimide, BCB, or similar materials. In other embodiments, dielectric layer 152 is made of a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), or similar materials. Dielectric layer 152 can be formed by processes such as spin coating, lamination, chemical vapor deposition (CVD), or combinations thereof. After dielectric layer 152 is formed, it can be patterned to expose underlying conductive features, such as through-hole 106, substrate through-hole 114, and / or a portion of metallization layer 154. Patterning can be performed by any acceptable process, such as exposing the dielectric layer when it is made of a photosensitive material, or etching using methods such as anisotropic etching. If dielectric layer 152 is made of a photosensitive material, it can be developed after exposure.

[0057] The metallization layer 154 includes conductive vias and / or conductive lines. The conductive vias pass through the corresponding dielectric layer 152, while the conductive lines extend along the corresponding dielectric layer 152. As an example of forming the metallization layer 154, a seed layer (not shown separately) is first formed on the corresponding underlying feature. For example, the seed layer can be formed on the corresponding dielectric layer 152 and within any opening therein. In some embodiments, the seed layer is a metal layer, which can be a single layer or a multilayer composite layer composed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer thereon. The seed layer can be formed by a deposition process, such as physical vapor deposition (PVD) or a similar process. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by methods such as spin coating and can be patterned by illumination. The pattern of the photoresist corresponds to the metallization layer 154. The patterning forms openings in the photoresist and exposes the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed seed layer. The conductive material can be formed through processes such as plating (e.g., electroless plating or electroplating from the seed layer). The conductive material may include metals or metal alloys, such as copper, titanium, tungsten, aluminum, or combinations thereof. Then, the photoresist and the portion of the seed layer not covered by the conductive material are removed. The photoresist can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma). Once the photoresist is removed, the exposed portion of the seed layer can be removed by an acceptable etching process (e.g., wet etching or dry etching). The remaining seed layer and conductive material form the metallization layer 154 of the back-side redistribution structure 150.

[0058] The backside redistribution structure 150 is illustrated as an example. By repeating the above steps, more or fewer dielectric layers 152 and metallization layers 154 can be formed as needed.

[0059] Other variations of the backside redistribution structure 150 are also under consideration. For example, a portion of the dielectric layer 152 may be made of an encapsulation material (such as a molding compound, epoxy resin, or similar material). The metallization layer 154 may be formed by plating conductive vias from conductive lines. The dielectric layer 152 may be formed by encapsulating the metallization layer 154. The dielectric layer 152 may employ any desired material stacking structure.

[0060] Under-bump metals (UBMs) 156 can be formed through the lower dielectric layer 152 of the back-side redistribution structure 150. The under-bump metals 156 are physically and electrically connected to the lower metallization layer 154 of the back-side redistribution structure 150. The under-bump metals 156 include conductive vias and conductive bumps. The conductive vias pass through the lower dielectric layer 152, while the conductive bumps extend along the lower dielectric layer 152. The under-bump metals 156 may be made of the same material as the metallization layer 154. In some embodiments, the dimensions of the under-bump metals 156 differ from those of the metallization layer 154.

[0061] In Figure 14, the package substrate 220 is attached to the intermediate wafer 100 (e.g., the back-side redistribution structure 150). The package substrate 220 includes a substrate core 222, which may be made of silicon, germanium, diamond, or similar semiconductor materials. Alternatively, composite materials may be used, such as germanium-silicon, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, germanium-silicon carbide, germanium arsenide phosphide, indium germanium phosphide, or combinations thereof. Furthermore, the substrate core 222 may also be an SOI substrate. Generally, an SOI substrate includes a single layer of semiconductor material, such as a silicon layer, a germanium layer, a germanium-silicon layer, or combinations thereof. In some embodiments, the substrate core 222 is an insulating core, such as a glass fiber reinforced resin core. An example core material is glass fiber resin, such as FR4. Other core material options include bismaleimide-triazine (BT) resin, or other printed circuit board (PCB) materials or films. The substrate core 222 can also use a building film, such as Ajinomoto build-up film (ABF) or other laminated materials.

[0062] The substrate core 222 may include passive and / or active devices (not shown separately). For example, devices such as transistors, capacitors, resistors, or combinations thereof may be used to fulfill the structural and functional requirements of the system design. These devices can be manufactured using any suitable method. In some embodiments, the substrate core 222 substantially does not include active or passive devices.

[0063] The substrate core 222 may also include a metallization layer (not shown separately). The package substrate 220 further includes bonding pads 224 located above the metallization layer of the substrate core 222. The metallization layer can be formed on passive and / or active devices and is designed to connect various components to form functional circuits. The metallization layer can be formed from alternating dielectric materials (e.g., low dielectric constant materials) and conductive materials (e.g., copper), and the conductive materials are connected by vias. These metallization layers can be formed using any suitable process, such as deposition, damascene, etc.

[0064] The package substrate 220 can be attached to the back-side redistribution structure 150 via soldering (e.g., conductive connection element 226). The conductive connection element 226 can be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or a similar structure. The conductive connection element 226 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive connection element 226 is formed by initially forming a layer of solder using one of the following methods: vapor deposition, electroplating, printing, solder transfer, solder ball placement, etc. After a layer of solder is formed structurally, reflow can be performed to shape the solder into the desired bump shape for the conductive connection element 226. Attaching the package substrate 220 to the back-side redistribution structure 150 may include placing the package substrate 220 on the back-side redistribution structure 150 and reflowing the conductive connection element 226. The package substrate 220 may be placed on the back-side redistribution structure 150 using, for example, a pick-and-place tool. After reflowing, the conductive connection element 226 connects the bonding pads 224 of the package substrate 220 to the under-bump metal 156 of the back-side redistribution structure 150. The conductive connection element 226 connects the intermediate wafer 100 (including the metallization layer of the back-side redistribution structure 150) to the package substrate 220 (including the metallization layer of the substrate core 222). Thus, the package substrate 220 is electrically connected to the integrated circuit device 202 within the package region 100P.

[0065] Furthermore, the passive device (not shown separately) may be attached to the interposer wafer 100 and / or the package substrate 220. For example, the passive device may be attached to the interposer wafer 100, such as to the same surface as the conductive interconnect element 226 on the back-side redistribution structure 150. Alternatively, the passive device may be attached to the package substrate 220, such as to the same surface as the conductive interconnect element 226 on the package substrate 220. The passive device may include capacitors, resistors, inductors, or combinations thereof. The passive device may be a surface mount device (SMD), a two-terminal integrated passive device (IPD), a multi-terminal integrated passive device, or a similar structure.

[0066] In some embodiments, an encapsulation material 232 is formed around each component. Once formed, the encapsulation material 232 laterally covers the passive device (if present), the conductive connection element 226, and the encapsulation substrate 220. The encapsulation material 232 may be formed between the encapsulation substrate 220 and the back-side redistribution structure 150. The encapsulation material 232 may be a molding compound, epoxy resin, or a similar material. The encapsulation material 232 may be applied by compression molding, transfer molding, or similar processes, and may be applied in a liquid or semi-liquid form, followed by curing.

[0067] Furthermore, a single-chip process (not shown separately) can be performed by cutting along a dicing region between package region 100P and adjacent package regions. The single-chip process may include sawing, dicing, or similar processes. The single-chip process singles the package regions from one another. The single-chip integrated circuit package 200 originates from package region 100P. The single-chip process forms an interposer 240, which originates from a single-chip portion of the interposer wafer 100. Due to the single-chip process, the outer walls of the interposer 240, package material 212, and package material 232 are substantially collinear laterally (within the range of process variations).

[0068] Figures 15A to 15C are plan views (e.g., top cross-sectional views) of exemplary layouts of interconnect grains 110 in the interposer layer 100 / 240, according to various embodiments. It should be noted that the interconnect grains 110 shown may represent an overall plan view or a portion thereof, depending on the features to be emphasized and described. For example, the shown grain interconnect elements 116 may have a greater number or a different layout, depending on the features to be emphasized and described.

[0069] In the illustrated embodiment, similar to the description above (see Figures 5A to 5C), the first protective cladding 122A may have a thickness TA around the sidewall of the first die-connecting element 116A. Furthermore, the second protective cladding 122B may have a thickness TB around the sidewall of the second die-connecting element 116B, wherein the thickness TB is greater than the thickness TA. According to various embodiments, both the thickness TA and the thickness TB may fall within the range described above regarding thickness T1.

[0070] Forming a protective coating 122 with varying thicknesses offers several advantages. For example, shrinkage of the protective coating 122 during curing (see Figures 5A to 5C) may be exacerbated by subsequent steps, such as the monolithization of interconnect dies 110 (see Figure 6), compression and polishing of the encapsulation material 128 (see Figures 7 and 8), removal of the carrier substrate 102 (see Figure 12), and the exposure of TSVs (see Figure 12). Specific areas of the interconnect dies 110 may be more susceptible to warping due to factors such as proximity to corners, the size of the corresponding die-connecting elements 116, or the layout density of the die-connecting elements 116.

[0071] Referring to Figure 15A, the first die connection element 116A may be located near a corner of the interconnect die 110. In this embodiment, the corner of the interconnect die 110 may be particularly susceptible to warping. Therefore, the first die connection element 116A may have a thinner first protective cladding 122A (thickness TA) to prevent or reduce warping near the corner of the interconnect die 110. Furthermore, the second die connection element 116B may have a thicker second protective cladding 122B (thickness TB) to provide greater insulation and structural support, since the second die connection element 116B may be located in a region of the interconnect die 110 less susceptible to warping (e.g., near the center or away from the corner).

[0072] Referring to Figure 15B, the first die connection element 116A may be located near the corners and edges of the interconnect die 110. In this embodiment, the corners and edges of the interconnect die 110 may be particularly susceptible to warping. Therefore, the first die connection element 116A may have a thinner first protective cladding 122A (thickness TA) to prevent or reduce warping near the corners and edges of the interconnect die 110. Furthermore, the second die connection element 116B may have a thicker second protective cladding 122B (thickness TB) to provide greater insulation and structural support.

[0073] Referring to Figure 15C, the first die connection element 116A may be located near the central region of the interconnect die 110, while the second die connection element 116B may be located near the peripheral region of the interconnect die 110. In this embodiment, the central region of the interconnect die 110 may be particularly susceptible to warping. Therefore, the first die connection element 116A may have a thinner first protective coating 122A (thickness TA) to prevent or reduce warping of the interconnect die 110. Furthermore, the second die connection element 116B may have a thicker second protective coating 122B (thickness TB) to provide greater insulation and structural support.

[0074] Referring again to Figures 15A through 15C, the first die-connecting element 116A may have a diameter DA, while the second die-connecting element 116B may have a diameter DB. Diameters DA and DB may be substantially the same, or diameter DB may be greater than or less than diameter DA. In some embodiments, the thicknesses TA and TB of the first protective coating 122A and the second protective coating 122B may be based on the respective diameters DA and DB of the first die-connecting element 116A and the second die-connecting element 116B. For example, the die-connecting element 116 with a larger diameter may have a thicker protective coating 122, and vice versa. According to various embodiments, both diameters DA and DB may fall within the aforementioned dimensional range related to the lateral diameter D1.

[0075] Figures 16A and 16B are plan views (e.g., top cross-sectional views) of an exemplary layout of interconnect grains 110 in the interposer layer 100 / 240, according to various embodiments. It should be noted that the illustrated interconnect grains 110 may represent an overall plan view or a portion thereof, depending on the features to be emphasized and described. For example, the illustrated grain connection elements 116 may have a greater number or a different layout, depending on the features to be emphasized and described. In the illustrated embodiment, similar to the description above (see Figures 5A to 5C), the first protective cladding layer 122A may have a thickness TA (e.g., one-to-one correspondence) around the sidewalls corresponding to the first grain connection elements 116A. Furthermore, a single second protective cladding layer 122B may surround the sidewalls of multiple second grain connection elements 116B. The second protective cladding layer 122B may have a thickness TA in some portions and a larger thickness TB in other portions (e.g., between adjacent second grain connection elements 116B). According to various embodiments, the thicknesses TA and TB may fall within the dimensional range described above related to thickness T1.

[0076] Forming a first protective coating 122A corresponding one-to-one with the first die-connecting element 116A, and a second protective coating 122B covering multiple second die-connecting elements 116B, offers several advantages. For example, the shrinkage of the protective coating 122 during curing (see Figures 5A to 5C) may be exacerbated by subsequent steps, such as the monolithization of the interconnect die 110 (see Figure 6), the compression and polishing of the encapsulation material 128 (see Figures 7 and 8), the removal of the carrier substrate 102 (see Figure 12), and the exposure process of TSVs (see Figure 12). Therefore, the first protective coating 122A can achieve similar benefits to those associated with the foregoing embodiments. Furthermore, the second die-connecting elements 116B can be arranged with a higher pattern density, making a separate second protective coating 122B less feasible. Therefore, a single second protective coating 122B surrounding multiple second die connection elements 116B can prevent the effects caused by the mismatch in the coefficient of thermal expansion between the second protective coating 122B and the encapsulation material 128 (e.g., preventing warping and peeling).

[0077] It should be noted that the difference in pattern density between the first die connector 116A and the second die connector 116B can be attributed to one or more factors. For example, the diameter DA of the first die connector 116A may be smaller than the diameter DB of the second die connector 116B. Furthermore, the spacing PA of the first die connector 116A may be greater than the spacing PB of the second die connector 116B. Additionally, the geometric layout may differ; for example, some die connectors 116 may be arranged in a lower density layout (e.g., a square arrangement as shown), while other die connectors 116 may be arranged in a higher density layout (e.g., a triangular or hexagonal arrangement). It should be noted that any combination of these factors can lead to differences in pattern density between the die connectors 116.

[0078] Referring to Figure 16A, the first die-connecting element 116A may be located near the peripheral region of the interconnect die 110, while the second die-connecting element 116B may be located near the central region of the interconnect die 110. In this embodiment, the second die-connecting elements 116B may be arranged with a higher pattern density than the first die-connecting elements 116A. Therefore, each first protective coating 122A surrounds a single first die-connecting element 116A, while the second protective coating 122B surrounds multiple second die-connecting elements 116B in a merged structure, these second die-connecting elements 116B having a smaller spacing PB and / or a larger diameter DB (compared to the first die-connecting elements 116A). It should be noted that multiple second protective coatings 122B may exist, each second protective coating 122B surrounding a different group or set of second die-connecting elements 116B.

[0079] Referring to Figure 16B, the first die-connecting element 116A may be located near the central region of the interconnect die 110, while the second die-connecting element 116B may be located near the peripheral region of the interconnect die 110. In this embodiment, the second die-connecting elements 116B can be arranged with a higher pattern density than the first die-connecting elements 116A. Therefore, each first protective coating 122A surrounds a single first die-connecting element 116A, while the second protective coating 122B surrounds multiple second die-connecting elements 116B in a merged structure, these second die-connecting elements 116B having a smaller spacing PB and / or a larger diameter DB (compared to the first die-connecting elements 116A). As shown, the second protective coating 122B can form a continuous ring surrounding part or all of the first die-connecting elements 116A and their corresponding first protective coating 122A. Furthermore, multiple second protective coatings 122B may exist, each surrounding a different group of second die-connecting elements 116B. For example, the second protective coating 122B may form a discontinuous ring surrounding part or all of the first grain connection element 116A and its first protective coating 122A.

[0080] Referring again to Figures 16A and 16B, the first die-connecting element 116A may have a diameter DA, while the second die-connecting element 116B has a minimum diameter DB. Diameters DA and DB may be substantially the same, or diameter DB may be greater than or less than diameter DA. In some embodiments, the thicknesses TA and TB of the first protective coating 122A and the second protective coating 122B may be based on the respective diameters DA and DB of the first die-connecting element 116A and the second die-connecting element 116B. For example, the die-connecting element 116 with a larger diameter may have a thicker protective coating 122, and vice versa. According to various embodiments, both diameters DA and DB may fall within the aforementioned dimensional range related to the lateral diameter D1.

[0081] Figures 17A to 17C are exemplary close-up cross-sectional side views of interconnect grains 110 in the interposer layer 100 / 240, according to various embodiments. The figures illustrate various cross-sectional shapes of the protective cladding layer 122, which provide various benefits described in detail below.

[0082] Referring to Figure 17A, the protective cladding 122 may have a straight or rectangular cross-sectional shape around the die-connecting element 116. For example, a process that patterns the protective layer 120 into the protective cladding 122 (see Figures 5A through 5C) can make the protective cladding 122 have substantially the same thickness T1 along the height of the die-connecting element 116 (e.g., from the bridging die 118 to the front redistribution structure 130). Thus, the sidewalls of the die-connecting element 116 can achieve consistent protection, insulation, and structural support.

[0083] Referring to Figure 17B, the protective coating 122 may have sloping sidewalls, forming an upright trapezoidal cross-sectional shape (e.g., an upright right-angled triangle on each side) surrounding the die-connecting element 116. Specifically, the process of patterning the protective layer 120 into the protective coating 122 can be designed to achieve this cross-sectional shape. For example, positive lithography can be used to expose portions of the protective layer 120 that will be removed by the developer, thereby leaving the remaining portion to form the protective coating 122. In some embodiments, the upper portion of the protective layer 120 near the mask (e.g., the portion close to the mask and far from the bridging die 118) receives more light exposure than the lower portion of the protective layer 120 farther from the mask (e.g., the portion far from the mask and close to the bridging die 118). Therefore, the exposed portions of the protective layer 120 may have V-shaped sidewalls, and after these exposed portions are removed during development, the protective coating 122 may exhibit an upright trapezoidal cross-sectional shape (e.g., an upright right-angled triangle on each side). It should be noted that the protective coating 122 may have minimum and maximum thicknesses along the sidewalls of the grain interconnect element 116, and these thicknesses may fall within the aforementioned dimensional range related to thickness T1. As shown, the protective coating 122 of some grain interconnect elements 116 near the periphery of the interconnect grain 110 may extend into the cut area. Therefore, these trapezoidal cross-sectional shapes (e.g., right-angled triangular portions along the sidewalls) can be removed during the single-piece fabrication process.

[0084] The protective cladding 122, with its upright trapezoidal cross-section, offers additional benefits. Specifically, the thicker portions of the protective cladding 122 provide enhanced protection for areas of the interconnect grains 110 that require additional protection (e.g., some upper conductive features of the bridging grains 118). Furthermore, the thinner portions of the protective cladding 122 reduce the aforementioned thermal expansion mismatch effects, particularly in the intermediate layers 100 / 240 near other components, thereby mitigating delamination risks, such as those associated with the front redistribution structure 130.

[0085] Referring to Figure 17C, the protective coating 122 may have sloping sidewalls, forming an inverted trapezoidal cross-sectional shape (e.g., an inverted right triangle on each side) surrounding the die-connecting element 116. Specifically, the process of patterning the protective layer 120 into the protective coating 122 can be designed to achieve this cross-sectional shape. For example, negative lithography can be used to expose portions of the protective layer 120 that will be retained (e.g., not removed by the developer), thereby forming the protective coating 122. In some embodiments, the upper portion of the protective layer 120 closer to the mask (e.g., the portion close to the mask and away from the bridging die 118) receives more light exposure than the lower portion of the protective layer 120 farther from the mask (e.g., the portion away from the mask and close to the bridging die 118). Therefore, the exposed portions of the protective layer 120 may have V-shaped sidewalls, which, after the development process, retain the inverted trapezoidal cross-sectional shape (e.g., an inverted right triangle on each side) of the protective coating 122. It should be noted that the protective coating 122 may have minimum and maximum thicknesses along the sidewalls of the grain interconnect element 116, and these thicknesses may fall within the aforementioned dimensional range related to thickness T1. As shown, for some grain interconnect elements 116 near the periphery of the interconnect grain 110, the protective coating 122 may extend into the cut area. Therefore, these trapezoidal cross-sectional portions (e.g., right-angled triangles along the sidewalls) can be removed during the single-piece fabrication process.

[0086] The inverted trapezoidal cross-sectional shape of the protective cladding 122 provides additional benefits. Specifically, the thicker portions of the protective cladding 122 can provide enhanced protection for certain areas of the interposer 100 / 240 that require additional protection (e.g., some lower conductive features of the front redistribution structure 130). Furthermore, the thinner portions of the protective cladding 122 can reduce the aforementioned thermal expansion mismatch effect, particularly in the portion of the interconnect grains 110 close to other components, thereby reducing the stress and warpage risk of the interconnect grains 110, such as the risks associated with the bridging grains 118 of the interconnect grains 110.

[0087] Various embodiments offer a number of advantages. The interconnect die 110 includes die connection elements 116 that facilitate electrical connections between the interconnect die 110 and various other elements (and the overall integrated circuit package 200) in the interposer 100 / 240. Therefore, a protective overlay 122 is formed over and around the die connection elements 116 to protect the conductive material of the die connection elements 116 while providing insulation and structural support. In some embodiments, forming the protective overlay 122 may include a curing process that may introduce stress into the interconnect die 110 and potentially cause warping of the interconnect die 110. Therefore, forming the protective overlay 122 with a limited thickness provides the aforementioned benefits while reducing such stress and minimizing or preventing such warping. In addition, the interconnect die 110 may have flatter front and back surfaces that are beneficial to subsequent processes, such as the formation of the front redistribution structure 130, the exposure of the substrate through-hole 114 of the interconnect die 110, and the formation of the back redistribution structure 150.

[0088] This disclosure provides a method for forming a semiconductor device, including forming an interconnect die, the interconnect die including a plurality of through-holes partially extending through a semiconductor substrate, an interconnect structure located on the semiconductor substrate, and a plurality of die connection elements located on the interconnect structure. A protective layer is applied to the die connection elements, and then the protective layer is patterned to form a plurality of protective overlays around the die connection elements. An encapsulation material is formed above and around the interconnect die and the protective overlays. A first planarization process is performed to make the encapsulation material, the protective overlays, and the die connection elements level. A first redistribution structure is formed above the die connection elements, and the first redistribution structure is electrically connected to the die connection elements. In some embodiments, a first thickness of a first group of protective overlays is greater than a second thickness of a second group of protective overlays. In some embodiments, in a top cross-sectional view, the first group is located near the peripheral region of the interconnect die, while in a top cross-sectional view, the second group is located near the central region of the interconnect die. In some embodiments, in a top cross-sectional view, the first group is located near the central region of the interconnect dies, while in a top cross-sectional view, the second group is located near the peripheral region of the interconnect dies. In some embodiments, a single protective overlay of the first group of protective overlays covers the first group of die interconnect elements, while the second group of protective overlays covers the second group of die interconnect elements on a one-to-one basis. In some embodiments, the first pattern density of the first group of die interconnect elements is greater than the second pattern density of the second group of die interconnect elements. In some embodiments, the method of forming a semiconductor device further includes attaching interconnect dies to a substrate after patterning a protective layer, and attaching a plurality of integrated circuit dies to a first redistribution structure. In some embodiments, the method of forming a semiconductor device further includes removing the substrate, performing a planarization process to expose substrate vias of the interconnect dies, and forming a second redistribution structure above the substrate vias, wherein the second redistribution structure is electrically connected to the substrate vias.

[0089] This disclosure provides a method for forming a semiconductor device, including forming interconnect dies. Forming the interconnect dies includes: forming through-holes partially through a substrate; forming an interconnect structure over the substrate; forming a first die connection element and a second die connection element over the interconnect structure; forming a first dielectric coating over the first die connection element; and forming a second dielectric coating over the second die connection element. The method further includes attaching the interconnect dies to a carrier substrate; forming an encapsulation material over and around the interconnect dies; planarizing the encapsulation material to expose the first die connection element and the second die connection element; forming a first redistribution structure over the encapsulation material, the first die connection element, and the second die connection element; and attaching an integrated circuit die to the first redistribution structure. In some embodiments, forming the first and second dielectric coatings includes depositing a dielectric layer over the first and second die connection elements and patterning the dielectric layer to form the first and second dielectric coatings. In some embodiments, the first thickness of the first dielectric coating is less than the second thickness of the second dielectric coating. In some embodiments, the first die connection element is located near the peripheral region of the interconnect die, while the second die connection element is located near the central region of the interconnect die. In some embodiments, the method of forming a semiconductor device further includes forming a third die connection element over the interconnect structure, wherein the second dielectric coating is disposed along the sidewalls of the second and third die connection elements respectively. In some embodiments, in a side cross-sectional view, both the first and second dielectric coatings include an upright right-angled triangular profile shape.

[0090] This disclosure provides a semiconductor device including a back-side redistribution structure disposed above a packaging substrate, a packaging material disposed above the back-side redistribution structure, a front-side redistribution structure disposed above the packaging material, a through-hole embedded in the packaging material and electrically coupled to the front-side redistribution structure, and an interconnect die embedded in the packaging material. The interconnect die includes a semiconductor substrate, an interconnect structure disposed above the semiconductor substrate, a first die connection element disposed above the interconnect structure and electrically connected to the front-side redistribution structure, and a first dielectric coating layer directly between the first die connection element and the packaging material, wherein the first lateral thickness of the first dielectric coating layer is smaller than the first lateral diameter of the first die connection element. In some embodiments, the interconnect die further includes a second die connection element disposed above the interconnect structure and a second dielectric coating layer directly between the second die connection element and the packaging material. In some embodiments, the second lateral thickness of the second dielectric coating layer is greater than the first lateral thickness of the first dielectric coating layer. In some embodiments, the second lateral diameter of the second die connection element is the same as the first lateral diameter. In some embodiments, the first die connection element is located near the peripheral region of the interconnect die, while the second die connection element is located near the central region of the interconnect die. In some embodiments, the semiconductor device further includes a memory device and a logic device attached to the front redistribution structure, wherein the front redistribution structure and the interconnect die electrically couple the memory device to the logic device.

[0091] The foregoing outlines the features of many embodiments, thus enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art can readily design or modify other processes and structures based on this disclosure to achieve the same objectives and / or obtain the same advantages as the embodiments disclosed herein. Those skilled in the art should also understand that various changes, substitutions, and modifications made without departing from the spirit and scope of this disclosure constitute equivalent creations that do not exceed the spirit and scope of this disclosure.

[0092] 50: Integrated circuit die 50A: First integrated circuit die 50B: Second Integrated Circuit Die 50F: Front 52: Semiconductor substrate 54: Internal Wiring Structure 56: Diode Interconnect Components 58: Dielectric layer 60A, 60B: Grain stacking 62: Conductive Through-hole 100: Intermediate wafer (intermediate layer) 100P: Package area 102: Supporting substrate 104: Release Layer 106: Perforation 110: Interconnection grains 110S: Cutting Zone 112:Substrate 114:Substrate perforation 116: Diode Interconnect Component 116A: First die interconnect element 116B: Second-stage die bonding element 118: Bridging Grains 120: Protective layer 122: Protective coating 122A: First protective coating 122B: Second protective coating 128: Packaging Material 130: Frontal redistribution structure 132, 152: Dielectric layer 134, 154: Metallization layer 136, 156: Under-bump metal 150: Backside redistribution structure 200: Integrated circuit package 202: Integrated circuit device 202A: Logic Device 202B: Memory Device 204, 226: Conductive connecting elements 206: Diode Interconnect Component 210: Bottom Filling Element 212, 232: Packaging materials 220: Packaging substrate 222: Substrate Core 224: Joint Pad 240: Intermediary Layer D1,DA,DB: Diameter E1, E2: Length H1: Height P1, PA, PB: Spacing T1, TA, TB: Thickness

Claims

1. A method of forming a semiconductor device, comprising: An interconnect die is formed, the interconnect die comprising: a plurality of through-holes partially extending through a semiconductor substrate; an interconnect structure located above the semiconductor substrate; and a plurality of die connection elements located above the interconnect structure; a protective layer is applied to the die connection elements; the protective layer is patterned to form a plurality of protective coatings around the die connection elements; an encapsulation material is formed above and around the interconnect die and the protective coatings; a first planarization process is performed to make the encapsulation material, the protective coatings, and the die connection elements level; and a first redistribution structure is formed above the die connection elements, the first redistribution structure being electrically connected to the die connection elements.

2. The method of forming a semiconductor device as described in claim 1, wherein a first thickness of a first group of the protective coatings is greater than a second thickness of a second group of the protective coatings.

3. The method of forming a semiconductor device as claimed in claim 2, wherein in a top cross-sectional view, the first group is located near a peripheral region of the interconnect die, and in the top cross-sectional view, the second group is located near a central region of the interconnect die.

4. The method of forming a semiconductor device as claimed in claim 2, wherein a single protective coating of the first group of the protective coatings covers a first group of the die interconnects, and the second group of the protective coatings covers a second group of the die interconnects in a one-to-one manner, wherein a first pattern density of one of the first group of the die interconnects is greater than a second pattern density of one of the second group of the die interconnects.

5. A method of forming a semiconductor device, comprising: Forming an interconnect die, wherein forming the interconnect die includes: forming a through-hole partially through a substrate; forming an interconnect structure on the substrate; forming a first die connection element and a second die connection element on the interconnect structure; forming a first dielectric coating on the first die connection element and a second dielectric coating on the second die connection element; attaching the interconnect die to a carrier substrate; forming an encapsulation material on and around the interconnect die; planarizing the encapsulation material to expose the first die connection element and the second die connection element; forming a first redistribution structure on the encapsulation material, the first die connection element, and the second die connection element; and attaching an integrated circuit die to the first redistribution structure.

6. The method of forming a semiconductor device as described in claim 5, wherein forming the first dielectric coating and the second dielectric coating comprises: A dielectric layer is deposited over the first and second grain connection elements; And patterning the dielectric layer to form the first dielectric coating and the second dielectric coating.

7. The method of forming a semiconductor device as described in claim 5 further includes forming a third die connection element above the interconnect structure, wherein the second dielectric coating is disposed along the sidewalls of the second die connection element and the third die connection element, respectively.

8. A semiconductor device, comprising: A back-side weighted distribution structure is disposed above a packaging substrate; An encapsulation material is disposed above the back-side redistribution structure; A front redistribution structure is disposed above the encapsulation material; a molding through-hole is embedded in the encapsulation material and electrically couples the front redistribution structure to the back redistribution structure. And an interconnect die embedded in the packaging material, the interconnect die comprising: a semiconductor substrate; An interconnect structure is disposed above the semiconductor substrate; a first die connection element is disposed above the interconnect structure and electrically connected to the front redistribution structure; and a first dielectric coating is directly between the first die connection element and the packaging material, wherein a first lateral thickness of one of the first dielectric coatings is smaller than a first lateral diameter of one of the first die connection elements.

9. The semiconductor device as claimed in claim 8, wherein the interconnect die further comprises: A second grain connection element is disposed above the interconnect structure; And a second dielectric coating, directly between the second die connection element and the encapsulation material.

10. The semiconductor device of claim 9, wherein the second lateral thickness of one of the second dielectric layers is greater than the first lateral thickness of the first dielectric layer, wherein the second lateral diameter of one of the second die connection elements is the same as the first lateral diameter, wherein the first die connection element is located near the peripheral region of one of the interconnect dies, and the second die connection element is located near the central region of one of the interconnect dies.

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