Semiconductor device with self-aligning contact

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a fin; a gate structure located on the fin, wherein the gate structure includes a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer; a plurality of impurity regions located on both sides of the fin; a plurality of contacts correspondingly located on the impurity regions; and a plurality of conductive capping layers correspondingly located on the contacts; wherein the contacts include a plurality of lower portions correspondingly located on the impurity regions, a plurality of intermediate portions correspondingly located on the lower portions, and a plurality of higher portions correspondingly located on the intermediate portions.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 773,874 (i.e., priority date "July 16, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having a resistance reduction element and a method for fabricating the same. Prior Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are becoming increasingly common. Therefore, challenges remain in reducing complexity while improving quality, yield, performance, and reliability.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above description of "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device, comprising: a fin; a gate structure located on the fin, wherein the gate structure includes a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer, wherein the gate dielectric layer is located on the fin, the gate bottom conductive layer is located on the gate dielectric layer, the gate top conductive layer is located on the gate bottom conductive layer, and the gate capping layer is located on the gate top conductive layer; a plurality of impurity regions located on both sides of the fin; a plurality of contacts correspondingly located on the impurity regions; and a plurality of conductive capping layers correspondingly located on the contacts; wherein the contacts include: a plurality of lower portions correspondingly located on the impurity regions, a plurality of intermediate portions correspondingly located on the lower portions, and a plurality of higher portions correspondingly located on the intermediate portions.

[0006] Another aspect of this disclosure provides a semiconductor device, comprising: a fin; a gate structure located on the fin, wherein the gate structure includes a gate dielectric layer, a bottom gate conductive layer, a top gate conductive layer, and a gate capping layer, wherein the gate dielectric layer is located on the fin, the bottom gate conductive layer is located on the gate dielectric layer, the top gate conductive layer is located on the bottom gate conductive layer, and the gate capping layer is located on the top gate conductive layer; and a plurality of impurity regions located on both sides of the fin. The device comprises: a domain; a plurality of contacts located on the impurity regions; and a plurality of top conductive layers located on the contacts, wherein the top conductive layers include titanium silicon, nickel silicon, nickel platinum silicon, tantalum silicon, or cobalt silicon; wherein the contacts include: a plurality of lower portions correspondingly located on the impurity regions, a plurality of intermediate portions correspondingly located on the lower portions, and a plurality of higher portions correspondingly located on the intermediate portions; wherein a width of the higher portions is greater than a width of the intermediate portions.

[0007] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: forming a gate structure on a fin, wherein the gate structure includes a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer, wherein the gate dielectric layer is formed on the fin, the gate bottom conductive layer is formed on the gate dielectric layer, the gate top conductive layer is formed on the gate bottom conductive layer, and the gate capping layer is formed on the gate top conductive layer; forming a plurality of impurity regions on both sides of the fin; forming a plurality of contacts on the impurity regions; and forming a plurality of conductive capping layers on the contacts; wherein the conductive capping layers include copper germanide.

[0008] Due to the design of the semiconductor device disclosed herein, the conductive capping layer formed by copper germanide can reduce the contact resistance of the semiconductor device. This, in turn, improves the performance of the semiconductor device and reduces its energy consumption.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages that form the subject matter of the claims of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] When considered in conjunction with the drawings, a more complete understanding of this disclosure can be obtained by referring to the detailed description and the claims, wherein similar reference numerals represent similar elements in the overall drawings, and: Figure 1 shows a method for fabricating a semiconductor device in the form of a flowchart according to an embodiment of the present disclosure. Figures 2 to 7 show the semiconductor device fabrication process in cross-sectional schematic diagrams according to the method in Figure 1. Figure 8 shows a method for fabricating a semiconductor device in the form of a flowchart according to another embodiment of this disclosure. Figures 9 to 15 show the fabrication process of semiconductor devices in cross-sectional schematic diagrams according to the method in Figure 8. Figures 16 to 19 show a cross-sectional schematic diagram of the fabrication process of a semiconductor device according to another embodiment of this disclosure. Figures 20 and 21 show the fabrication process of a semiconductor device in cross-sectional schematic diagram according to another embodiment of this disclosure. Figure 22 shows a method for fabricating a semiconductor device in the form of a flowchart according to another embodiment of the present disclosure. Figures 23 to 30 show the fabrication process of semiconductor devices in cross-sectional schematic diagrams according to the method in Figure 22. Figures 31 to 33 show semiconductor devices in cross-sectional schematic diagrams according to some embodiments of the present disclosure. Implementation

[0011] The following disclosure provides many different embodiments or examples of different components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to define relationships between the different embodiments and / or structures discussed.

[0012] Furthermore, spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate the description of the relationship between one element or component shown in the diagram and another. These spatial relation terms are used to cover different orientations of the element in use or operation, beyond the orientation depicted in the diagram. Element may be rotated to different orientations (90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted in the same way.

[0013] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be a direct connection or coupling to another component or layer, or there may be an intermediate component or layer.

[0014] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0015] Unless the context otherwise indicates, the use of terms such as “same,” “equal,” “planar,” or “coplanar” in reference to orientation, layout, location, shape, size, quantity, or other measures does not necessarily imply identical orientation, layout, location, shape, size, quantity, or other measures, but is intended to cover orientation, layout, location, shape, size, quantity, or other measures that are substantially identical, for example, due to manufacturing processes, within acceptable variations. The term “substantially” may be used in this document to reflect this meaning. For example, items described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar, for example, due to manufacturing processes, within acceptable variations.

[0016] In this disclosure, semiconductor devices generally refer to devices that can perform functions by utilizing the properties of semiconductors, and electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices are all included in the category of semiconductor devices.

[0017] It should be noted that in the description disclosed herein, "above" or "up" corresponds to the direction of the arrow in the Z direction, and "below" or "down" corresponds to the direction of the arrow opposite to the Z direction.

[0018] Figure 1 shows a flowchart of a method 10 for fabricating a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 7 show the fabrication process of the semiconductor device 1A in cross-sectional view according to method 10 in Figure 1.

[0019] Referring to Figures 1 and 2, in step S11, a fin 403 can be formed on a substrate 401, a plurality of gate structures 200 can be formed on the fin 403, and a plurality of impurity regions 301 can be formed between adjacent pairs of gate structures 200.

[0020] Referring to FIG2, substrate 401 may include bulk silicon or another suitable substrate material, such as bulk semiconductor. In some embodiments, substrate 401 may include a silicon-containing material. Exemplary examples of silicon-containing materials suitable for substrate 401 may include, but are not limited to, silicon, silicon germanium, carbon-doped silicon germanium, silicon germanium carbide, carbon-doped silicon, silicon carbide, and the aforementioned multilayers. Although silicon is the primary semiconductor material used in wafer fabrication, in some embodiments, alternative semiconductor materials may be used as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, germanium tin, etc.

[0021] Referring to Figure 2, fins 403 may be formed on and separated from each other on a substrate 401. In some embodiments, fins 403 may be formed by recessing a portion of the substrate 401. In other words, fins 403 may comprise the same material as the substrate 401. In some embodiments, the fabrication technique for fins 403 may include depositing a semiconductor layer and subsequently patterning it. The semiconductor layer may comprise, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors; or combinations thereof. It should be noted that Figure 2 shows three fins 403, but the number of fins 403 is not limited to this. For example, the number of fins 403 may be less than three or more.

[0022] Referring to Figure 2, gate structures 200 may be formed on and separated from each other on fins 403. Specifically, dummy gate structures (not shown) may be formed on fins 403. Gate spacers 209 may be formed on the sides of the dummy gate structures. A selective etching process may be performed to remove the dummy gate structures and form gate recesses GR with stepped cross-sectional profiles in the space previously occupied by the dummy gate structures, wherein each gate spacer 209 has a shoulder 2091. That is, the gate recesses GR are formed on fins 403. Gate structures 200 may be formed in the gate recesses GR. Each gate structure 200 may include a gate dielectric layer 201, a bottom gate conductive layer 203, a top gate conductive layer 205, and a gate capping layer 207.

[0023] For the sake of brevity, clarity, and convenience, only one gate dielectric layer 201 is described. Referring to FIG2, the gate dielectric layer 201 may be conformally formed on the gate recess GR, which is formed on the fin 403 and may include a U-shaped or V-shaped cross-sectional profile. The two ends of the gate dielectric layer 201 may extend in opposite directions and be aligned with the top surface 2091TS of the shoulder 2091.

[0024] Specifically, the gate dielectric layer 201 may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, titanium strontium oxide, titanium barium oxide, zirconium barium oxide, silicon lanthanum oxide, silicon aluminum oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or combinations thereof.

[0025] For the sake of brevity, clarity, and convenience, only one gate bottom conductive layer 203 is described. Referring to Figure 2, the gate bottom conductive layer 203 may be conformally formed on the gate dielectric layer 201. The gate bottom conductive layer 203 may have a V-shaped or U-shaped cross-sectional profile. The bottom 203BP of the gate bottom conductive layer 203 may be disposed within the gate recess GR, thereby forming a first valley VY1. The two ends of the gate bottom conductive layer 203 may protrude above the top surface 2091TS of the shoulder 2091. The top of the top surface 203TS of the gate bottom conductive layer 203 may be at a vertical level VL3, which is higher than the top surface 2091TS of the shoulder 2091.

[0026] For the sake of brevity, clarity, and convenience, only one gate top conductive layer 205 is described. Referring to Figure 2, the gate top conductive layer 205 may be conformally formed on the gate bottom conductive layer 203. The gate top conductive layer 205 may have a V-shaped or U-shaped cross-sectional profile. The bottom of the gate top conductive layer 205 may be disposed within the gate groove GR, thereby forming a second valley VY2. The two ends of the gate top conductive layer 205 may protrude above the top surface 2091TS of the shoulder 2091. The top of the top surface 205TS of the gate top conductive layer 205 may be at a vertical horizontal VL4, which is higher than the top surface 2091TS of the shoulder 2091. Conversely, the bottom surface 205BS of the gate top conductive layer 205 may be at a vertical horizontal VL1, which is lower than the top surface 2091TS of the shoulder 2091.

[0027] For the sake of brevity, clarity, and convenience, only one gate capping layer 207 is described. Referring to Figure 2, the gate capping layer 207 may be formed on the top conductive layer 205 of the gate. The bottom 207BP of the gate capping layer 207 may have a downwardly pointing protruding cross-sectional profile. The vertical horizontal VL2 of the bottom 207BP (or bottom surface) of the gate capping layer 207 may be lower than the top surface 2091TS of the shoulder 2091. The gate dielectric layer 201, the bottom conductive layer 203, the top conductive layer 205, and the gate capping layer 207 together constitute the gate structure 200.

[0028] Compared to a gate structure with the same width as gate structure 200 but featuring a planar gate dielectric layer (not shown), the U-shaped profile of gate dielectric layer 201 provides a greater channel length. This greater channel length can mitigate or reduce leakage current issues in semiconductor devices including gate structures. This improved leakage current control can facilitate gate miniaturization.

[0029] In some embodiments, a gate interface layer (not shown) may be formed between the gate dielectric layer 201 and the fin 403. The gate interface layer may include an oxide, and its fabrication techniques may include thermal oxidation, atomic layer deposition, chemical vapor deposition, or similar techniques. For example, the gate interface layer may be silicon oxide. In some embodiments, the thickness of the gate interface layer may be between approximately 8 angstroms and approximately 10 angstroms. The gate interface layer facilitates the formation of the gate dielectric layer 201 during the fabrication of the semiconductor device 1A.

[0030] Referring to Figure 2, an impurity region 301 can be formed on the side 403S of the fin 403 and between the adjacent gate structure 200. The vertical level of the top surface 301TS of the impurity region 301 can be higher than the vertical level of the top surface 403TS of the fin 403 and lower than the vertical level of the top surface 200TS of the gate structure 200. The fabrication techniques for the impurity region 301 can include epitaxial growth processes, such as rapid thermal chemical vapor deposition, low-energy plasma deposition, ultra-high vacuum chemical vapor deposition, atmospheric pressure chemical vapor deposition, or molecular beam epitaxy. In some embodiments, the epitaxial material for n-type devices may include silicon, silicon carbide, phosphorus-doped silicon carbide, phosphorus-doped germanium silicon, silicon phosphide, phosphorus-doped germanium silicon tin, or similar materials, and the epitaxial material for p-type devices may include germanium silicon, boron-doped germanium silicon, germanium, boron-doped germanium, germanium tin, boron-doped germanium tin, boron-doped group III-V compound materials, or similar materials.

[0031] In some embodiments, dopant may be added in situ using a suitable precursor. The dopant concentration in impurity region 301 may be between approximately 1E19 atoms / cm³ and approximately 1E21 atoms / cm³. It should be noted that the term "in situ" means that the dopant, which determines the conductivity type of the doped layer, is introduced during the fabrication steps (e.g., epitaxial deposition) that form the doped layer. The conductivity type indicates whether the doped region is a p-type or n-type region.

[0032] In some embodiments, an epitaxial pre-cleaning process may be used to remove a thin layer of oxide material from the side 403S of the fin 403. The epitaxial pre-cleaning process may be a plasma-assisted dry etch process involving simultaneous exposure of the substrate to plasma byproducts of hydrogen, NF3, and NH3, or a wet etch using a hydrofluoric acid solution.

[0033] Referring to FIG2, a gate spacer 209 may be formed on the side 200S of the gate structure 200 and adjacent to the impurity region 301. The top surface 209TS of the gate spacer 209 may be substantially coplanar with the top surface 200TS of the gate structure 200. The width of the gate spacer 209 may be between approximately 3 nm and approximately 10 nm. The gate spacer 209 may include, for example, silicon nitride, silicon boron carbide nitride, silicon oxy-carbon nitride, silicon carbonitride, silicon carbide oxide, or similar materials.

[0034] Referring to FIG2, an inter-gate dielectric layer 405 may be formed on the impurity region 301 and between adjacent gate structures 200. The inter-gate dielectric layer 405 may be adjacent to the gate structure 200, and a gate spacer 209 may be located between them. The inter-gate dielectric layer 405 may include, for example, silica, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, similar materials, or combinations thereof.

[0035] Referring to Figures 1, 3 and 4, in step S13, a first dielectric layer 501 is formed on the gate structure 200, a second dielectric layer 503 is formed on the first dielectric layer 501, and a plurality of first openings 601O are formed to expose the impurity region 301.

[0036] Referring to FIG3, a first dielectric layer 501 may be formed on the gate structure 200, the gate spacer 209, and the inter-gate dielectric layer 405. The thickness of the first dielectric layer 501 may be between approximately 3 nm and approximately 10 nm, or approximately 5 nm. The fabrication technique of the first dielectric layer 501 may include any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In some embodiments, the first dielectric layer 501 may include, for example, silicon nitride, borosilicate silicon, silicon carbonitride, or silicon oxycarbonitride. In some embodiments, the first dielectric layer 501 may include, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, silicon nitride, silicon nitride oxide, silicon boron carbon nitride, silicon carbon nitride, or silicon oxy-carbon nitride.

[0037] Referring to Figure 3, a second dielectric layer 503 may be formed on the first dielectric layer 501. The thickness of the second dielectric layer 503 may be between approximately 10 nm and approximately 30 nm. The fabrication technique for the second dielectric layer 503 may include any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In some embodiments, the second dielectric layer 503 may include a material that is etch-selective towards the first dielectric layer 501. In some embodiments, the second dielectric layer 503 may include an oxide, such as silicon oxide.

[0038] Referring to FIG3, a first mask layer 601 may be formed on the second dielectric layer 503. In some embodiments, the first mask layer 601 may be a photoresist layer. In some embodiments, the first mask layer 601 may include a rigid mask layer located on the second dielectric layer 503 and a photoresist layer located on the rigid mask layer. The first mask layer 601 may have a pattern of a first opening 601O.

[0039] Referring to Figure 4, an etching process can be performed to remove portions of the second dielectric layer 503, the first dielectric layer 501, and the inter-gate dielectric layer 405 to form a first opening 601O. In other words, the first opening 601O can be formed in the second dielectric layer 503, the first dielectric layer 501, and the inter-gate dielectric layer 405. The impurity region 301 can be exposed through the first opening 601O. The width W1 of the first opening 601O can be smaller than the width W2 of the impurity region 301. The inter-gate dielectric layer 405 can be divided by the first opening 601O and become a contact spacer 407 adjacent to the gate spacer 209. After forming the first opening 601O, the first mask layer 601 can be removed.

[0040] Referring to Figures 1 and 5, in step S15, a plurality of contacts 101 can be formed in the first opening 601O.

[0041] Referring to Figure 5, conductive materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof, can be deposited into the first opening 601O through a deposition process. After the deposition process, a planarization process such as chemical mechanical polishing can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming the contact 101. The contact 101 can be electrically coupled to the impurity region 301. Contact spacers 407 can be disposed on the side 101S of the contact 101 and between the first dielectric layer 501 and the impurity region 301 to electrically isolate the contact 101 from the gate structure 200.

[0042] Referring to Figures 1 and 6, in step S17, the second dielectric layer 503 can be recessed to expose the higher portion of the side 101S of the contact 101.

[0043] Referring to Figure 6, an etching process can be performed to recess the top surface 503TS of the second dielectric layer 503. During the etching process, the ratio of the etching rate of the second dielectric layer 503 to the etching rate of the contact 101 can be between approximately 100:1 and approximately 1.05:1, approximately 15:1 and approximately 2:1, or approximately 10:1 and approximately 2:1. After the etching process, the higher portion of the side edge 101S of the contact 101 can protrude from the top surface 503TS of the second dielectric layer 503. In other words, the vertical level of the top surface 101TS of the contact 101 can be higher than the vertical level of the top surface 503TS of the second dielectric layer 503.

[0044] Referring to Figures 1 and 7, in step S19, a plurality of conductive capping layers 103 can be formed on the contacts 101.

[0045] Referring to FIG7, a conductive capping layer 103 may be formed on the top surface 101TS of the contact 101, on the higher portion of the side edge 101S of the contact 101, and on the second dielectric layer 503. The conductive capping layer 103 may include, for example, copper germanide. In some embodiments, the fabrication techniques for the conductive capping layer 103 may include, for example, sputtering, electron beam thermal evaporation, vapor-solid reaction, or epitaxial growth. In this embodiment, epitaxial growth is preferred to form the conductive capping layer 103 in order to provide a lower resistivity.

[0046] The conductive capping layer 103, formed of copper germanide with high thermal stability, low bulk resistivity, and diffusion barrier properties, can reduce the contact resistance between the contact 101 and the conductive features to be electrically connected to the contact 101. The conductive capping layer 103 can be referred to as a resistance reduction element.

[0047] In some embodiments, one of dielectric layers 501 or 503 may be omitted. For example, the second dielectric layer 503 may be omitted. Contact 101 may protrude from the top surface of the first dielectric layer 501. In such embodiments, a conductive capping layer 103 may be formed on the top surface 101TS of contact 101, on the higher portion of the side edge 101S of contact 101, and on the first dielectric layer 501. In other embodiments, the first dielectric layer 501 may be omitted.

[0048] Figure 8 shows a flowchart of a method 20 for fabricating a semiconductor device 1B according to another embodiment of this disclosure. Figures 9 to 15 show the fabrication process of the semiconductor device 1B in cross-sectional view according to method 20.

[0049] Referring to Figures 8 and 9, in step S21, fins 403 can be formed on substrate 401, gate structures 200 can be formed on fins 403, impurity regions 301 can be formed between adjacent pairs of gate structures 200, and a dielectric etching process can be performed to expose the impurity regions 301.

[0050] Referring to Figure 9, an intermediate semiconductor device can be fabricated using a process similar to that shown in Figure 2. After the dielectric etching process, the inter-gate dielectric layer 405 (as shown in Figure 2) can be removed. During the dielectric etching process, the ratio of the etching rate of the inter-gate dielectric layer 405 to the etching rate of the gate spacer 209 can be between approximately 100:1 and approximately 1.05:1, approximately 15:1 and approximately 2:1, or approximately 10:1 and approximately 2:1. During the dielectric etching process, the ratio of the etching rate of the inter-gate dielectric layer 405 to the etching rate of the gate structure 200 can be between approximately 100:1 and approximately 1.05:1, approximately 15:1 and approximately 2:1, or approximately 10:1 and approximately 2:1. During the dielectric etching process, the ratio of the etching rate of the intergate dielectric layer 405 to the etching rate of the impurity region 301 may be between approximately 100:1 and approximately 1.05:1, approximately 15:1 and approximately 2:1, or approximately 10:1 and approximately 2:1. After the dielectric etching process, corner erosion may occur in the gate spacer 209.

[0051] Referring to Figures 8 and 10, in step S23, a lower portion 101-1 of contact 101 can be formed on the impurity region 301.

[0052] Referring to Figure 10, a contact material can be deposited to overfill the intermediate semiconductor element shown in Figure 9. A planarization process, such as chemical mechanical polishing, can then be performed to remove excess material, providing a substantially flat surface for subsequent processing steps, and simultaneously forming the lower portion 101-1 of contact 101. The planarization process can "over-polish" to remove portions of the gate spacer 209 with eroded corners. The lower portion 101-1 of contact 101 can be disposed adjacent to the gate structure 200, with the gate spacer 209 positioned between them. It should be noted that, unlike the embodiment shown in Figure 7, in this current embodiment, no contact spacers are provided on the sides of contact 101.

[0053] Referring to Figures 8 and 11 to 13, in step S25, a first dielectric layer 501 can be formed on the gate structure 200, a second dielectric layer 503 can be formed on the first dielectric layer 501, a plurality of second openings 603O can be formed in the first dielectric layer 501, and a plurality of third openings 605O can be formed in the second dielectric layer 503.

[0054] Referring to FIG11, a first dielectric layer 501 may be formed on the gate structure 200, the gate spacer 209, and the lower portion 101-1 of the contact 101. The thickness of the first dielectric layer 501 may be between approximately 3 nm and approximately 10 nm, or approximately 5 nm. The fabrication technique of the first dielectric layer 501 may include any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In some embodiments, the first dielectric layer 501 may include, for example, silicon nitride, borosilicate silicon carbonitride, silicon carbonitride, or silicon oxycarbonitride. In some embodiments, the first dielectric layer 501 may include, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, silicon nitride, silicon nitride oxide, borosilicate silicon carbonitride, silicon carbonitride, or silicon oxynitride.

[0055] Referring to FIG11, a second dielectric layer 503 may be formed on the first dielectric layer 501. The thickness of the second dielectric layer 503 may be between approximately 10 nm and approximately 30 nm. The fabrication technique of the second dielectric layer 503 may include any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. In some embodiments, the second dielectric layer 503 may include a material that is etch-selective on the first dielectric layer 501. In some embodiments, the second dielectric layer 503 may include an oxide, such as silicon oxide.

[0056] Referring to FIG11, a second mask layer 603 may be formed on the second dielectric layer 503. In some embodiments, the second mask layer 603 may be a photoresist layer. In some embodiments, the second mask layer 603 may include a rigid mask layer located on the second dielectric layer 503 and a photoresist layer located on the rigid mask layer. The second mask layer 603 may have a pattern of a second opening 603O.

[0057] Referring to Figure 12, a first etching process can be performed to remove a portion of the second dielectric layer 503 and a portion of the first dielectric layer 501 to form a second opening 603O. During this stage, the second opening 603O can be formed in both the second dielectric layer 503 and the first dielectric layer 501. The lower portion 101-1 of the contact 101 can be exposed through the second opening 603O. The width W3 of the second opening 603O can be smaller than the width W4 of the lower portion 101-1 of the contact 101. After forming the second opening 603O, the second mask layer 603 can be removed.

[0058] Referring to FIG12, a third mask layer 605 may be formed on the second dielectric layer 503. In some embodiments, the third mask layer 605 may be a photoresist layer. In some embodiments, the third mask layer 605 may include a rigid mask layer located on the second dielectric layer 503 and a photoresist layer located on the rigid mask layer. The third mask layer 605 may have a pattern of a third opening 605O.

[0059] Referring to FIG13, a second etching process may be performed to remove a portion of the second dielectric layer 503 to form a third opening 605O. Forming the third opening 605O may include widening the previously formed second opening 603O in the second dielectric layer 503. The width W5 of the third opening 605O may be greater than the width W3 of the second opening 603O. In some embodiments, the width W5 of the third opening 605O may be equal to or greater than the width W4 of the lower portion 101-1 of the contact 101.

[0060] Referring to Figures 8, 14, and 15, in step S27, the middle portion 101-3 of the contact 101 can be formed in the second opening 603O, the higher portion 101-5 of the contact 101 can be formed in the third opening 605O, and a conductive covering layer 103 can be formed on the higher portion 101-5.

[0061] Referring to Figure 14, conductive materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof can be deposited into the second opening 603O and the third opening 605O through a deposition process. After the deposition process, a planarization process such as chemical mechanical polishing can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming the middle portion 101-3 of the contact 101 in the second opening 603O and the higher portion 101-5 of the contact 101 in the third opening 605O.

[0062] The width (or size) of contact 101 can be critical. If the width of contact 101 is relatively small, this structure can reduce unwanted short circuits with gate structure 200, but at the cost of potentially high contact resistance through contact 101 to impurity region 301. Conversely, if the width of contact 101 is relatively large, this structure can provide low contact resistance through contact 101 to impurity region 301, but at the cost of increased probability of unwanted short circuits with gate structure 200. Referring to FIG14, the width W8 of the higher portion 101-5 can be greater than the width W7 of the middle portion 101-3. In some embodiments, the width W8 of the higher portion 101-5 can be equal to or greater than the width W4 of the lower portion 101-1. In this embodiment, the larger widths of the lower portion 101-1 and the higher portion 101-5 can reduce contact resistance by increasing the contact area. Meanwhile, the smaller width of the middle portion 101-3 avoids increasing the probability of short circuits with gate structure 200. Therefore, the total contact resistance of semiconductor element 1B with the currently designed contact 101 is reduced.

[0063] Referring to Figure 15, an etching process can be performed to recess the top surface 503TS of the second dielectric layer 503. After the etching process, the higher portion of the side edge 101-5S of the higher portion 101-5 can protrude from the top surface 503TS of the second dielectric layer 503. In other words, the vertical level of the top surface 101-5TS of the higher portion 101-5 can be higher than the vertical level of the top surface 503TS of the second dielectric layer 503.

[0064] Referring to FIG15, a conductive capping layer 103 may be formed on the top surface 101-5TS of the higher portion 101-5, on the higher portion of the side edge 101-5S of the higher portion 101-5, and on the second dielectric layer 503. The conductive capping layer 103 may include, for example, copper germanide. In some embodiments, the fabrication techniques of the conductive capping layer 103 may include, for example, sputtering, electron beam thermal evaporation, gas-solid phase reaction, or epitaxial growth. In this embodiment, epitaxial growth is preferably used to form the conductive capping layer 103 in order to provide a lower resistivity.

[0065] Furthermore, using copper germanide, which has high thermal stability, low bulk resistivity, and diffusion barrier properties, to form the conductive capping layer 103 can further reduce the contact resistance between the higher portion 101-5 of the contact 101 and the conductive features to be electrically connected to the contact 101.

[0066] Figures 16 to 19 show the fabrication process of a semiconductor device 1C in cross-sectional schematic diagram according to another embodiment of the present disclosure.

[0067] Referring to Figure 16, an intermediate semiconductor device can be fabricated using a process similar to that shown in Figures 2 to 4. A barrier material can be conformally formed in the first opening 601O and on the top surface 503TS of the second dielectric layer 503. The barrier material may include, for example, titanium, titanium nitride, platinum, nickel, or combinations thereof. In this embodiment, the barrier material may be titanium. Subsequently, a conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum nitrides, or combinations thereof can be deposited into the first opening 601O via a deposition process. After the deposition process, a planarization process such as chemical mechanical polishing can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, while simultaneously forming contacts 101 and transforming the barrier material into barrier layer 105.

[0068] Referring to FIG17, an etching process can be performed to recess the top surface 503TS of the second dielectric layer 503. During the etching process, the ratio of the etching rate of the second dielectric layer 503 to the etching rate of the contact 101 can be between approximately 100:1 and approximately 1.05:1, approximately 15:1 and approximately 2:1, or approximately 10:1 and approximately 2:1. During the etching process, the ratio of the etching rate of the second dielectric layer 503 to the etching rate of the barrier layer 105 can be between approximately 100:1 and approximately 1.05:1, approximately 15:1 and approximately 2:1, or approximately 10:1 and approximately 2:1. After the etching process, the higher portions of the contact 101 and the higher portions of the barrier layer 105 can protrude from the top surface 503TS of the second dielectric layer 503.

[0069] Referring to FIG18, a semiconductor material 701 may be conformally formed to cover the top surface 503TS of the second dielectric layer 503, the higher portion of the contact 101, and the higher portion of the barrier layer 105. The semiconductor material 701 may be, for example, silicon or germanium. In this embodiment, the semiconductor material 701 may be silicon.

[0070] Referring to Figure 19, heat treatment can be performed. During heat treatment, the metal atoms of the contact 101 and the barrier layer 105 can chemically react with the silicon atoms of the semiconductor material 701 to form a top conductive layer 107 on the contact 101 and barrier spacers 109 on the side edges 105S and top surface 105TS of the barrier layer 105. The top conductive layer 107 and barrier spacers 109 may include titanium silicon, nickel silicon, nickel platinum silicon, tantalum silicon, or cobalt silicon. The heat treatment can be a dynamic surface annealing process. After heat treatment, a cleaning process can be performed to remove unreacted semiconductor material 701. The cleaning process can be, for example, wet etching using potassium hydroxide. The top conductive layer 107 and barrier spacers 109 can reduce the contact resistance of the contact 101. The top conductive layer 107 and barrier spacers 109 can be referred to as resistance-reducing elements.

[0071] In some embodiments, one of the dielectric layers may be omitted. For example, the second dielectric layer 503 may be omitted. In such an embodiment, the contact 101 may protrude from the top surface of the first dielectric layer 501. A top conductive layer 107 may be formed on the top surface 101TS of the contact 101, while barrier spacers 109 may be formed on the higher portion of the sidewalls 105S of the barrier layer 105 and on the first dielectric layer 501. In other embodiments, the first dielectric layer 501 may be omitted.

[0072] Figures 20 and 21 show, in cross-sectional schematic diagram, the fabrication process of a semiconductor device 1D according to another embodiment of the present disclosure.

[0073] Referring to Figure 20, an intermediate semiconductor device can be fabricated using a process similar to that shown in Figures 9 to 13. A barrier material can be conformally formed in the second opening 603O and the third opening 605O on the top surface 503TS of the second dielectric layer 503. The barrier material can be, for example, titanium, titanium nitride, platinum, nickel, or a combination thereof. Subsequently, a conductive material such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, or a combination thereof can be deposited into the second opening 603O and the third opening 605O through a deposition process. After the deposition process, a planarization process such as chemical mechanical polishing can be performed until the top surface 503TS of the second dielectric layer 503 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, while forming the intermediate portion 101-3 and the upper portion 101-5 of the contact 101 and transforming the barrier material into the barrier layer 105.

[0074] Referring to FIG20, the barrier layer 105 may be formed between the lower portion 101-1 and the middle portion 101-3, between the first dielectric layer 501 and the middle portion 101-3, between the first dielectric layer 501 and the higher portion 101-5, and on the side 101-5S of the higher portion 101-5.

[0075] Referring to FIG21, a process similar to that shown in FIG17 to FIG19 can be performed to form the top conductive layer 107 and the barrier spacer 109. The top conductive layer 107 can be formed on the top surface 101-5TS of the higher portion 101-5. The barrier spacer 109 can be formed on the side edge 105S of the barrier layer 105, on the top surface 105TS of the barrier layer 105, and on the top surface 503TS of the second dielectric layer 503.

[0076] Figure 22 shows a flowchart of a method 30 for fabricating a semiconductor device 1E according to another embodiment of the present disclosure. Figures 23 to 30 show the fabrication process of the semiconductor device 1E in cross-sectional view according to method 30.

[0077] Referring to Figures 22 and 23, in step S31, a fin 403 can be formed on a substrate 401, a gate structure 200 can be formed on the fin 403, an impurity region 301 can be formed between adjacent pairs of gate structures 200, and a first dielectric layer 501 can be formed on the gate structure 200.

[0078] Referring to Figure 23, a process similar to that shown in Figures 2 and 3 can be used to form the gate structure 200, gate spacer 209, impurity region 301, substrate 401, fin 403, inter-gate dielectric layer 405, and first dielectric layer 501. A fourth mask layer 607 can be formed on the first dielectric layer 501. The fourth mask layer 607 may have a pattern of a fourth opening 607O.

[0079] Referring to Figures 22 to 25, in step S33, a plurality of fourth openings 607O may be formed to expose the impurity region 301, and a sacrificial material 703 may be formed on the first dielectric layer 501 to fill the fourth openings 607O.

[0080] Referring to Figures 23 and 24, an etching process can be performed to remove a portion of the first dielectric layer 501 and a portion of the inter-gate dielectric layer 405 to form a fourth opening 607O. In other words, the fourth opening 607O can be formed in the first dielectric layer 501 and the inter-gate dielectric layer 405. The impurity region 301 can be exposed through the fourth opening 607O. The inter-gate dielectric layer 405 can be divided by the fourth opening 607O and become a contact spacer 407 adjacent to the gate spacer 209. After forming the fourth opening 607O, the fourth mask layer 607 can be removed.

[0081] Referring to Figure 25, a sacrificial material 703 can be deposited on the intermediate semiconductor device shown in Figure 24. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent process steps. A fifth mask layer 609 can be formed on the sacrificial material 703. The fifth mask layer 609 may have a pattern of a fifth opening 609O.

[0082] In some embodiments, the sacrificial material 703 may be, for example, a doped oxide, such as borosilicate glass, phosphosilicate glass, borosilicate glass, fluorosilicate glass, carbon-doped silicon oxide, or similar materials. Doped oxides exhibit a faster etching rate when etched by hydrofluoric acid vapor compared to undoped oxides. This may be due to the lower density characteristics of undoped oxides. Alternatively, in some embodiments, the sacrificial material 703 may comprise, for example, a thermally decomposable polymer or a thermally degradable polymer. Thermally decomposable polymers or thermally degradable polymers will decompose or degrade into a gaseous state when exposed to temperatures exceeding their decomposition or degradation temperatures.

[0083] Referring to Figures 22 and 25 to 28, in step S35, a plurality of fifth openings 609O may be formed to expose the first dielectric layer 501, and an insulating layer 113 may be formed in the fifth openings 609O.

[0084] Referring to Figures 25 and 26, an etching process can be performed to remove a portion of the sacrificial material 703 to form a fifth opening 609O. A portion of the first dielectric layer 501 can be exposed through the fifth opening 609O. After the fifth opening 609O is formed, the fifth masking layer 609 can be removed.

[0085] Referring to FIG27, an insulating material 705 may be formed on the sacrificial material 703 to fill the fifth opening 609O. In some embodiments, the insulating material 705 may be, for example, an undoped oxide, such as silicon oxide or undoped silica glass. Alternatively, in some embodiments, the insulating material 705 may be, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, flowable oxide, undoped silica glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorosilicate glass, carbon-doped silicon oxide, or a combination thereof.

[0086] Referring to FIG28, a planarization process such as chemical mechanical polishing can be performed until the top surface 703TS of the sacrificial material 703 is exposed to remove excess material, provide a substantially flat surface for subsequent process steps, and simultaneously form an insulating layer 113.

[0087] Referring to Figures 22 and 29, in step S37, space 611 can be formed by removing the sacrificial material 703.

[0088] Referring to Figure 29, the sacrificial material 703 can be removed and a space 611 can be formed in situ; in other words, a space 611 can be formed in the position previously occupied by the sacrificial material 703. The impurity region 301 can be exposed through the space 611.

[0089] In some embodiments, hydrofluoric acid vapor can be used to remove the sacrificial material 703 and form the space 611. Due to the difference between the density of the sacrificial material 703 (doped oxide) and the density of the insulating layer 113 (undoped oxide), hydrofluoric acid vapor has a higher etching rate on the doped oxide; therefore, the sacrificial material 703 can be removed by hydrogen fluoride vapor, and the insulating layer 113 can be preserved.

[0090] Alternatively, in some embodiments, a thermal process is applied to remove the sacrificial material 703 layer, which comprises a thermally decomposable polymer or a thermally degradable polymer. The temperature of the thermal process can be between about 300°C and about 450°C. Preferably, the temperature of the thermal process can be between about 350°C and about 420°C.

[0091] Referring to Figures 22 and 30, in step S39, contact 101 can be formed in space 611.

[0092] Referring to Figure 30, conductive materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof can be deposited into space 611 through a deposition process. After the deposition process, a planarization process such as chemical mechanical polishing can be performed until the top surface 113TS of the insulating layer 113 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming contact 101. Contact 101 can be electrically coupled to impurity region 301.

[0093] For ease of description, only one contact 101 is described. Contact 101 may include a lower portion 101-1, a middle portion 101-3, and a higher portion 101-5. The lower portion 101-1 may be formed on the impurity region 301, below the first dielectric layer 501, and between the contact spacer 407. The middle portion 101-3 may be formed on the lower portion 101-1 and in the first dielectric layer 501. The higher portion 101-5 may be formed on the middle portion 101-3 and between a corresponding adjacent pair of insulating layers 113. The width W10 of the higher portion 101-5 may be greater than the width W9 of the middle portion 101-3. This larger width of the higher portion 101-5 can reduce contact resistance by increasing the contact area. In some embodiments, the contact 101 is formed correspondingly on the impurity region 301 in a self-aligned manner and may be referred to as a self-aligned element.

[0094] Figures 31 to 33 show semiconductor elements 1F, 1G, and 1H in cross-sectional schematic diagrams according to some embodiments of the present disclosure.

[0095] Referring to FIG31, semiconductor device 1F may have a structure similar to that shown in FIG7. Elements in FIG31 that are the same as or similar to those in FIG7 are indicated by similar reference numerals, and repeated descriptions are omitted. Semiconductor device 1F may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed between contact 101 and impurity region 301. The bottom conductive layer 111 may include, for example, titanium silicon, nickel silicon, nickel platinum silicon, tantalum silicon, or cobalt silicon. The thickness of the bottom conductive layer 111 may be between approximately 2 nm and approximately 20 nm. The bottom conductive layer 111 may reduce the contact resistance between contact 101 and impurity region 301.

[0096] Referring to FIG32, semiconductor element 1G may have a structure similar to that shown in FIG7. Elements identical or similar to those in FIG7 in FIG32 are indicated by similar reference numerals, and repeated descriptions are omitted. Semiconductor element 1G may include a buried insulation layer 409 disposed beneath fin 403. The buried insulation layer 409 may be disposed between fin 403 and substrate 401. The buried insulation layer 409 may include crystalline or amorphous dielectric materials, such as oxides and / or nitrides. In some embodiments, the buried insulation layer 409 may be a dielectric oxide, such as silicon oxide. In other embodiments, the buried insulation layer 409 may be a dielectric nitride, such as silicon nitride or boron nitride. In other embodiments, the buried insulation layer 409 may include a stack of dielectric oxides and dielectric nitrides, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The thickness of the buried insulation layer 409 may be between approximately 10 nm and approximately 200 nm. The buried insulation layer 409 can eliminate leakage current between gate structures 200 and reduce parasitic capacitance associated with impurity region 301.

[0097] Referring to FIG33, the semiconductor device 1H may have a structure similar to that shown in FIG21. Elements in FIG33 that are the same as or similar to those in FIG21 are indicated by similar reference numerals, and repeated descriptions are omitted. The semiconductor device 1H may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed between the lower portion 101-1 of the contact 101 and the impurity region 301. The bottom conductive layer 111 may include, for example, titanium silicon, nickel silicon, nickel platinum silicon, tantalum silicon, or cobalt silicon. The thickness of the bottom conductive layer 111 may be between approximately 2 nm and approximately 20 nm. The bottom conductive layer 111 may reduce the contact resistance between the lower portion 101-1 of the contact 101 and the impurity region 301.

[0098] One aspect of this disclosure provides a semiconductor device, comprising: a fin; a gate structure located on the fin, wherein the gate structure includes a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer, wherein the gate dielectric layer is located on the fin, the gate bottom conductive layer is located on the gate dielectric layer, the gate top conductive layer is located on the gate bottom conductive layer, and the gate capping layer is located on the gate top conductive layer; a plurality of impurity regions located on both sides of the fin; a plurality of contacts correspondingly located on the impurity regions; and a plurality of conductive capping layers correspondingly located on the contacts; wherein the contacts include: a plurality of lower portions correspondingly located on the impurity regions, a plurality of intermediate portions correspondingly located on the lower portions, and a plurality of higher portions correspondingly located on the intermediate portions.

[0099] Another aspect of this disclosure provides a semiconductor device, comprising: a fin; a gate structure located on the fin, wherein the gate structure includes a gate dielectric layer, a bottom gate conductive layer, a top gate conductive layer, and a gate capping layer, wherein the gate dielectric layer is located on the fin, the bottom gate conductive layer is located on the gate dielectric layer, the top gate conductive layer is located on the bottom gate conductive layer, and the gate capping layer is located on the top gate conductive layer; and a plurality of impurity regions located on both sides of the fin. The device comprises: a domain; a plurality of contacts located on the impurity regions; and a plurality of top conductive layers located on the contacts, wherein the top conductive layers include titanium silicon, nickel silicon, nickel platinum silicon, tantalum silicon, or cobalt silicon; wherein the contacts include: a plurality of lower portions correspondingly located on the impurity regions, a plurality of intermediate portions correspondingly located on the lower portions, and a plurality of higher portions correspondingly located on the intermediate portions; wherein a width of the higher portions is greater than a width of the intermediate portions.

[0100] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: forming a gate structure on a fin, wherein the gate structure includes a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer, wherein the gate dielectric layer is formed on the fin, the gate bottom conductive layer is formed on the gate dielectric layer, the gate top conductive layer is formed on the gate bottom conductive layer, and the gate capping layer is formed on the gate top conductive layer; forming a plurality of impurity regions on both sides of the fin; forming a plurality of contacts on the impurity regions; and forming a plurality of conductive capping layers on the contacts; wherein the conductive capping layers include copper germanide.

[0101] Due to the design of the semiconductor device disclosed herein, the conductive capping layer formed by copper germanide can reduce the contact resistance of the semiconductor device. This, in turn, improves the performance of the semiconductor device and reduces its energy consumption.

[0102] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0103] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0104] 1A: Semiconductor components 1B: Semiconductor components 1C: Semiconductor components 1D: Semiconductor Components 1E: Semiconductor components 1F: Semiconductor components 1G: Semiconductor components 1H: Semiconductor components 10: Method 20: Method 30: Method 101: Contact 101S: Side 101TS: Top Surface 101-1: Lower part 101-3: Middle Section 101-5: Higher section 101-5S: Side 101-5TS: Top Surface 103: Conductive coating 105: Barrier layer 105S: Side 105TS: Top surface 107: Top conductive layer 109: Barrier spacers 111: Bottom conductive layer 113: Insulation layer 113TS: Top surface 200: Gate structure 200S: Side 200TS: Top Surface 201: Gate Dielectric Layer 203: Bottom conductive layer of the gate 203BP: Bottom 203TS: Top Surface 205: Top conductive layer of the gate 205BS: Bottom surface 205TS: Top Surface 207: Gate Cover Layer 207BP: Bottom 209: Gate spacer 209TS: Top Surface 301: Impurity Region 301TS: Top Surface 401:Substrate 403: Fins 403S: Side 403TS: Top Surface 405: Intergate dielectric layer 407: Contact spacer 409: Buried Insulation Layer 501: Dielectric layer 503: Dielectric layer 503TS: Top Surface 601: First Cover Layer 601O: First Opening 603: Second Cover Layer 603O: Second opening 605: Third Cover Layer 605O: Third opening 607: Fourth Cover Layer 607O: Fourth opening 609: Fifth Cover Layer 609O: The Fifth Opening 611: Space 701: Semiconductor Materials 703: Sacrificial Material 703TS: Top Surface 705: Insulating materials 2091: Shoulder 2091TS: Top Surface GR: Gate Groove S11: Steps S13: Steps S15: Steps S17: Steps S19: Steps S21: Steps S23: Steps S25: Steps S27: Steps S31: Steps S33: Steps S35: Steps S37: Steps S39: Steps VY1: Valley VY2: Valley VL1: Vertical and horizontal VL2: Vertical and Horizontal VL3: Vertical and Horizontal VL4: Vertical and Horizontal W1: Width W2: Width W3: Width W4: Width W5: Width W7: Width W8: Width W9: Width W10: Width Z: Direction

Claims

1. A semiconductor element, comprising: One fin; A gate structure is located on the fin, wherein the gate structure includes a gate dielectric layer, a gate bottom conductive layer, a gate top conductive layer, and a gate capping layer, wherein the gate dielectric layer is located on the fin, the gate bottom conductive layer is located on the gate dielectric layer, the gate top conductive layer is located on the gate bottom conductive layer, and the gate capping layer is located on the gate top conductive layer; a plurality of impurity regions are located on both sides of the fin; a plurality of contacts are correspondingly located on the impurity regions; and a plurality of conductive capping layers, correspondingly located on the contacts, wherein the contacts include: a plurality of lower portions, correspondingly located on the impurity regions; a plurality of intermediate portions, correspondingly located on the lower portions; and a plurality of higher portions, correspondingly located on the intermediate portions, wherein the conductive capping layers are correspondingly formed on a plurality of top surfaces of the higher portions and correspondingly formed on the upper parts of a plurality of side edges of the higher portions.

2. The semiconductor device as claimed in claim 1 further includes a first dielectric layer located on the gate structures and on the lower portions of the contacts.

3. The semiconductor device as claimed in claim 2 further includes a plurality of gate spacers located on the side of the gate structure and adjacent to the impurity regions.

4. The semiconductor device as claimed in claim 3, wherein a vertical level of the top surface of the impurity regions is higher than a vertical level of the top surface of the fin.

5. The semiconductor device as claimed in claim 4, wherein the top surfaces of the gate spacers are substantially coplanar with the top surface of the gate structure.

6. The semiconductor device as claimed in claim 5, wherein the gate spacer has a shoulder.

7. The semiconductor device as claimed in claim 6, wherein the gate dielectric layer includes a U-shaped or V-shaped cross-sectional profile, and the two ends of the gate dielectric layer extend in opposite directions and are aligned with a top surface of the shoulder.

8. The semiconductor device as claimed in claim 7, wherein the bottom gate conductive layer has a V-shaped or U-shaped cross-sectional profile, and a bottom of the bottom gate conductive layer forms a first valley, wherein both ends of the bottom gate conductive layer protrude above the top surface of the shoulder, and a top of the top surface of the bottom gate conductive layer is located at a third vertical level, the third vertical level being higher than the top surface of the shoulder.

9. The semiconductor device of claim 8, wherein the gate top conductive layer has a V-shaped or U-shaped cross-sectional profile, and a bottom of the gate top conductive layer forms a second valley, wherein both ends of the gate top conductive layer protrude above the top surface of the shoulder, a top of a top surface of the gate top conductive layer is located at a fourth vertical level, the fourth vertical level being higher than the top surface of the shoulder, and a bottom surface of the gate top conductive layer is located at a first vertical level, the first vertical level being lower than the top surface of the shoulder.

10. The semiconductor device as claimed in claim 9, wherein a bottom of the gate cap has a downwardly projecting cross-sectional profile, wherein the bottom of the gate cap is located at a second vertical level, the second vertical level being lower than the top surface of the shoulder.

11. The semiconductor device of claim 10 further includes a plurality of bottom conductive layers located between the contacts and the impurity regions, wherein the bottom conductive layers include titanium silicon, nickel silicon, nickel platinum silicon, tantalum silicon, or cobalt silicon.

12. The semiconductor device as claimed in claim 10 further includes a buried insulating layer located beneath the fin.

13. The semiconductor device as claimed in claim 1 further includes a first dielectric layer on the gate structure and a second dielectric layer on the first dielectric layer, wherein the contacts are located within the first dielectric layer and the second dielectric layer and protrude from a top surface of the second dielectric layer.

14. The semiconductor element as claimed in claim 13, wherein the intermediate portions are located within the first dielectric layer and the higher portions are located within the second dielectric layer.

15. The semiconductor element as claimed in claim 14, wherein the width of the lower portions is greater than the width of the middle portions.

16. The semiconductor element as claimed in claim 14, wherein the width of the higher portions is greater than the width of the intermediate portions.

17. The semiconductor element as claimed in claim 14, wherein the width of the higher portions is greater than the width of the lower portions.

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