Semiconductor device with isolation structure and method for fabricating the same

Abstract

This application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a substrate, a plurality of through-substrate vias, a plurality of insulating segments, and a plurality of liner layers. The substrate includes a first surface and a second surface opposite to the first surface. The plurality of through-substrate vias penetrate the substrate. Each of the plurality of insulating segments includes an embedded portion disposed in the through-substrate via and an extension portion disposed above the embedded portion. The liner layers are disposed on one side surface of the through-substrate via and located between the side surface of the through-substrate via and the embedded portion of the insulating segment. The plurality of first insulating segments and the plurality of liner layers are exposed through the second surface of the substrate.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 788,323 (i.e., priority date "July 30, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having an isolation structure and a method for manufacturing the same. Prior Technology

[0003] Semiconductor components are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, the challenges brought about by this shrinking size are becoming increasingly frequent and impactful. Therefore, challenges remain in improving quality, yield, performance, and reliability while reducing complexity.

[0004] The discussion in the preceding technical paragraphs is for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; a plurality of first through-substrate vias penetrating the substrate; a plurality of first embedding portions of a plurality of first insulating segments disposed in the plurality of first through-substrate vias; and a plurality of first liner layers, each of the plurality of first liner layers disposed on a side surface of one of the plurality of first through-substrate vias and located between the side surface of the first through-substrate via and one of the plurality of first insulating segments. The plurality of first insulating segments and the plurality of first liner layers are exposed through the second surface of the substrate.

[0006] In some embodiments, the substrate includes a doped region disposed in the first surface of the substrate and on the plurality of side surfaces of the plurality of first through-substrate vias.

[0007] In some embodiments, each of the plurality of first insulating segments further includes a first extension portion disposed on the first embedded portion and the first surface of the substrate.

[0008] In some embodiments, the width of the first extension portion is greater than the width of the first embedded portion.

[0009] In some embodiments, the plurality of first insulating segments include a T-shaped cross-sectional profile.

[0010] In some embodiments, the first extension portion and the first embedded portion are made of the same material.

[0011] In some embodiments, the first extension portion and the first embedded portion comprise different materials.

[0012] In some embodiments, the semiconductor element further includes a fill layer disposed on the first surface, wherein the fill layer surrounds the plurality of first extension portions of the plurality of first insulating segments.

[0013] In some embodiments, the filler layer is made of silicon nitride.

[0014] In some embodiments, the semiconductor device further includes a word line hard mask layer disposed over the fill layer and the plurality of first extensions of the plurality of first insulating segments.

[0015] In some embodiments, the substrate includes a first region and a second region, wherein the plurality of first trenches are disposed in the first region.

[0016] In some embodiments, the semiconductor device further includes: a second through-substrate via penetrating the substrate in the second region; a second embedded portion of a second insulating segment disposed in the second through-substrate via; and a second liner disposed on one side surface of the second through-substrate via and located between the side surface of the second through-substrate via and the second insulating segment, wherein the second insulating segment and the second liner are exposed through the second surface of the substrate.

[0017] In some embodiments, the doped region is also disposed on the side surface of the second through-substrate via.

[0018] In some embodiments, the second insulating segment further includes a second extension portion disposed on the second embedded portion and the first surface of the substrate.

[0019] In some embodiments, the width of the second extension portion is greater than the width of the second embedded portion.

[0020] In some embodiments, the second insulating segment includes a T-shaped cross-sectional profile.

[0021] In some embodiments, the second extension and the second embedding portion are made of the same material.

[0022] In some embodiments, the second extension portion and the second embedded portion comprise different materials.

[0023] In some embodiments, the width of the second embedded portion is greater than the width of the first embedded portion.

[0024] In some embodiments, the width of the second extension is greater than the width of the first extension.

[0025] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate; at least one isolation feature disposed in the substrate, wherein the at least one isolation feature defines a plurality of active regions; a storage capacitor disposed on the substrate; a storage transistor including a plurality of impurity regions disposed in the active regions; and a conductive feature extending from the storage capacitor into the substrate for electrically coupling the storage capacitor to the storage transistor.

[0026] In some embodiments, each of the at least one isolation feature includes: a first filler layer filling a trench disposed in the substrate; a second filler layer disposed within the first filler layer; and a liner lining an inner surface of the trench and surrounding the first filler layer.

[0027] In some embodiments, the first filler layer and the liner layer include a U-shaped cross-sectional profile.

[0028] In some embodiments, a top surface of the first filling layer, a top surface of the second filling layer, and a top surface of the liner are coplanar.

[0029] In some embodiments, a bottom surface of the second filling layer is at a vertical height above a bottom surface of the first filling layer.

[0030] In some embodiments, the conductive feature includes: a lower portion located in the substrate; and an upper portion inserted between the substrate and the storage capacitor, wherein the lower portion has a first critical dimension and the upper portion has a second critical dimension, the second critical dimension being greater than the first critical dimension.

[0031] In some embodiments, the first critical dimension of the lower portion of the conductive feature gradually decreases at locations where the distance from the upper portion increases.

[0032] In some embodiments, the access transistor further includes: a word line disposed in the substrate and spanning the active region, wherein the impurity region is disposed on either side of the word line; and an insulating liner sandwiched between the substrate and the word line.

[0033] In some embodiments, the semiconductor element further includes: a dielectric layer located between the storage capacitor and the substrate to encapsulate the access transistor and surround the conductive feature; a bit line embedded in the dielectric layer; and a conductive plug extending from the bit line.

[0034] In some embodiments, the storage capacitor includes: a plurality of storage nodes, each in contact with the conductive feature; a capacitor insulator encapsulating the plurality of storage nodes; and a top electrode disposed on the capacitor insulator.

[0035] In some embodiments, the storage capacitor includes: a plurality of storage nodes, each in contact with the conductive feature; a capacitor insulator encapsulating the plurality of storage nodes; and a top electrode disposed on the capacitor insulator. The method includes: providing a substrate including a first region and a second region, wherein the substrate has a first surface and a second surface opposite to the first surface; forming a plurality of first trenches in the first region and a second trench in the second region; forming a doped region in the substrate; forming a plurality of first liner layers in the plurality of first trenches and a second liner layer in the second trench; forming a plurality of first embedding portions of a plurality of first insulating segments in the plurality of first trenches and a second embedding portion of a second insulating segment in the second trench; forming a plurality of first extension portions of the plurality of first insulating segments over the plurality of first embedding portions and a second extension portion of the second insulating segment over the second embedding portions; and removing a portion of the substrate from the second surface to expose the plurality of first insulating segments, the plurality of first liner layers, the second insulating segment, and the second liner layer.

[0036] In some embodiments, the plurality of first trenches and the second trenches are formed by photolithography and etching processes.

[0037] In some embodiments, the formation of the doped region includes performing an implantation process on the first surface of the substrate.

[0038] In some embodiments, the formation of the plurality of first liner layers and the second liner layer includes: depositing a liner layer on the first surface, on the plurality of side surfaces of the plurality of first trenches, on one side surface of the second trench, and on a bottom surface of the second trench; and performing an etching process on the liner layer to form the plurality of first liner layers and the second liner layer.

[0039] In some embodiments, forming the plurality of first embedded portions and the second embedded portions includes: depositing a first insulating layer in the plurality of first trenches and the second trenches and covering the first surface of the substrate; and performing a planarization process to remove a portion of the first insulating layer located on the first surface of the substrate.

[0040] In some embodiments, the formation of the plurality of first extension portions and the second extension portions includes: depositing a second insulating layer on the first surface of the substrate; performing a photolithography process to form a second mask layer; performing an etching process based on the second mask layer; and removing the second mask layer.

[0041] In some embodiments, the method further includes: forming a fill layer on the first surface of the substrate to surround the extension portions of the plurality of first insulating segments and the extension portions of the second insulating segments.

[0042] In some embodiments, the method further includes forming a character line hard mask layer on the plurality of first extensions, the plurality of second extensions and the fill layer.

[0043] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0044] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments with the scope of the patent application. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased. Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor element according to some embodiments of this disclosure. Figures 2 to 17 are cross-sectional views illustrating the manufacturing process of semiconductor devices according to some embodiments of this disclosure. Figure 18 is a flowchart illustrating methods for manufacturing semiconductor devices according to various embodiments of this disclosure. Figures 19 to 29 are cross-sectional views illustrating the manufacturing process of semiconductor devices according to various embodiments of this disclosure. Figure 30 is a cross-sectional view illustrating semiconductor elements of various embodiments of this disclosure. Implementation

[0045] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0046] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used in this document to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagram, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0047] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0048] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0049] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure when referring to orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, quantities, or other measures within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly the same, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0050] In this disclosure, semiconductor devices generally refer to devices that can operate using semiconductor properties, and electro-optic devices, light-emitting display devices, semiconductor circuits and electronic devices are all included in the category of semiconductor devices.

[0051] It should be noted that in the description disclosed herein, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0052] Figure 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor element 1 according to some embodiments of this disclosure. Figures 2 to 17 are cross-sectional views illustrating the manufacturing process of a semiconductor element 1 according to some embodiments of this disclosure.

[0053] Referring to Figures 1 to 6, in step S11, a substrate 101 including a first region R1 and a second region R2 can be provided. A plurality of first trenches TR1 can be formed in the first region R1, and a second trench TR2 can be formed in the second region R2.

[0054] Referring to Figure 2, substrate 101 may include a main semiconductor substrate. The main semiconductor substrate may be formed of materials such as elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0055] In some embodiments, substrate 101 may include an insulator-on-semiconductor structure comprising, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may be formed of the same material as the main semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides in any order, specifically a stack of silicon oxide and either silicon nitride or boron nitride. The insulating layer may have a thickness between about 10 nm and 200 nm.

[0056] It should be noted that in the description of this disclosure, when the term "about" is used to modify the amount of an ingredient, component, or reactant of this disclosure, it refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method, etc. On one hand, the term "about" means within 10% of the reported value. On another hand, the term "about" means within 5% of the reported value. And yet another hand, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0057] Referring to Figure 2, in some embodiments, the first region R1 and the second region R2 may be adjacent to each other. In some embodiments, the first region R1 and the second region R2 may be separated from each other. It should be noted that the first region R1 may include a portion of the substrate 101 and the space above this portion of the substrate 101. Describing an element disposed on the first region R1 means that the element is disposed on the top surface of this portion of the substrate 101. Describing an element disposed in the first region R1 means that the element is disposed in this portion of the substrate 101; however, the top surface of the element may be flush with the top surface of this portion of the substrate 101. Describing an element disposed above the first region R1 means that the element is disposed above the top surface of this portion of the substrate 101. Accordingly, the second region R2 includes another portion of the substrate 101 and the space above this other portion of the substrate 101. In some embodiments, the first region R1 and the second region R2 may have different element densities, which will be described below.

[0058] Referring to FIG3, a bottom hard mask layer 701 can be formed on substrate 101. In some embodiments, the bottom hard mask layer 701 can be formed of, for example, silicon oxide. In some embodiments, the bottom hard mask layer 701 can be formed by rapidly thermally oxidizing the intermediate semiconductor element shown in FIG2 in an oxide / oxygen oxide gas environment. In some embodiments, the rapid thermal oxidation temperature can be about 1000°C.

[0059] Referring to Figure 3, a top hard mask layer 703 can be formed on the bottom hard mask layer 701. In some embodiments, the top hard mask layer 703 can be formed of, for example, silicon oxide. In some embodiments, the top hard mask layer 703 can be formed by, for example, chemical vapor deposition or plasma-enhanced chemical vapor deposition. For example, a silicate or silicon source, a plurality of dopant sources, and an ozone source can be used, and the top hard mask layer 703 can be deposited by chemical vapor deposition. In some embodiments, the dopant source can be, for example, triethyl borate, triethyl phosphate, triethyl phosphite, trimethyl phosphate, or trimethyl phosphite. In some embodiments, the silicate or silicon source can be, for example, tetramethyl orthosilicate. The dopant source can generate impurity atoms, for example, phosphorus or boron, in the top hard mask layer 703.

[0060] Referring to Figure 3, a first masking layer 901 can be formed on the top rigid masking layer 703. In some embodiments, the first masking layer 901 may be a photoresist layer and may include a pattern of a plurality of first trenches TR1 and second trenches TR2.

[0061] Referring to Figure 4, a hard mask etching process can be performed using a first mask layer 901 as a mask to remove a portion of the top hard mask layer 703 and a portion of the bottom hard mask layer 701. After the hard mask etching process, the pattern of the first mask layer 901 can be transferred to the top hard mask layer 703 and the bottom hard mask layer 701. The patterns transferred from the first mask layer 901 can be referred to as the first pattern P1 and the second pattern P2. The first pattern P1 can be formed over a first region R1. The second pattern P2 can be formed over a second region R2. Multiple portions of the top surface 101T of the substrate 101 can be exposed by the first pattern P1 and the second pattern P2.

[0062] In some embodiments, the etching rate of the top hard mask layer 703 (or the etching rate of the bottom hard mask layer 701) during the hard mask etching process may be greater than the etching rate of the substrate 101 during the hard mask etching process. For example, the ratio of the etching rate of the top hard mask layer 703 (or the etching rate of the bottom hard mask layer 701) to the etching rate of the substrate 101 during the hard mask etching process may be between about 100:1 and about 2:1. As another example, the ratio of the etching rate of the top hard mask layer 703 (or the etching rate of the bottom hard mask layer 701) to the etching rate of the substrate 101 during the hard mask etching process may be between about 100:1 and about 10:1.

[0063] Referring to Figure 5, after the first pattern P1 and the second pattern P2 are formed, the first mask layer 901 can be removed. In some embodiments, the removal of the first mask layer 901 may include, for example, an ashing process or other suitable semiconductor process.

[0064] Referring to Figure 5, a trench etching process can be performed using a bottom hard mask layer 701 and a top hard mask layer 703 as masks to remove a portion of the substrate 101. This process results in the formation of a plurality of first trenches TR1 in a first region R1 of the substrate 101 and a second trench TR2 in a second region R2 of the substrate 101.

[0065] In some embodiments, the etching rate of substrate 101 during the trench etching process may be greater than the etching rate of the top hard mask layer 703 (or the etching rate of the bottom hard mask layer 701) during the trench etching process. For example, the ratio of the etching rate of substrate 101 to the etching rate of the top hard mask layer 703 (or the etching rate of the bottom hard mask layer 701) during the trench etching process may be between about 100:1 and about 2:1. As another example, the ratio of the etching rate of substrate 101 to the etching rate of the top hard mask layer 703 (or the etching rate of the bottom hard mask layer 701) during the trench etching process may be between about 100:1 and about 10:1.

[0066] In some embodiments, the first region R1 may have a larger element density (or pattern density or feature density) than the second region R2. Element density is a value determined by dividing the number of elements (e.g., first trenches TR1 or second trenches TR2) formed in the first region R1 (or the second region R2) by the surface area of ​​the corresponding region as viewed from the top view. From a cross-sectional perspective, regions with higher element density include more elements, and the distance between adjacent elements (or features) in this region is smaller than the distance between adjacent elements (or features) in regions with lower element density. As shown in Figure 5, the presence of more first trenches TR1 emphasizes that the first region R1 has a greater element density than the second region R2. It should be noted that the number of first trenches TR1 and second trenches TR2 shown in Figure 5 are for illustrative purposes only.

[0067] In some embodiments, a post-etch cleaning process can be performed after the formation of a plurality of first trenches TR1 and second trenches TR2. The post-etch cleaning process may include three stages, with inter-stage rinsing between each stage. Specifically, during the first stage of the post-etch cleaning process, after the formation of the plurality of first trenches TR1 and second trenches TR2, a first cleaning solution may be applied to the intermediate semiconductor device. The first cleaning solution may be rinsed by a first inter-stage rinsing. During the second stage of the post-etch cleaning process, a second cleaning solution may be applied to the intermediate semiconductor device, and the second cleaning solution may subsequently be rinsed by a second inter-stage rinsing. During the third stage of the post-etch cleaning process, a third cleaning solution may be applied to the intermediate semiconductor device, and then rinsed by a post-stage rinsing.

[0068] In some embodiments, during the first stage of the post-etch cleaning process, the intermediate semiconductor element may be rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and about 1000 rpm. A first cleaning solution may be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. Simultaneously, water or a suitable solution may be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0069] In some embodiments, the first cleaning solution may include dilute hydrofluoric acid. The concentration of the first cleaning solution may be between about 5 parts deionized water to 1 part hydrofluoric acid, about 1000 parts deionized water to 1 part hydrofluoric acid, about 300 parts deionized water to 1 part hydrofluoric acid, or about 50 parts deionized water to 1 part hydrofluoric acid. Generally, the front side of the intermediate semiconductor device may be exposed to the first cleaning solution for a sufficient time to etch sacrificial oxide (typically about 50 Å to 200 Å) or native oxide (typically about 10 Å). In some embodiments, the process time of the first stage of the post-etching cleaning process may be between about 20 seconds and about 50 seconds, about 40 seconds, or about 30 seconds. In some embodiments, the process time of the first stage of the post-etching cleaning process may be between about 1 minute and about 5 minutes.

[0070] In some embodiments, the first cleaning solution may further include fluorides, organic acid salts, and / or glyoxylic acid.

[0071] The first cleaning solution may include fluorides as a component for removing etching residues from the trench etching process. Examples of fluorides may include hydrofluoric acid and ammonium fluoride or amine fluoride salts, such as ammonium fluoride, ammonium hydrogen fluoride, methylamine hydrofluoride, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrofluoride, methylethanolamine hydrofluoride, dimethylethanolamine hydrofluoride, and triethylenediamine hydrofluoride. In some embodiments, the concentration of fluoride in the first cleaning solution may be determined based on the composition of the etching residues. For example, the concentration of fluoride may be between about 0.1% by mass and about 5% by mass of the total composition of the first cleaning solution, or between about 0.2% by mass and about 3% by mass of the total composition of the first cleaning solution.

[0072] Organic acid salts may include, for example, ammonium oxalate, ammonium tartrate, ammonium citrate, and ammonium acetate. Organic acid salts may act as pH adjusters or buffers in the first cleaning solution. The concentration of the organic acid salt may be between about 0.1% by mass and about 10% by mass of the total composition of the first cleaning solution, or between about 0.3% by mass and about 5% by mass of the total composition of the first cleaning solution.

[0073] The glyoxylic acid contained in the first cleaning solution can act as a corrosion inhibitor.

[0074] In some embodiments, the first cleaning solution may further include a photoresist removal component. Examples of photoresist removal components may include tetramethylammonium hydroxide and monomethylamine.

[0075] An inter-stage rinse can be performed after the first stage of the post-etching cleaning process. During the inter-stage rinse, the intermediate semiconductor device can be rotated at a rate between about 10 rpm and about 100 rpm while being rinsed with deionized water. In some embodiments, the rinse temperature can be between about 19°C and about 23°C. In some embodiments, the process time for the inter-stage rinse can be between about 20 seconds and about 50 seconds or about 30 seconds.

[0076] In some embodiments, before rinsing the intermediate semiconductor components, the deionized water used for the first interstage rinse can be oxygenated or ozonated by dissolving oxygen or ozone gas. Dissolved oxygen or dissolved ozone can be added to the deionized water at a concentration greater than 1 ppm as an oxidant. For example, the concentration of dissolved oxygen or dissolved ozone can be between about 1 ppm and about 200 ppm, or between about 2 ppm and about 20 ppm. Alternatively, the deionized water can be saturated with dissolved oxygen or dissolved ozone. Alternatively, hydrogen peroxide can be added to the deionized water at a concentration greater than 100 ppm as an oxidant. Regardless of the oxidant used, it should have an oxidation potential sufficient to oxidize the most inert metal in the solution. Copper (Cu²⁺) has a standard reduction potential of 0.3 V and is typically the most inert metal present. Therefore, a standard reduction potential greater than 0.5 V is required. Oxygen or ozone solubilizes the metal ions and prevents precipitation by oxidizing the metal ions in the solution. This makes the first interstage rinse more effective and helps reduce process time.

[0077] In some embodiments, the deionized water used for the first-stage inter-rinse may include dissolved carbon dioxide to dissipate static electricity accumulated in the deionized water. Static electricity in the deionized water may originate from the rotation of intermediate semiconductor elements. The dissolved carbon dioxide may also make the deionized water more acidic, thus reducing any metal contamination. In some embodiments, the amount of carbon dioxide dissolved in the deionized water may be sufficient to dissipate static electricity. For example, the amount of carbon dioxide dissolved in the deionized water may be sufficient to reduce the resistivity of the deionized water to less than 5 MΩ-cm.

[0078] In some embodiments, the deionized water used for the first-stage inter-rinse may be mixed with isopropanol or any other liquid with a surface tension less than that of deionized water. Isopropanol can assist in faster removal of chemicals by spreading the deionized water over the front side of the intermediate semiconductor element. Isopropanol can also aid in rinsing and spin-drying the intermediate semiconductor element during rotation. Alternatively, isopropanol vapor can be blown onto the front side of the intermediate semiconductor element during rinsing to assist in the first-stage inter-rinse.

[0079] In some embodiments, during the second stage of the post-etching cleaning process, the intermediate semiconductor element may be rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. A second cleaning solution may be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. Simultaneously, water or a suitable solution may be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0080] In some embodiments, the second cleaning solution may be an alkaline solution, comprising, for example, an aqueous solution of an inorganic compound (e.g., sodium hydroxide, potassium hydroxide, and ammonium hydroxide) and an aqueous solution of an organic compound (e.g., tetramethylammonium hydroxide and choline). The second cleaning solution may also include hydrogen peroxide. The purpose of the ammonium hydroxide and hydrogen peroxide in the second cleaning solution is to remove particles and residual organic contaminants from the front side of the intermediate semiconductor device.

[0081] In this embodiment, the second cleaning solution may include, for example, ammonium hydroxide, hydrogen peroxide, and water. The ammonium hydroxide, hydrogen peroxide, and water may be present at concentrations defined by dilution ratios between 5 / 1 / 1 and 1000 / 1 / 1. In some embodiments, the ammonium hydroxide / hydrogen peroxide ratio may be between 0.05 / 1 and 5 / 1. In some embodiments, hydrogen peroxide is not used. The ammonium hydroxide in the second cleaning solution may include ammonium hydroxide with a concentration of 28-29% w / w. The hydrogen peroxide in the second cleaning solution may include hydrogen peroxide with a concentration of 31-32% w / w relative to water. Due to the ammonium hydroxide and hydrogen peroxide, the pH of the second cleaning solution may be between about 9 and 12 or between about 10 and 11.

[0082] In some embodiments, the second cleaning solution may further include dissolved hydrogen. The dissolved hydrogen in the second cleaning solution can provide cavitation (bubble generation) to the second cleaning solution. Providing cavitation to the second cleaning solution can enhance the post-etching cleaning process. In some embodiments, the concentration of dissolved hydrogen may be between about 0.01 mg / L and about 5 mg / L, or between about 0.1 mg / L and about 5 mg / L. In some embodiments, other suitable cavitation gases may also be used, such as nitrogen, helium, argon, or oxygen. For example, dissolved oxygen at a concentration between about 1 mg / L and about 20 mg / L can be used in the second cleaning solution.

[0083] In some embodiments, the process time for the second stage of the post-etching cleaning process may be between about 30 seconds and about 100 seconds, between about 30 seconds and 90 seconds, or between about 30 seconds and about 60 seconds. In some embodiments, the temperature of the second cleaning solution may be between about 40°C and about 85°C.

[0084] A second-stage rinse can be performed after the second stage of the post-etching cleaning process. The procedure for the second-stage rinse is similar to that for the first-stage rinse and will not be repeated here.

[0085] In some embodiments, during the third stage of the post-etching cleaning process, the intermediate semiconductor element may be rotated at a rate between about 10 rpm and about 2000 rpm, or between about 100 rpm and 1000 rpm. A third cleaning solution may be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. Simultaneously, water or a suitable solution may be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0086] In some embodiments, the third cleaning solution may be an acidic solution, including, for example, aqueous solutions of inorganic acids (e.g., hydrochloric acid, hydrofluoric acid, sulfuric acid, and nitric acid) and aqueous solutions of organic acids (e.g., oxalic acid, citric acid, malonic acid, malic acid, fumaric acid, and maleic acid). In some embodiments, the third cleaning solution may also include hydrogen peroxide. The concentration of the acidic solution may be between about 0.001% by weight and about 10% by weight, or between about 0.01% by weight and about 5% by weight. When the concentration is too low, the cleaning effect may be insufficient. When the concentration is too high, metal corrosion of the washing equipment or other related equipment may occur.

[0087] Post-stage rinsing can be performed after the third stage of the post-etching cleaning process. The post-stage rinsing procedure is similar to the inter-stage rinsing and will not be described in detail here.

[0088] In some embodiments, the second and third stages of the post-etching cleaning process are not necessary. In other words, in some embodiments, only the first stage of the post-etching cleaning process is performed. In some embodiments, the third stage of the post-etching cleaning process is not necessary. In other words, in some embodiments, only the first and second stages of the post-etching cleaning process are performed.

[0089] Referring to Figure 6, the top hard mask layer 703 and the bottom hard mask layer 701 can be removed by, for example, an etching process (e.g., a wet etching process or a dry etching process). In this embodiment, the top hard mask layer 703 and the bottom hard mask layer 701 can be removed by a wet etching process. In some embodiments, during the etching process, the ratio of the etching rate of the top hard mask layer 703 (or the etching rate of the bottom hard mask layer 701) to the etching rate of the substrate 101 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0090] Referring to Figures 1 and 7 to 12, in step S13, a plurality of first outer filling layers 301 can be formed in a plurality of first trenches TR1, a plurality of first central layers 303 can be formed on the plurality of first outer filling layers 301 and in the plurality of first trenches TR1, a second outer filling layer 401 can be formed in the second trench TR2, a second central layer 403 can be compliantly formed on the second outer filling layer 401, and a second inner filling layer 405 can be formed on the second central layer 403 and in the second trench TR2.

[0091] Referring to Figure 7, a repair layer 201 can be compliantly formed on substrate 101, in a plurality of first trenches TR1, and in second trenches TR2. In some embodiments, the repair layer 201 may be formed of, for example, silicon. In some embodiments, the repair layer 201 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes. In some embodiments, the repair layer 201 may fill the seams of the plurality of first trenches TR1 and second trenches TR2. In some embodiments, the repair layer 201 may serve as a buffer layer or a stress-reducing layer. The repair layer 201 can be used to mitigate mechanical stress caused by the difference in the coefficients of thermal expansion between substrate 101 and subsequently deposited insulating material.

[0092] Referring to Figure 8, a first filler material 601 can be compliantly formed on the repair layer 201. This first filler material 601 may only partially cover the plurality of first trenches TR1 and second trenches TR2. Specifically, this first filler material 601 can be compliantly formed on the surface of the repair layer 201 in the plurality of first trenches TR1 and second trenches TR2, thereby forming an upward-facing groove RS1 (or first groove RS1) in the plurality of first trenches TR1 and an upward-facing groove RS2 (or second groove RS2) in the second trenches TR2. In some embodiments, the top surface of this first filler material 601 may vary with region due to the loading effect of the deposit. In some embodiments, the first filler material 601 may include silicon oxide or other suitable insulating materials.

[0093] In some embodiments, the first filler material 601 may be formed of, for example, silicon oxide. In some embodiments, the first filler material 601 may be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition or other suitable deposition processes.

[0094] In some embodiments, the first filler material 601 can be formed by thermal oxidation and subsequent deposition processes. For example, the first filler material 601 can be formed by: firstly, performing rapid thermal oxidation on the intermediate semiconductor device shown in FIG7 in an oxide / oxide-nitrogen atmosphere to compliantly form a thin layer (not shown for clarity) on the repair layer 201. Subsequently, a flowable layer (not shown for clarity) can be compliantly formed on this thin layer. Finally, this flowable layer can be converted into the first filler material 601.

[0095] In some embodiments, the flowable layer may include a compound having unsaturated bonds (e.g., double and triple bonds). The flowable layer may be characterized as a soft jelly-like layer, a gel with liquid flow properties, or a liquid layer, but is not limited thereto. The flowable layer can flow into and fill small substrate gaps without forming voids or weak seams. Subsequently, a heat treatment can be performed to solidify the flowable layer, thereby transforming it into the first filler material 601. The heat treatment can break unsaturated bonds into free radicals, and the compound can be cross-linked by the free radicals. This allows the flowable layer to solidify. In some embodiments, the volume of the flowable layer may be reduced during the thermal process. Therefore, the density of the first filler material 601 may be greater than the density of the flowable layer. The first filler material 601 may be located in positions previously occupied by the flowable layer. In other words, the first filler material 601 may be compliantly disposed on the top surface 101T of the substrate 101, in a plurality of first trenches TR1, and in second trenches TR2.

[0096] In some embodiments, the flowable layer may be a flowable silicon-and-nitrogen-containing layer. A carbon-free silicon-containing precursor can be mixed with a radical-nitrogen precursor to form the flowable silicon-and-nitrogen-containing layer. The flowability of the flowable silicon-and-nitrogen-containing layer allows it to flow into narrow substrate gaps or narrow trenches. During the formation of the flowable silicon-and-nitrogen-containing layer, the temperature of the substrate 101 may be less than 120°C, less than 100°C, less than 80°C, or less than 60°C.

[0097] The carbon-free silicon-containing precursor can be, for example, a silicon-and-nitrogen precursor, a silicon-and-hydrogen precursor, or a silicon-nitrogen-and-hydrogen-containing precursor. In some embodiments, the carbon-free silicon-containing precursor can also be oxygen-free. The lack of oxygen results in a lower concentration of silanol (Si-OH) groups in the flowable silicon-and-nitrogen-containing layer formed from the carbon-free silicon-and-nitrogen precursor. Excess silanol in the flowable silicon-and-nitrogen-containing layer can lead to increased porosity and shrinkage during subsequent processes that remove the hydroxyl (-OH) moiety from the flowable silicon-and-nitrogen-containing layer.

[0098] In some embodiments, the carbon-free silicon-containing precursor may include silyl-amines, such as monosilyl-amines (H₂N(SiH₃)), disilyl-amines (HN(SiH₃)₂), and trisilyl-amines (N(SiH₃)₃). The flow rate of the silyl-amine may be greater than or about 200 sccm, greater than or about 300 sccm, or greater than or about 500 sccm. The silyl-amine may be mixed with an additional gas, which may be used as a carrier gas, a reactant gas, or both. Examples of additional gases include hydrogen (H₂), nitrogen (N₂), ammonia (NH₃), helium (He), and argon (Ar).

[0099] In some embodiments, carbon-free silicon-containing precursors may include silane alone or silane mixed with other silicon-containing gases (e.g., trisilylamine, N(SiH3)3), hydrogen-containing gases (e.g., H2), and / or nitrogen-containing gases (e.g., N2, NH3).

[0100] In some embodiments, carbon-free silicon-containing precursors may include disilane, trisilane, higher-order silane, or chlorosilane, either alone or in combination with silylamine.

[0101] A radical nitrogen precursor can be generated by delivering ammonia to the plasma region. The radical nitrogen precursor can then be delivered to mix with a carbon-free silicon-containing precursor. The flow rate of ammonia delivered to the plasma region can be greater than or about 300 sccm, greater than or about 500 sccm, or greater than or about 700 sccm. In some embodiments, a gas (e.g., nitrogen and hydrogen) can be used to adjust the nitrogen:hydrogen atomic flow ratio. In some embodiments, a gas (e.g., helium or argon) can be used as the carrier gas for delivering ammonia to the plasma region.

[0102] In some embodiments, radical nitrogen precursors can be generated without the use of ammonia. One or more gases, including hydrogen, nitrogen, and hydrazine, can be delivered to the plasma region to generate radical nitrogen precursors.

[0103] Subsequently, a curing process and an annealing process can be sequentially applied to the flowable silicon and nitrogen-containing layer (i.e., the flowable layer) in an oxygen-containing atmosphere to transform the flowable silicon and nitrogen-containing layer into a first filler material 601 comprising silicon oxide. In some embodiments, the substrate temperature of the curing process can be below or at about 400°C. For example, the substrate temperature of the curing process can be between about 100°C and about 200°C. In some embodiments, the substrate temperature of the annealing process can be between about 500°C and about 1100°C. In some embodiments, the oxygen-containing atmosphere can include one or more oxygen-containing gases, such as molecular oxygen, ozone, water vapor, hydrogen peroxide, and nitrogen oxides (e.g., nitric oxide, nitrous oxide, etc.).

[0104] Alternatively, in some embodiments, a flowable layer can be formed by reacting a vapor precursor with a co-reactant. The flowable layer can have flow characteristics capable of providing consistent filling of the substrate gaps of the substrate 101. Subsequently, a post-deposition treatment can be performed, and the flowable layer can be physically densified and / or chemically transformed to reduce its flowability. After the post-deposition treatment, the flowable layer can be transformed into a first filler material 601. In some embodiments, the densified flowable layer can be considered as cured. In some embodiments, physical densification of the flowable layer can involve shrinking the flowable layer. In some embodiments, the post-deposition treatment can involve replacing the chemical substances in the flowable layer, thereby producing a denser layer of first filler material 601 with a larger volume.

[0105] In some embodiments, the flowable layer may include flowable silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the flowable layer may include silicon carbide or silicon carbide. In some embodiments, the cavity pressure for forming the flowable layer may be between about 1 Torr and 200 Torr, between 10 Torr and 75 Torr, or about 10 Torr. In some embodiments, the substrate temperature for forming the flowable layer may be between about -20°C and about 100°C, between about -20°C and about 30°C, or between about -10°C and about 10°C.

[0106] In some embodiments, the gas-phase precursor may include a silicon-containing precursor or a carbon-containing precursor. Co-reactants may include an oxidant, a catalyst, a surfactant, or an inert carrier gas.

[0107] Silicon-containing precursors may include, but are not limited to: silane, disilane, trisilane, hexasilane, cyclohexasilane, alkoxysilane, aminosilane, alkylsilane, tetraisocyanatesilane (TIS), hydrogen silsesquioxane, T8-hydridospherosiloxane, or 1,2-dimethoxy-1,1,2,2-tetramethyldisilane.

[0108] Alkoxysilanes can include tetraoxymethylcyclotetrasiloxane (TOMCTS), octamethylcyclotetrasiloxane (OMCTS), tetraethoxysilane (TES), triethoxysilane (TES), trimethoxysilane (TriMOS), methyltriethoxyorthosilicate (MTEOS), tetramethylorthosilicate (TMS), methyltrimethoxysilane (MTMOS), dimethyldimethoxysilane (DMDMOS), diethoxysilane (DES), and dimethoxysilane. DMOS), triphenylethoxysilane, 1-(triethoxysilyl)-2-(diethoxymethylsilyl)ethane, tri-t-butoxylsilanol, hexamethoxydisilane (HMODS), hexaethoxydisilane (HEODS), or tert-butoxydisilane. Aminosilanes may include bis-tert-butylaminosilane (BTBAS) or tris(dimethylamino)silane.

[0109] Carbon-containing precursors may include, but are not limited to: trimethylsilane (3MS), tetramethylsilane (4MS), diethoxymethylsilane (DEMS), dimethyldimethoxysilane, methyl-triethoxysilane (MTES), methyl-trimethoxysilane, methyl-diethoxysilane, trimethoxymethylsilane, dimethoxymethylsilane, or bis(trimethylsilyl)carbodiimide.

[0110] Oxidizing agents may include, but are not limited to: ozone, hydrogen peroxide, oxygen, water, alcohols, nitric oxide, nitrogen dioxide, nitrous oxide, carbon monoxide, or carbon dioxide. Alcohols may include, for example, methanol, ethanol, or isopropanol.

[0111] Catalysts may include, but are not limited to: proton precursor catalysts, halogenated compounds, inorganic acids, bases, chlorodiethoxysilanes, methanesulfonic acid, trifluoromethanesulfonic acid, chlorodimethoxysilanes, pyridine, acetyl chloride, chloroacetic acid, dichloroacetic acid, trichloroacetic acid, oxalic acid, benzoic acid, or triethylamine. Proton precursor catalysts may include nitric acid, hydrofluoric acid, phosphoric acid, sulfuric acid, hydrochloric acid, bromic acid, carboxylic acid derivatives, ammonia, ammonium hydroxide, hydrazine, or hydroxylamine. Halogenated compounds may include dichlorosilanes, trichlorosilanes, methylchlorosilanes, chlorotriethoxysilanes, chlorotrimethoxysilanes, chloromethyldiethoxysilanes, chloromethyldimethoxysilanes, vinyltrichlorosilanes, diethoxydichlorosilanes, or hexachlorodisiloxanes. Inorganic acids may include formic acid or acetic acid. Bases may include phosphine.

[0112] Surfactants can include solvents, alcohols, ethylene glycol, or polyethylene glycol. Surfactants can be used to reduce surface tension and increase the wettability of reactants on substrate surfaces. Surfactants can also increase the miscibility of vapor-phase precursors with other reactants.

[0113] Solvents can be nonpolar or polar, and protic or aprotic. The choice of solvent can be matched to the gas-phase precursor to improve miscibility with the oxidant. Nonpolar solvents can include alkanes and alkenes; polar aprotic solvents can include acetone and acetates; polar protic solvents can include alcohols and carboxylic acid compounds.

[0114] Examples of solvents include, but are not limited to: methanol, ethanol, isopropanol, acetone, diethyl ether, acetonitrile, dimethylformamide, dimethyl sulfoxide, tetrahydrofuran, dichloromethane, hexane, benzene, toluene, and isoheptane. In some embodiments, the solvent may be introduced before other reactants.

[0115] Inert carrier gases may include nitrogen, helium, or argon.

[0116] Post-deposition treatments can crosslink and remove terminal groups, such as hydroxyl (-OH) and hydrogen (-H) groups, from the flowable layer, thereby increasing the density and stiffness of the flowable layer. Post-deposition treatments can include thermal curing, exposure to downstream or direct plasma, exposure to ultraviolet or microwave radiation, or exposure to other energy sources.

[0117] When thermosetting is used as a post-deposition treatment, the thermosetting temperature can be between approximately 200°C and 600°C. The post-deposition treatment can be performed in an inert environment, an oxidizing environment, a nitriding environment, or an environment that is both oxidizing and nitriding. An inert environment can include argon or helium. An oxidizing environment can include oxygen, ozone, water, hydrogen peroxide, nitrous oxide, nitric oxide, nitrogen dioxide, carbon monoxide, or carbon dioxide. A nitriding environment can include nitrogen, ammonia, nitrous oxide, nitric oxide, or nitrogen dioxide. The thermosetting pressure can be between approximately 0.1 Torr and approximately 10 Torr.

[0118] When using exposure to downstream or direct plasma as a post-deposition treatment, the plasma can be an inert or reactive plasma. Inert plasmas can include helium or argon plasmas. Reactive plasmas can include oxidizing or hydrogen-containing plasmas, wherein oxidizing plasmas include oxygen and vapor, and hydrogen-containing plasmas include hydrogen and a diluent, such as an inert gas. In some embodiments, the temperature during plasma exposure can be about 25°C or higher. In some embodiments, the temperature during plasma exposure can be between about -15°C and about 25°C.

[0119] Referring to Figure 8, the width W1 of the first groove RS1 can be smaller than the width W2 of the second groove RS2. In some embodiments, the thickness T1 of the first filling material 601 layer formed in the first groove TR1 can be greater than the thickness T2 of the first filling material 601 layer formed in the second groove TR2.

[0120] Referring to Figure 9, a second filler material 603 can be compliantly formed on this first filler material 601. Specifically, this second filler material 603 can completely fill the first groove RS1 and can only partially fill the second groove RS2. This second filler material 603 can be compliantly formed on the surface of this first filler material 601 in the second trench TR2 (i.e., in the second groove RS2), thereby forming an upward-facing groove RS3 (or a third groove RS3) in the second trench TR2.

[0121] In some embodiments, the second filler material 603 may be formed of a material having etch selectivity relative to the first filler material 601. In some embodiments, the second filler material 603 may include silicon nitride or other suitable insulating materials. In some embodiments, this layer of second filler material 603 may serve as a stop layer for subsequent planarization or etching processes. In some embodiments, this layer of second filler material 603 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0122] Referring to Figure 10, a third filler material 605 can be formed on this second filler material 603. In some embodiments, this third filler material 605 can completely fill the third trench RS3. In some embodiments, a pit may be formed above the second trench TR2. In some embodiments, the third filler material 605 can be formed of a material having etch selectivity relative to the second filler material 603. In some embodiments, the third filler material 605 can include the same material as the first filler material 601. In some embodiments, the third filler material 605 can include silicon oxide or other suitable insulating materials. In some embodiments, this third filler material 605 can be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0123] In some embodiments, a high aspect ratio process can be performed to deposit the third filler material 605, ensuring complete filling of the third groove RS3 and covering the second filler material 603. The high aspect ratio process can involve two stages. During the first stage, a low deposition rate is used to achieve more uniform trench filling and reduce the likelihood of void formation. In the second stage, a fast deposition rate is used to increase overall production efficiency by reducing deposition time. This high aspect ratio process combines stages with lower and higher deposition rates, strategically utilizing the low deposition rate to reduce defects and the fast deposition rate to shorten deposition time. Furthermore, in some embodiments, the pressure during the high aspect ratio process can range between about 200 Torr and about 760 Torr, while the temperature can range between about 400°C and about 570°C.

[0124] In some embodiments, a two-stage annealing process can be performed after the high aspect ratio process. During the first stage of the two-stage annealing, a lower temperature environment is used, comprising one or more oxygen-containing substances (e.g., water, oxygen, nitric oxide, or nitrous oxide). The purpose of the first stage is to rearrange and strengthen the silicon oxide network, thereby preventing the formation of voids and the opening of weak seams in the third groove RS3. Furthermore, the lower temperature in the first stage prevents oxygen from reacting with the trench walls and other parts of the substrate 101, which could potentially lead to the formation of an undesirable oxide layer.

[0125] Subsequently, in the second stage of the two-stage annealing, a higher temperature environment without oxygen is employed. The purpose of the second stage is to further rearrange the structure of the third filler material 605 and remove moisture, both of which increase the density of this layer of third filler material 605. The environment during the second stage includes, for example, substantially pure nitrogen, a mixture of nitrogen and an inert gas (e.g., helium, neon, argon, or xenon), or substantially pure inert gas. The environment during the second stage may also include gases with reduced content, such as hydrogen or ammonia. The second stage facilitates high-temperature densification without causing oxidation of the substrate 101.

[0126] Referring to Figure 11, after the two-stage annealing process, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 603T of the second filler material 603 is exposed to remove excess material and provide a substantially planar surface for subsequent process steps. This second filler material 603 can serve as a stop layer in the planarization process. At this stage, the top surface 603T of the second filler material 603 and the top surface 605T of the third filler material 605 can be substantially coplanar.

[0127] Referring to Figure 12, an etch-back process can be performed, in which most of the first filler material 601 is exposed and most of the second filler material 603 above the substrate 101 is removed. During the etch-back process, the etching rate of the third filler material 605 can be substantially the same as the etching rate of the second filler material 603. In some embodiments, the etch-back process can be a dry etching process. In some embodiments, a post-etch cleaning process can be performed after the etch-back process. The post-etch cleaning process can be performed using a process similar to that shown in Figure 5, and will not be described again here.

[0128] Referring to Figure 12, the remaining portion of the first filler material 601 may be referred to as the first outer filler layer 301 and the second outer filler layer 401. In some embodiments, the first outer filler layer 301 is disposed in the first region R1 and may include a plurality of first recessed portions 301C and a plurality of first flat portions 301F. The plurality of first recessed portions 301C are respectively and correspondingly disposed on the repair layer 201 and within the plurality of first trenches TR1. Each of the plurality of first recessed portions 301C may include a U-shaped cross-sectional profile forming an upward-facing first groove RS1. The ends of the plurality of first recessed portions 301C may protrude above the top surface 101T of the substrate 101. In some embodiments, the first flat portions 301F are disposed on the repair layer 201 and may be parallel to the top surface 101T of the substrate 101. The first flat portions 301F may extend between the ends of the plurality of first recessed portions 301C.

[0129] Referring to FIG12, in some embodiments, a second outer filler layer 401 is disposed in a second region R2 and may include a second recessed portion 401C and a second flat portion 401F. In some embodiments, the second recessed portion 401C is disposed on the repair layer 201 and in a second trench TR2. The second recessed portion 401C may include a U-shaped cross-sectional profile forming an upward-facing second groove RS2. The ends of the second recessed portion 401C may protrude above the top surface 101T of the substrate 101. In some embodiments, the second flat portion 401F is disposed on the repair layer 201 and may be parallel to the top surface 101T of the substrate 101. The second flat portion 401F may extend between the ends of the second recessed portion 401C. The first flat portion 301F and the second flat portion 401F may be connected and can be considered as a uniformly flat layer formed on the repair layer 201 and parallel to the top surface 101T of the substrate 101.

[0130] Referring to Figure 12, the remaining portion of the second filling material 603 can be referred to as a plurality of first central layers 303 and second central layers 403. For the sake of brevity, clarity, and convenience, only one first central layer 303 is described. In some embodiments, the first central layer 303 is disposed within the first recessed portion 301C and can completely fill the first groove RS1. At this stage, the top surface 303T of the first central layer 303, the top surface 301CT of the first recessed portion 301C, and the top surface 301FT of the first flat portion 301F can be substantially coplanar.

[0131] Referring to Figure 12, a second central layer 403 may be compliantly formed on the second recessed portion 401C and may include a U-shaped cross-sectional profile forming an upward-facing third groove RS3. The end of the second central layer 403 may protrude above the top surface 101T of the substrate 101. A second internal filling layer 405 may be formed within the second central layer 403 and completely fill the third groove RS3. At this stage, the top surface 405T of the second internal filling layer 405, the top surface 403T of the second central layer 403, the top surface 401CT of the second recessed portion 401C, and the top surface 401FT of the second flat portion 401F may be substantially coplanar. In some embodiments, the top surface 401FT of the second flat portion 401F and the top surface 301FT of the first flat portion 301F may be substantially coplanar.

[0132] Referring to Figure 12, in some embodiments, the thickness T1 of the first recessed portion 301C and the thickness T3 of the first flat portion 301F may be substantially the same. In some embodiments, the thickness T1 of the first recessed portion 301C and the thickness T3 of the first flat portion 301F may be different. In some embodiments, the thickness T2 of the second recessed portion 401C and the thickness T4 of the second flat portion 401F may be substantially the same. In some embodiments, the thickness T2 of the second recessed portion 401C and the thickness T4 of the second flat portion 401F may be different. In some embodiments, the thickness T3 of the first flat portion 301F and the thickness T4 of the second flat portion 401F may be substantially the same. In some embodiments, the thickness T1 of the first recessed portion 301C may be greater than the thickness T2 of the second recessed portion 401C.

[0133] Referring to Figures 1 and 13, in step S15, a plurality of first protective layers 501 can be formed on a plurality of first central layers 303, and a second protective layer 503 can be formed on a second central layer 403.

[0134] Referring to Figure 13, a surface oxidation process can be performed to oxidize the top ends of a plurality of first central layers 303 and the top ends of second central layers 403. In this embodiment, the plurality of first central layers 303 and second central layers 403 are formed of silicon nitride. The oxidized ends of the plurality of first central layers 303 and the oxidized ends of the second central layers 403 can be referred to as a plurality of first protective layers 501 and a plurality of second protective layers 503, respectively. The plurality of first protective layers 501 can be respectively disposed on the plurality of first central layers 303. The plurality of second protective layers 503 can be respectively disposed on the two ends 403E of the second central layer 403.

[0135] In some embodiments, the surface oxidation process can be a cryogenic plasma oxidation process. The cryogenic plasma oxidation process for converting silicon nitride to silicon oxide may involve multiple steps and specific process conditions. First, the intermediate semiconductor device shown in Figure 12 is loaded into a plasma-enhanced chemical vapor deposition (PECVD) chamber maintained at a low temperature between about 200°C and about 400°C. Then, a mixture of oxygen and an inert gas (e.g., nitrogen or argon) can be introduced into the chamber at a controlled flow rate. The oxygen flow rate can be between about 10 standard cubic centimeters per minute (sccm) and about 100 sccm, while the inert gas flow rate can vary between about 50 sccm and about 500 sccm. Radio frequency (RF) power can be applied to generate cryogenic plasma with power levels between about 50 watts and about 300 watts. Radio frequency power excites a gas mixture to generate active substances, including oxygen free radicals, which play a key role in cryogenic plasma oxidation processes.

[0136] During the cryogenic plasma oxidation process, oxygen radicals react with the silicon nitride surface, converting it into silicon oxide without requiring high temperatures. The cryogenic plasma oxidation process is self-limiting, meaning the reaction rate decreases as the silicon nitride layer is converted into silicon oxide. The oxidation time can be carefully controlled to achieve the desired thickness of the silicon oxide layers (i.e., the plurality of first protective layers 501 and second protective layers 503), typically ranging from several minutes to tens of minutes, depending on the desired film thickness and properties. After the oxidation step, the plasma is deactivated, and a purge gas (typically nitrogen) is introduced into the chamber to remove any residual active material and byproducts.

[0137] For the sake of brevity, clarity and convenience, only the first protective layer 501 will be described.

[0138] Referring to Figure 13, the bottom surface 501B of the first protective layer 501 may be at a vertical height VL1 higher than the top surface 101T of the substrate 101 or the top surface 201T of the repair layer 201. In some embodiments, the thickness T5 of the first protective layer 501 may be less than the thickness T3 of the first flat portion 301F. In some embodiments, the ratio of the thickness T5 of the first protective layer 501 to the thickness T3 of the first flat portion 301F may be between about 0.1 and about 0.8 or between about 0.3 and about 0.6. In some embodiments, the width W1 of the first central layer 303 and the width W3 of the first protective layer 501 may be substantially the same. In some embodiments, the ratio of the width W3 of the first protective layer 501 to the width W5 of the first recessed portion 301C may be between about 0.05 and about 0.35 or between about 0.10 and about 0.30.

[0139] Referring to Figure 13, the bottom surface 503B of the second protective layer 503 may be at a vertical height VL2 higher than the top surface 101T of the substrate 101 or the top surface 201T of the repair layer 201. In some embodiments, the thickness T6 of the second protective layer 503 may be less than the thickness T4 of the second flat portion 401F. In some embodiments, the ratio of the thickness T6 of the second protective layer 503 to the thickness T4 of the second flat portion 401F may be between about 0.1 and about 0.8 or between about 0.3 and about 0.6. In some embodiments, the width W4 of the second protective layer 503 and the width W6 of the second central layer 403 may be substantially the same. In some embodiments, the ratio of the width W7 of the second inner filling layer 405 to the width W8 of the second recessed portion 401C may be between about 0.60 and about 0.95 or between about 0.70 and about 0.90.

[0140] Referring to Figure 13, in some embodiments, the bottom surface 501B of the first protective layer 501 and the bottom surface 503B of the second protective layer 503 may be substantially coplanar. In some embodiments, the bottom surface 501B of the first protective layer 501 and the bottom surface 503B of the second protective layer 503 may be at different vertical heights.

[0141] Referring to Figures 1 and 14 to 17, in step S17, the Implantation Process (IMP) can be performed on the substrate 101, and a character line hard mask layer 203 can be formed on the substrate 101.

[0142] Referring to FIG. 14, a sacrificial mask layer 801 can be formed on the substrate 101 to cover the first outer filler layer 301, the first protective layer 501, the second outer filler layer 401, the second inner filler layer 405, and the second protective layer 503. In some embodiments, the sacrificial mask layer 801 can be formed of a material with high etch selectivity relative to the first outer filler layer 301 and the second outer filler layer 401. In some embodiments, the sacrificial mask layer 801 can be formed of a material different from the materials of the first outer filler layer 301 and the second outer filler layer 401. In some embodiments, the sacrificial mask layer 801 can be formed of silicon nitride. In some embodiments, the sacrificial mask layer 801 can be formed using a process similar to that used to form the second filler material 603 shown in FIG. 9, which will not be described again here.

[0143] During subsequent fabrication processes, the sacrificial mask layer 801 protects the first outer filler layer 301 and the second outer filler layer 401. As a protective shield, the sacrificial mask layer 801 prevents potential damage to the top surfaces of the aforementioned layers, which could occur during the fabrication process or during post-fabrication cleaning. Therefore, the sacrificial mask layer 801 is crucial in ensuring the integrity of the contact area of ​​the semiconductor device 1. Without the protection of the sacrificial mask layer 801, the active area of ​​the semiconductor device 1 would experience a reduction in contact area, leading to potential reliability issues and performance degradation. Therefore, the sacrificial mask layer 801 makes a significant contribution to the overall reliability and functionality of the semiconductor device 1.

[0144] Referring to Figure 15, implantation process IMP (Integrated Precipitation Manipulation) can be performed using p-type or n-type dopants to form the active region of semiconductor device 1 in substrate 101 (not shown for clarity). P-type dopants can be added to the intrinsic semiconductor to generate valence electron defects. Examples of p-type dopants in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium. N-type dopants can be added to the intrinsic semiconductor to contribute free electrons to it. Examples of n-type dopants in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus.

[0145] Following the implantation process (IMP), a post-implantation cleaning process can be performed. This post-implantation cleaning process is a critical step in ensuring the integrity and reliability of semiconductor device 1. After the implantation process (IMP), the intermediate semiconductor device can be rinsed with deionized water to remove loose particles and debris. Subsequently, a pre-cleaning step can be performed using a dilute acid solution (typically a 3:1 mixture of sulfuric acid and hydrogen peroxide) to remove metal contaminants and / or surface oxide layers. The intermediate semiconductor device can then be rinsed multiple times with deionized water to thoroughly remove any residual cleaning solution and contaminants. Next is the RCA cleaning step, using an RCA-2 solution composed of deionized water, hydrogen peroxide, and ammonium hydroxide in a 5:1:1 ratio, heated to a temperature between approximately 70°C and approximately 80°C. This step effectively removes metal ion contaminants and organic residues and ensures a cleaner surface. The intermediate semiconductor device can then be rinsed again to remove any residual cleaning chemicals or particles. Finally, the intermediate semiconductor device can be dried using a rotary dryer or a nitrogen stream to prevent watermarks or contamination.

[0146] Referring to Figure 16, the sacrificial mask layer 801 is selectively removed. This removal is achieved by an etching process with high etch selectivity relative to the sacrificial mask layer 801. During the etching process, in some embodiments, the etching rate of the sacrificial mask layer 801, which can be formed from silicon nitride, is greater than the etching rate of the first outer filler layer 301, the second outer filler layer 401, the first protective layer 501, and the second protective layer 503, which can be formed from silicon oxide, in some embodiments. For example, the etching process selectively removes silicon nitride while leaving silicon oxide intact.

[0147] The first protective layer 501 and the second protective layer 503 are used to prevent the first central layer 303 located beneath them and the second central layer 403 located beneath them from being removed during the etching process. Therefore, after the sacrificial mask layer 801 is removed, the top surfaces, namely the top surface 301FT of the first flat portion 301F, the top surface 301CT of the first recessed portion 301C, the top surface 501T of the first protective layer 501, the top surface 401FT of the second flat portion 401F, the top surface 401CT of the second recessed portion 401C, the top surface 405T of the second internal filling layer 405, and the top surface 503T of the second protective layer 503, are substantially coplanar. In other words, for subsequent semiconductor processes, the surface of the semiconductor element 1 can be complete and substantially flat. In some embodiments, the first protective layer 501, the first outer filling layer 301 and the first central layer 303 together constitute the first isolation structure of the semiconductor device 1, and the second inner filling layer 405, the second protective layer 503, the second central layer 403 and the second outer filling layer 401 together constitute the first isolation structure of the semiconductor device 1.

[0148] Referring to Figure 17, a character line hard mask layer 203 can be formed on the first outer filler layer 301, the second outer filler layer 401, the first protective layer 501, the second inner filler layer 405, and the second protective layer 503. In some embodiments, the character line hard mask layer 203 can be formed of the same material as the first central layer 303 or the second central layer 403. In some embodiments, the character line hard mask layer 203 can be formed of, for example, silicon nitride. In some embodiments, the character line hard mask layer 203 can be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0149] Figure 18 is a flowchart illustrating a method 20 for manufacturing a semiconductor element 2 according to various embodiments of the present disclosure. Figures 19 to 29 are cross-sectional views illustrating the manufacturing process of the semiconductor element 2 according to various embodiments of the present disclosure.

[0150] Referring to Figures 18 and 19, in step S21, a substrate 101 including a first region R1 and a second region R2 can be provided. A plurality of first trenches 107 can be formed in the first region R1, and a second trench 107' can be formed in the second region R2.

[0151] Referring to FIG19, substrate 101 may include a first surface 103 and a second surface 105. The first surface 103 of substrate 101 faces upward and is parallel to the second surface 105. The second surface 105 of substrate 101 faces downward and is opposite to the first surface 103 of substrate 101.

[0152] Referring to FIG19, a first trench 107 and a second trench 107' can be formed in a substrate 101. The first trench 107 and the second trench 107' can be recessed in the substrate 101 and have openings on a first surface 103 of the substrate 101. In some embodiments, a photolithography process can be performed by depositing a mask layer (not shown) on the first surface 103 of the substrate 101 to define the positions of the first trench 107 and the second trench 107' on the first surface 103 of the substrate. Next, an etching process, such as an anisotropic dry etching process, can be performed to form the first trench 107 and the second trench 107' in the substrate 101.

[0153] Referring to Figures 18 and 20, in step S23, a doped region 211 can be formed in the substrate 101. The doping region 211 can be formed in the substrate 101 by performing a placement process above the first surface 103 of the substrate 101. The doped region 211 can be disposed in the first surface 103 of the substrate 101, on the side surfaces of the first trench 107 and the second trench 107', and at the bottom of the first trench 107 and the second trench 107'. The resistivity of the doped region 211 can be less than or equal to the resistivity of the substrate 101.

[0154] Referring to Figures 18 and 21-22, in step S25, a plurality of first substrates 313 and second substrates 303' can be formed in the first trench 107 and the second trench 107', respectively. Referring to Figure 21, substrates 311 can be deposited on the first surface 103 of the substrate 101, the side surface 107S of the first trench 107, the side surface 107'S of the second trench 107', and the bottom 107B of the first trench 107 and the bottom 107'B of the second trench 107'. Substrate 311 can be formed of materials such as titanium, titanium nitride, titanium-tungsten alloy, tantalum, tantalum nitride, or combinations thereof. Referring to FIG22, an etching process, such as an anisotropic dry etching process, can be performed to form a plurality of first substrates 313 attached to the side surface 107S (see FIG21) of the first trench 107 and a second substrate 303' attached to the side surface 107'S (see FIG21) of the second trench 107'. The first substrates 313 and the second substrates 303' can be electrically connected to the doped region 211.

[0155] Referring to Figures 18 and 23 to 26, in step S27, a plurality of first insulating segments 406 may be formed in the first trench 107 and on the substrate 101, and a second insulating segment 406' may be formed in the second trench 107' and on the substrate 101. The first insulating segments 406 and 406' may include T-shaped cross-sectional profiles. In other words, the first insulating segment 406 includes a first embedded portion 407 disposed in the first trench 107 and a first extension portion 409 disposed on the first embedded portion 407 and located on the first surface 103 of the substrate 101. The second insulating segment 406' includes a second embedded portion 407' disposed in the second trench 107' and a second extension portion 409' disposed on the second embedded portion 407' and located on the first surface 103 of the substrate 101.

[0156] Referring to Figure 23, a first deposition process can be performed to deposit a first insulating layer 411 in the first trench 107 and the second trench 107' and on the first surface 103 of the substrate 101. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material (i.e., portions 401P of the first insulating layer 411) and to provide a substantially flat surface for subsequent process steps. The first insulating layer 411 deposited in the first trench 107 and the second trench 107' can be regarded as the first embedded portion 407 of the first insulating segment 406 and the second embedded portion 407' of the second insulating segment 406', respectively, as shown in Figure 26.

[0157] The first insulating layer 411 may be formed from the following materials: silicon nitride, silicon oxide, silicon oxynitride, flowable oxide, tonnen silazane, undoped quartz glass, borosilicate glass, phosphor glass, borophosphorus silicate glass, plasma-reinforced tetraethyl orthosilicate, fluoride silicate glass, carbon-doped silicon oxide, degel, aerogel, amorphous fluorinated carbon, organosilicon glass, parylene, bisbenzocyclobutene, polyimide, porous polymer materials, or combinations thereof, but not limited to these.

[0158] Referring to FIG. 24, a second deposition process can be performed to deposit a second insulating layer 412 on the first surface 103 of the substrate 101. The second insulating layer 412 is preferably formed of the same material as the first insulating layer 411, but is not limited thereto. Referring to FIG. 25, a photolithography process can be performed by depositing a second masking layer 713 on the second insulating layer 412 to define the positions of the first extension 409 of the first insulating segment 406 and the second extension 409' of the second insulating segment 406'. Referring to FIG. 26, after the photolithography process, an etching process, such as anisotropic dry etching, can be performed to transform the second insulating layer 412 into the first extension 409 of the first insulating segment 406 and the second extension 409' of the second insulating segment 406'.

[0159] In some embodiments, the first embedded portion 407 of the first insulating segment 406 may include a width D1, and the first extended portion 409 of the first insulating segment 406 may include a width D2 that is larger than the width D1 of the first embedded portion 407.

[0160] In some embodiments, the second embedded portion 407' of the second insulating segment 406' may include a width D3, and the second extended portion 409' of the second insulating segment 406' may include a width D4 that is larger than the width D3 of the second embedded portion 407'.

[0161] In some embodiments, the width D1 of the first embedded portion 407 is smaller than the width D3 of the second embedded portion 407'. In some embodiments, the width D2 of the first extended portion 409 is smaller than the width D4 of the second extended portion 409'.

[0162] Referring to Figures 18 and 27, in step S29, a filler layer 413 may be formed on the substrate 101 to surround the first extension 409 of the first insulating segment 406 and the second extension 409' of the second insulating segment 406'. In some embodiments, the filler layer 413 may be formed of silicon nitride. In some embodiments, the filler layer 413 may be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. A planarization process, such as chemical mechanical polishing, may be performed to remove a portion of the filler layer 413 until the top surface 409T of the first extension 409 of the first insulating segment 406 and the top surface 409'T of the second extension 409' of the second insulating segment 406' are exposed, and to provide a substantially planar surface for subsequent process steps. In some embodiments, after the planarization process, the top surface 413T of the filler layer 413, the top surface 409T of the first extension 409 of the first insulating segment 406, and the top surface 409'T of the second extension 409' of the second insulating segment 406' are substantially coplanar.

[0163] Referring to Figures 18 and 28, in step S31, a character line hard mask layer 513 can be formed on the first extension 409 of the first insulating segment 406, the second extension 409' of the second insulating segment 406', and the filler layer 413. Some of the materials and processes used to form the character line hard mask layer 513 are similar to or the same as those used to form the character line hard mask layer 203 shown in Figures 1 and 14 to 17 in step S17 of method 10, and their details will not be repeated here.

[0164] Referring to Figures 18 and 29, in step S33, a portion of the substrate 101 (part 101P in Figure 28) can be removed from the second surface 105 until a plurality of first liner 313, second liner 303', first embedded portion 407 of first insulating segment 406, and second embedded portion 407' of second insulating segment 406' are exposed. In some embodiments, the second surface 105 of the substrate 101 can be subjected to a removal process, such as chemical mechanical polishing, to expose the first liner 313, second liner 303', first embedded portion 407, and second embedded portion 407'. In some embodiments, after removing a portion 101P of substrate 101, substrate 101 may have a modified second surface 105', doped region 211 may be transformed into a modified doped region 201', and a plurality of first trenches 107 and second trenches 107' may be transformed into a plurality of first through-substrate vias (TSVs) 408 and second through-substrate vias 408', respectively. It should be noted that the side surfaces 408S of the first through-substrate vias 408 and 107S of the first trenches 107 are substantially identical, and the side surfaces 408S' of the second through-substrate vias 408' are substantially identical to the side surfaces 107'S of the second trenches 107'.

[0165] Figure 30 is a cross-sectional view illustrating a semiconductor element 3 of various embodiments of this disclosure. The semiconductor element 3 may be a semiconductor memory element, such as dynamic random-access memory (DRAM), which includes one or more storage capacitors 20 and one or more access transistors 30, wherein the access transistors 30 are turned on in response to a potential conducted thereon to couple the storage capacitors 20 to an associated bit line 44. The access transistor 30 shown in Figure 30 is in the form of a recessed access device (RAD) transistor; however, in some embodiments, the access transistor 30 may be a planar access device (PAD) transistor.

[0166] The semiconductor device 3 further includes a dielectric layer 40 located between the storage capacitor 20 and the access transistor 30, and a plurality of conductive features 50 extending from the storage capacitor 20 into the substrate 110 to electrically couple the storage capacitor 20 to the access transistor 30. In other words, the conductive features 50 serve as an electrical connection between the storage capacitor 20 and the corresponding access transistor 30, and the dielectric layer 40 insulates the conductive features 50. Bit lines 44 may be embedded in the dielectric layer 40 and electrically coupled to the access transistor 30 via at least one conductive plug 42 in the dielectric layer 40.

[0167] A storage capacitor 20 is disposed on a transistor 30 and includes a plurality of storage nodes 210 respectively contacting a conductive feature 50, a capacitor insulator 220 encapsulating the storage nodes 210, and a top electrode 230 disposed on the capacitor insulator 220. More specifically, the plurality of storage nodes 210 disposed on the conductive feature 50 and the dielectric layer 40 are spaced apart from each other and electrically isolated. In some embodiments, the storage nodes 210 include a U-shaped configuration and serve as the lower electrode of the storage capacitor 20. The capacitor insulator 220 may have a topology that follows the topology of the storage nodes 210 and the dielectric layer 40. The top electrode 230 serves as the upper electrode of the storage capacitor 20 and may have a substantially flat top surface 232; however, in some embodiments, the top electrode 230 may be a compliant layer.

[0168] A transistor 30 is disposed in a substrate 110. The substrate 110 has one or more isolation features 130 defining an active region 104, in which the isolation features 130 are formed. The active region 104 may be an elongated island-shaped region. For example, the active region 104 may have an elliptical shape as observed in the plan view. Furthermore, the active region 104 may be configured such that the principal axis (along its length) of the active region 104 is not parallel to the x-axis or y-axis of an orthogonal coordinate system.

[0169] The isolation feature 130 may include a first filling layer 334 filling a trench TR1 disposed in the substrate 110, a second filling layer 314 disposed within the first filling layer 334, and a liner 333 lining the inner surface S1 of the trench TR1 and surrounding the first filling layer 334. In some embodiments, the first filling layer 334 and the liner 333 have a U-shaped cross-sectional profile. The top surface 301T of the first filling layer 334, the top surface 303T of the second filling layer 314, and the top surface 333T of the liner 333 are coplanar. In some embodiments, the bottom surface 303B of the second filling layer 314 is at a vertical height VL3 higher than the bottom surface 301B of the first filling layer 334.

[0170] The access transistor 30 in the active region 104 includes a plurality of word lines 322 embedded in the substrate 110 and covered by a capping layer 330, a plurality of insulating liner layers 312 disposed between the substrate 110 and the word lines 322 and between the substrate 110 and the capping layer 330, and a plurality of impurity regions 340 and 350 disposed on both sides of the word lines 322. The word lines 322 extend along the y-axis and cross the active region 104, and the bit lines 44 extend along the x-axis, which is orthogonal to the y-axis. The active regions 104 can be oriented such that their principal axes are inclined relative to the word lines 322 and the bit lines 44. The active regions 104 can be sized such that one active region 104 intersects two word lines 322 and one bit line 44.

[0171] Referring again to Figure 30, impurity regions 340 and 350 serve as the drain and source regions of the access transistor 30, respectively. Impurity regions 340 and 350 can be connected to the upper surface 1102 of the substrate 110. Impurity region 340 is electrically coupled to the lower electrode 210 of the storage capacitor 20 via conductive feature 50, while impurity region 350 is electrically coupled to bit lines 44 via conductive plugs 42. The word lines 322 serve as gates in the access transistor 30 through which they pass, and the bit lines 44, formed using a damascene process, provide signals to the access transistor 30.

[0172] The conductive feature 50 is disposed on either side of the conductive plug 42. Because the active region 104 has an elliptical shape, the contact area of ​​the conductive feature 50 is smaller than the contact area of ​​the conductive plug 42. As a result, the contact area between the access transistor 30 and the conductive feature 50 is reduced, and the contact resistance between them is increased. To overcome this problem, the conductive feature 50 of the present invention is designed to extend into the substrate 110.

[0173] More specifically, each conductive feature 50 includes a lower portion 510 protruding into the impurity region 340 of the access transistor 30, and an upper portion 520 inserted between the upper surface 1102 of the substrate 110 and the storage capacitor 20. The lower portion 510 extending into the substrate 110 increases the contact area between the conductive feature 50 and the substrate 110 in which the access transistor 30 is disposed. Therefore, the contact resistance between the access transistor 30 and the associated conductive feature 50 can be effectively reduced. The upper portion 520 of the conductive feature 50 is surrounded by a dielectric layer 40, which includes a first dielectric layer 402 covering the substrate 110 and a second dielectric layer 404 sandwiched between the first dielectric layer 402 and the storage capacitor 20.

[0174] Referring again to FIG. 30, the lower portion 510 of the conductive feature 50 below the upper surface 1102 of the substrate 110 may have a first critical dimension CD1, and the upper portion 520 of the conductive feature 50 above the upper surface 1102 of the substrate 110 may have a second critical dimension CD2 greater than the first critical dimension CD1. In some embodiments, the first critical dimension CD1 gradually decreases at positions with increasing distance from the upper surface 1102 of the substrate 110, while the second critical dimension CD2 is constant. Specifically, the peripheral surface 512 of the lower portion 510 of the conductive feature 50 is discontinuous with the peripheral surface 522 of the upper portion 520 of the conductive feature 50. It is worth noting that the lower portion 510 and the upper portion 520 of the conductive feature 50, which includes polycrystalline silicon, are integrally formed.

[0175] One aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; a plurality of first through-substrate vias penetrating the substrate; a plurality of first embedding portions of a plurality of first insulating segments disposed in the plurality of first through-substrate vias; and a plurality of first liner layers, each of the plurality of first liner layers disposed on a side surface of one of the plurality of first through-substrate vias and located between the side surface of the first through-substrate via and one of the plurality of first insulating segments. The plurality of first insulating segments and the plurality of first liner layers are exposed through the second surface of the substrate.

[0176] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a substrate; at least one isolation feature disposed in the substrate, wherein the at least one isolation feature defines a plurality of active regions; a storage capacitor disposed on the substrate; a storage transistor including a plurality of impurity regions disposed in the active regions; and a conductive feature extending from the storage capacitor into the substrate for electrically coupling the storage capacitor to the storage transistor.

[0177] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes: providing a substrate including a first region and a second region, wherein the substrate has a first surface and a second surface opposite to the first surface; forming a plurality of first trenches in the first region and a second trench in the second region; forming a doped region in the substrate; forming a plurality of first liner layers in the plurality of first trenches and a second liner layer in the second trench; forming a plurality of first embedding portions of a plurality of first insulating segments in the plurality of first trenches and a second embedding portion of a second insulating segment in the second trench; forming a plurality of first extension portions of the plurality of first insulating segments over the plurality of first embedding portions and a second extension portion of the second insulating segment over the second embedding portions; and removing a portion of the substrate from the second surface to expose the plurality of first insulating segments, the plurality of first liner layers, the second insulating segment, and the second liner layer.

[0178] This disclosure provides some embodiments of semiconductor devices. In some embodiments, the semiconductor device includes an isolation structure with a liner. Therefore, leakage current between the source and drain regions can be avoided. This improves overall device performance and can increase the yield of the semiconductor device.

[0179] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0180] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0181] 1: Semiconductor components 2: Semiconductor components 3: Semiconductor components 10: Method 20: Method 30: Access Transistor 40: Dielectric layer 42: Conductive plug 44: Bitline 50: Electrical conductivity characteristics 101:Substrate 101P: Partial 101T: Top Surface 103: First Surface 104: Active Zone 105: Second Surface 105': Second surface 107: First trench 107B: Bottom 107S: Side surface 107': Second groove 107'B: Bottom 107'S: Side surface 110:Substrate 130: Isolation Features 201: Repair Layer 201': Modified doped region 201T: Top Surface 203: Character Line Hard Mask Layer 210: Lower electrode 211: Doped region 220: Capacitor insulator 230: Top electrode 232: Top surface 301: First outer filler layer 301B: Bottom surface 301C: First recessed portion 301CT: Top Surface 301F: First flat section 301T: Top Surface 301FT: Top Surface 303: First Central Layer 303B: Bottom surface 303T: Top surface 303': Second Liner 311: Lining 312: Insulating Liner 313: First Liner 314: Second filler layer 322: Character Line 330: Covering layer 333: Lining 333T: Top Surface 334: First fill layer 340: Impurity Zone 350: Impurity Zone 401: Second outer filler layer 401C: Second recessed portion 401CT: Top Surface 401F: Second flat section 401FT: Top Surface 401P: Partial 402: First dielectric layer 403: Second Central Layer 403E: End 403T: Top surface 404: Second dielectric layer 405: Second internal filling layer 405T: Top Surface 406: First Insulation Segment 406': Second Insulation Segment 407: First Embedded Part 407': Second Embedded Part 408: First through-substrate via 408': Second through-hole 408S: Side surface 408S': Side surface 409: First Extension 409T: Top Surface 409': Second extension 409'T: Top surface 411: First insulating layer 412: Second insulating layer 413: Fill layer 413T: Top surface 501: First protective layer 501B: Bottom surface 501T: Top Surface 503: Second protective layer 503B: Bottom surface 503T: Top Surface 510: Lower part 512: Peripheral Surface 513: Character Line Hard Mask Layer 520: Upper Part 522: Peripheral Surface 601: First filler material 603: Second filler material 603T: Top Surface 605: Third filler material 605T: Top Surface 701: Bottom rigid cover layer 703: Top Rigid Coverage Layer 713: Second Cover Layer 801: Sacrificial Shield Layer 901: First Cover Layer 1102: Upper surface CD1: First critical size CD2: Second critical size D1: Width D2: Width D3: Width D4: Width IMP: Fabrication Process P1: First Pattern P2: Second Pattern R1: First Region R2: Second Region RS1: First Groove RS2: Second groove S1: Internal surface S11: Steps S13: Steps S15: Steps S17: Steps S21: Steps S23: Steps S25: Steps S27: Steps S29: Steps S31: Steps S33: Steps T1: Thickness T2: Thickness T3: Thickness T4: Thickness T5: Thickness T6: Thickness TR1: First trench TR2: Second trench VL1: Vertical height VL2: Vertical height VL3: Vertical Height W1: Width W2: Width W3: Width W4: Width W5: Width W6: Width W7: Width W8: Width

Claims

1. A semiconductor element, comprising: A substrate having a first surface and a second surface opposite to the first surface; a plurality of first through-substrate holes penetrating the substrate; A plurality of first embedded portions of a plurality of first insulating segments are disposed in the plurality of first through-substrate vias; and a plurality of first liner layers, each of the plurality of first liner layers being disposed on one side surface of one of the plurality of first through-substrate vias and located between the side surface of the plurality of first through-substrate vias and one of the plurality of first insulating segments, wherein the plurality of first insulating segments and the plurality of first liner layers are exposed by the second surface of the substrate, wherein each of the plurality of first insulating segments further includes a first extension portion disposed on the first embedded portion and the first surface of the substrate.

2. The semiconductor device of claim 1, wherein the substrate includes a doped region disposed in the first surface of the substrate and on the plurality of side surfaces of the plurality of first through-substrate vias.

3. The semiconductor element as claimed in claim 2, wherein a width of the first extension is greater than a width of the first embedded portion.

4. The semiconductor element as claimed in claim 3, wherein the first insulating segment includes a T-shaped cross-sectional profile.

5. The semiconductor element as claimed in claim 4, wherein the first extension portion and the first embedded portion are made of the same material.

6. The semiconductor element as claimed in claim 4, wherein the first extension portion and the first embedded portion comprise different materials.

7. The semiconductor device of claim 4 further includes a filling layer disposed on the first surface, wherein the filling layer surrounds the plurality of first extensions of the plurality of first insulating segments.

8. The semiconductor device as claimed in claim 7, wherein the filling layer is made of silicon nitride.

9. The semiconductor device of claim 8 further includes a word line hard mask layer disposed over the fill layer and the plurality of first extensions of the plurality of first insulating segments.

10. The semiconductor device of claim 9, wherein the substrate includes a first region and a second region, wherein the plurality of first through-substrate vias are disposed in the first region.

11. The semiconductor element as claimed in claim 10, wherein the semiconductor element further comprises: A second through-substrate via penetrating the substrate in the second region; a second embedded portion of a second insulating segment disposed in the second through-substrate via; and a second liner disposed on one side surface of the second through-substrate via and located between the side surface of the second through-substrate via and the second insulating segment, wherein the second insulating segment and the second liner are exposed through the second surface of the substrate.

12. The semiconductor element as claimed in claim 11, wherein the doped region is also disposed on the side surface of the second through-substrate via.

13. The semiconductor element of claim 12, wherein the second insulating segment further includes a second extension disposed on the second embedded portion and the first surface of the substrate.

14. The semiconductor element of claim 13, wherein a width of the second extension is greater than a width of the second embedded portion.

15. The semiconductor element as claimed in claim 14, wherein the second insulating segment includes a T-shaped cross-sectional profile.

16. The semiconductor element of claim 15, wherein the second extension portion and the second embedded portion are made of the same material.

17. The semiconductor element of claim 15, wherein the second extension portion and the second embedded portion comprise different materials.

18. The semiconductor element of claim 15, wherein the width of the second embedded portion is greater than the width of the first embedded portion.

19. The semiconductor element of claim 15, wherein the width of the second extension is greater than the width of the first extension.

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