Power converting circuit and control method thereof

Abstract

A power conversion circuit includes a transformer, a resonant capacitor, an upper-bridge transistor, a lower-bridge transistor, and a control circuit. The transformer includes a primary coil and a secondary coil, with the primary coil coupled between a switching node and a resonant node. The resonant capacitor is coupled between the resonant node and ground. The upper-bridge transistor provides an input voltage to the switching node based on an upper-bridge drive signal. The lower-bridge transistor couples the switching node to ground based on a lower-bridge drive signal. The control circuit generates upper-bridge drive signals and lower-bridge drive signals. When the control circuit executes a startup procedure, it discharges the resonant capacitor.

Description

[Technical Field]

[0001] This invention relates to a power conversion circuit and its control method, and more particularly to a resonant power conversion circuit and its control method for discharging a resonant capacitor during startup. [Previous Technology]

[0002] With the continuous development of portable electronic devices, the development trend of power conversion circuits, like most power products, is towards higher efficiency, higher power density, higher reliability, and lower cost. Since resonant power conversion circuits (including LLC resonant power conversion circuits, flyback power conversion circuits, etc.) are a type of high-efficiency and high-power-density power conversion circuit, the power conversion circuits of portable electronic devices are gradually moving towards resonant power conversion circuits.

[0003] However, current resonant power conversion circuits still have many defects, so it is necessary to further optimize resonant power conversion circuits. [Summary of the Invention]

[0004] The present invention proposes a power conversion circuit and its control method. By discharging the resonant capacitor before driving the upper and lower bridge transistors, the ratio of the resonant voltage and the output voltage can be effectively maintained to avoid voltage surges on the secondary side, thereby increasing the reliability of the circuit components.

[0005] This invention proposes a power conversion circuit, including a transformer, a resonant capacitor, an upper-bridge transistor, a lower-bridge transistor, and a control circuit. The transformer includes a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and a resonant node. The resonant capacitor is coupled between the resonant node and a ground terminal. The upper-bridge transistor provides an input voltage to the switching node based on an upper-bridge drive signal. The lower-bridge transistor couples the switching node to the ground terminal based on a lower-bridge drive signal. The control circuit generates the upper-bridge drive signal and the lower-bridge drive signal. When the control circuit executes a startup procedure, the control circuit discharges the resonant capacitor.

[0006] According to one embodiment of the present invention, when the power conversion circuit receives the input voltage, the control circuit begins to execute the startup procedure. After the startup procedure, the power conversion circuit stably outputs an output voltage.

[0007] According to another embodiment of the present invention, when the power conversion circuit receives the input voltage, the control circuit begins to execute the startup procedure. When the startup procedure ends, the control circuit begins to generate the upper bridge drive signal and the lower bridge drive signal.

[0008] According to one embodiment of the present invention, the startup circuit includes a normally open transistor, a startup transistor, a startup resistor, and a startup diode. The normally open transistor is coupled to the input voltage. The startup transistor includes a startup gate terminal, a startup drain terminal, and a startup source terminal, wherein the startup drain terminal is coupled to the normally open transistor. The startup resistor is coupled between the startup gate terminal and the startup drain terminal. The startup diode includes a positive terminal and a negative terminal, wherein the positive terminal is coupled to the startup source terminal, and the negative terminal generates a supply voltage. In the startup procedure, the control circuit is powered by the supply voltage.

[0009] According to one embodiment of the present invention, the startup circuit further includes a comparator. The comparator compares the supply voltage with a threshold voltage to generate a comparison result. The comparison result is provided to the startup gate terminal. When the supply voltage exceeds the threshold voltage, the comparator disables the comparison result and turns off the startup transistor. When the supply voltage does not exceed the threshold voltage, the input voltage enables the comparison result via the normally open transistor and the startup resistor, thereby turning on the startup transistor and causing the startup circuit to generate the supply voltage.

[0010] According to one embodiment of the present invention, the power conversion circuit further includes a blocking transistor and a discharge resistor. The discharge resistor is coupled between the blocking transistor and the resonant node. The startup circuit further includes a discharge transistor. The discharge transistor includes a discharge gate terminal, a discharge drain terminal, and a discharge power supply terminal. The discharge gate terminal receives the comparison result, the discharge drain terminal is coupled to the blocking transistor, and the discharge power supply terminal is coupled to the ground terminal. The blocking transistor system is normally open.

[0011] According to one embodiment of the present invention, when the control circuit executes the startup procedure, the input voltage turns on the discharge transistor through the normally open transistor and the startup resistor, so that the charge of the resonant capacitor is discharged to the ground terminal through the discharge resistor, the blocking transistor and the discharge transistor.

[0012] According to one embodiment of the present invention, when the supply voltage exceeds the threshold voltage, the comparator turns off the start-up transistor to stop generating the supply voltage, and turns off the discharge transistor to stop discharging the resonant capacitor.

[0013] According to another embodiment of the present invention, when the supply voltage exceeds the threshold voltage, the control circuit terminates the startup procedure. When the startup circuit starts generating the supply voltage, the control circuit executes the startup procedure.

[0014] According to one embodiment of the present invention, the power conversion circuit further includes a voltage generating circuit. The voltage generating circuit includes a supply capacitor and a supply diode. The supply capacitor is used to maintain the supply voltage. The supply diode is used to generate the supply voltage by unidirectionally charging the supply capacitor using the auxiliary coil voltage, and to prevent the supply voltage from affecting the operation of the transformer. The transformer further includes an auxiliary coil. The auxiliary coil generates an auxiliary coil voltage. When the start-up transistor is turned off, the auxiliary coil generates the supply voltage to power the control circuit.

[0015] According to one embodiment of the present invention, when the auxiliary coil generates the supply voltage, the starting diode is used to isolate the supply voltage and the starting source terminal.

[0016] According to another embodiment of the present invention, the startup circuit further includes a timer. The timer counts for a period of time based on the comparison result of the disability. When the supply voltage exceeds the threshold voltage, the timer starts counting for the period of time. When the counting time reaches a predetermined time, the controller starts generating the upper bridge drive signal and the lower bridge drive signal. The predetermined time is used to determine the time for the control circuit to execute the startup procedure.

[0017] According to one embodiment of the present invention, the above-mentioned and the predetermined time exceeds 0.5 seconds.

[0018] According to another embodiment of the present invention, the power conversion circuit further includes a discharge resistor. The discharge resistor is coupled across the two ends of the resonant capacitor. During the startup procedure, the resonant capacitor discharges through the discharge resistor.

[0019] According to one embodiment of the present invention, the above-mentioned power conversion circuit is a resonant flyback power conversion circuit.

[0020] The present invention further proposes a control method for controlling a power conversion circuit. The power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, an upper-bridge transistor providing an input voltage to a switching node, and a lower-bridge transistor coupling the switching node to the ground terminal. The primary coil is coupled between the switching node and the resonant node. The control method includes: receiving the input voltage; discharging the resonant capacitor after receiving the output voltage; and driving the upper-bridge transistor and the lower-bridge transistor after discharging the resonant capacitor.

[0021] According to one embodiment of the present invention, the power conversion circuit further includes a startup circuit and a control circuit, and the transformer further includes an auxiliary coil. The startup circuit generates a supply voltage using the input voltage. The control circuit is used to execute the control method. When the supply voltage exceeds a threshold voltage, the auxiliary coil generates the supply voltage. The control circuit is powered by the supply voltage.

[0022] According to one embodiment of the present invention, the step of discharging the resonant capacitor further includes: generating the supply voltage using the startup circuit; discharging the resonant capacitor when the supply voltage does not exceed the threshold value; and stopping the discharge of the resonant capacitor when the supply voltage exceeds the threshold value.

[0023] According to another embodiment of the present invention, the step of discharging the resonant capacitor further includes: when the supply voltage exceeds the threshold value, counting for a counting time; and when the counting time reaches a predetermined time, driving the upper bridge transistor and the lower bridge transistor.

[0024] According to one embodiment of the present invention, a discharge resistor system is coupled to the above-mentioned resonant node to discharge the above-mentioned resonant capacitor.

Implementation Method

[0026] The following description is an embodiment of this disclosure. Its purpose is to illustrate the general principles of this disclosure and should not be regarded as a limitation of this disclosure. The scope of this disclosure shall be defined by the claims.

[0027] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this disclosure. The specific examples and arrangements of components described below are only used to briefly illustrate the spirit of this disclosure and are not intended to limit the scope of this disclosure. Furthermore, the same component symbols or words may be used repeatedly in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear explanation and is not intended to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0028] Furthermore, the description in the following specification of a feature being connected to, coupled to, and / or formed on another feature may actually include multiple different embodiments, including the features being in direct contact, or including other additional features formed between the features, such that the features are not in direct contact.

[0029] Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element described as being on the "lower" side will become the element on the "higher" side.

[0030] It is understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein.

[0031] Some embodiments disclosed herein can be understood in conjunction with the accompanying drawings, which are also considered part of the description of the embodiments disclosed herein. It should be understood that the drawings of the embodiments disclosed herein are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments disclosed herein. Furthermore, the structures and devices in the drawings are drawn schematically to clearly show the features of the embodiments disclosed herein.

[0032] Here, the terms "about," "approximately," and "roughly" generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, even without specific explanation of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0034] In some embodiments disclosed herein, terms such as "connection" and "interconnection" used to refer to joining or connecting, unless otherwise defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein other structures are disposed between the two structures. Furthermore, these terms regarding joining or connecting may also include situations where both structures are movable or both structures are fixed.

[0035] In the diagram, similar elements and / or features may have the same element symbol. Various elements of the same type may be distinguished by adding letters or numbers after the element symbol to differentiate similar elements and / or similar features.

[0036] Figure 1 shows a block diagram of a power conversion circuit according to one embodiment of the present invention. As shown in Figure 1, the power conversion circuit 100 includes an upper bridge transistor 111, a lower bridge transistor 112, a resonant capacitor CR, a transformer TM, a voltage generation circuit 120, a rectifier circuit 130, a secondary control circuit 140, an optocoupler PD, a control circuit 150, a level shifting circuit 160, an upper bridge drive circuit HSD, and a lower bridge drive circuit LSD.

[0037] The upper bridge transistor 111 provides the input voltage VIN to the switching node SW based on the upper bridge gate drive signal HSG. According to one embodiment of the present invention, the upper bridge transistor 111 includes an upper bridge parasitic diode 111D, wherein the upper bridge parasitic diode 111D is coupled between the switching node SW and the input voltage VIN. The lower bridge transistor 112 couples the switching node SW to ground based on the lower bridge gate drive signal LSG. According to one embodiment of the present invention, the lower bridge transistor 112 includes a lower bridge parasitic diode 112D, wherein the lower bridge parasitic diode 112D is coupled between the switching node SW and the ground.

[0038] The resonant capacitor CR is coupled between the resonant node NR and the ground terminal, and a resonant voltage VCR is generated across the resonant capacitor CR. The transformer TM includes a primary coil PS, a secondary coil SS, and an auxiliary coil AS. The primary coil PS is coupled between the switching node SW and the resonant node NR. The auxiliary coil AS is coupled between the auxiliary node NA and the ground terminal, and an auxiliary coil voltage VNA is generated at the auxiliary node NA. The output current IOUT generated by the secondary coil SS is rectified by the rectifier circuit 130 to generate the output voltage VOUT.

[0039] According to some embodiments of the present invention, the primary coil SS and the resonant capacitor CR are connected in series between the switching node SW and the ground terminal. In other words, the resonant capacitor CR can also be coupled between the switching node SW and the resonant node NR, and the primary coil PS is coupled between the resonant node NR and the ground terminal.

[0040] The voltage generating circuit 120 is used to generate a supply voltage VDD using the auxiliary coil voltage VNA. The voltage generating circuit 120 includes a supply diode DSP and a supply capacitor CSP. The supply diode DSP is used to unidirectionally charge the supply capacitor CSP using the auxiliary coil voltage VNA to generate the supply voltage VDD, thereby preventing the supply voltage VDD from affecting the operation of the transformer TM. According to one embodiment of the present invention, when the auxiliary coil voltage VNA generated by the auxiliary coil AS is less than the supply voltage VDD, the supply capacitor CSP is used to maintain the supply voltage VDD.

[0041] The rectifier circuit 130 is used to convert the output current IOUT generated by the secondary coil SS into an output voltage VOUT, and includes a rectifier transistor TR and an output capacitor COUT. According to some embodiments of the present invention, the rectifier transistor TR further includes a rectifier parasitic diode DR. The rectifier transistor TR is turned on based on the gate signal SG, so that the output current IOUT output by the secondary coil SS charges the output capacitor COUT to generate the output voltage VOUT. When the rectifier transistor TR is not turned on, the voltage across the drain terminal to the source terminal of the rectifier transistor TR is the drain voltage VD.

[0042] The secondary control circuit 140 generates a feedback current IFB based on the output voltage VOUT, wherein the feedback current IFB generates a feedback voltage VFB via the optocoupler PD. The secondary control circuit 140 further generates a gate signal SG to convert the output current IOUT generated by the secondary coil SS into an output voltage VOUT.

[0043] The control circuit 150 is powered by the supply voltage VDD and generates an upper bridge drive signal SH and a lower bridge drive signal SL based on the feedback voltage VFB. The level shifting circuit 160 shifts the voltage level of the upper bridge drive signal SH to the input voltage VIN. The upper bridge drive circuit HSD generates an upper bridge gate drive signal HSG based on the shifted signal to drive the upper bridge transistor 111. The lower bridge drive circuit LSD generates a lower bridge gate drive signal LSG based on the lower bridge drive signal SL to drive the lower bridge transistor 112.

[0044] According to some embodiments of the present invention, the control circuit 150 further generates an upper bridge drive signal SH and a lower bridge drive signal SL based on the voltage of the switching node SW, so that both the upper bridge transistor 111 and the lower bridge transistor 112 achieve zero voltage switching (ZVS), thereby improving the conversion efficiency of the power conversion circuit 100. According to some embodiments of the present invention, the power conversion circuit 100 may be a resonant power conversion circuit. According to some embodiments of the present invention, the power conversion circuit 100 may be a resonant flyback power conversion circuit. According to some embodiments of the present invention, the power conversion circuit 100 may be an asymmetrical half-bridge flyback power converter.

[0045] Figure 2 shows a waveform diagram of a power conversion circuit according to an embodiment of the present invention. The following description of waveform 200 will be provided in conjunction with the power conversion circuit 100 of Figure 1 for detailed explanation. Between a first time point T1 and a second time point T2, the upper bridge transistor 111 is turned on based on the upper bridge drive signal SH (i.e., high logic level), wherein the upper bridge turn-on time TW is the turn-on time of the upper bridge transistor 111. During the upper bridge turn-on time TW, the transformer TM is magnetized, generating a magnetizing current IM. As the turn-on time TW increases, the magnetizing current IM of the transformer TM, the primary current IP flowing through the primary coil PS, and the resonant voltage VCR all continuously increase. In other words, the upper bridge turn-on time TW is the magnetization time of the transformer TM.

[0046] When the upper bridge transistor 111 is not conducting (i.e., the upper bridge drive signal SH is at a low logic level), the transformer 10 demagnetizes. During the demagnetization time TDS, the transformer 10 generates an output current IOUT, and the conduction time of the lower bridge transistor 112 (i.e., the lower bridge drive signal SL is at a high logic level) corresponds to the demagnetization time TDS. According to some embodiments of the present invention, the lower bridge conduction time TSL under the lower bridge drive signal SL is equal to or greater than the demagnetization time TDS. During the demagnetization time TDS, the voltage across the primary coil PS is equal to the resonant voltage VCR, and the output voltage VOUT is as shown in Formula 1: (Formula 1)

[0047] Wherein, NP is the number of turns of the primary coil PS, NS is the number of turns of the secondary coil SS, and the turns ratio n is the number of turns of the primary coil PS divided by the number of turns of the secondary coil SS.

[0048] The demagnetization time TDS system is shown in Formula 2: (Formula 2)

[0049] When the upper bridge transistor 111 is turned on, it is used to magnetize the voltage of the transformer TM.

[0050] At the second time point T2, the upper bridge drive signal SH changes to a low logic level and the upper bridge transistor 111 is not turned on. At the third time point T3, the lower bridge drive signal SL changes to a high logic level and the lower bridge transistor 112 is turned on. According to some embodiments of the present invention, the first dead time TRL from the second time point T2 to the third time point T3 is the dead time from when the upper bridge transistor 111 is not turned on to when the lower bridge transistor 112 is turned on.

[0051] According to some embodiments of the present invention, during the first dead time TRL, the circulating current generated by the primary coil PS turns on the lower bridge parasitic diode 112D, thereby pulling down the voltage of the switching node SW, so that the lower bridge transistor 112 achieves zero-voltage switching. At the third time point T3, the trans-voltage system of the primary coil PS is the resonant voltage VCR of the resonant capacitor CR.

[0052] Between the third time point T3 and the fourth time point T4, the upper bridge transistor 111 is not conducting, and the lower bridge transistor 112 is conducting under zero-voltage switching. The rectifier transistor TR is conducting, causing the output current IOUT to flow through the rectifier transistor TR and generate the output voltage VOUT, where the output voltage VOUT is equal to the resonant voltage VCR divided by the number of turns n, as shown in Formula 1. In addition, the primary current IP remains positive and flows into the resonant capacitor CR.

[0053] According to some embodiments of the present invention, the leakage inductance of the primary coil PS and the resonant capacitor CR form a resonant tank. The output current IOUT is of sine wave type and its frequency is determined by the resonant frequency of the resonant circuit. The primary current IP is the magnetizing current IM plus the reflection of the output current IOUT.

[0054] From the fourth time point T4 to the fifth time point T5, the upper bridge transistor 111 remains non-conducting while the lower bridge transistor 112 remains on. The energy of the transformer TM is continuously transferred to the secondary coil SS, and at this time the energy is provided by the resonant capacitor CR. In addition, since the lower bridge transistor 112 remains on, the energy of the resonant capacitor CR is used to bring the magnetizing current IM to a negative value.

[0055] At the fifth time point T5, the rectifier transistor TR does not conduct based on the gate signal SG, thus ending the demagnetization time TDS. From the fifth time point T5 to the sixth time point T6, the resonant capacitor CR continuously reverse magnetizes the primary coil PS, causing the primary current IP to remain negative until the lower bridge transistor 112 does not conduct.

[0056] From the sixth time point T6 to the seventh time point T7, both the upper bridge transistor 111 and the lower bridge transistor 112 are not conducting. Furthermore, from the fifth time point T5 to the sixth time point T6, the primary current IP, which induces a negative current, turns on the upper bridge parasitic diode 111D, causing the voltage at the switching node SW to rise to the input voltage VIN. According to some embodiments of the present invention, the second dead time TRH from the sixth time point T6 to the seventh time point T7 is the dead time from when the lower bridge transistor 112 is not conducting to when the upper bridge transistor 111 is conducting.

[0057] At the seventh time point T7, the upper bridge drive signal SH is at a high logic level. As the voltage of the switching node SW rises to the input voltage VIN, the upper bridge transistor 111 can be turned on in a zero-voltage switching state.

[0058] Since the resonant capacitor CR is connected in parallel with the primary coil PS during the demagnetization of the transformer TM, the resonant voltage VCR is the output voltage VOUT multiplied by the number of turns of the transformer TM. When the difference between the resonant voltage VCR and the output voltage VOUT multiplied by the number of turns is too large, the drain voltage VD will generate a very high voltage spike, which will reduce the reliability of the rectifier transistor TR and even damage the rectifier transistor TR.

[0059] Under normal operation, the resonant voltage VCR is very close to the output voltage VOUT multiplied by the turns ratio of the transformer TM, thus avoiding voltage surges in the drain voltage VD. However, when the power conversion circuit 100 undergoes rapid and frequent switching on and off, the output voltage VOUT discharges through the load, causing a significant difference between the resonant voltage VCR and the output voltage VOUT multiplied by the turns ratio of the transformer TM, resulting in voltage surges in the drain voltage VD. To protect the rectifier transistor TR from damage caused by voltage surges, it is necessary to optimize the power conversion circuit 100.

[0060] Figure 3 shows a block diagram of a power conversion circuit according to another embodiment of the present invention. Compared with the power conversion circuit 100 in Figure 1, the power conversion circuit 300 in Figure 3 further includes a charging resistor RH, a discharging resistor RDG, and a blocking transistor TB, and the control circuit 310 of the power conversion circuit 300 further includes a startup circuit 311.

[0061] The input voltage VIN is stepped down via the charging resistor RH to generate a high voltage VH. According to some embodiments of the present invention, the input voltage VIN generates a charging current ICHG via the charging resistor RH, thereby generating a stepped-down high voltage VH. When the power conversion circuit 300 executes the startup procedure, the startup circuit 311 discharges the resonant capacitor CR using the discharge resistor RDG and the blocking transistor TB through the control signal CNTR. In addition, the startup circuit 311 generates a supply voltage VDD during the startup procedure and uses the supply voltage VDD to power the control circuit 310.

[0062] The gate of the blocking transistor TB is coupled to ground to withstand high voltage. The discharge resistor RDG is used to limit the discharge current of the resonant capacitor CR. According to some embodiments of the present invention, the discharge resistor RDG and the blocking transistor TB are used to discharge the resonant voltage VCR to near the ground level when the upper bridge transistor 111 and the lower bridge transistor 112 are not driven.

[0063] According to some embodiments of the present invention, the blocking transistor TB may be a normally open transistor. According to some embodiments of the present invention, the blocking transistor TB may be a normally open junction field-effect transistor. According to other embodiments of the present invention, when the element used to generate the control signal CNTR in the startup circuit 311 can withstand the high voltage of the resonant voltage VCR, the blocking transistor TB may also be omitted. According to some embodiments of the present invention, since the control circuit 310 discharges the resonant capacitor CR during the startup procedure, it can effectively prevent the drain voltage VD from generating voltage surges, thereby protecting the rectifier transistor TR.

[0064] According to some embodiments of the present invention, when the power conversion circuit 100 receives the input voltage VIN, the control circuit 310 starts executing the startup procedure, and after the startup procedure, the power conversion circuit 100 stably outputs the output voltage VOUT. In other words, the startup procedure can be defined as the period from when the power conversion circuit 100 receives the input voltage VIN to when the power conversion circuit 100 stably outputs the output voltage VOUT.

[0065] According to other embodiments of the present invention, when the power conversion circuit 100 receives the input voltage VIN, the power conversion circuit 100 executes a startup procedure, and when the startup procedure ends, the control circuit 310 starts generating the upper bridge drive signal SH and the lower bridge drive signal SL. In other words, the startup procedure can also be defined as the period from when the power conversion circuit 100 receives the input voltage VIN to when the control circuit 310 starts driving the upper bridge transistor 111 and the lower bridge transistor 112.

[0066] Figure 4 shows a block diagram of a startup circuit according to one embodiment of the present invention. As shown in Figure 4, the startup circuit 400 includes a normally open transistor TNO, a startup transistor TST, a startup resistor RST, a startup diode DST, a charging diode DCHG, a comparator CMP, and a discharge transistor TDCG. According to some embodiments of the present invention, the startup circuit 400 corresponds to the startup circuit 311.

[0067] The gate terminal of the normally open transistor TNO is coupled to ground and receives the high voltage VH generated by the charging resistor RH in Figure 3. According to some embodiments of the invention, the charging resistor RH may be omitted, and the input voltage VIN may be directly supplied to the normally open transistor TNO. The startup transistor TST includes a gate terminal G, a drain terminal D, and a source terminal S, wherein the startup resistor RST is coupled to the gate terminal G and the drain terminal D. The startup diode DST is coupled between the source terminal S and the supply voltage VDD in Figure 3.

[0068] According to some embodiments of the present invention, the start-up diode DST is used to charge the supply voltage VDD in a unidirectional manner. According to some embodiments of the present invention, when the start-up transistor TST is turned off, the start-up diode DST is used to isolate the supply voltage VDD and the source terminal S. The comparator CMP is used to compare the supply voltage VDD and the threshold voltage VTH, and provides the comparison result RCM to the gate terminal G. According to some embodiments of the present invention, when the supply voltage VDD exceeds the threshold voltage VTH, the comparator CMP disables the comparison result RCM, and turns off the start-up transistor TST and the discharge transistor TDCG. According to some embodiments of the present invention, the comparator CMP has hysteresis.

[0069] According to some embodiments of the present invention, when the comparator CMP turns off the start transistor TST, the output terminal of the comparator CMP couples the gate G of the start transistor TST and the gate of the discharge transistor TDCG to the ground terminal, wherein the resistance values ​​of the charging resistor RH and the start resistor RST are used to determine the current flowing through the normally open transistor TNO. According to some embodiments of the present invention, the current flowing through the charging resistor RH, the normally open transistor TNO, and the start resistor RST is the charging current ICHG in Figure 3.

[0070] According to some embodiments of the present invention, when the input voltage VIN is supplied to the power conversion circuit 300, the output terminal of the comparator CMP is floating to the gate terminal G of the startup transistor TST, and the input voltage VIN enables the comparison result RCM through the charging resistor RH, the normally open transistor TNO, and the startup resistor RST, thereby turning on the startup transistor TST and the discharge transistor TDCG. In other words, when the supply voltage VDD does not exceed the threshold voltage VTH, the output terminal of the comparator CMP is electrically isolated from the startup transistor TST, and the startup transistor TST is turned on by the input voltage VIN through the charging resistor RH, the normally open transistor TNO, and the startup resistor RST.

[0071] When the start-up transistor TST is turned on, the input voltage VIN charges the supply capacitor CSP via the normally open transistor TNO, the start-up transistor TST, and the start-up diode DST to generate a supply voltage VDD, which powers the control circuit 310. In other words, once the input voltage VIN is supplied to the power conversion circuit 300, the start-up circuit 400 immediately generates the supply voltage VDD to power the control circuit 310. According to some embodiments of the present invention, the supply voltage VDD can also power the comparator CMP.

[0072] According to other embodiments of the present invention, when the high voltage VH continuously charges the supply capacitor CSP due to the on-state transistor TNO, the start-up transistor TST, and the start-up diode DST, causing the supply voltage VDD to exceed the threshold voltage VTH, the comparator CMP disables the start-up transistor TST and the discharge transistor TDCG by the comparison result RCM, which means that the power conversion circuit 300 has completed the startup procedure. The control circuit 310 further drives the upper bridge transistor 111 and the lower bridge transistor 112 based on the disable comparison result RCM. When the start-up transistor TST is not turned on, the startup circuit 400 stops generating the supply voltage VDD.

[0073] According to some embodiments of the present invention, since the startup circuit 400 generates the supply voltage VDD when the input voltage VIN is provided to the power conversion circuit 300, and the control circuit 310 starts to drive the upper bridge transistor 111 and the lower bridge transistor 112 after the startup circuit 400 stops generating the supply voltage VDD, the period during which the supply voltage VDD is generated by the startup circuit 400 can be regarded as the startup procedure.

[0074] In other words, the startup procedure can be defined as the startup circuit 400 starting to generate the supply voltage VDD until the startup circuit 400 stops generating the supply voltage VDD, and the control circuit 310 starting to drive the upper bridge transistor 111 and the lower bridge transistor 112 based on the disabling comparison result RCM.

[0075] According to some embodiments of the present invention, when the startup circuit 400 stops generating the supply voltage VDD, the auxiliary coil AS then generates the supply voltage VDD to power the control circuit 311 because the control circuit 310 starts driving the upper bridge transistor 111 and the lower bridge transistor 112. In other words, when the comparison result RCM fails, the startup circuit 400 stops generating the supply voltage VDD, and the auxiliary coil AS starts generating the supply voltage VDD.

[0076] When the input voltage VIN turns on the start-up transistor TST via the charging resistor RH, normally open transistor TNO and start-up resistor RST in Figure 3, the discharge transistor TDCG turns on at the same time and couples the control signal CNTR to the ground terminal, so that the resonant capacitor CR discharges via the discharge resistor RDG, blocking transistor TB and discharge transistor TDCG.

[0077] When the resonant capacitor CR discharges to the point where the supply voltage VDD exceeds the threshold voltage VTH, the resonant voltage VCR is very close to the grounding level. At this time, the control circuit 310 can drive the upper bridge transistor 111 and the lower bridge transistor 112 based on the disabling comparison result RCM. In addition, the startup program ends when the control circuit 310 starts driving the upper bridge transistor 111 and the lower bridge transistor 112.

[0078] Figure 5 shows a block diagram of a power conversion circuit according to another embodiment of the present invention. Compared with the power conversion circuit 100 in Figure 1, the power conversion circuit 500 in Figure 5 further includes a discharge resistor RDG, and the control circuit 510 of the power conversion circuit 500 further includes a startup circuit 511.

[0079] As shown in Figure 5, the discharge resistor RDG is coupled across the resonant capacitor CR to continuously discharge the resonant voltage VCR. According to some embodiments of the present invention, the discharge resistor RDG in Figure 5 must be large enough to avoid excessive power loss. When the power conversion circuit 500 receives the input voltage VIN, the startup circuit 511 delays the control circuit 510 from driving the upper bridge transistor 111 and the lower bridge transistor 112, so that the discharge resistor RDG has sufficient time to discharge the resonant voltage VCR to near the grounding level.

[0080] Figure 6 shows a block diagram of a startup circuit according to another embodiment of the present invention. According to some embodiments of the present invention, startup circuit 600 corresponds to startup circuit 511 in Figure 5. Compared with startup circuit 400 in Figure 4, startup circuit 600 omits the discharge transistor TDCG of startup circuit 400, and further includes inverter INV, counter 610, and flip-flop FF.

[0081] As shown in Figure 6, when the supply voltage VDD does not exceed the threshold voltage VTH, the comparator CMP does not affect the gate G of the start-up transistor TST. The high voltage VH enables the comparison result RCM via the normally open transistor TNO and the start-up resistor RST, thus turning on the start-up transistor TST, indicating that the comparison result RCM is at a high voltage level. The inverter INV inverts the comparison result RCM, generating an inverted comparison result RCMB. The inverted comparison result RCMB resets the counter 610 and the flip-flop FF, as well as the disabling count signal CNT and the reset signal RST.

[0082] The drive circuit 60 stops generating the upper bridge drive signal SH and the lower bridge drive signal SL based on the disabled reset signal RST. According to some embodiments of the present invention, the control circuit 510 further includes the drive circuit 60, wherein the drive circuit 60 is used to generate the upper bridge drive signal SH and the lower bridge drive signal SL to drive the upper bridge transistor 111 and the lower bridge transistor 112 respectively.

[0083] When the supply voltage VDD exceeds the threshold voltage VTH, the comparator CMP disables the comparison result RCM, causing the counter 610 to start counting for a counting time based on the clock signal CLK. When the counting time reaches a predetermined time, the counter 610 enables the counting signal CNT. The flip-flop FF enables the reset signal RST based on the clock signal CLK and the enabled counting signal CNT, thereby enabling the drive circuit 60 to start generating the upper bridge drive signal SH and the lower bridge drive signal SL to drive the upper bridge transistor 111 and the lower bridge transistor 112 respectively.

[0084] According to some embodiments of the present invention, when the counter 610 counts, the control circuit 510 executes a startup procedure. In other words, the startup procedure can be defined as the period from when the startup circuit 600 stops generating the supply voltage VDD to when the drive circuit 60 starts driving the upper bridge transistor 111 and the lower bridge transistor 112. According to some embodiments of the present invention, the predetermined time is longer than 0.5 seconds. In other words, the duration of the startup procedure is longer than 0.5 seconds. That is, before driving the upper bridge transistor 111 and the lower bridge transistor 112, the resonant capacitor CR is discharged for at least 0.5 seconds.

[0085] Figure 7 shows a flowchart of a control method according to an embodiment of the present invention. As shown in the control method 700 of Figure 7, firstly, an input voltage VIN is received (step S710). After receiving the input voltage VIN, a startup procedure is executed to discharge the resonant capacitor CR (step S720). After discharging the resonant capacitor, the upper bridge transistor 111 and the lower bridge transistor 112 are started to be driven (step S730).

[0086] In the embodiments of Figures 3 and 4, when the power conversion circuit 300 receives the input voltage VIN (step S710), the start transistor TST and the discharge transistor TDCG in Figure 4 are turned on, and the resonant capacitor CR discharges through the discharge resistor RDG in Figure 3 and the blocking transistor TB and the discharge transistor TDCG in Figure 4 (step S720). When the comparison result RCM is disabled, both the start transistor TST and the discharge transistor TDCG are not turned on, and the control circuit 310 starts driving the upper bridge transistor 111 and the lower bridge transistor 112 based on the disabled comparison result RCM (step S730).

[0087] In the embodiments of Figures 5 and 6, when the power conversion circuit 500 receives the input voltage VIN (step S710), the startup circuit 600 generates the supply voltage VDD. When the supply voltage VDD exceeds the threshold voltage VTH, the startup circuit 600 stops generating the supply voltage VDD and the counter 610 starts counting for a counting time. When the counting time is less than a predetermined time, the discharge resistor RDG continues to discharge the resonant capacitor CR (step S720) and the drive circuit 60 stops generating the upper bridge drive signal SH and the lower bridge drive signal SL. When the counting time of the counter 610 reaches the predetermined time, the drive circuit 60 starts generating the upper bridge drive signal SH and the lower bridge drive signal SL, respectively driving the upper bridge transistor 111 and the lower bridge transistor 112.

[0088] The present invention proposes a power conversion circuit and its control method. By discharging the resonant capacitor before driving the upper and lower bridge transistors, the ratio of the resonant voltage and the output voltage can be effectively maintained to avoid voltage surges on the secondary side, thereby increasing the reliability of the circuit components.

[0089] Although the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Anyone skilled in the art can understand from the disclosure of some embodiments of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments. [Simplified Explanation of the Diagram]

[0025] Figure 1 shows a block diagram of a power conversion circuit according to one embodiment of the present invention; Figure 2 shows a waveform diagram of a power conversion circuit according to one embodiment of the present invention; Figure 3 shows a block diagram of a power conversion circuit according to another embodiment of the present invention; Figure 4 shows a block diagram of a startup circuit according to one embodiment of the present invention; Figure 5 shows a block diagram of a power conversion circuit according to another embodiment of the present invention; Figure 6 shows a block diagram of a startup circuit according to another embodiment of the present invention; and Figure 7 shows a flowchart of a control method according to one embodiment of the present invention.

Claims

1. A power conversion circuit, comprising: A transformer includes a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and a resonant node; a resonant capacitor is coupled between the resonant node and a ground terminal; an upper-bridge transistor provides an input voltage to the switching node based on an upper-bridge drive signal; a lower-bridge transistor couples the switching node to the ground terminal based on a lower-bridge drive signal; and a control circuit that generates the upper-bridge drive signal and the lower-bridge drive signal; wherein when the control circuit executes a startup procedure, the control circuit discharges the resonant capacitor.

2. The power conversion circuit of claim 1, wherein when the power conversion circuit receives the input voltage, the control circuit begins to execute the startup procedure; wherein after the startup procedure, the power conversion circuit stably outputs an output voltage.

3. The power conversion circuit of claim 1, wherein when the power conversion circuit receives the input voltage, the control circuit starts executing the startup procedure; wherein when the startup procedure ends, the control circuit starts generating the upper bridge drive signal and the lower bridge drive signal.

4. The power conversion circuit of claim 1, wherein the control circuit further includes a startup circuit, wherein the startup circuit includes: A normally open transistor coupled to the input voltage; a start-up transistor including a start-up gate, a start-up drain, and a start-up source, wherein the start-up drain is coupled to the normally open transistor; a start-up resistor coupled between the start-up gate and the start-up drain; and a start-up diode including an anode and a cathode, wherein the anode is coupled to the start-up source, and the cathode generates a supply voltage; wherein, in the start-up procedure, the control circuit is powered by the supply voltage.

5. The power conversion circuit of claim 4, wherein the aforementioned startup circuit further includes: A comparator compares the supply voltage with a threshold voltage to generate a comparison result; wherein the comparison result is provided to the start-up gate terminal; wherein when the supply voltage exceeds the threshold voltage, the comparator disables the comparison result and turns off the start-up transistor; wherein when the supply voltage does not exceed the threshold voltage, the input voltage enables the comparison result via the normally open transistor and the start-up resistor, thereby turning on the start-up transistor and causing the start-up circuit to generate the supply voltage.

6. The power conversion circuit as described in claim 5 further includes: A blocking transistor; And a discharge resistor, coupled between the aforementioned blocking transistor and the aforementioned resonant node; The aforementioned startup circuit further includes: a discharge transistor, comprising a discharge gate terminal, a discharge drain terminal, and a discharge power supply terminal; wherein the discharge gate terminal receives the aforementioned comparison result, the discharge drain terminal is coupled to the aforementioned blocking transistor, and the discharge power supply terminal is coupled to the aforementioned ground terminal; wherein the aforementioned blocking transistor system is normally open.

7. The power conversion circuit of claim 6, wherein when the control circuit executes the startup procedure, the input voltage turns on the discharge transistor via the normally open transistor and the startup resistor, so that the charge of the resonant capacitor is discharged to the ground terminal via the discharge resistor, the blocking transistor and the discharge transistor.

8. The power conversion circuit of claim 7, wherein when the supply voltage exceeds the threshold voltage, the comparator turns off the start-up transistor to stop generating the supply voltage, and turns off the discharge transistor to stop discharging the resonant capacitor.

9. The power conversion circuit of claim 8, wherein when the supply voltage exceeds the threshold voltage, the control circuit terminates the startup procedure; wherein when the startup circuit begins to generate the supply voltage, the control circuit executes the startup procedure.

10. The power conversion circuit as described in claim 7 further includes: A voltage generating circuit includes: a supply capacitor for maintaining the supply voltage; and a supply diode for unidirectionally charging the supply capacitor using an auxiliary coil voltage to generate the supply voltage, and preventing the supply voltage from affecting the operation of the transformer; wherein the transformer further includes: an auxiliary coil for generating the auxiliary coil voltage; wherein when the start-up transistor is turned off, the auxiliary coil generates the supply voltage to power the control circuit.

11. The power conversion circuit of claim 10, wherein when the auxiliary coil generates the supply voltage, the start-up diode is used to isolate the supply voltage and the start-up source terminal.

12. The power conversion circuit of claim 5, wherein the aforementioned startup circuit further includes: A timer counts for a period of time based on the comparison result of the disability; wherein the timer starts counting for a period of time when the supply voltage exceeds the threshold voltage; wherein the control circuit starts generating the upper bridge drive signal and the lower bridge drive signal when the counting time reaches a predetermined time; wherein the predetermined time is used to determine the time when the control circuit executes the startup procedure.

13. The power conversion circuit of request item 12, wherein the predetermined time exceeds 0.5 seconds.

14. The power conversion circuit of claim 12 further includes: A discharge resistor is coupled to both ends of the aforementioned resonant capacitor; In the aforementioned startup procedure, the resonant capacitor discharges through the aforementioned discharge resistor.

15. The power conversion circuit of claim 1, wherein the power conversion circuit is a resonant flyback power conversion circuit.

16. A control method for controlling a power conversion circuit, wherein the power conversion circuit includes a resonant capacitor coupled between a resonant node and a ground terminal, a transformer including a primary coil and a secondary coil, an upper-bridge transistor for providing an input voltage to a switching node, and a lower-bridge transistor for coupling the switching node to the ground terminal, wherein the primary coil is coupled between the switching node and the resonant node, wherein the control method includes: Receive the above-mentioned input voltage; After receiving the above-mentioned input voltage, discharge the above-mentioned resonant capacitor; And after the above-mentioned step of discharging the resonant capacitor, drive the upper bridge transistor and the lower bridge transistor.

17. The control method of claim 16, wherein the power conversion circuit further includes a starting circuit and a control circuit, and the transformer further includes an auxiliary coil; wherein the starting circuit generates a supply voltage using the input voltage; wherein the control circuit is used to execute the control method; wherein when the supply voltage exceeds a threshold voltage, the auxiliary coil is used to generate the supply voltage; wherein the control circuit is powered by the supply voltage.

18. The control method of claim 17, wherein the step of discharging the resonant capacitor further includes: The above-mentioned start-up circuit generates the above-mentioned supply voltage; when the above-mentioned supply voltage does not exceed the above-mentioned threshold voltage, the above-mentioned resonant capacitor is discharged; and when the above-mentioned supply voltage exceeds the above-mentioned threshold voltage, the discharge of the above-mentioned resonant capacitor is stopped.

19. The control method of claim 17, wherein the step of discharging the resonant capacitor further includes: When the supply voltage exceeds the threshold voltage, a counting time is recorded; and when the counting time reaches a predetermined time, the upper bridge transistor and the lower bridge transistor are driven.

20. The control method of claim 16, wherein a discharge resistor is coupled to the resonant node to discharge the resonant capacitor.

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