Memory device and method of manufacturing the same

Abstract

An apparatus includes a plurality of memory cells, each memory cell including a diffusion region and a plurality of transistors. The diffusion region is formed above a substrate. Each transistor is fabricated above the diffusion region and includes one or more source / drain contacts and one or more gate regions. The source / drain contacts and the gate regions are arranged along a first direction, extend along a second direction transverse to the first direction, and overlap with the diffusion region along a third direction transverse to both the first and second directions. There are no source / drain contacts between the gate regions of adjacent pairs of memory cells, but they have a contact polypitch (CPP) substantially the same as that between adjacent pairs of gate regions of the memory cells.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] Memory devices are responsible for storing and retrieving data. Memory devices come in various forms and can be programmable or non-programmable. Programmable memory devices allow data to be written to and rewritten multiple times, making them suitable for applications requiring frequent updates, such as random access memory (RAM) devices. On the other hand, non-programmable memory devices can only be written to once, ensuring that data remains unchanged, and are used in various applications that require data security and immutability, such as one-time programmable (OTP) memory devices. Regardless of whether they are programmable or not, memory devices facilitate the reading of the data stored within them, enabling electronic systems to access and utilize information as needed. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides many different embodiments or instances for implementing different features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] A memory device comprises a plurality of memory cells, for example, arranged in an array of columns and rows, to facilitate the storage and retrieval of data stored in the memory cells, and may be programmable or non-programmable. As mentioned above, programmable memory devices allow data to be written and rewritten multiple times, making them suitable for applications requiring frequent updates, such as random access memory (RAM) devices. Conversely, non-programmable memory devices, such as one-time programmable (OTP) memory devices, can only be written to once, thus ensuring that the data remains unchanged. Memory devices are used in various applications where data security and immutability are required. However, such memory cells may occupy a relatively large cell area of ​​the memory device. For example, one or more gate regions may exist between adjacent pairs of memory cells, such as dummy gate regions or gate regions located at the edge of diffusion regions or between diffusion regions. This results in low memory cell density, limiting the storage capacity of the memory device.

[0008] In some instances described herein, the systems and methods include devices having relatively high-density memory cells. For example, cut regions (e.g., trenches filled with dielectric material) are formed between adjacent pairs of memory cells, between adjacent pairs of transistors of memory cells, and / or between adjacent pairs of components of transistors of memory cells, rather than the gate regions found in structures such as poly over diffusion edge (PODE) and continuous poly over diffusion edge (CPODE). This minimizes the contact poly pitch (CPP) between regions. PODE and CPODE are scheme types for reducing CPP, wherein CPODE has a smaller CPP than PODE. Therefore, the device area of ​​the devices of this disclosure can be reduced, for example, by 20% to 50% compared to PODE and CPODE structures. More specifically, Figure 1 is a schematic block diagram illustrating an exemplary device 100 according to various embodiments of this disclosure.

[0009] As illustrated in Figure 1, the exemplary device 100 (e.g., a memory device, such as a RAM device or an OTP memory device) includes a plurality of memory cells 110, a plurality of word lines (WL0~WLn), and a plurality of bit lines (BL0-BLn). An OTP memory device is a type of memory device that permanently stores data bits that cannot be changed once written. For example, an OTP memory device includes a plurality of memory cells, each including an antifuse that is initially non-conductive, representing logic "0" (or "1"). The antifuse can be programmed to be conductive, for example, by applying a high-voltage signal to the antifuse. This state represents a programmed bit, such as logic "1" (or "0"). Unlike a fuse that blows during programming (i.e., becomes non-conductive, sometimes permanently), an antifuse creates a conductive path during programming.

[0010] Memory cells 110 may be arranged in an array, for example, columns and rows. Memory cells 110 in each column are connected to corresponding word lines (WL0-WLn). Similarly, memory cells 110 in each row are connected to corresponding bit lines (BL0-BLn). Memory cells 110 store bits, which may be logic "0" or "1", and undergo permanent and irreversible changes when written to or programmed, in some embodiments, such as OTP memory devices. For example, this irreversible change occurs when a high-voltage signal is applied to the corresponding word lines (WL0-WLn), thereby ensuring that memory cells 110 cannot be reprogrammed (i.e., the bits stored therein cannot be overwritten).

[0011] In an exemplary embodiment, the memory cell 110 is implemented using antifuse technology. Unlike a fuse (which is initially conductive and becomes non-conductive upon "melting" or programming), an antifuse is initially open, representing logic "0" (or "1"), and can be programmed to create a conductive path, representing logic "1" (or "0"), thereby making the antifuse permanently conductive and non-reprogrammable. In some embodiments, cut regions (e.g., trenches filled with dielectric material) are formed between adjacent pairs of memory cells 110, between adjacent pairs of transistors of memory cells 110, and / or between adjacent pairs of components of transistors of memory cells 110, instead of the gate regions found in, for example, PODE and CPODE structures. This minimizes the CPP between memory cells. Compared to PODE and CPODE structures, this further results in a reduction in the device area of ​​the device of this disclosure, for example, by 20% to 50%.

[0012] Figure 2 is a schematic circuit diagram illustrating another exemplary memory cell 200 according to various embodiments of the present disclosure. As illustrated in Figure 2, the exemplary memory cell 200 (e.g., memory cell 110) is in the form of a two-transistor (2T) memory cell and includes an antifuse transistor (T1) and a select transistor (T2). In an exemplary embodiment, the transistors (T1, T2) are n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs). In an alternative embodiment, at least one of the transistors (T1, T2) is a p-type metal-oxide-semiconductor field-effect transistor (pMOSFET).

[0013] Transistor (T1) has a floating source / drain terminal 210 that does not receive any signal, such as voltage or ground signal. Transistor (T2) has a bit line (BL) source / drain terminal 220 connected to the bit line (BL) for sensing bits stored in the memory cell 200 during a read operation on the memory cell 200. The second source / drain terminal 230 of transistor (T1) and the second source / drain terminal 240 of transistor (T2) are connected to each other and to source / drain contacts (MD). MD (or metal layer) is a conductive material (e.g., tungsten (W), cobalt (Co), titanium (T1), other suitable metals and their alloys) deposited over the source / drain regions to serve as a conductive path.

[0014] The gate of transistor (T1) is connected to a first word line, which receives a word line programming (WLP) signal for changing the state of transistor (T1) during a write (or program) operation on memory cell 200. The gate of transistor (T2) is connected to a second word line, which receives a word line read (WLR) signal for retrieving bits stored in memory cell 200 during a read operation on memory cell 200.

[0015] As described above, the memory cell 200 permanently stores bits using a combination of two transistors (T1, T2) by changing the state of the transistor (T1). For example, before programming, the gate dielectric layer of the transistor (T1) is intact, that is, there is no conductive path in the transistor (T1). No conductive path means that logic "0" (or "1") is stored in the memory cell 200. During writing to or programming operations on the memory cell 200, a word-line programming (WLP) signal (e.g., a high-voltage signal) is applied to the gate of the transistor (T1). This may cause the dielectric of the gate dielectric layer of the transistor (T1) to break down, thereby forming a permanent conductive path (short circuit) in the transistor (T1). This permanent conductive path means that logic "1" (or "0") is stored in the transistor (T1).

[0016] Subsequently, when a read operation is required on the memory cell 200, the bit line (BL) is precharged to a predetermined voltage level. Then, a word line read (WLR) signal is applied to the gate of the transistor (T2), thereby activating the transistor (T2). This connects the bit line (BL) to the transistor (T1) via the transistor (T2). If the transistor (T1) is programmed, current flows through the transistors (T1, T2), and the sense amplifier connected to the bit line (BL) interprets the bits stored in the transistor (T1) as logic "1" (or "0"). Conversely, if the transistor (T1) is not programmed, it remains non-conductive, and essentially no current flows through it. In this state, the sense amplifier interprets the bits stored in the memory cell 200 as logic "0" (or "1").

[0017] Figure 3 is a schematic layout diagram illustrating another exemplary memory cell 300 (e.g., memory cell 110) according to various embodiments of the present disclosure. As illustrated in Figure 3, the exemplary memory cells (only one of the memory cells is labeled 300 in Figure 3) are arranged along a first direction (x). Since the structures of memory cells are similar, only one memory cell is described. Memory cell 300 includes a diffusion region 310, a first source / drain contact 320, a second source / drain contact 330, a first gate region 340, a second gate region 350, and a dicing region 360. The diffusion region 310 (e.g., an active region or a region for manufacturing transistors) is formed above the substrate and extends along the first direction (x).

[0018] The diced region 360 surrounds the memory cell 300 and includes a plurality of diced region portions 360a to 360d. For example, diced region portion 360a extends in a first direction (x). Each diced region portion 360b, 360c extends in a second direction (y) transverse to the first direction (x), is interconnected by the diced region portion 360a, and adjoins (or defines) a corresponding edge of the diffusion region 310. The diced region portion 360d cuts (or divides) the diffusion region 310 into two halves and defines the edge of each half. The diced region portions 360a and 360d together form a generally T-shape. The diced region 360 is a trench formed in the substrate and filled with a dielectric material. Examples of dielectric materials used for the diced region 360 include SiO2, SiN, HfO2, TaO2, TiO2, and other suitable dielectric materials.

[0019] Source / drain contacts 320, 330 (e.g., MD layer) and gate regions 340, 350 (e.g., polycrystalline silicon wires or metal gates) are arranged along the length of diffusion region 310, extending along the second direction (y), and overlapping diffusion region 310 in a third direction (z) transverse to the first and second directions (x, y). Source / drain contacts 320 are connected to source / drain regions 230 of transistor (T1) and source / drain regions 240 of transistor (T2). Source / drain contacts 330 are connected to source / drain regions 220 of transistor (T2) and bit lines (BL).

[0020] Gate regions 340 and 350 correspond to the gate terminals of transistors (T1, T2). In some embodiments, gate regions 340 and 350 comprise polycrystalline silicon. In other embodiments, gate regions 340 and 350 comprise TiN, W, Ta, Al, Mo, Co, other suitable metallic gate materials, or alloys thereof. In this exemplary embodiment, the memory cell 300 is a two-contact polypitch (2 CPP) memory cell. CPP refers to the distance between adjacent features (such as MD contacts 320 and 330 and polycrystalline silicon lines 340 and 350). As can be seen from Figure 3, the CPP between the cut-out region 360d and the source / drain contact 320 is 1 unit (e.g., 1 nanometer), and the CPP between the source / drain contacts 320 and 330 is also 1 unit.

[0021] As described above, a cut-out region 360d is provided between adjacent pairs of memory cells, thereby reducing the cut-out ratio (CPP) between memory cells. This reduction in CPP results in a relatively small device area for the device 100 of this disclosure. For example, Figure 4 is a schematic layout diagram illustrating another exemplary memory cell 400 (e.g., memory cell 110) according to various embodiments of this disclosure. As shown in Figure 4, a cut-out region 410 is formed between adjacent pairs of memory cells 400, instead of the gate region and / or MD layer found in structures such as PODE and CPODE. This minimizes the CPP between adjacent pairs of memory cells 400 from more than 1 unit (e.g., 5 units) to less than 5 units (e.g., 1 unit). This, in turn, reduces the device area of ​​the device 100 of this disclosure by up to 20% to 50% compared to PODE and CPODE structures.

[0022] Figure 5 is a schematic layout diagram illustrating another exemplary memory cell 500 (e.g., memory cell 110) according to various embodiments of the present disclosure. As shown in Figure 5, the exemplary memory cell of this embodiment (only one memory cell is labeled 500 in Figure 5) differs from the previous embodiment in that the cut regions 560 surround the memory cell 500 (i.e., are disposed at the left, right, top, and bottom boundaries of the memory cell 500) and include cut region portions 560a to 560e. The cut region portions 560a and 560e extend in a first direction (x) and are opposite to each other in a second direction (y). Each cut region portion 560b and 560c extends along the second direction (y), interconnects with the cut region portions 560a and 560e, and adjoins (or defines) the corresponding edge of the diffusion region 310. The dicing region 560d divides the diffusion region 310 into two halves, defining the edges of each half, and forms a generally T-shape with the dicing region 560a. The dicing region 560 is a trench formed in the substrate and filled with a dielectric material. Examples of dielectric materials used for the dicing region 560 include SiO2, SiN, HfO2, TaO2, TiO2, and other suitable dielectric materials.

[0023] Although memory cells 200 to 500 are illustrated as 2T memory cells, it should be understood that the number of transistors in memory cells 200 to 500 may be increased or decreased as needed after reading this disclosure. For example, Figure 6 is a schematic circuit diagram illustrating another exemplary memory cell 600 according to various embodiments of this disclosure. As shown in Figure 6, the exemplary memory cell 600 (e.g., memory cell 110) is in the form of a three-transistor (3T) memory cell and includes an antifuse transistor (T3), a transmission transistor (T4), and a select transistor (T5). In this exemplary embodiment, the transistors (T3-T5) are nMOSFETs. In an alternative embodiment, at least one of the transistors (T3-T5) is a pMOSFET.

[0024] Transistor (T3) has a floating source / drain terminal 610, which does not receive any signal, such as voltage or ground signal. Transistor (T5) has a bit line (BL) source / drain terminal 620, which is connected to the bit line (BL) for sensing bits stored in the memory cell 600 during a read operation on the memory cell 600. The second source / drain terminal 630 of transistor (T3) and the first source / drain terminal 640 of transistor (T4) are connected to each other and to the first source / drain contact (MD1). The second source / drain terminal 650 of transistor (T4) and the second source / drain terminal 660 of transistor (T5) are connected to each other and to the second source / drain contact (MD2).

[0025] The gate of transistor (T3) is connected to a first word line, which receives a first word line programming (WLP) signal for changing the state of transistor (T3) during a write (or program) operation on memory cell 600. The gate of transistor (T4) is connected to a second word line and receives a word line activating (WLM) signal for connecting transistor (T5) to transistor (T4) during a program and / or read operation on memory cell 600. The gate of transistor (T5) is connected to a third word line, which receives a word line read (WLR) signal for retrieving bits stored in memory cell 300 during a read operation on memory cell 600.

[0026] As described above, the memory cell 600 involves permanently storing bits using three transistors (T3~T5) by changing the state of transistor (T3). For example, before programming, the gate dielectric layer of transistors (T3, T4) is intact, that is, there is no conductive path in transistors (T3, T4). No conductive path means that logic "0" (or "1") is stored in memory cell 600. During writing or programming operations on memory cell 600, a word line programming (WLP) signal (e.g., a high voltage signal) is applied to the gate terminal of transistor (T3). This may cause the dielectric of the gate dielectric layer of transistors (T3, T4) to break down, thereby forming a permanent conductive path (short circuit) in transistor (T3). This permanent conductive path means that logic "1" (or "0") is stored in transistor (T3).

[0027] Subsequently, when a read operation is required on the memory cell 600, the bit line (BL) is precharged to a predetermined voltage level. Then, a word line reading (WLR) signal is applied to the gate of transistor (T5), thereby activating transistor (T5). Simultaneously, transistor (T5) is turned on by a word line activating (WLM) signal at its gate. The bit line (BL) is connected to transistor (T3) via transistors (T4, T5). If transistor (T3) is programmed, current flows through transistors (T3~T5), and the sense amplifier connected to the bit line (BL) interprets the bits stored in transistor (T3) as logic "1" (or "0"). Conversely, if transistors (T3, T4) are not programmed, transistor (T3) remains non-conductive, and essentially no current flows through transistor (T3). In this state, the sensing amplifier interprets the bits stored in memory cell 600 as logic "0" (or "1").

[0028] Figure 7 is a schematic layout diagram illustrating another exemplary memory cell 700 according to various embodiments of the present disclosure. As shown in Figure 7, exemplary memory cells (only one memory cell is labeled 700 in Figure 7) are arranged along a first direction (x). Since the structures of memory cells are similar, only one memory cell is described. Memory cell 700 includes a diffusion region 710, first source / drain contacts to third source / drain contacts 720 to 740 (source / drain contacts 720, 730, 740), a first gate region to a second gate region 750 to 760 (gate regions 750, 760), and a cut-out region 780. The diffusion region 710 (e.g., an OD region) is formed above the substrate and extends along the first direction (x).

[0029] The diced region 780 surrounds the memory cell and includes a plurality of diced region portions 780a to diced region portions 780d (diced region portions 780a, 780b, 780c, 780d). For example, diced region portion 780a extends along a first direction (x). Each diced region portion 780b, 780c extends along a second direction (y), is interconnected by diced region portion 780a, and adjoins (or defines) a corresponding edge of the diffusion region 710. Dicing region portion 780d cuts (or divides) the diffusion region 710 into two halves and defines the edge of each half. Dicing region portions 780a, 780d together form a generally T-shape. The diced region 780 is a trench formed in the substrate and filled with a dielectric material. Examples of such dielectric materials used for the diced region 780 include SiO2, SiN, HfO2, TaO2, TiO2, and other suitable dielectric materials.

[0030] The source / drain contacts 720 to 740 (e.g., MD layer) and gate regions 750 to 770 (e.g., polycrystalline silicon wire or metal gate) of the memory cell 700 are arranged along the length of the diffusion region 710, extending along the second direction (y) and overlapping with the diffusion region 710 in the third direction (z). The source / drain contacts 720 are connected to the source / drain region 630 (second source / drain end 630) of transistor (T3) and the source / drain region 640 (first source / drain end 640) of transistor (T4). The source / drain contacts 730 are connected to the source / drain region 650 (second source / drain end 650) of transistor (T4) and the source / drain region 660 (second source / drain end 660) of transistor (T5). Source / drain contacts 740 are connected to the source / drain regions 620 (bit line source / drain terminals 620) and bit lines (BL) of the transistor (T5). In some embodiments, source / drain contacts 720 to 740 (source / drain contacts 720, 730, 740) are made of a conductive material, such as copper, aluminum, tungsten, titanium, other suitable conductive materials, or alloys thereof.

[0031] Gate regions 750 to 770 (gate regions 750, 760, 770) correspond to the gate terminals of the transistors (T3-T5). In some embodiments, gate regions 750 to 770 comprise polycrystalline silicon. In other embodiments, gate regions 750 to 770 comprise TiN, W, Ta, Al, Mo, Co, other suitable metallic gate materials or alloys thereof. In this exemplary embodiment, the memory cell 700 is a three-contact polycrystalline silicon pitch (3 CPP) memory cell. CPP refers to the distance between adjacent features (e.g., MD contacts 720 to 740 and polycrystalline silicon lines 750 to 770). As can be seen from Figure 7, the CPP between the cut-out region 780d and the source / drain contact 720 is 1 unit (e.g., 1 nanometer). Similarly, the CPP between source / drain contacts 720 and 730 is 1 unit, and the CPP between source / drain contacts 730 and 740 is also 1 unit.

[0032] As described above, the cut region 780d is located between a pair of adjacent memory cells 700, thereby reducing the CPP between memory cells. This reduction in CPP results in a relatively small device area for the device 100 of this disclosure. For example, as illustrated in Figure 7, the cut region 780d (cut region 780d) is formed between a pair of adjacent memory cells, rather than the gate region and / or MD layer found in structures such as PODE and CPODE. This minimizes the CPP between a pair of adjacent memory cells of the device 100 from greater than 1 unit (e.g., 5 units) to less than 5 units (e.g., 1 unit). Consequently, the device area of ​​the device 100 of this disclosure is reduced by up to 20% to 50% compared to PODE and CPODE structures.

[0033] Figure 8 is a schematic layout diagram illustrating another exemplary memory cell 800 (e.g., memory cell 110) according to various embodiments of the present disclosure. As shown in Figure 8, the exemplary memory cell in this embodiment (only one memory cell is labeled 800 in Figure 8) differs from the previous embodiment in that a cut region 880 surrounds the memory cell 800 (i.e., is disposed at the left, right, top, and bottom boundaries of the memory cell 800) and includes cut region portions 880a to 880e. Cut region portions 880a and 880e extend in a first direction (x) and are opposite to each other in a second direction (y). Each cut region portion 880b and 880c extends along the second direction (y), interconnects with cut region portions 880a and 880e, and adjoins (or defines) the corresponding edge of the diffusion region 710. The dicing region 880d divides the diffusion region 710 into two halves, defining the edges of each half, and forms a generally T-shape with the dicing region 880a. The dicing region 880 is a trench formed in the substrate and filled with a dielectric material. Examples of dielectric materials for the dicing region 880 include SiO2, SiN, HfO2, TaO2, TiO2, and other suitable dielectric materials.

[0034] Figure 9 is a schematic circuit diagram illustrating another exemplary memory cell 900 according to various embodiments of the present disclosure. As shown in Figure 9, the exemplary memory cell 900 (e.g., memory cell 110) is in the form of a four-transistor (4T) memory cell and includes first to third antifuse transistors (T6 to T8) and a select transistor (T9). In this exemplary embodiment, transistors (T6, T9) are nMOSFETs, while transistors (T7, T8) are pMOSFETs. In an alternative embodiment, at least one of transistors (T6, T9) is a pMOSFET, and at least one of transistors (T7, T8) is an nMOSFET.

[0035] Transistors (T6 to T8) have floating source / drain terminals 910a, 910b, and 910c, which do not receive any signals, such as voltage or ground signals. Transistor (T9) has a bit line (BL) source / drain terminal 920, which is connected to the bit line (BL) for sensing bits stored in the memory cell 900 during a read operation on the memory cell 900. The second source / drain terminal 930 of transistor (T6) and the second source / drain terminal 940 of transistor (T9) are connected to each other and to the source / drain contact (A).

[0036] The gate of transistor (T6) is connected to a first word line, which receives a word line programming (WLP) signal for changing the state of transistor (T6) during a write (or program) operation on memory cell 900. The gate of transistor (T9) is connected to a second word line, which receives a word line read (WLR) signal for retrieving bits stored in memory cell 900 during a read operation on memory cell 900. The second source / drain terminal 950 of transistor (T7) and the second source / drain terminal 960 of transistor (T8) are interconnected and connected to the gate of transistor (T6). The gates of transistors (T7) and (T8) are interconnected and connected to the source / drain contact (A).

[0037] As described above, the memory cell 900 includes four transistors (T6 to T9) to permanently store bits therein by changing the state of at least one of the transistors (T6 to T8). For example, before programming, the gate dielectric layer of the transistors (T6 to T8) is intact, that is, there is no conductive path in the transistors (T6 to T8). No conductive path means that logic "0" (or "1") is stored in the memory cell 900. During writing or programming operations on the memory cell 900, a word line programming (WLP) signal (e.g., a high voltage signal) is applied to the gate terminal of the transistor (T6) and the source / drain terminals 950, 960 (second source / drain terminals 950, 960) of the transistors (T7, T8). This could cause dielectric breakdown of the gate dielectric layer of at least one of the transistors (T6 to T8), thereby forming a permanent conductive path (short circuit) in at least one of the transistors (T6 to T8). This permanent conductive path represents a logic "1" (or "0") stored in the transistor (T6 to T8).

[0038] Subsequently, when a read operation is required on the memory cell 900, the bit line (BL) is precharged to a predetermined voltage level. Then, a word line reading (WLR) signal is applied to the gate of the transistor (T9), thereby activating the transistor (T9). The bit line (BL) is connected to the transistors (T6 to T8) via the transistor (T9). If the transistors (T6 to T8) are programmed, current flows through the transistors (T6 to T9), and the sense amplifier connected to the bit line (BL) interprets the bits stored in the transistors (T6 to T8) as logic "1" (or "0"). Conversely, if the transistors (T6 to T8) are not programmed, the transistors (T6 to T8) remain non-conductive, and essentially no current flows through them. In this state, the sense amplifier interprets the bits stored in the memory cell 900 as logic "0" (or "1").

[0039] Figure 10 is a schematic layout diagram illustrating another exemplary memory cell 1000 according to various embodiments of the present disclosure. As shown in Figure 10, the exemplary memory cell 1000 includes a first diffusion region 1010a, a second diffusion region 1010b, first source / drain contacts to fifth source / drain contacts 1020a to 1020e (source / drain contacts 1020a to 1020e), a first gate region to an eighth gate region 1030a to 1030h (gate regions 1030a to 1030h), and a cut-out region 1040. The diffusion regions 1010a and 1010b (first diffusion region 1010a and second diffusion region 1010b) (e.g., OD regions) are formed above a substrate, extending along a first direction (x) and spaced apart from each other along a second direction (y).

[0040] The cut region 1040 includes a plurality of cut region portions 1040a to 1040g. For example, cut region portions 1040a and 1040b extend along a first direction (x) and are spaced apart from each other along a second direction (y). Each cut region portion 1040c and 1040e extends along the second direction (y), interconnects cut region portions 1040a and 1040b, and adjoins (or defines) a corresponding edge of the diffusion region 1010a (the first diffusion region 1010a). Cut region portion 1040d cuts (or divides) the diffusion region 1010a into two halves, defines the edge of each half, and cooperates with cut region portion 1040a to form a generally T-shape. In this exemplary embodiment, cut region portions 1040a, 1040b, 1040c, and 1040e surround transistors (T7, T8). Furthermore, the cut regions 1040a to 1040d are located at the boundary of one of the transistors (T7, T8). Additionally, the cut regions 1040a, 1040b, 1040d, and 1040e are located at the boundary of the other transistor (T7, T8).

[0041] Each cut region portion 1040f, 1040g extends in the second direction (y), is interconnected by the cut region portion 1040b, and adjoins (or defines) the corresponding edge of the diffusion region 1010b (the second diffusion region 1010b). In this exemplary embodiment, the cut region portions 1040b, 1040f, and 1040g surround the transistors (T6, T9). The cut region 1040 is a trench formed in the substrate and filled with a dielectric material. Examples of dielectric materials for the cut region 1040 include SiO2, SiN, HfO2, TaO2, TiO2, and other suitable dielectric materials.

[0042] The source / drain contacts 1020a, 1020b (e.g., the MD layer) and gate regions 1030a to 1030d (e.g., polycrystalline silicon wires or metal gates) are arranged along the length of the diffusion region 1010a (the first diffusion region 1010a), extending along the second direction (y) and overlapping with the diffusion region 1010a (the first diffusion region 1010a) in the third direction (z). The source / drain contacts 1020c to 1020e (e.g., the MD layer) and gate regions 1030e to 1030h (e.g., polycrystalline silicon wires or metal gates) are arranged along the length of the diffusion region 1010b (the second diffusion region 1010b), extending along the second direction (y) and overlapping with the diffusion region 1010b in the third direction (z). Source / drain contacts 1020a and 1020b are connected to the source / drain regions 950 and 960 (second source / drain regions 950 and 960) of transistors (T7 and T8) and the gate terminal of transistor (T6).

[0043] Source / drain contacts 1020c and 1020e are connected to the source / drain regions 930 and 940 (second source / drain regions 930 and 940) of transistors (T6 and T9) and the gate terminals of transistors (T7 and T8). Source / drain contact 1020d is connected to the source / drain terminal 920 (bit line source / drain terminal 920) of transistor (T9) and the bit line (BL). In some embodiments, source / drain contacts 1020a to 1020e are made of a conductive material, such as copper, aluminum, tungsten, titanium, other suitable conductive materials, or alloys thereof.

[0044] Gate regions 1030a to 1030d correspond to the gate terminals of transistors (T7, T8). Gate regions 1030e and 1030h correspond to the gate terminals of transistor (T6). Gate regions 1030f and 1030g correspond to the gate terminals of transistor (T9). In some embodiments, gate regions 1030a to 1030h comprise polycrystalline silicon. In other embodiments, gate regions 1030a to 1030h comprise TiN, W, Ta, Al, Mo, Co, other suitable metallic gate materials, or alloys thereof.

[0045] In this exemplary embodiment, the memory cell 1000 is a 2 CPP memory cell. CPP refers to the distance between adjacent features (such as MD contacts 1020a to 1020e and polysilicon lines 1030a and 1030f). As can be seen from Figure 10, the CPP between the diced region 1040f and the source / drain contact 1020c is 1 unit (e.g., 1 nanometer), and the CPP between the source / drain contacts 1020c and 1020d is also 1 unit.

[0046] As described above, the cut region 1040 is located between an adjacent pair of memory cells, thereby reducing the cut-down ratio (CPP) between memory cells. This reduction in CPP results in a relatively small device area for the device 100 of this disclosure. For example, as illustrated in Figure 10, cut regions 1040a to 1040g (1040a~1040g) are formed between an adjacent pair of memory cells 1000, instead of the gate region and / or MD layer found in structures such as PODE and CPODE. This minimizes the CPP between an adjacent pair of memory cells of the device 100 from more than 1 unit (e.g., 5 units) to less than 5 units (e.g., 1 unit). Consequently, the device area of ​​the device 100 of this disclosure is reduced by up to 20% to 50% compared to PODE and CPODE structures.

[0047] Figure 11 is a schematic circuit diagram illustrating another exemplary memory cell 1100 according to various embodiments of the present disclosure. As shown in Figure 11, the exemplary memory cell 1100 is in the form of a six-transistor (6T) memory cell and includes a first antifuse transistor to a fourth antifuse transistor (T10 to T13), a transmission transistor (T14), and a selection transistor (T15). In this exemplary embodiment, the transistors (T10, T14, T15) are nMOSFETs, while the transistors (T11 to T13) are pMOSFETs. In an alternative embodiment, at least one of the transistors (T10, T14, T15) is a pMOSFET, and at least one of the transistors (T11 to T13) is an nMOSFET.

[0048] Transistors (T10, T11, T13) have floating source / drain terminals 1110a, 1110b, and 1110c, which do not receive any signals, such as voltage or ground signals. Transistor (T15) has a bit line (BL) source / drain terminal 1120, which is connected to the bit line (BL) for sensing bits stored in the memory cell 1100 during a read operation on the memory cell 1100. The second source / drain terminal 1130 of transistor (T10) and the first source / drain terminal 1140 of transistor (T14) are connected to each other and to the source / drain contact (A). The second source / drain terminals of transistor (T14) and (T15) are connected to each other.

[0049] The gate of transistor (T10) is connected to a first word line, which receives a word line programming (WLP) signal for changing the state of transistor (T10) during a write (or program) operation on memory cell 1100. The gate of transistor (T14) is connected to a second word line and receives a word line activating (WLM) signal for connecting transistor (T15) to transistor (T10) during a program and / or read operation on memory cell 1100. The gate of transistor (T15) is connected to a third word line, which receives a word line read (WLR) signal for retrieving bits stored in memory cell 1100 during a read operation on memory cell 1100.

[0050] The second source / drain terminal 1150 of transistor (T11) and the first source / drain terminal 1160 of transistor (T12) are interconnected and connected to the gate terminal of transistor (T10). The second source / drain terminal 1170 of transistor (T12) and the second source / drain terminal 1180 of transistor (T13) are interconnected and connected to the gate terminal of transistor (T10). The gate terminals of transistor (T12), transistor (T13), and transistor (T4) are interconnected and connected to the source / drain contact (A).

[0051] As described above, the memory cell 1100 is implemented using six transistors (T10 to T15) to permanently store bits therein by changing the state of at least one of the transistors (T10 to T13). For example, before the program runs, the gate dielectric layer of the transistors (T10 to T13) is intact, that is, there are no conductive paths in the transistors (T10 to T13). No conductive path means that logic "0" (or "1") is stored in the memory cell 1100. During writing or programming of memory cell 1100, a word-line programming (WLP) signal (e.g., a high-voltage signal) is applied to the gate of transistor (T10) and the source / drain terminals 1150 to 1180 (second source / drain terminal 1150, first source / drain terminal 1160, second source / drain terminal 1170, second source / drain terminal 1180) of transistors (T12 to T14). This may cause dielectric breakdown of the gate dielectric layer of at least one of the transistors (T10 to T13), thereby forming a permanent conductive path (short circuit) in at least one of the transistors (T10 to T13). This permanent conductive path represents a logic "1" (or "0") stored in transistor (T1 to T14).

[0052] Subsequently, when a read operation is required on memory cell 1100, the bit line (BL) is precharged to a predetermined voltage level. Then, a word line reading (WLR) signal is applied to the gate of transistor (T15), thereby activating transistor (T15). Simultaneously, each transistor (T14) is turned on with a word line activating (WLM) signal at its gate. The bit line (BL) is connected to transistors (T10 to T13) via transistor (T14). If transistors (T10 to T13) are programmed, current flows through transistors (T10 to T15), and the sense amplifier connected to the bit line (BL) interprets the bits stored in transistors (T10 to T13) as logic "1" (or "0"). Conversely, if the transistors (T10 to T13) are not programmed, they remain non-conductive, and essentially no current flows through them. In this state, the sense amplifier interprets the bits stored in memory cell 1100 as logic "0" (or "1").

[0053] Figure 12 is a schematic layout diagram illustrating another exemplary memory cell 1200 according to various embodiments of the present disclosure. As shown in Figure 12, the exemplary memory cell 1200 includes a first diffusion region 1210a, a second diffusion region 1210b, first to ninth source / drain contacts 1220a~1220i, a first gate region to twelfth gate regions 1230a~1230l, and a cut-out region 1240. The diffusion regions 1210a (first diffusion region 1210a) and 1210b (e.g., OD region) (second diffusion region 1210b) are formed above the substrate, extending along a first direction (x) and spaced apart from each other along a second direction (y).

[0054] The cut region 1240 includes a plurality of cut region portions 1240a to 1240g. For example, cut region portions 1240a and 1240b extend along a first direction (x) and are spaced apart from each other along a second direction (y). Each cut region portion 1240c and 1240e extends along the second direction (y), interconnects with cut region portions 1240a and 1240b, and adjoins (or defines) a corresponding edge of the diffusion region 1210a. Cut region portion 1240d cuts (or divides) the diffusion region 1210a into two halves, defines the edge of each half, and cooperates with cut region portion 1240a to form a generally T-shape. In this exemplary embodiment, cut region portions 1240a, 1240b, 1240c, and 1240e surround a transistor (T11 to T13). Furthermore, the cut regions 1240a to 1240d are located at the boundaries of the transistors (T11 to T13). Additionally, the cut regions 1240a, 1240b, 1240d, and 1240e are located at the boundaries of the transistors (T11 to T13).

[0055] Each cut region portion 1240f, 1240g extends in the second direction (y), is interconnected by cut region portion 1240b, and adjoins (or defines) the corresponding edge of diffusion region 1210b. In this exemplary embodiment, cut region portions 1240b, 1240f, and 1240g surround transistors (T10, T14, T15). Cut region 1240 is a trench formed in the substrate and filled with a dielectric material. Examples of dielectric materials for cut region 1240 include SiO2, SiN, HfO2, TaO2, TiO2, and other suitable dielectric materials.

[0056] The source / drain contacts 1220a to 1220d (e.g., the MD layer) and gate regions 1230a to 1230f (e.g., polycrystalline silicon wires or metal gates) are arranged along the length of the diffusion region 1210a, extending along the second direction (y) respectively, and overlapping with the diffusion region 1210a in the third direction (z). The source / drain contacts 1220e to 1220i (e.g., the MD layer) and gate regions 1230g to 1230l (e.g., polycrystalline silicon wires or metal gates) are arranged along the length of the diffusion region 1210b, extending along the second direction (y) respectively, and overlapping with the diffusion region 1210b in the third direction (z). Source / drain contacts 1220a to 1220d are connected to the source / drain regions 1150, 1160, 1170, and 1180 (second source / drain terminal 1150, first source / drain terminal 1160, second source / drain terminal 1170, and second source / drain terminal 1180) of transistors (T11 to T13) and the gate terminal of transistor (T10).

[0057] Source / drain contacts 1220e and 1220i are connected to the source / drain regions 1130 and 1140 (second source / drain terminal 1130 and first source / drain terminal 1140) of transistors (T10 and T14) and the gate terminals of transistors (T11 to T13). Source / drain contacts 1220f and 1220h are connected to the source / drain regions of transistors (T14 and T15). Source / drain contact 1220g is connected to the source / drain terminal 1120 (bit line source / drain terminal 1120) of transistor (T15) and the bit line (BL). In some embodiments, source / drain contacts 1220a to 1220i are made of a conductive material, such as copper, aluminum, tungsten, titanium, other suitable conductive materials, or alloys thereof.

[0058] Gate regions 1230a to 1230f correspond to the gate terminals of transistors (T11 to T13). Gate regions 1230g and 1230l correspond to the gate terminals of transistor (T10). Gate region 1230h corresponds to the gate terminal of transistor (T14). Gate regions 1230i to 1230k correspond to the gate terminals of transistor (T15). In some embodiments, gate regions 1230a to 1230l comprise polycrystalline silicon. In other embodiments, gate regions 1230a to 1230l comprise TiN, W, Ta, Al, Mo, Co, other suitable metallic gate materials, or alloys thereof.

[0059] In this exemplary embodiment, the memory cell 1100 is a 3CPP memory cell. CPP refers to the distance between adjacent features (e.g., MD contacts 1220a to 1220i and polysilicon lines 1230a to 1230l). As can be seen from Figure 12, the CPP between the diced region 1240f and the source / drain contact 1220e is 1 unit (e.g., 1 nanometer). Similarly, the CPP between source / drain contacts 1220e and 1220f is 1 unit, and the CPP between source / drain contacts 1220f and 1220g is also 1 unit.

[0060] As described above, the cut region 1240 (cut region 1240) is located between an adjacent pair of memory cells, thereby reducing the CPP between memory cells. This reduction in CPP results in a relatively small device area for the device 100 of this disclosure. For example, as shown in Figure 12, the cut region 1240 is formed between an adjacent pair of memory cells 1100, rather than the gate region and / or MD layer found in, for example, PODE and CPODE structures. This minimizes the CPP between an adjacent pair of memory cells of the device 100 from greater than 1 unit (e.g., 5 units) to less than 5 units (e.g., 1 unit). Therefore, the device area of ​​the device 100 of this disclosure can be reduced by up to 20% to 50% compared to PODE and CPODE structures.

[0061] Figure 13 is a flowchart of an exemplary method 1300 of a manufacturing apparatus 100 according to various embodiments of the present disclosure. For ease of understanding, the exemplary method 1300 will now be described further with reference to Figures 1 through 12. It will be understood that method 1300 is applicable to structures other than those shown in Figures 1 through 12. Furthermore, it will be understood that in alternative embodiments of method 1300, additional operations may be provided before, during, and after method 1300, and some operations described below may be replaced or eliminated.

[0062] In operation 1310, the device manufacturing tool receives a memory cell layout, such as a memory cell 300 layout. Subsequently, the device manufacturing tool receives a substrate, which may be made of silicon, germanium, III-V semiconductors, other suitable substrate materials, or alloys thereof. In operation 1320, the device manufacturing tool forms a diffusion region, such as diffusion region 310, over the substrate. Next, the device manufacturing tool uses the memory cell 300 layout received in operation 1310 to manufacture a plurality of transistors, such as transistors (T1, T2), over the diffusion region 310. For example, in operation 1330, the device manufacturing tool forms source and drain regions, such as source and drain regions 210 to 240 (floating source / drain end 210, bit-line source / drain end 220, second source / drain end 230, second source / drain end 240), over the diffusion region 310. In this exemplary embodiment, operation 1330 includes planting dopants in the diffusion region 310. Dopants may include arsenic, phosphorus, boron, gallium, antimony, other suitable source / drain dopants, or combinations thereof.

[0063] In operation 1340, the apparatus fabrication tool lightly dops the channel regions of the transistors (T1, T2) to control conductivity. In an alternative embodiment, the apparatus fabrication tool leaves the channel regions undoped. In operation 1350, the apparatus fabrication tool forms gate regions (e.g., gate regions 340, 350) above the channel regions, for example by applying a thin layer of insulating material (e.g., silicon dioxide) to the channel regions to form a gate dielectric layer; depositing a conductive material on the gate dielectric layer; and patterning the conductive material.

[0064] In operation 1360, the device fabrication tool forms source / drain contacts, such as MD layers 320 and 330, above the source and drain regions 210 to 240. In operation 1370, the device fabrication tool, using the memory cell 300 received in operation 1310, etches trenches through the diffusion region 310 in a dicing region (e.g., dicing region 360) of the substrate. In operation 1380, the device fabrication tool fills the trenches with a dielectric material. As previously described, dicing region 360 helps to reduce the CPP in device 100, thereby reducing the device area of ​​device 100 by up to 20% to 50% compared to PODE and CPODE structures.

[0065] In an embodiment, a device includes a plurality of memory cells, each memory cell including a diffusion region and a plurality of transistors. The diffusion region is formed above a substrate. Each transistor is fabricated above the diffusion region and includes one or more source / drain contacts and one or more gate regions. The source / drain contacts and gate regions are arranged along a first direction, extend along a second direction transverse to the first direction, and overlap with the diffusion region along a third direction transverse to the first and second directions. There are no source / drain contacts between the gate regions of an adjacent pair of memory cells, and they have a contact polypitch (CPP) substantially the same as that of an adjacent pair of gate regions in one of the memory cells.

[0066] In another embodiment, a device includes a plurality of memory cells, each memory cell including a diffusion region and a plurality of transistors. The diffusion region is formed above a substrate. Each transistor is fabricated above the diffusion region and includes one or more source / drain contacts and one or more gate regions. The source / drain contacts and gate regions are arranged along a first direction, extend along a second direction transverse to the first direction, and overlap with the diffusion region along a third direction transverse to the first and second directions. There are no source / drain contacts between the gate regions of an adjacent pair of transistors, and they have a contact polypitch (CPP) substantially the same as that of an adjacent pair of gate regions of one of the transistors.

[0067] In another embodiment, a method of manufacturing an apparatus includes the steps of: receiving a memory cell layout; and forming a plurality of memory cells using the memory cell layout. The step of forming memory cells includes the steps of: forming a diffusion region over a substrate; and fabricating a plurality of transistors over the diffusion region. Each transistor includes one or more source / drain contacts and one or more gate regions. The source / drain contacts and gate regions are arranged along a first direction, extend along a second direction transverse to the first direction, and overlap with the diffusion region along a third direction transverse to the first and second directions. The memory cells are formed such that the gate regions of an adjacent pair of memory cells have a smaller contact polypitch (CPP) than one of the memory cells.

[0068] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Figure 1 is a schematic block diagram illustrating various embodiments of the present disclosure; Figure 2 is a schematic circuit diagram illustrating an exemplary memory cell illustrating various embodiments of the present disclosure; Figure 3 is a schematic layout diagram illustrating another exemplary memory cell illustrating various embodiments of the present disclosure; Figure 4 is a schematic layout diagram illustrating another exemplary memory cell illustrating various embodiments of the present disclosure; Figure 5 is a schematic layout diagram illustrating another exemplary memory cell illustrating various embodiments of the present disclosure; Figure 6 is a schematic circuit diagram illustrating another exemplary memory cell illustrating various embodiments of the present disclosure; Figure 7 is a schematic layout diagram illustrating another exemplary memory cell illustrating various embodiments of the present disclosure; Figure 8 is a schematic layout diagram illustrating another exemplary memory cell 800 illustrating various embodiments of the present disclosure; Figure 9 is a schematic circuit diagram illustrating another exemplary memory cell illustrating various embodiments of the present disclosure; Figure 10 is a schematic layout diagram illustrating another exemplary memory cell illustrating various embodiments of the present disclosure. Figure 11 is a schematic circuit diagram illustrating another exemplary memory cell according to various embodiments of the present disclosure; Figure 12 is a schematic layout diagram illustrating another exemplary memory cell according to various embodiments of the present disclosure; and Figure 13 is a flowchart illustrating an exemplary method of a manufacturing apparatus according to various embodiments of the present disclosure.

Claims

1. A memory device comprising: a plurality of memory cells, each memory cell comprising: A diffusion region is formed above the substrate; A plurality of transistors are fabricated above the diffusion region, wherein: each transistor includes one or more source / drain contacts and one or more gate regions; the source / drain contacts and the gate regions are arranged along a first direction, extend along a second direction transverse to the first direction, and overlap with the diffusion region in a third direction transverse to the first and second directions; and there are no source / drain contacts between the gate regions of an adjacent pair of memory cells, and the contacts have a polysilicon pitch substantially the same as that of an adjacent pair of gate regions of one of the memory cells.

2. The memory device as claimed in claim 1, wherein: These memory cells are dual-contact polycrystalline silicon pitch memory cells; The transistors further include: a first source / drain contact connected to a floating source / drain terminal; and a second source / drain contact connected to a bit line; and the first source / drain contact and the second source / drain contact have a contact polysilicon pitch of 1 unit.

3. The memory device of claim 1, further comprising a diced region located between the gate regions of the adjacent pair of memory cells, wherein the diced region includes a trench formed in the substrate and a dielectric layer deposited in the trench.

4. The memory device as claimed in claim 1, wherein the memory cells further comprise: The first source / drain contact is connected to the source / drain region of the first transistor and the source / drain region of the second transistor. The dicing region includes a trench formed in the substrate and a dielectric material deposited in the trench; a first gate region corresponding to the gate end of the first transistor and located between the first source / drain contact and the dicing region; a second source / drain contact connected to a bit line; and a second gate region corresponding to the gate end of the second transistor and located between the first source / drain contact and the second source / drain contact.

5. A memory device comprising: a plurality of memory cells, each memory cell comprising: The first diffusion region is formed above the substrate; A plurality of transistors are manufactured above the first diffusion region, wherein: each transistor includes one or more source / drain contacts and one or more gate regions; the source / drain contacts and the gate regions are arranged along a first direction, extend along a second direction transverse to the first direction, and overlap with the first diffusion region in a third direction transverse to the first and second directions; and there are no source / drain contacts between the gate regions of an adjacent pair of transistors, and the transistors have a contact polysilicon pitch substantially the same as that of an adjacent pair of gate regions of one of the transistors.

6. The memory device as claimed in claim 5, wherein: One of these memory cells is a two-contact polycrystalline silicon pitch memory cell; the transistors further include a source / drain end and a first source / drain contact and a second source / drain contact connected to the source / drain end; and the first source / drain contact and the second source / drain contact have a contact polycrystalline silicon pitch of 1 unit.

7. The memory device as claimed in claim 5, wherein: One of these memory cells is a three-contact polycrystalline silicon pitch memory cell; These transistors further include: a first source / drain contact; and a second source / drain contact connected to a bit line; and a third source / drain contact, located between the first source / drain contact and the second source / drain contact; the first source / drain contact and the third source / drain contact have a contact polycrystalline silicon pitch of 1 unit; and the second source / drain contact and the third source / drain contact have a contact polycrystalline silicon pitch of 1 unit.

8. The memory device as claimed in claim 5, further comprising: a first cut-out region portion defining a first edge of the first diffusion region; a second cut-out region portion adjacent to a second edge of the first diffusion region; and a third cut-out region portion interconnecting the first cut-out region portion and the second cut-out region portion.

9. A method for manufacturing a memory device, the method comprising the steps of: forming a diffusion region over a substrate; and fabricating a plurality of transistors over the diffusion region, wherein: Each transistor includes one or more source / drain contacts and one or more gate regions; and the source / drain contacts and the gate regions are arranged along a first direction, extend along a second direction transverse to the first direction, and overlap with the diffusion region in a third direction transverse to the first and second directions; and form a plurality of memory cells, each memory cell including the transistors, such that a plurality of gate regions of an adjacent pair of memory cells have a smaller contact polysilicon pitch than one of the memory cells, and have a contact polysilicon pitch substantially the same as that of an adjacent pair of gate regions of the memory cells.

10. The method of claim 9, further comprising: connecting a first source / drain contact to a source / drain region of a first transistor and a source / drain region of a second transistor; forming a dicing region by: etching a trench in the substrate; and depositing a dielectric material in the trench; depositing a gate material to form a first gate region corresponding to a gate terminal of the first transistor and located between the first source / drain contact and the dicing region; connecting a second source / drain contact to a bit line; and depositing a gate material to form a second gate region corresponding to a gate terminal of the second transistor and located between the first source / drain contact and the second source / drain contact.

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