Semiconductor device with dipole portion

Abstract

This disclosure provides a semiconductor device having a gate structure disposed above a semiconductor substrate; and a dielectric layer surrounding the gate structure. The semiconductor device also includes a source region and a drain region disposed in the semiconductor substrate and located on opposite sides of the gate structure. The semiconductor device further includes a first dipole portion disposed above the semiconductor substrate and covering the source region; and a first dielectric spacer disposed above the first dipole portion and adjacent to the dielectric layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 888,460 (i.e., priority date "September 18, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having a dipole portion and a method for fabricating the same. Prior Technology

[0003] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a larger number of integrated circuits. Due to the miniaturization of semiconductor components, different types and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor components.

[0004] However, the fabrication and integration of these semiconductor devices involve many complex steps and operations. This increased complexity can lead to several defects. For example, transistors with reduced channel lengths suffer from short-channel effects, such as increased off-state leakage current. Therefore, there is a need for continuous improvement in the fabrication processes of these semiconductor devices to address these defects and enhance their performance.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a gate structure disposed above a semiconductor substrate; and a dielectric layer surrounding the gate structure. The semiconductor device also includes a source region and a drain region disposed in the semiconductor substrate and located on opposite sides of the gate structure. The semiconductor device further includes a first dipole portion disposed above the semiconductor substrate and covering the source region; and a first dielectric spacer disposed above the first dipole portion and adjacent to the dielectric layer.

[0007] In one embodiment, an upper surface of the gate structure is covered by the dielectric layer. In one embodiment, the dielectric layer and the first dielectric spacer comprise different materials. In one embodiment, the first dielectric spacer is spaced from the source by the first dipole portion. In one embodiment, the semiconductor device further includes a source contact that extends through the first dipole portion to directly contact the source region. In one embodiment, the semiconductor device further includes a first lightly doped region disposed in the semiconductor substrate and extending from the source region to the gate structure. In one embodiment, the first lightly doped region is in direct contact with the first dipole portion.

[0008] In one embodiment, the first lightly doped region is spaced apart from the first dielectric spacer by the first dipole portion. In one embodiment, the semiconductor device further includes a first halo implantation region disposed in the semiconductor substrate and extending from the source region to the gate structure, wherein the first lightly doped region is located above the first halo implantation region. In one embodiment, the semiconductor device further includes a second dipole portion disposed above the semiconductor substrate and covering the drain region, wherein a material of the first dipole portion is the same as a material of the second dipole portion. In one embodiment, the semiconductor device further includes a drain contact that passes through the second dipole portion to directly contact the drain region.

[0009] In one embodiment, the semiconductor device further includes a second dielectric spacer disposed above the second dipole portion and adjacent to the dielectric layer, wherein the second dielectric spacer is spaced apart from the drain region by the second dipole portion. In one embodiment, the semiconductor device further includes a second lightly doped region disposed in the semiconductor substrate and extending from the drain region to the gate structure, wherein the second lightly doped region is in direct contact with the second dipole portion. In one embodiment, the semiconductor device further includes a second halo implantation region disposed in the semiconductor substrate and extending from the drain region to the gate structure, wherein the second lightly doped region is located above the second halo implantation region.

[0010] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a gate structure disposed above the semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and located on opposite sides of the gate structure. The semiconductor device also includes a first lightly doped region disposed in the semiconductor substrate and extending from the source region to the gate structure; and a first dipole portion disposed above the semiconductor substrate and covering the source region and the first lightly doped region. The semiconductor device further includes a first dielectric spacer covering the first dipole portion.

[0011] In one embodiment, the first dipole portion is in direct contact with the source region and the first dielectric spacer. In one embodiment, the first lightly doped region is in direct contact with the first dipole portion. In one embodiment, the semiconductor device further includes a source contact extending through the first dipole portion to directly contact the source region, wherein the source contact is spaced apart from the first dielectric spacer. In one embodiment, the semiconductor device further includes a first halo implantation region disposed below the first lightly doped region, wherein the first lightly doped region and the first halo implantation region have different conductivity types.

[0012] In one embodiment, the semiconductor device further includes a second dielectric spacer covering and directly contacting the drain region, wherein the first dielectric spacer is spaced from the source region by the first dipole portion. In one embodiment, the first lightly doped region is spaced from the first dielectric spacer by the first dipole portion. In one embodiment, in cross-sectional view, the first dipole portion is L-shaped. In one embodiment, the semiconductor device further includes a first dielectric layer covering the gate structure, wherein the first dielectric spacer is spaced from the gate structure by the first dielectric layer. In one embodiment, the first dipole portion is in direct contact with the first dielectric layer.

[0013] In one embodiment, the semiconductor device further includes a second dielectric layer covering the first dipole portion, the first dielectric spacer, and the first dielectric layer. In another embodiment, the semiconductor device further includes a second lightly doped region disposed in the semiconductor substrate and extending from the drain region to the gate structure. Furthermore, the semiconductor device includes a second dipole portion disposed above the semiconductor substrate and covering the drain region and the second lightly doped region, wherein the drain region is spaced from the second dielectric layer by the second dipole portion. In one embodiment, a material of the first dipole portion is the same as a material of the second dipole portion. In one embodiment, the drain region is covered by the second dielectric layer and is in direct contact with the second dielectric layer.

[0014] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a gate structure over a semiconductor substrate; and forming a first dielectric layer to cover the gate structure. The method further includes depositing a dipole layer over the semiconductor substrate and the first dielectric layer; and performing an etching process on the dipole layer to form a first dipole portion. The method also includes forming a first dielectric spacer over the first dipole portion; and after forming the first dielectric spacer, forming a source region and a drain region in the semiconductor substrate and on opposite sides of the gate structure. The source region is covered by the first dipole portion.

[0015] In one embodiment, before depositing the dipole layer, an upper surface and sidewalls of the gate structure are covered by the first dielectric layer. In one embodiment, the fabrication method further includes performing an etching process on the dipole layer to form a second dipole portion; and forming a second dielectric spacer above the second dipole portion, wherein the drain region is formed after the formation of the second dielectric spacer, and the drain region is covered by the second dipole portion. In one embodiment, the first dipole portion and the second dipole portion are spaced apart, and in cross-sectional view, the first dipole portion and the second dipole portion are L-shaped. In one embodiment, the fabrication method further includes forming a second dielectric layer to cover the first dipole portion, the first dielectric spacer, and the first dielectric layer; and forming a source contact that penetrates the second dielectric layer and the first dipole portion to directly contact the source region. In one embodiment, the source region and the second dielectric layer are spaced apart by the first dipole portion.

[0016] In one embodiment, the drain region is in direct contact with the second dielectric layer. In one embodiment, the first dipole portion is in direct contact with the first dielectric layer. In one embodiment, the fabrication method further includes forming a first lightly doped region and a second lightly doped region in the semiconductor substrate before depositing the dipole layer, wherein the source region penetrates the first lightly doped region and the drain region penetrates the second lightly doped region.

[0017] In one embodiment, prior to performing the etching process, the first lightly doped region and the second lightly doped region are covered by the dipole layer and the first dielectric layer. In another embodiment, the fabrication method further includes forming a first halo implantation region below the first lightly doped region and forming a second halo implantation region below the second lightly doped region before depositing the dipole layer. In one embodiment, the first halo implantation region and the first lightly doped region have different conductivity types, wherein the second halo implantation region and the second lightly doped region have different conductivity types.

[0018] This disclosure provides an embodiment of a semiconductor device having a dipole portion and a method for fabricating the same. In some embodiments, the semiconductor device includes a gate structure disposed above a semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and located on opposite sides of the gate structure; and a dipole portion disposed above the semiconductor substrate and covering the source region. Depending on the conductivity type of the semiconductor device, the dipole portion is used to increase the on-state current and / or suppress the off-state leakage current. Furthermore, it can reduce the parasitic capacitance in a portion of the channel between the gate structure and the dipole portion, thereby improving the operating speed of the semiconductor device. Therefore, the performance of the semiconductor device can be improved.

[0019] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0020] When referring to the drawings in conjunction with the embodiments and the scope of the patent application, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements. Figure 1 is a cross-sectional schematic diagram illustrating a semiconductor element according to some embodiments of the present disclosure. Figure 2 is a cross-sectional schematic diagram illustrating a semiconductor element according to some other embodiments of the present disclosure. Figure 3 is a flowchart illustrating a method for fabricating a semiconductor element according to some embodiments of this disclosure. Figure 4 is a flowchart illustrating a method for fabricating a semiconductor element according to some other embodiments of this disclosure. Figure 5 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a gate structure over a semiconductor substrate during the formation of a semiconductor device, according to some embodiments of the present disclosure. Figure 6 is a cross-sectional schematic diagram illustrating an intermediate stage in which a first dielectric layer and a patterned mask are sequentially formed over a gate structure during the formation of a semiconductor device, according to some embodiments of the present disclosure. Figure 7 is a cross-sectional schematic diagram illustrating an intermediate stage in the etching of a first dielectric layer during semiconductor device formation, according to some embodiments of the present disclosure. Figure 8 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a first lightly doped region, a second lightly doped region, a first halo implantation region, and a second halo implantation region in a semiconductor substrate during the formation of a semiconductor device, according to some embodiments of the present disclosure. Figure 9 is a cross-sectional schematic diagram illustrating the intermediate stage of depositing a dipole layer over a semiconductor substrate and a first dielectric layer during semiconductor device formation according to some embodiments of the present disclosure. Figure 10 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a patterned mask over a dipole layer during semiconductor device formation, according to some embodiments of the present disclosure. Figure 11 is a cross-sectional schematic diagram illustrating an intermediate stage in the etching of a dipole layer during semiconductor device formation to form a first dipole portion and a second dipole portion, according to some embodiments of the present disclosure. Figure 12 is a cross-sectional schematic diagram illustrating an intermediate stage of removing a patterned mask during semiconductor device formation according to some embodiments of the present disclosure. Figure 13 is a cross-sectional schematic diagram illustrating the intermediate stage of forming a spacer sublayer over the first dipole portion, the second dipole portion, and the first dielectric layer during the formation of a semiconductor device according to some embodiments of the present disclosure. Figure 14 is a cross-sectional schematic diagram illustrating the intermediate stages of forming a first dielectric spacer, a second dielectric spacer, a source region, and a drain region during the formation of a semiconductor device according to some embodiments of the present disclosure. Figure 15 is a cross-sectional schematic diagram illustrating an intermediate stage in which a second dielectric layer is formed during the formation of a semiconductor device, according to some embodiments of the present disclosure, to cover the first dipole portion, the second dipole portion, the first dielectric spacer, the second dielectric spacer, and the first dielectric layer. Figure 16 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of an interlayer dielectric layer above a second dielectric layer during semiconductor device formation, according to some embodiments of the present disclosure. Figure 17 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of an opening for exposing the source region and an opening for exposing the drain region during the formation of a semiconductor device according to some embodiments of the present disclosure. Figure 18 is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a patterned mask over a dipole layer during semiconductor device formation, according to some embodiments of the present disclosure. Figure 19 is a cross-sectional schematic diagram illustrating an intermediate stage in the etching of a dipole layer to form a first dipole portion during semiconductor device formation according to some embodiments of the present disclosure. Figure 20 is a cross-sectional schematic diagram illustrating the intermediate stages of forming a first dielectric spacer, a second dielectric spacer, a source region, and a drain region during the formation of a semiconductor device according to some embodiments of the present disclosure. Implementation

[0021] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplification and clarity, and unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0022] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0023] FIG1 is a cross-sectional schematic diagram illustrating a semiconductor device 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100 includes a semiconductor substrate 101 and a gate structure 107 disposed above the semiconductor substrate 101. In some embodiments, the gate structure 107 includes a gate dielectric layer 103 and a gate electrode layer 105 disposed above the gate dielectric layer 103.

[0024] In some embodiments, a source region 113a and a drain region 113b are disposed in the semiconductor substrate 101 and located on opposite sides of the gate structure 107. In some embodiments, a lightly doped region 117a (also referred to as a first lightly doped region) and a halo implantation region 115a (also referred to as a first halo implantation region) are disposed in the semiconductor substrate 101 and extend from the source region 113a to the gate structure 107. In some embodiments, the lightly doped region 117a and the halo implantation region 115a are disposed adjacent to the source region 113a, and the lightly doped region 117a is disposed above the halo implantation region 115a.

[0025] In some embodiments, a lightly doped region 117b (also referred to as a second lightly doped region) and a halo implantation region 115b (also referred to as a second halo implantation region) are disposed in the semiconductor substrate 101 and extend from the drain region 113b to the gate structure 107. In some embodiments, the lightly doped region 117b and the halo implantation region 115b are disposed adjacent to the drain region 113b, and the lightly doped region 117b is disposed above the halo implantation region 115b.

[0026] In some embodiments, source region 113a, drain region 113b, and lightly doped regions 117a and 117b have a first conductivity type, while halo implanted regions 115a and 115b have a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is n-type, and the second conductivity type is p-type. Furthermore, in some embodiments, the doping concentration of source region 113a and the doping concentration of drain region 113b are greater than the doping concentration of lightly doped regions 117a and 117b.

[0027] In some embodiments, the semiconductor element 100 includes dipole portions 121a and 121b disposed above a semiconductor substrate 101. In some embodiments, the source region 113a is covered by the dipole portion 121a, and the drain region 113b is covered by the dipole portion 121b. The dipole portion 121a is also referred to as a first dipole portion, and the dipole portion 121b is also referred to as a second dipole portion.

[0028] In some embodiments, the lightly doped region 117a is partially covered by the dipole portion 121a, and the lightly doped region 117b is partially covered by the dipole portion 121b. In some embodiments, the dipole portion 121a is in direct contact with the source region 113a and the lightly doped region 117a, and the dipole portion 121b is in direct contact with the drain region 113b and the lightly doped region 117b. In some embodiments, a material of the dipole portion 121a is the same as a material of the dipole portion 121b.

[0029] In some embodiments, the semiconductor device 100 includes a dielectric layer 109 covering a gate structure 107, and dielectric spacers 141a and 141b disposed on opposite sides of the gate structure 107. In some embodiments, the upper surface T1 and the sidewalls SW1 and SW2 of the gate structure 107 are covered by the dielectric layer 109. In some embodiments, the dielectric spacers 141a and 141b are spaced apart from the gate structure 107 by the dielectric layer 109. Dielectric spacer 141a is also referred to as a first dielectric spacer of the semiconductor device 100, and dielectric spacer 141b is also referred to as a second dielectric spacer of the semiconductor device 100.

[0030] In some embodiments, dielectric layer 109 is in direct contact with dielectric spacers 141a and 141b. In some embodiments, dielectric spacer 141a is in direct contact with dipole portion 121a, and dielectric spacer 141b is in direct contact with dipole portion 121b. In some embodiments, dipole portion 121a is L-shaped in the cross-sectional view of FIG1 and extends between dielectric spacer 141a and dielectric layer 109. In some embodiments, dipole portion 121b is L-shaped in the cross-sectional view of FIG1 and extends between dielectric spacer 141b and dielectric layer 109.

[0031] In some embodiments, the lightly doped region 117a is partially covered by dielectric spacer 141a, and the lightly doped region 117b is partially covered by dielectric spacer 141b. In some embodiments, the dipole portion 121a is partially covered by dielectric spacer 141a, and the dipole portion 121b is partially covered by dielectric spacer 141b. In some embodiments, the material of the dielectric layer 109 is different from the material of the dielectric spacers 141a and 141b.

[0032] In some embodiments, the lightly doped region 117a is spaced apart from the dielectric spacer 141a by a dipole portion 121a. In some embodiments, the lightly doped region 117b is spaced apart from the dielectric spacer 141b by a dipole portion 121b. In some embodiments, the dielectric spacer 141a is spaced apart from the source region 113a by a dipole portion 121a, and the dielectric spacer 141b is spaced apart from the drain region 113b by a dipole portion 121b. In some embodiments, the dielectric layer 109 is in direct contact with the lightly doped regions 117a and 117b. In some embodiments, the lightly doped regions 117a and 117b extend to contact the gate dielectric layer 103 of the gate structure 107.

[0033] In some embodiments, the semiconductor element 100 includes a dielectric layer 143 covering the dipole portions 121a and 121b, the dielectric spacers 141a and 141b, and the dielectric layer 109. The dielectric layer 109 is also referred to as a first dielectric layer, and the dielectric layer 143 is also referred to as a second dielectric layer. In some embodiments, the dielectric layer 143 is in direct contact with the dipole portions 121a and 121b, the dielectric spacers 141a and 141b, and the dielectric layer 109.

[0034] In some embodiments, the source region 113a is spaced apart from the dielectric layer 143 by the dipole portion 121a, and the drain region 113b is spaced apart from the dielectric layer 143 by the dipole portion 121b. In some embodiments, the dielectric spacer 141a is surrounded by the dipole portion 121a, the dielectric layer 109, and the dielectric layer 143. In some embodiments, the dielectric spacer 141b is surrounded by the dipole portion 121b, the dielectric layer 109, and the dielectric layer 143.

[0035] Referring again to FIG1, according to some embodiments, the semiconductor element 100 includes an interlayer dielectric (ILD) 145 disposed above a dielectric layer 143, a source contact 151a penetrating the interlayer dielectric 145, the dielectric layer 143, and the dipole portion 121a to contact the source region 113a, and a drain contact 151b penetrating the interlayer dielectric 145, the dielectric layer 143, and the dipole portion 121b to contact the drain region 113b. In some embodiments, the source contact 151a is spaced apart from the dielectric spacer 141a, and the drain contact 151b is spaced apart from the dielectric spacer 141b.

[0036] In some embodiments, the semiconductor element 100 is an n-type field-effect transistor (nFET), and the dipole portions 121a and 121b can be positive dipole portions formed of a material inherently containing positive polarity. For example, dipole portions 121a and 121b include yttrium (Y), lanthanum (La), strontium (Sr), yttrium oxide (Y₂O₃), lanthanum oxide (La₂O₃), strontium oxide (SrO), or combinations thereof. In this case, dipole portions 121a and 121b can help increase the on-state current of the nFET.

[0037] In some embodiments, the semiconductor element 100 is a p-type field-effect transistor (pFET), and the dipole portions 121a and 121b can be negative dipole portions formed of a material inherently including a negative polarity. For example, dipole portions 121a and 121b include aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), magnesium (Mg), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), zirconium oxide (ZrO₂), hafnium oxide (HfO₂), magnesium oxide (MgO), or combinations thereof. In this case, dipole portions 121a and 121b can help increase the on-state current of the pFET.

[0038] In some embodiments, the semiconductor element 100 is an nFET, and the dipole portions 121a and 121b can be negative dipole portions formed of a material inherently including a negative polarity. For example, dipole portions 121a and 121b include aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), magnesium (Mg), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), zirconium oxide (ZrO₂), hafnium oxide (HfO₂), magnesium oxide (MgO), or combinations thereof. In this case, dipole portions 121a and 121b can help suppress the off-state leakage current of the nFET. Furthermore, the parasitic capacitance of the portion of the channel between the gate structure 107 and the dipole portions 121a and 121b can be reduced to improve the operating speed of the nFET.

[0039] In some embodiments, the semiconductor element 100 is a pFET, and the dipole portions 121a and 121b can be positive dipole portions formed of a material inherently including positive polarity. For example, dipole portions 121a and 121b include yttrium (Y), lanthanum (La), strontium (Sr), yttrium oxide (Y₂O₃), lanthanum oxide (La₂O₃), strontium oxide (SrO), or combinations thereof. In this case, dipole portions 121a and 121b can help suppress the off-state leakage current of the pFET. Furthermore, the parasitic capacitance of the portion of the channel between the gate structure 107 and the dipole portions 121a and 121b can be reduced to improve the operating speed of the pFET.

[0040] This disclosure provides an embodiment of a semiconductor device 100 having dipole portions 121a and 121b and a method for fabricating the same. In this embodiment, dipole portions 121a and 121b are used to increase the on-state current of the semiconductor device 100 or suppress the off-state leakage current of the semiconductor device 100. Furthermore, the parasitic capacitance of the portion of the channel between the gate structure 107 and the dipole portions 121a and 121b can be reduced to improve the operating speed of the semiconductor device 100. Therefore, the performance of the semiconductor device 100 can be improved.

[0041] Figure 2 is a cross-sectional schematic diagram illustrating a semiconductor device 200 according to some other embodiments of the present disclosure. In some embodiments, the semiconductor device 200 includes a semiconductor substrate 101, a gate structure 107 disposed above the semiconductor substrate 101, and a dielectric layer 109 covering the upper surface T1 and sidewalls SW1, SW2 of the gate structure 107. In some embodiments, the gate structure 107 includes a gate dielectric layer 103 and a gate electrode layer 105. The features of the semiconductor substrate 101, gate structure 107, and dielectric layer 109 in the semiconductor device 200 are the same as or similar to those of the semiconductor substrate 101, gate structure 107, and dielectric layer 109 in the semiconductor device 100, and therefore will not be repeated.

[0042] In some embodiments, source region 113a, drain region 113b, lightly doped regions 117a and 117b, and halo implantation regions 115a and 115b are disposed in the semiconductor substrate 101 of semiconductor device 200. The characteristics of source region 113a, drain region 113b, lightly doped regions 117a and 117b, and halo implantation regions 115a and 115b in semiconductor device 200 are the same as or similar to those of source region 113a, drain region 113b, lightly doped regions 117a and 117b, and halo implantation regions 115a and 115b in semiconductor device 100, and therefore will not be repeated.

[0043] In some embodiments, the semiconductor element 200 includes a dipole portion 221 (also referred to as a first dipole portion in the semiconductor element 200) disposed above the semiconductor substrate 101 and covering the source region 113a. In some embodiments, a lightly doped region 117a is partially covered by the dipole portion 221. In some embodiments, the dipole portion 221 is in direct contact with the source region 113a and the lightly doped region 117a.

[0044] In some embodiments, the semiconductor element 200 includes dielectric spacers 241a and 241b disposed on opposite sides of the gate structure 107, and a dielectric layer 243 covering the dipole portion 221, dielectric spacers 241a and 241b, and dielectric layer 109. In some embodiments, dielectric spacers 241a and 241b are spaced apart from the gate structure 107 by the dielectric layer 109. In some embodiments, the dielectric layer 109 is in direct contact with dielectric spacers 241a and 241b. Dielectric spacer 241a is also referred to as a first dielectric spacer of the semiconductor element 200, and dielectric spacer 241b is also referred to as a second dielectric spacer of the semiconductor element 200.

[0045] In some embodiments, the dielectric spacer 241a is in direct contact with the dipole portion 221. In some embodiments, the dipole portion 221 is L-shaped in the cross-sectional view of FIG2 and extends between the dielectric spacer 241a and the dielectric layer 109. In some embodiments, the lightly doped region 117a is partially covered by the dielectric spacer 241a, and the lightly doped region 117b is partially covered by the dielectric spacer 241b. In some embodiments, the dipole portion 221 is partially covered by the dielectric spacer 241a.

[0046] In some embodiments, the material of dielectric layer 109 is different from the materials of dielectric spacers 241a and 241b. In some embodiments, lightly doped region 117a is spaced apart from dielectric spacer 241a by dipole portion 221. In some embodiments, lightly doped region 117b is in direct contact with dielectric spacer 241b. In some embodiments, dielectric layer 109 is in direct contact with lightly doped regions 117a and 117b. In some embodiments, lightly doped regions 117a and 117b extend to contact gate dielectric layer 103 of gate structure 107.

[0047] In some embodiments, dielectric spacer 241a is spaced apart from source region 113a by dipole portion 221, while dielectric spacer 241b is in direct contact with drain region 113b. Additionally, dielectric layer 109 is also referred to as a first dielectric layer, and dielectric layer 243 is also referred to as a second dielectric layer. In some embodiments, source region 113a is spaced apart from dielectric layer 243 by dipole portion 221, while drain region 113b is covered by dielectric layer 243 and is in direct contact with dielectric layer 243. In some embodiments, dielectric layer 243 is in direct contact with dipole portion 221, dielectric spaces 241a and 241b, and dielectric layer 109. In some embodiments, dielectric spacer 241a is surrounded by dipole portion 221, dielectric layer 109, and dielectric layer 243.

[0048] Referring again to FIG2, according to some embodiments, the semiconductor element 200 includes an interlayer dielectric layer 245 disposed above the dielectric layer 243, a source contact 251a passing through the interlayer dielectric layer 245, the dielectric layer 243 and the dipole portion 221, and a drain contact 251b penetrating the interlayer dielectric layer 245 and the dielectric layer 243 to contact the drain region 113b. In some embodiments, the source contact 251a is spaced apart from the dielectric spacer 241a, and the drain contact 251b is spaced apart from the dielectric spacer 241b.

[0049] In some embodiments, the semiconductor element 100 is an nFET, and the dipole portion 221 can be a positive dipole portion formed of a material inherently containing positive polarity. For example, the dipole portion 221 includes yttrium (Y), lanthanum (La), strontium (Sr), yttrium oxide (Y₂O₃), lanthanum oxide (La₂O₃), strontium oxide (SrO), or combinations thereof. In this case, the dipole portion 221 can help increase the on-state current of the nFET while avoiding an increase in the off-state leakage current.

[0050] In some embodiments, the semiconductor element 200 is a pFET, and the dipole portion 221 can be a negative dipole portion formed of a material inherently including a negative polarity. For example, the dipole portion 221 includes aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), magnesium (Mg), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), zirconium oxide (ZrO₂), hafnium oxide (HfO₂), magnesium oxide (MgO), or combinations thereof. In this case, the dipole portion 221 can help increase the on-state current of the pFET while avoiding an increase in the off-state leakage current.

[0051] This disclosure provides an embodiment of a semiconductor device 200 having a dipole portion 221 and a method for fabricating the same. In this embodiment, the dipole portion 221 is used to increase the on-state current of the semiconductor device 200 and suppress the off-state leakage current. Therefore, the performance of the semiconductor device 200 can be improved.

[0052] Figure 3 is a flowchart illustrating a method 10 for fabricating a semiconductor element 100 according to some embodiments of the present disclosure. Method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, S27, and S29. Figure 4 is a flowchart illustrating a method 30 for fabricating a semiconductor element 200 according to other embodiments of the present disclosure. Method 30 includes steps S31, S33, S35, S37, S39, S41, S43, S45, S47, and S49. Steps S11 to S29 of Figure 3 will be described in detail with reference to Figures 5 to 17.

[0053] Figures 5 to 17 are schematic cross-sectional views illustrating intermediate stages during the formation of a semiconductor element 100 according to some embodiments. As shown in Figure 5, a semiconductor substrate 101 is provided according to some embodiments.

[0054] The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0055] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer located above a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is an insulator-on-semiconductor substrate, which may include a substrate, a buried oxide layer above the substrate, and a semiconductor layer above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The insulator-on-semiconductor substrate can be fabricated using SIMOX, wafer bonding, and / or other suitable methods.

[0056] Referring again to Figure 5, according to some embodiments, a gate structure 107, including a gate dielectric layer 103 and a gate electrode layer 105, is formed on the semiconductor substrate 101. The corresponding steps are shown in step S11 of fabrication method 10 in Figure 3. In some embodiments, the gate electrode layer 105 is formed on the gate dielectric layer 103.

[0057] In some embodiments, the gate dielectric layer 103 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the gate electrode layer 105 includes a conductive material, such as polycrystalline silicon, aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), a metal alloy, other suitable materials, or combinations thereof.

[0058] In some embodiments, forming the gate structure 107 includes sequentially depositing a gate dielectric material (not shown) and a gate electrode material (not shown) over a semiconductor substrate 101, forming a patterned mask (not shown) over the gate electrode material, and using the patterned mask as an etching mask to perform an etching process on the gate electrode material and the gate dielectric material. In some embodiments, the gate dielectric material and the gate electrode material are deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable deposition processes.

[0059] In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. After the gate structure 107 is formed, the patterned mask can be removed. In some embodiments, the patterned mask is removed by a stripping process, an ashing process, an etching process, or other suitable processes.

[0060] Next, according to some embodiments, as shown in FIG6, a dielectric layer 109 is formed covering the semiconductor substrate 101 and the gate structure 107, and a patterned mask 111 is formed over the dielectric layer 109. In some embodiments, the upper surface T1 of the gate structure 107 and the opposite sidewalls SW1, SW2 are covered by the dielectric layer 109. In some embodiments, the upper surface T2 of the semiconductor substrate 101 is covered by the dielectric layer 109.

[0061] In some embodiments, a patterned mask 111 is disposed above the gate structure 107 and spaced apart from the gate structure 107 by a dielectric layer 109. In some embodiments, the dielectric layer 109 includes silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. In some embodiments, the dielectric layer 109 is fabricated using a deposition process, such as CVD, PVD, ALD, spin coating, or other suitable deposition processes.

[0062] Subsequently, according to some embodiments, as shown in FIG7, a patterned mask 111 is used as an etching mask to perform an etching process on the dielectric layer 109. In some embodiments, after the etching process is completed, the upper surface T2 of the semiconductor substrate 101 is exposed, while the upper surface T1 of the gate structure 107 and the opposite sidewalls SW1, SW2 are still covered by the remaining portion of the dielectric layer 109. The corresponding steps are shown in step S13 of fabrication method 10 as shown in FIG3.

[0063] In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. After the etching process is performed, the patterned mask 111 can be removed. In some embodiments, the patterned mask 111 is removed by a stripping process, an ashing process, an etching process, or other suitable processes.

[0064] Then, according to some embodiments, lightly doped regions 117a and 117b and halo implantation regions 115a and 115b are formed in the semiconductor substrate 101, as shown in FIG8. In some embodiments, the lightly doped region 117a and the halo implantation region 115a are located on one side of the gate structure 107, and the lightly doped region 117b and the halo implantation region 115b are located on the other side of the gate structure 107. The corresponding steps are shown in step S15 of the fabrication method 10 shown in FIG3.

[0065] In some embodiments, the halo implantation region 115a is located below the lightly doped region 117a. In some embodiments, the halo implantation region 115b is located below the lightly doped region 117b. In some embodiments, the lightly doped regions 117a and 117b extend to directly contact the dielectric layer 109. In some embodiments, the lightly doped regions 117a and 117b also extend to directly contact the gate dielectric layer 103 of the gate structure 107. In some embodiments, the halo implantation regions 115a and 115b extend directly below the dielectric layer 109.

[0066] In some embodiments, the lightly doped regions 117a and 117b and the halo implantation regions 115a and 115b are formed by an ion implantation process using a dielectric layer 109 as an ion implantation mask. In some embodiments, the ion implantation process involves applying tilted ion implantation with a tilt angle to the semiconductor substrate 101.

[0067] As described above, according to some embodiments, the lightly doped regions 117a and 117b have a first conductivity type, while the halo implantation regions 115a and 115b have a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is n-type, and the second conductivity type is p-type.

[0068] Next, according to some embodiments, as shown in FIG9, a dipole layer 121 is deposited over the semiconductor substrate 101 and the dielectric layer 109. The corresponding steps are shown in step S17 of fabrication method 10 shown in FIG3. In some embodiments, the lightly doped region 117a, halo implantation region 115a, lightly doped region 117b, and halo implantation region 115b are covered by the dipole layer 121. In some embodiments, the lightly doped regions 117a and 117b are covered by the dipole layer 121 and are in direct contact with the dipole layer 121.

[0069] In some embodiments, the dipole layer 121 comprises a material inherently having positive or negative polarity, depending on the design requirements of the semiconductor device 100. In some embodiments, the dipole layer 121 comprises aluminum (Al), titanium (Ti), zirconium (Zr), hafnium (Hf), magnesium (Mg), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), zirconium oxide (ZrO₂), europium oxide (HfO₂), magnesium oxide (MgO), yttrium (Y), lanthanum (La), strontium (Sr), yttrium oxide (Y₂O₃), lanthanum oxide (La₂O₃), strontium oxide (SrO), or combinations thereof. In some embodiments, the fabrication technique of the dipole layer 121 includes a deposition process, such as CVD, PVD, ALD, spin-coating, or other suitable deposition processes.

[0070] Subsequently, according to some embodiments, as shown in FIG10, a patterned mask having patterns 131a and 131b is formed over the dipole layer 121. In some embodiments, pattern 131a is disposed over the lightly doped region 117a and spaced apart from the lightly doped region 117a by the dipole layer 121, and pattern 131b is disposed over the lightly doped region 117b and spaced apart from the lightly doped region 117b by the dipole layer 121.

[0071] Then, according to some embodiments, as shown in FIG11, an etching process is performed on the dipole layer 121 using a patterned mask having patterns 131a and 131b as an etching mask. In some embodiments, the etching process removes a portion of the dipole layer 121 covering the dielectric layer 109 to form a dipole portion 121a covering the lightly doped region 117a and a dipole portion 121b covering the lightly doped region 117b. In some embodiments, the etching process removes a portion of the dipole layer 121 located above the upper surface T3 of the patterned mask pattern 131a and a portion of the dipole layer 121 located above the upper surface T4 of the patterned mask pattern 131b. The corresponding steps are shown in step S19 of fabrication method 10 shown in FIG3.

[0072] In some embodiments, after the etching process, the pattern 131a of the patterned mask is spaced apart from the dielectric layer 109 by dipole portions 121a, which, in cross-sectional view, are L-shaped. In some embodiments, after the etching process, the pattern 131b of the patterned mask is spaced apart from the dielectric layer 109 by dipole portions 121b, which, in cross-sectional view, are L-shaped. In some embodiments, dipole portions 121a and 121b are located on opposite sides of the gate structure 107. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0073] Next, as shown in FIG12, according to some embodiments, patterns 131a and 131b of the patterned mask are removed. In some embodiments, patterns 131a and 131b are removed by stripping, ashing, etching or other suitable processes. According to some embodiments, after removing patterns 131a and 131b, a portion of the dipole portion 121a sandwiched between pattern 131a and lightly doped region 117a is exposed, and a portion of the dipole portion 121b sandwiched between pattern 131b and lightly doped region 117b is exposed.

[0074] Subsequently, according to some embodiments, as shown in FIG13, a spacer sublayer 141 is formed covering the dipole portions 121a, 121b and the dielectric layer 109. In some embodiments, a lightly doped region 117a is spaced apart from the spacer sublayer 141 by means of the dipole portion 121a. In some embodiments, a lightly doped region 117b is spaced apart from the spacer sublayer 141 by means of the dipole portion 121b. In some embodiments, the spacer sublayer 141 is in direct contact with the dipole portion 121a, the dielectric layer 109 and the dipole portion 121b.

[0075] In some embodiments, the spacer layer 141 includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. In some embodiments, the spacer layer 141 and the dielectric layer 109 include different materials, such that the etching selectivity may differ in subsequent etching processes. In some embodiments, the fabrication technique of the spacer layer 141 includes a deposition process, such as CVD, PVD, ALD, spin coating, or other suitable deposition processes.

[0076] Then, according to some embodiments, as shown in FIG14, an etching process is performed on the spacer layer 141 to form dielectric spacer layers 141a and 141b on opposite sides of the gate structure 107. In some embodiments, dielectric spacer 141a is formed above dipole portion 121a and in direct contact with dielectric layer 109, and dielectric spacer 141b is formed above dipole portion 121b and in direct contact with dielectric layer 109. In some embodiments, dipole portion 121a is partially covered by dielectric spacer 141a, and dipole portion 121b is partially covered by dielectric spacer 141b. The corresponding steps are shown in step S21 of fabrication method 10 shown in FIG3. In some embodiments, the etching process is an isotropic etching process.

[0077] Furthermore, according to some embodiments, as shown in FIG14, a source region 113a and a drain region 113b are formed in the semiconductor substrate 101. The corresponding steps are shown in step S23 of fabrication method 10 shown in FIG3. In some embodiments, the source region 113a and the drain region 113b are located on opposite sides of the gate structure 107. In some embodiments, the source region 113a is formed through the lightly doped region 117a and the halo implantation region 115a, and the drain region 113b is formed through the lightly doped region 117b and the halo implantation region 115b.

[0078] In some embodiments, the lightly doped region 117a and the halo implantation region 115a are located between the source region 113a and the gate structure 107, and the lightly doped region 117b and the halo implantation region 115b are located between the drain region 113b and the gate structure 107. In some embodiments, the source region 113a and the drain region 113b are formed by an ion implantation process using dielectric spacers 141a, 141b and dielectric layer 109 as an ion implantation mask. In some embodiments, the ion implantation process is a tilted ion implantation applied to the semiconductor substrate 101 at a tilt angle.

[0079] As described above, according to some embodiments, the source region 113a, drain region 113b, and lightly doped regions 117a and 117b have a first conductivity type, while the halo implanted regions 115a and 115b have a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is n-type, and the second conductivity type is p-type. Furthermore, according to some embodiments, the doping concentration of the source region 113a and drain region 113b is greater than the doping concentration of the lightly doped regions 117a and 117b.

[0080] Next, according to some embodiments, as shown in FIG15, a dielectric layer 143 is formed covering the dipole portions 121a and 121b, the dielectric spacers 141a and 141b, and the dielectric layer 109. The corresponding steps are shown in step S25 of the fabrication method 10 shown in FIG3. The materials and processes used to form the dielectric layer 143 are similar to or the same as those used to form the dielectric layer 109, and will not be described again here.

[0081] Subsequently, according to some embodiments, as shown in FIG16, an interlayer dielectric layer 145 covering the dielectric layer 143 is formed. The corresponding steps are shown in step S27 of fabrication method 10 in FIG3. In some embodiments, the interlayer dielectric layer 145 includes a dielectric layer, such as an oxide formed of silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), undoped silicate glass, doped silicon oxide (e.g., phosphosilate glass (PSG), borosilicate glass (BPSG), borosilicate glass (BSG)), a low-k dielectric material, other suitable dielectric materials, or combinations thereof. The fabrication technique of the interlayer dielectric layer 145 may include a deposition process, such as CVD, PVD, ALD, spin-coating, or other suitable deposition processes.

[0082] Then, according to some embodiments, as shown in FIG17, an opening 148a is formed penetrating the interlayer dielectric layer 145, dielectric layer 143, and dipole portion 121a to expose the source region 113a, and an opening 148b is formed penetrating the interlayer dielectric layer 145, dielectric layer 143, and dipole portion 121b to expose the drain region 113b. In some embodiments, forming openings 148a and 148b includes forming a patterned mask (not shown) over the interlayer dielectric layer 145 and using the patterned mask as an etching mask to perform an etching process. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. After forming openings 148a and 148b, the patterned mask can be removed.

[0083] Next, according to some embodiments, as shown in FIG1, a source contact 151a and a drain contact 151b are formed in openings 148a and 148b, respectively. In some embodiments, the source contact 151a is electrically connected to the source region 113a, and the drain contact 151b is electrically connected to the drain region 113b. In some embodiments, the source contact 151a is in direct contact with the source region 113a, and the drain contact 151b is in direct contact with the drain region 113b. The corresponding steps are shown in step S29 of the fabrication method 10 shown in FIG3.

[0084] In some embodiments, the source contact 151a and drain contact 151b comprise aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable conductive materials. In some embodiments, the fabrication techniques for the source contact 151a and drain contact 151b include a deposition process and a planarization process. The deposition process may include CVD, PVD, ALD, electroplating, or other suitable deposition processes. The planarization process may include a chemical mechanical polishing (CMP) process. After forming the source contact 151a and drain contact 151b, a semiconductor device 100 is obtained.

[0085] Figures 18 to 20 are cross-sectional schematic diagrams illustrating intermediate stages during the formation of semiconductor element 200 according to some embodiments. It should be understood that the operations preceding the structure shown in Figure 18 are substantially the same as those shown in Figures 5 to 9; detailed descriptions of these operations can be found in the preceding paragraphs and will not be repeated here. Steps S31, S33, S35, and S37 in fabrication method 30 shown in Figure 4 are substantially the same as steps S11, S13, S15, and S17 in fabrication method 10 shown in Figure 3.

[0086] After the dipole layer 121 is formed, according to some embodiments, as shown in FIG18, a patterned mask 231 is formed over the dipole layer 121. In some embodiments, the patterned mask 231 is disposed over the lightly doped region 117a and spaced apart from the lightly doped region 117a by the dipole layer 121.

[0087] Next, according to some embodiments, as shown in FIG19, an etching process is performed on the dipole layer 121 using a patterned mask 231 as an etching mask. In some embodiments, the etching process removes a portion of the dipole layer 121 covering the dielectric layer 109, thereby forming a dipole portion 221 covering the lightly doped region 117a. In some embodiments, the etching process removes a portion of the dipole layer 121 located above the upper surface T3 (see FIG18) of the patterned mask 231 and a portion of the dipole portion 221 located above the lightly doped region 117b. The corresponding steps are shown in step S39 of the fabrication method 30 shown in FIG4.

[0088] In some embodiments, after an etching process is performed, the patterned mask 231 is spaced apart from the dielectric layer 109 by the remaining portion of the dipole layer 121 (e.g., the dipole portion 221). In some embodiments, the dipole portion 221 is L-shaped in cross-sectional view. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. After the dipole portion 221 is obtained, the patterned mask 231 can be removed. In some embodiments, the patterned mask 231 is removed by a stripping process, an ashing process, an etching process, or other suitable processes.

[0089] Subsequently, according to some embodiments, as shown in FIG20, dielectric spacers 241a and 241b are formed on opposite sides of the gate structure 107. In some embodiments, dielectric spacer 241a is formed above the dipole portion 221 and in direct contact with the dielectric layer 109, while dielectric spacer 241b is formed above the lightly doped region 117b and in direct contact with the dielectric layer 109. The corresponding steps are shown in step S41 of the fabrication method 30 shown in FIG4. The materials and processes used to form dielectric spacers 241a and 241b of the semiconductor element 200 are similar to or the same as those used to form dielectric spacers 141a and 141b of the semiconductor element 100, and will not be described again here.

[0090] Furthermore, according to some embodiments, as shown in FIG20, a source region 113a and a drain region 113b are formed in the semiconductor substrate 101. The corresponding steps are shown in step S43 of the fabrication method 30 shown in FIG4. In some embodiments, the source region 113a and the drain region 113b are located on opposite sides of the gate structure 107. In some embodiments, the source region 113a is formed to penetrate the lightly doped region 117a and the halo implantation region 115a, and the drain region 113b is formed to penetrate the lightly doped region 117b and the halo implantation region 115b. The materials and processes for forming the source region 113a and the drain region 113b of the semiconductor device 200 are similar to or the same as those for forming the source region 113a and the drain region 113b of the semiconductor device 100, and the details are not repeated here.

[0091] Then, according to some embodiments, as shown in FIG2, a dielectric layer 243 is formed covering the dipole portion 221, dielectric spacers 241a and 241b, and dielectric layer 109; an interlayer dielectric layer 245 is formed covering the dielectric layer 243; and a source contact 251a and a drain contact 251b are formed in the interlayer dielectric layer 245. In some embodiments, the source contact 251a penetrates the interlayer dielectric layer 245, the dielectric layer 243, and the dipole portion 221. In some embodiments, the drain contact 251b penetrates the interlayer dielectric layer 245 and the dielectric layer 243. Some materials and processes used to form the dielectric layer 243 and the interlayer dielectric layer 245 of the semiconductor element 200 are similar to or the same as those used to form the dielectric layer 143 and the interlayer dielectric layer 145 of the semiconductor element 100, and will not be described again here.

[0092] In some embodiments, source contact 251a is electrically connected to source region 113a, and drain contact 251b is electrically connected to drain region 113b. In some embodiments, source contact 251a is in direct contact with source region 113a, and drain contact 251b is in direct contact with drain region 113b. The steps are shown in steps S43, S45, and S47 of the fabrication method 30 shown in FIG4.

[0093] Some of the materials and processes used in the source contact 251a and drain contact 251b of semiconductor device 200 are similar to or the same as those used in the source contact 151a and drain contact 151b of semiconductor device 100, and the details will not be repeated here. After forming the source contact 251a and drain contact 251b, semiconductor device 200 is obtained.

[0094] This disclosure provides embodiments of a semiconductor device having one dipole portion (e.g., semiconductor device 200 having dipole portion 221), a semiconductor device having two dipole portions (e.g., semiconductor device 100 having dipole portions 121a and 121b), and a method for fabricating them. The dipole portion is used to increase the on-state current of the semiconductor device and / or suppress the off-state leakage current. Furthermore, the parasitic capacitance of the channel portion between the gate structure (e.g., gate structure 107) and the dipole portion can be reduced to improve the operating speed of the semiconductor device. Therefore, the performance of the semiconductor device can be improved.

[0095] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a gate structure disposed above a semiconductor substrate; and a dielectric layer surrounding the gate structure. The semiconductor device also includes a source region and a drain region disposed in the semiconductor substrate and located on opposite sides of the gate structure. The semiconductor device further includes a first dipole portion disposed above the semiconductor substrate and covering the source region; and a first dielectric spacer disposed above the first dipole portion and adjacent to the dielectric layer.

[0096] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a gate structure disposed above the semiconductor substrate; a source region and a drain region disposed in the semiconductor substrate and located on opposite sides of the gate structure. The semiconductor device also includes a first lightly doped region disposed in the semiconductor substrate and extending from the source region to the gate structure; and a first dipole portion disposed above the semiconductor substrate and covering the source region and the first lightly doped region. The semiconductor device further includes a first dielectric spacer covering the first dipole portion.

[0097] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a gate structure over a semiconductor substrate; and forming a first dielectric layer to cover the gate structure. The method further includes depositing a dipole layer over the semiconductor substrate and the first dielectric layer; and performing an etching process on the dipole layer to form a first dipole portion. The method also includes forming a first dielectric spacer over the first dipole portion; and after forming the first dielectric spacer, forming a source region and a drain region in the semiconductor substrate and on opposite sides of the gate structure. The source region is covered by the first dipole portion.

[0098] The embodiments disclosed herein have several advantageous characteristics. Depending on the conductivity type of the semiconductor device, the dipole portion covering the source region is configured to increase the on-state current of the semiconductor device and / or suppress the off-state leakage current. Furthermore, parasitic capacitance can be reduced to improve the operating speed of the semiconductor device. Therefore, the performance of the semiconductor device can be improved.

[0099] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0100] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0101] 10: Preparation method 30: Preparation method 100: Semiconductor components 101: Semiconductor substrate 103: Gate dielectric layer 105: Gate electrode layer 107: Gate Structure 109: Dielectric layer 111: Patterned Mask 113a: Source region 113b: Drainage Zone 115a: Halo implantation area 115b: Halo implantation area 117a: Lightly doped region 117b: Lightly doped region 121: Dipole layer 121a: Dipole portion 121b: Dipole 131a: Pattern 131b: Pattern 141: Interstitial Sublayer 141a: Dielectric gap 141b: Dielectric gap 143: Dielectric layer 145: Interlayer dielectric layer 148a: Opening 148b: Opening 151a: Source contact 151b: Drain contact 200: Semiconductor components 221: Dipole 231: Patterned Masking 241a: Dielectric gap 241b: Dielectric gap 243: Dielectric layer 245: Interlayer dielectric layer 251a: Source contact 251b: Drain contact S11~S29: Steps S31~S49: Steps [] SW1: Sidewall SW2: Sidewall T1: Upper surface T2: Upper surface T3: Upper surface T4: Upper surface

Claims

1. A semiconductor element, comprising: A gate structure is disposed above a semiconductor substrate; A dielectric layer surrounds the gate structure; A source region and a drain region are disposed in the semiconductor substrate and located on opposite sides of the gate structure; a first dipole portion is disposed above the semiconductor substrate and covers the source region; and a first dielectric spacer is disposed above the first dipole portion and adjacent to the dielectric layer, wherein the first dielectric spacer is spaced apart from the gate structure by the dielectric layer, and the first dipole portion extends between the first dielectric spacer and the dielectric layer.

2. The semiconductor device as claimed in claim 1, wherein an upper surface of the gate structure is covered by the dielectric layer.

3. The semiconductor device as claimed in claim 1, wherein the dielectric layer and the first dielectric spacer comprise different materials.

4. The semiconductor device as claimed in claim 1, wherein the first dielectric spacer is spaced apart from the source region by the first dipole portion.

5. The semiconductor device as claimed in claim 1 further includes a source contact that passes through the first dipole portion to directly contact the source region.

6. The semiconductor device as claimed in claim 1 further includes a first lightly doped region disposed in the semiconductor substrate and extending from the source region to the gate structure.

7. The semiconductor device as claimed in claim 6, wherein the first lightly doped region is in direct contact with the first dipole portion.

8. The semiconductor device as claimed in claim 6, wherein the first lightly doped region is spaced apart from the first dielectric spacer by the first dipole portion.

9. The semiconductor device as claimed in claim 6 further includes a first halo implantation region disposed in the semiconductor substrate and extending from the source region to the gate structure, wherein the first lightly doped region is located above the first halo implantation region.

10. The semiconductor device as claimed in claim 1 further includes a second dipole portion disposed above the semiconductor substrate and covering the drain region, wherein a material of the first dipole portion is the same as a material of the second dipole portion.

11. The semiconductor device as claimed in claim 10 further includes a drain contact that passes through the second dipole portion to directly contact the drain region.

12. The semiconductor device as claimed in claim 10 further includes a second dielectric spacer disposed above the second dipole portion and adjacent to the dielectric layer, wherein the second dielectric spacer is spaced apart from the drain region by the second dipole portion.

13. The semiconductor device as claimed in claim 10 further includes a second lightly doped region disposed in the semiconductor substrate and extending from the drain region to the gate structure, wherein the second lightly doped region is in direct contact with the second dipole portion.

14. The semiconductor device as claimed in claim 13 further includes a second halo implantation region disposed in the semiconductor substrate and extending from the drain region to the gate structure, wherein the second lightly doped region is located above the second halo implantation region.

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