Control circuit and method for reducing reverse recovery charge in switching power converter

Abstract

A control circuit for reducing reverse recovery charge in a switching converter includes: a first control signal for switching a first transistor; a second control signal for switching a second transistor; and an auxiliary control signal for switching an auxiliary transistor; wherein a first terminal and a second terminal of the first transistor are coupled in parallel to the first terminal and the second terminal of the auxiliary transistor. The first transistor and the second transistor are jointly coupled to a switching node for periodically switching an inductor to convert an input voltage into an output voltage. There is a delay between the time when the auxiliary control signal becomes disabled and the time when the first control signal becomes disabled. The auxiliary control signal becomes disabled only after the second control signal becomes enabled.

Description

[Technical Field]

[0001] This invention relates to a control circuit, and more particularly to a control circuit for reducing reverse recovery charge in a switching converter. This invention also relates to a control method for reducing reverse recovery charge in a switching converter. [Previous Technology]

[0002] Figure 1 shows a prior art switching converter. As shown in Figure 1, when the upper bridge transistor 42 is turned on according to the relevant signal of the control signal SH, the inductor 30 charges the output capacitor 81 through the switching node LX, thereby generating an output voltage VO. When the upper bridge transistor 42 is turned off, the lower bridge transistor 41 is turned on according to the relevant signal of the control signal SL, so that the current of the inductor 30 flows through the lower bridge transistor 41.

[0003] During the idle time before the start of the next switching cycle, both the upper bridge transistor 42 and the lower bridge transistor 41 are off, causing the current in the inductor 30 to flow through the body diode 43 inside the lower bridge transistor 41. When the next switching cycle begins, the upper bridge transistor 42 turns on, which will apply a rapidly switching reverse voltage to the body diode 43. The process of the body diode 43 switching from forward conduction during the idle time to non-conduction will require a large amount of reverse recovery charge, which, together with the parasitic inductance, will cause a voltage spike on the switching voltage at the switching node LX. This voltage spike may exceed the rated voltage values ​​of the lower bridge transistor 41 and the upper bridge transistor 42 or other components, causing reliability problems or even damage to the components.

[0004] The prior art switching converter 1001 uses a filter circuit composed of capacitor 81 and resistor 82 to suppress voltage spikes on the switching node LX. However, while suppressing the voltage spikes, resistor 82 also causes power loss. In addition, parasitic inductance 91 may also make the suppression effect of the filter circuit poor.

[0005] In view of the above, and to overcome the shortcomings of the prior art, the present invention proposes a control circuit for reducing reverse recovery charge in a switching converter. The present invention uses a first transistor (lower bridge transistor) connected in parallel with an auxiliary transistor and an auxiliary control signal. When the first control signal controlling the first transistor is disabled, the auxiliary transistor remains on (before being turned off after a delay time), allowing the inductor current to flow through the auxiliary transistor, thereby avoiding or reducing the accumulation of reverse recovery charge. The auxiliary transistor is turned off only after the second transistor (upper bridge transistor) is enabled, thereby avoiding or reducing voltage spikes caused by reverse recovery charge. The switching converter of the present invention can also adaptively adjust the delay time to further reduce losses. [Summary of the Invention]

[0006] In one viewpoint, the present invention provides a control circuit for reducing the reverse recovery charge in a switching converter, comprising: a first control signal for switching a first transistor; a second control signal for switching a second transistor; and an auxiliary control signal for switching an auxiliary transistor; wherein a first terminal and a second terminal of the first transistor are coupled in parallel to the first terminal and the second terminal of the auxiliary transistor; wherein the first transistor and the second transistor are coupled together to a switching node for periodically switching an inductor to convert an input voltage into an output voltage; wherein there is a delay time between the time when the auxiliary control signal becomes disabled and the time when the first control signal becomes disabled, and the auxiliary control signal becomes disabled only after the second control signal becomes enabled.

[0007] In a preferred embodiment, the first transistor, the second transistor, and the auxiliary transistor are integrated into a chip.

[0008] In a preferred embodiment, the control circuit further includes: a delay circuit for delaying the first control signal to generate the auxiliary control signal having the delay time.

[0009] In a preferred embodiment, the delay time is determined based on a delay resistor.

[0010] In a preferred embodiment, the first transistor and the auxiliary transistor are located on the same substrate, wherein the first transistor and the auxiliary transistor respectively correspond to a portion and another portion of a transistor array on the substrate.

[0011] In a preferred embodiment, the on-resistance value of the auxiliary transistor is at least 5 times greater than the on-resistance value of the first transistor.

[0012] In a preferred embodiment, the control circuit further includes: a non-overlapping circuit for generating a dead-time between the first control signal and the second control signal, wherein both the first control signal and the second control signal are disabled during the dead-time.

[0013] In a preferred embodiment, the first transistor, the second transistor and the inductor are configured as a synchronous buck converter, a synchronous boost converter or a buck-boost converter.

[0014] In a preferred embodiment, the on-resistance value of the auxiliary transistor is less than an upper limit of the resistance value, so as to prevent the body diode of the first transistor from being turned on.

[0015] In a preferred embodiment, the on-resistance value of the auxiliary transistor is greater than a lower limit of the resistance value, so that the current flowing through the auxiliary transistor is less than a preset current value.

[0016] In a preferred embodiment, the on-resistance value of the auxiliary transistor is inversely related to the reverse recovery charge value of one of the body diodes of the first transistor.

[0017] In a preferred embodiment, the auxiliary control signal is switched to disabled only after the second control signal is switched to enabled, thereby avoiding or reducing the effect of reverse recovery charge of the body diode of the first transistor.

[0018] In a preferred embodiment, the switching time of a switching voltage at the switching node is shortened by avoiding or reducing the reverse recovery charge of the body diode.

[0019] In a preferred embodiment, the switching voltage changes in response to the second control signal being enabled, wherein when the switching voltage exceeds a preset threshold, the auxiliary control signal is disabled.

[0020] In a preferred embodiment, the delay circuit further includes a control transistor for switching when the switching voltage exceeds the preset threshold, so as to disable the auxiliary control signal.

[0021] In a preferred embodiment, the control transistor is coupled to one of the control terminals of the auxiliary transistor, the control transistor is controlled by the switching voltage, and the preset threshold corresponds to the turn-on threshold voltage of the control transistor.

[0022] In a preferred embodiment, the delay circuit further includes a voltage clamping transistor coupled between the control transistor and the switching voltage to clamp the voltage at a control terminal of the control transistor so that it does not exceed a clamping voltage.

[0023] From another perspective, the present invention provides a control method for reducing reverse recovery charge in a switching converter, comprising: generating a first control signal to switch a first transistor; generating a second control signal to switch a second transistor; generating an auxiliary control signal to switch an auxiliary transistor; wherein a first terminal and a second terminal of the first transistor are coupled in parallel to the first terminal and the second terminal of the auxiliary transistor; periodically switching an inductor according to the first control signal and the second control signal to convert an input voltage into an output voltage; and controlling a delay time between the time when the auxiliary control signal is disabled and the time when the first control signal is disabled, and controlling the auxiliary control signal to be disabled only after the second control signal is enabled.

[0024] The following detailed description of specific embodiments will make it easier to understand the purpose, technical content, features and effects of the present invention.

Implementation Method

[0035] The drawings in this invention are all schematic and are mainly intended to illustrate the coupling relationships between circuits and the relationships between signal waveforms. The circuits, signal waveforms, and frequencies are not drawn to scale. For clarity, many practical details will be described in the following description, but this is not intended to limit the scope of the patent application of this invention.

[0036] Figure 2 shows a schematic diagram of a switching converter according to one embodiment of the present invention. In one embodiment, the control circuit 202 of the present invention is used to reduce the reverse recovery charge in the switching converter 2002. Specifically, the reverse recovery charge refers to the reverse recovery charge of the body diode 15 of the first transistor 10, the details of which are described below. In one embodiment, the control circuit 202 includes: a first control signal S10, a second control signal S20, and an auxiliary control signal S11.

[0037] In one embodiment, a first control signal S10 is used to switch the first transistor 10, a second control signal S20 is used to switch the second transistor 20, and an auxiliary control signal S11 is used to switch the auxiliary transistor 11. In one embodiment, the first and second terminals of the first transistor 10 are connected in parallel to the first and second terminals of the auxiliary transistor 11. Specifically, in this embodiment, the drain and source of the first transistor 10 are connected in parallel to the drain and source of the auxiliary transistor 11. In one embodiment, the first transistor 10 and the second transistor 20 are jointly coupled to the switching node SW to periodically switch the inductor 30 to convert the input voltage VIN into the output voltage VO. In one embodiment, the first transistor 10, the second transistor 20, and the auxiliary transistor 11 are integrated into a single chip. In this embodiment, the first transistor 10, the second transistor 20, and the auxiliary transistor 11 are all NMOS transistors.

[0038] In this embodiment, as shown in FIG2, the power stage circuit in the switching converter 2002 includes a first transistor 10, a second transistor 20, and an inductor 30, configured as a synchronous buck converter. The first transistor 10 is configured as the lower bridge transistor, and the second transistor 20 is configured as the upper bridge transistor. It should be noted that the following embodiment will be described using a synchronous buck converter as an example of the power stage circuit configuration, but this is not intended to limit the scope of the present invention. In other embodiments, the power stage circuit may also be configured with other topologies.

[0039] Figure 3 shows the operation waveform diagram of the control circuit in one embodiment of the present invention. In one embodiment, there is a delay time Td between the time point when the auxiliary control signal S11 turns off (time point t3 in Figure 3) and the time point when the first control signal S10 turns off (time point t1 in Figure 3). In one embodiment, the auxiliary control signal S11 turns off after the second control signal S20 turns on (time point t2 in Figure 3). In one embodiment, there is a dead-time Ta between the first control signal S10 and the second control signal S20, during which both the first control signal S10 and the second control signal S20 are off.

[0040] Please refer to Figures 2 and 3 simultaneously. In one embodiment, to avoid the accumulation of excessive reverse recovery charge in the main diode 15 during forward conduction, the auxiliary transistor 11 remains on during the idle time Ta and at the time (t2) when the second control signal S20 is enabled, and is disabled only at an appropriate time, so as to effectively reduce the reverse recovery charge and suppress the voltage spike on the switching node SW.

[0041] It should be noted that in the prior art, when the body diode 15 of the first transistor 10 is forward-conducting during the idle time Ta, a large amount of reverse recovery charge will accumulate. When the second control signal S20 is enabled at time t2 when the idle time Ta ends, the body diode 15 needs to be cleared (or recombined) to switch the diode to reverse-off state. This process causes a voltage spike in the switching voltage VSW on the switching node SW. The present invention can avoid the body diode 15 from conducting or reduce the forward conduction current of the body diode 15 by enabling the auxiliary control signal S11. Therefore, by enabling the second control signal S20 and then disabling the auxiliary control signal S11, the effect of the reverse recovery charge of the body diode 15 of the first transistor 10 can be avoided or reduced, thereby avoiding or reducing the voltage spike in the switching voltage VSW on the switching node SW caused by the reverse recovery charge value of the body diode 15.

[0042] It should also be noted that, in one embodiment, the first transistor 10 and the auxiliary transistor 11 are located on the same substrate, and the first transistor 10 and the auxiliary transistor 11 respectively correspond to a part and another part of a transistor array on the substrate. Thereby, the body diode 15 of the first transistor 10 is also the body diode of the auxiliary transistor 11.

[0043] Figure 4 shows a circuit block diagram of a switching converter according to one embodiment of the present invention. The switching converter 2004 in Figure 4 is an embodiment of the switching converter 2002 in Figure 2. In one embodiment, the control circuit 204 in the switching converter 2004 further includes a delay circuit 500 and a non-overlapping circuit 600. In one embodiment, the non-overlapping circuit 600 generates a first control signal S10 and a second control signal S20 according to the control signal SH and the control signal SL, and uses them to control a lag time Ta between the first control signal S10 and the second control signal S20. In one embodiment, the delay circuit 500 is used to delay the first control signal S10 to generate an auxiliary control signal S11 with a delay time Td. For other details not described, please refer to the descriptions of Figures 2 and 3.

[0044] Figure 5 shows a circuit block diagram of a switching converter according to another embodiment of the present invention. The switching converter 2005 in Figure 5 is another embodiment of the switching converter 2002 in Figure 2. The switching converter 2005 in Figure 5 is similar to the switching converter 2004 in Figure 4, except that the delay circuit 500 in Figure 5 is more coupled to the switching node SW, thereby adaptively adjusting the delay time Td according to the switching voltage VSW on the switching node SW. For other details not described, please refer to the descriptions of Figures 2, 3 and 4.

[0045] Figure 6 shows a schematic diagram of a switching converter in one specific embodiment of the present invention. The switching converter 2006 of Figure 6 corresponds to a specific embodiment of the switching converter 2004 of Figure 4. In the embodiment of Figure 6, the control circuit 206 in the switching converter 2006 includes a first control signal S10, a second control signal S20, an auxiliary control signal S11, a delay circuit 510, and a non-overlapping circuit 600. In one embodiment, the non-overlapping circuit 600 includes logic gates (e.g., gates 61 and 65) and inverters (e.g., inverters 63 and 67) to control the idle time Ta between the first control signal S10 and the second control signal S20, thereby preventing the second transistor 20 (upper bridge transistor) and the first transistor 10 (lower bridge transistor 10) from being turned on simultaneously.

[0046] In one embodiment, the delay circuit 510 includes a delay resistor 50 and a delay capacitor 51, used to delay the first control signal S10 to generate an auxiliary control signal S11 with a delay time Td. In this embodiment, the delay time Td is determined according to the delay resistor 50. In one embodiment, by means of the delay time Td, after the first control signal S10 is disabled, the auxiliary control signal S11 continues to be enabled for a period of time, so that the auxiliary transistor 11 remains on, thereby avoiding or significantly reducing the reverse recovery charge of the body diode 15 at the moment when the second transistor 20 is turned on.

[0047] It should be noted that, in one embodiment, the on-resistance value of the auxiliary transistor 11 is at least 5 times greater than the on-resistance value of the first transistor 10; in another embodiment, the on-resistance value of the auxiliary transistor 11 is at least 10 times greater than the on-resistance value of the first transistor 10. In one embodiment, the on-resistance value of the auxiliary transistor 11 is greater than a lower resistance limit, such that during the period when the second transistor 20 and the auxiliary transistor 11 may be simultaneously turned on, the current flowing through the auxiliary transistor 11 is less than a preset current value, thereby reducing the forward conduction current of the main diode 15 (if present) while avoiding excessive power loss. In one embodiment, the on-resistance value of the auxiliary transistor 11 is inversely related to the reverse recovery charge value of the main diode 15 of the first transistor 10.

[0048] In one embodiment, the on-resistance value of the auxiliary transistor 11 may optionally be less than an upper limit of a resistance value, thereby completely preventing the body diode 15 of the first transistor 10 from turning on. This prevents the accumulation of reverse recovery charge during the aforementioned idle time, and thus completely avoids voltage spikes caused by the clearing or recombination of the aforementioned reverse recovery charge. For other details not shown in FIG6, please refer to the description of the foregoing embodiments.

[0049] Figure 7 shows the operation waveform diagram corresponding to the control circuit of Figure 6 in one embodiment of the present invention. In one embodiment, as shown in Figure 7, during the period when the first control signal S10 is enabled (before time point t1), the level of the switching voltage VSW is usually close to the ground potential (or less than 0, depending on the load). When the idle time Ta is entered, both the first control signal S10 and the second control signal S20 are disabled, and the level of the switching voltage VSW drops further. At this time, current (e.g., inductor current from freewheeling) flows through the main diode 15 or the auxiliary transistor 11. When the second control signal S20 is enabled (as shown at time point t2 in Figure 7), the level of the switching voltage VSW gradually rises to the input voltage VIN. At time t2 when the second control signal S20 is enabled, the auxiliary control signal S11 remains enabled. During the idle time Ta, the current in the inductor 30 can flow through the auxiliary transistor 11, thereby significantly reducing or completely avoiding the reverse recovery charge of the body diode 15, and thus suppressing the voltage spike of the switching voltage VSW. In this embodiment, by means of the delay circuit 510, the auxiliary control signal S11 is disabled at the end of the delay time Td (as shown at time t3 in Figure 7). In other words, in a preferred embodiment, the delay time Td is longer than the aforementioned idle time Ta.

[0050] Figure 8 shows a schematic diagram of a switching converter and control circuit in another specific embodiment of the present invention. The switching converter 2008 in Figure 8 corresponds to a specific embodiment of the switching converter 2005 in Figure 5. In the embodiment of Figure 8, the control circuit 208 in the switching converter 2008 includes a first control signal S10, a second control signal S20, an auxiliary control signal S11, a delay circuit 520, and a non-overlapping circuit 600. In one embodiment, the delay circuit 520 includes a delay resistor 50, a delay capacitor 51, a delay resistor 52, a voltage clamping transistor 71, and a control transistor 72. In one specific embodiment, both the voltage clamping transistor 71 and the control transistor 72 are NMOS transistors. The voltage clamping transistor 71 operates according to the bias voltage VCP, and its source is coupled to the gate of the control transistor 72 to clamp the gate voltage of the control transistor 72 so that it does not exceed a clamping voltage, wherein the clamping voltage is approximately equal to the bias voltage VCP minus the turn-on threshold voltage of the clamping transistor 71. The drain of the control transistor 72 is coupled to the switching node SW through the clamping transistor 71 to receive the switching voltage VSW, thereby making the control transistor 72 controlled by the switching voltage VSW, but without having to withstand the high voltage of the switching voltage VSW.

[0051] Please also refer to Figure 9, which shows the operation waveform diagram of the control circuit corresponding to Figure 8 in one embodiment of the present invention. In one embodiment, when the second control signal S20 is enabled and the level of the switching voltage VSW exceeds (is higher than) the preset threshold Vth (time point t3), the control transistor 72 is turned on, causing the auxiliary control signal S11 to be disabled to turn off the auxiliary transistor 11. In this embodiment, the end point of the delay time Td is adaptively adjusted according to the switching voltage VSW, wherein the switching voltage VSW changes in response to the second control signal S20 turning on (in this embodiment, it rises), and when the switching voltage VSW exceeds the preset threshold Vth, the auxiliary control signal S11 is disabled. In a specific embodiment, the preset threshold Vth corresponds to the turn-on threshold voltage of the control transistor 72 (e.g., 0.7V). For other details not mentioned in Figures 8 and 9, please refer to the description of the foregoing embodiments.

[0052] It should be noted that in the above embodiments, the switching time of the switching voltage VSW on the switching node SW (i.e., the time for the switching voltage VSW to gradually rise to the input voltage VIN according to the enable of the second control signal S20) is shortened due to the avoidance or reduction of the reverse recovery charge of the main body diode 15. In one embodiment, the mechanism of adaptively adjusting the delay time Td according to the switching voltage VSW has a transmission delay of less than 2ns from the switching voltage VSW exceeding the preset threshold Vth to the auxiliary transistor 11 being turned off. Therefore, in the embodiments of FIG8 and FIG9, the losses caused by the short-circuit current of the auxiliary transistor 11 and the second transistor 20 can be greatly reduced.

[0053] Figures 10A to 10G show various embodiments of the power stage circuit of the switching converter of the present invention. The power stage circuit of the switching converter of the present invention includes at least one switch and an inductor coupled to each other, wherein the at least one switch switches the inductor according to a control signal to convert the input power supply into the output power supply. As shown in Figures 10A to 10G, the power stage circuit of the present invention includes, for example, but not limited to, a synchronous buck converter, a synchronous boost converter, a buck-boost converter, a half-bridge flyback converter, or a full-bridge or half-bridge switched resonant converter.

[0054] The present invention has been described above with reference to preferred embodiments. However, the above description is only for the purpose of enabling those skilled in the art to easily understand the content of the present invention and is not intended to limit the scope of the present invention. The various embodiments described are not limited to individual applications and can also be combined. For example, two or more embodiments can be used in combination, and some components in one embodiment can be used to replace corresponding components in another embodiment. Furthermore, under the same spirit of the present invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the present invention's statement of "processing or calculating based on a signal or generating an output result" is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, under the same spirit of the present invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many combinations, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes. [Simplified Explanation of the Diagram]

[0025] Figure 1 shows a prior art switching converter.

[0026] Figure 2 shows a schematic diagram of a switching converter in one embodiment of the present invention.

[0027] Figure 3 shows the operation waveform of the control circuit in one embodiment of the present invention.

[0028] Figure 4 shows a circuit block diagram of a switching converter in one embodiment of the present invention.

[0029] Figure 5 shows a circuit block diagram of a switching converter in another embodiment of the present invention.

[0030] Figure 6 shows a schematic diagram of a switching converter in one specific embodiment of the present invention.

[0031] Figure 7 shows an operation waveform diagram corresponding to the control circuit in Figure 6 in one embodiment of the present invention.

[0032] Figure 8 shows a schematic diagram of a switching converter and control circuit in another specific embodiment of the present invention.

[0033] Figure 9 shows an operation waveform diagram corresponding to the control circuit in Figure 8 in one embodiment of the present invention.

[0034] Figures 10A to 10G show various embodiments of the power stage circuit of the switching converter of the present invention.

Claims

1. A control circuit for reducing reverse recovery charge in a switching converter, comprising: a first control signal for switching a first transistor; a second control signal for switching a second transistor; and an auxiliary control signal for switching an auxiliary transistor; wherein a first terminal and a second terminal of the first transistor are coupled in parallel to the first terminal and the second terminal of the auxiliary transistor; wherein the first transistor and the second transistor are coupled together to a switching node for periodically switching an inductor to convert an input voltage into an output voltage; wherein there is a delay time between the time when the auxiliary control signal becomes disabled and the time when the first control signal becomes disabled, and the auxiliary control signal becomes disabled only after the second control signal becomes enabled.

2. The control circuit as claimed in claim 1, wherein the first transistor, the second transistor, and the auxiliary transistor are integrated into a chip.

3. The control circuit as described in claim 1 further includes: a delay circuit for delaying the first control signal to generate the auxiliary control signal having the delay time.

4. The control circuit as described in claim 1, wherein the delay time is determined by a delay resistor.

5. The control circuit as claimed in claim 1, wherein the first transistor and the auxiliary transistor are located on the same substrate, wherein the first transistor and the auxiliary transistor respectively correspond to a portion and another portion of a transistor array on the substrate.

6. The control circuit as claimed in claim 1, wherein the on-resistance value of the auxiliary transistor is at least 5 times greater than the on-resistance value of the first transistor.

7. The control circuit as claimed in claim 1 further includes: a non-overlapping circuit for generating a dead-time between the first control signal and the second control signal, wherein both the first control signal and the second control signal are disabled during the dead-time.

8. The control circuit as claimed in claim 1, wherein the first transistor, the second transistor and the inductor are configured as a synchronous buck converter, a synchronous boost converter or a buck-boost converter.

9. The control circuit as claimed in claim 1, wherein a conduction resistance value of the auxiliary transistor is less than an upper limit of a resistance value to prevent a body diode of the first transistor from conducting.

10. The control circuit as claimed in claim 1, wherein a conduction resistance value of the auxiliary transistor is greater than a lower resistance value, such that a current flowing through the auxiliary transistor is less than a preset current value.

11. The control circuit as claimed in claim 1, wherein the on-resistance value of the auxiliary transistor is inversely related to the reverse recovery charge value of one of the body diodes of the first transistor.

12. The control circuit as claimed in claim 1, wherein the auxiliary control signal is switched off only after the second control signal is switched on to enable, thereby avoiding or reducing the effect of reverse recovery charge of the body diode of the first transistor.

13. The control circuit as claimed in claim 12, wherein the switching time of a switching voltage at the switching node is shortened by avoiding or reducing the reverse recovery charge of the body diode.

14. The control circuit as claimed in claim 3, wherein a switching voltage on the switching node changes in response to the second control signal being enabled, wherein the auxiliary control signal is disabled when the switching voltage exceeds a preset threshold.

15. The control circuit as claimed in claim 14, wherein the delay circuit further includes a control transistor for switching when the switching voltage exceeds the preset threshold, so as to disable the auxiliary control signal.

16. The control circuit as claimed in claim 15, wherein the control transistor is coupled to a control terminal of the auxiliary transistor, the control transistor is controlled by the switching voltage, and the preset threshold corresponds to the turn-on threshold voltage of the control transistor.

17. The control circuit as claimed in claim 15, wherein the delay circuit further includes a voltage clamping transistor coupled between the control transistor and the switching voltage for clamping the voltage at a control terminal of the control transistor so that it does not exceed a clamping voltage.

18. A control method for reducing reverse recovery charge in a switching converter, comprising: generating a first control signal to switch a first transistor; generating a second control signal to switch a second transistor, wherein the first transistor and the second transistor are coupled together to a switching node; generating an auxiliary control signal to switch an auxiliary transistor; wherein a first terminal and a second terminal of the first transistor are coupled in parallel to the first terminal and the second terminal of the auxiliary transistor; periodically switching an inductor according to the first control signal and the second control signal to convert an input voltage into an output voltage; and controlling a delay time between the time when the auxiliary control signal is disabled and the time when the first control signal is disabled, and controlling the auxiliary control signal to be disabled only after the second control signal is enabled.

19. The control method as described in claim 18 further includes: delaying the first control signal to generate the auxiliary control signal having the delay time.

20. The control method as described in claim 18, wherein the delay time is determined based on a delay resistor.

21. The control method as described in claim 18, wherein the on-resistance value of the auxiliary transistor is at least 5 times greater than the on-resistance value of the first transistor.

22. The control method as described in claim 18 further comprises: generating a dead-time between the first control signal and the second control signal, wherein both the first control signal and the second control signal are disabled during the dead-time.

23. The control method as described in claim 18, wherein a conduction resistance value of the auxiliary transistor is less than an upper limit of a resistance value to prevent a body diode of the first transistor from conducting.

24. The control method as described in claim 18, wherein a conduction resistance value of the auxiliary transistor is greater than a lower resistance value limit, such that a current flowing through the auxiliary transistor is less than a preset current value.

25. The control method as claimed in claim 18, wherein the on-resistance value of the auxiliary transistor is inversely correlated with the reverse recovery charge value of one of the body diodes of the first transistor.

26. The control method as described in claim 18, wherein the auxiliary control signal is switched to disabled only after the second control signal is switched to enabled, thereby avoiding or reducing the effect of reverse recovery charge of the bulk diode of the first transistor.

27. The control method as described in claim 26, wherein the switching time of a switching voltage at the switching node is shortened by avoiding or reducing the reverse recovery charge of the body diode.

28. The control method as described in claim 18, wherein a switching voltage on the switching node changes in response to the second control signal being enabled, the control method further comprising: when the switching voltage exceeds a preset threshold, controlling the auxiliary control signal to be disabled.

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