Semiconductor devices

Abstract

The present invention provides a semiconductor device capable of suppressing the generation of defects. One embodiment of the semiconductor device includes: a wiring layer comprising a plurality of wirings; and a pillar electrode integrally disposed with the wirings and extending from the bottom of the wirings in a direction substantially perpendicular to the wiring layer; wherein the wirings have conductive films alternately deposited in a direction substantially perpendicular to the wiring layer and a first film different from the conductive films.

Description

[Technical Field]

[0001] The embodiments of the present invention relate to a semiconductor device. [Previous Technology]

[0002] Semi-damascene wiring and other wiring are formed, for example, by processing a film formed using CVD (Chemical Vapor Deposition). Depending on the surface roughness of the film formed using CVD, the wiring may produce recessed defects. [Summary of the Invention]

[0003] A semiconductor device capable of suppressing the generation of defects is provided.

[0004] A semiconductor device according to one embodiment includes: a wiring layer comprising a plurality of wirings; and a pillar electrode integrally disposed with the wirings and extending from the bottom of the wirings in a direction substantially perpendicular to the wiring layer; and the wirings having conductive films alternately deposited in a direction substantially perpendicular to the wiring layer and a first film different from the conductive films.

Implementation Method

[0006] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0007] This embodiment does not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be the same as in the actual situation. In the specification and drawings, the same symbols are used for elements that are the same as those described above for existing drawings, and detailed descriptions are omitted where appropriate.

[0008] (First Embodiment) FIG1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the first embodiment. FIG1 shows a wiring layer 50 used in the semiconductor device.

[0009] The semiconductor device includes a wiring layer 50, an insulating layer 60, a barrier metal film 70, a columnar electrode (through-hole plug) 80, and an insulating film 90.

[0010] Wiring layer 50 is disposed on the XY plane. Wiring layer 50 includes a plurality of wirings 51. When the semiconductor device is a memory (memory element), wiring layer 50 may include wiring for memory cell arrays and wiring for peripheral circuits such as circuits. Hereinafter, the case where the semiconductor device is a memory will be described, but it is not limited thereto; the semiconductor device may also be a logic circuit (logic element).

[0011] A plurality of wirings 51 are configured, for example, in a specific pattern. A plurality of wirings 51 are configured, for example, in a line and gap pattern. The wirings 51 extend in a direction perpendicular to the plane of the paper in FIG1 (Y direction). A plurality of wirings 51 are arranged in the X direction. The wirings 51 are, for example, used for memory bit lines.

[0012] The material used for wiring 51 is, for example, a conductive material such as tungsten (W). Furthermore, details regarding the structure of wiring 51 will be explained below with reference to Figures 3A to 3E.

[0013] The insulating layer 60 insulates the wiring 51. The material of the insulating layer 60 is, for example, SiO2. The insulating layer 60 is formed using, for example, TEOS (Tetraethoxysilane).

[0014] The barrier metal film 70 suppresses the diffusion of W contained in the material of the wiring 51. The barrier metal film 70 is disposed between the wiring 51 and the insulating layer 60. The barrier metal film 70 is disposed between the pillar electrode 80 and the insulating layer 60. The barrier metal film 70 is, for example, made of titanium (Ti), tantalum (Ta), or tantalum nitride film (TaN).

[0015] The columnar electrode 80 electrically connects the wiring 51 to the underlying wiring (not shown). The columnar electrode 80 is integrally formed with the wiring 51 and extends from the bottom of the wiring 51 in a direction substantially perpendicular to the wiring layer 50 (Z direction). The material of the columnar electrode 80 is the same as that of the wiring 51. For example, a conductive material such as tungsten (W) is used for the columnar electrode 80.

[0016] An insulating film 90 is disposed on the wiring 51. The material of the insulating film 90 is, for example, SiN.

[0017] Figures 2A and 2B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0018] First, as shown in FIG2A, a hole H is formed in the insulating film 61, and a barrier metal film 70 is formed on the insulating film 61 and inside the hole H. A wiring member 52 is formed such that the hole H is embedded and disposed on the insulating film 61. An insulating film 90 is formed on the wiring member 52, and a semiconductor film 100 is formed on the insulating film 90. The wiring member 52 is formed, for example, by CVD (Chemical Vapor Deposition). The material of the semiconductor film 100 is, for example, amorphous silicon.

[0019] Furthermore, the wiring component 52 embedded in the hole H becomes a columnar electrode 80. That is, the columnar electrode 80 and the wiring component 52, which becomes wiring 51 after processing, are formed simultaneously.

[0020] Furthermore, details regarding the formation of the wiring component 52 will be explained below with reference to Figures 3A to 3E.

[0021] Next, as shown in FIG2B, a plurality of wirings 51 arranged in a specific pattern are formed by processing the wiring component 52. The processing of the wiring component 52 is performed, for example, by RIE (Reactive Ion Etching).

[0022] Subsequently, the wiring 51 is embedded in an insulating film identical to the insulating film 61, and polishing is performed (e.g., CMP (Chemical Mechanical Polishing)) until the insulating film 90 is exposed, thereby completing the structure shown in FIG1.

[0023] Next, the formation of the wiring component 52 will be explained.

[0024] Figures 3A to 3E are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Furthermore, the barrier metal film 70 is omitted.

[0025] First, as shown in FIG3A, a nucleation layer 53 is formed on the insulating film 61. The nucleation layer 53 is formed, for example, by alternately supplying diborane (B2H6) gas and tungsten hexafluoride (WF6) gas into the processing chamber and performing processing.

[0026] Next, as shown in FIG3B, a conductive film 54 is formed. The conductive film 54 is formed by growing and enlarging the grain size of the metal contained in the nucleation layer 53. The main component of the conductive film 54 is, for example, tungsten (W). The conductive film 54 is formed, for example, by processing one side of the processing chamber with tungsten hexafluoride (WF6) and hydrogen (H2) gas. The conductive film 54 is formed, for example, until the thickness is about 15 nm. The thickness of the conductive film 54 is the thickness in the vertical direction (Z direction) of the paper. Furthermore, the thickness of the conductive film 54 is determined within a range where the wiring 51, as described below with reference to FIG5, will not produce defects. Also, the grain boundary 54a of the conductive film 54 is shown in FIG3B.

[0027] Next, as shown in FIG3C, a film 55 is formed on the conductive film 54. The film 55 is an amorphous film. The film 55 is formed, for example, by impregnation (soaking) with diborane. In this case, the film 55 is a film containing diborane adsorbed on the surface of the conductive film 54. The film 55 as an impregnated film is formed, for example, by processing one side of the film to which diborane gas is supplied to the processing chamber. Furthermore, the upper surface of the film 55 shown in FIG3C is flat, but the upper surface of the film 55 may not necessarily be flat.

[0028] Next, as shown in FIG3D, a conductive film 54 is formed on the film 55. The conductive film 54 is formed, for example, in the same manner as in FIG3B, until the thickness is about 15 nm.

[0029] Next, as shown in FIG3E, the steps shown in FIG3C and FIG3D are repeated (cyclic film formation). This forms the wiring component 52. In the example shown in FIG3E, three conductive films 54 are formed.

[0030] The wiring member 52 has conductive films 54 and 55 alternately deposited in a direction substantially perpendicular to the wiring layer 50 (Z direction). Therefore, the wiring 51 shown in FIG1 also has conductive films 54 and 55 alternately deposited in a direction substantially perpendicular to the wiring layer 50 (Z direction). The main component of the conductive film 54 is, for example, tungsten (W). The type of film 55 is different from that of the conductive film 54. In the first embodiment, the main component of the film 55 is boron (B), which is different from the main component of the conductive film 54. The number of layers of the conductive films 54 and 55 is, for example, two or more. For example, when the wiring member 52 is formed with a thickness of 40 nm, three conductive films 54 of about 13 nm are formed.

[0031] The auxiliary film 55 functions as a segmentation film that is arranged between the two conductive films 54 sandwiched between the film 55 to segment the grains of the conductive films 54. Using the film 55, grain growth of the conductive films 54 can be prevented, thereby allowing the grain size of the conductive films 54 to be below a specific grain size. This suppresses the enlargement of the conductive films 54, thereby suppressing (improving) the surface roughness of the wiring member 52. As a result, defects in the wiring 51 during the processing of the wiring member 52 can be suppressed. Furthermore, details regarding defects in the wiring 51 caused by the surface roughness of the wiring member 52 will be explained below with reference to Figures 6A to 6E.

[0032] Furthermore, the film 55 is formed until its thickness is sufficient to cover the conductive film 54 and appropriately break down the crystallinity of the conductive film 54. Therefore, the film 55 can be thinner than the conductive film 54. Since the film 55 is an impregnated film, it can be formed simply by adsorbing diborane onto the surface of the conductive film 54. Furthermore, the impregnated film containing diborane acts as a reducing agent during the formation of the conductive film 54, thus the film 55 becomes even thinner. In this way, the ratio of the thickness of the conductive film 54 to the overall thickness of the wiring member 52 can be increased. As a result, the wiring resistance of the wiring 51 can be further reduced.

[0033] As described above, according to the first embodiment, the wiring 51 has conductive films 54 and 55 alternately deposited in a direction substantially perpendicular to the wiring layer 50 (Z direction). Furthermore, the wiring 51 has at least two or more conductive films 54. This suppresses the large particle size of the conductive films 54, thereby suppressing (improving) the surface roughness of the wiring member 52. As a result, defects in the wiring 51 can be suppressed. The greater the surface step difference (see FIG5) of the wiring member 52, that is, the higher the protrusion of the upper surface of the wiring member 52 is from the reference surface, the greater the roughness.

[0034] Furthermore, as shown in FIG2A, the wiring component 52 and the columnar electrode 80 are integrally formed simultaneously using CVD. This reduces the number of steps.

[0035] Furthermore, an insulating film 90 is disposed on a plurality of wirings 51. The insulating film 90 is configured according to the shape of the plurality of wirings 51 as viewed from a direction substantially perpendicular to the wiring layer 50 (Z direction). More specifically, the plurality of insulating films 90 are disposed along the plurality of wirings 51. For example, the outer edge shape of the plurality of insulating films 90 may be substantially the same as the outer edge shape of the plurality of wirings 51 as viewed from a direction substantially perpendicular to the wiring layer 50 (Z direction). When forming an upper columnar electrode (not shown) that is electrically connected to the upper part of the wirings 51, a portion of the insulating film 90 on the wirings 51 is recessed (processed) and a conductive material is embedded therein. This allows the shape of the bottom of the upper columnar electrode to be adjusted, for example, so that the bottom of the upper columnar electrode is located only above the wirings 51. As a result, concerns about withstand voltage can be suppressed.

[0036] Furthermore, membrane 55 is not limited to the examples described above. Membrane 55 is more preferably a membrane capable of forming within the same chamber or the same device.

[0037] (First Comparative Example) FIG4 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first comparative example. The first comparative example differs from the first embodiment in that the conductive film 54 is continuously grown without the film 55 being provided.

[0038] In the first comparative example, the steps shown in FIG. 3B of the first embodiment were continued to form a wiring member 52 having a conductive film 54 with a large particle size. Since the larger the particle size of the conductive film 54, the smaller the resistivity of the wiring 51, the wiring resistance of the wiring 51 can be reduced. However, the larger the particle size of the conductive film 54, the worse the surface roughness of the wiring member 52 becomes. In the example shown in FIG. 4, a local protrusion is formed on the upper surface of the wiring member 52. The protrusion 52a shown in FIG. 4 is the protrusion with the largest height difference.

[0039] Figure 5 is a diagram illustrating an example of the relationship between the thickness of the conductive film 54 and the defects generated in the wiring 51 according to the first embodiment. The horizontal axis of the figure represents the thickness of the conductive film 54. The vertical axis of the figure represents the surface step difference. The surface step difference is the maximum value of the height difference of the local protrusions generated on the upper surface of the wiring member 52. (In the example shown in Figure 4, it is the height difference of the protrusion 52a shown in Figure 4.)

[0040] When the thickness of the conductive film 54 is about 38 nm or more (first comparative example), the surface step difference of the wiring component 52 is about 35 nm or more, and the wiring 51 may have defects.

[0041] On the other hand, when the thickness of the conductive film 54 is about 15 nm or less (first embodiment), the surface gradient of the wiring member 52 is about 15 nm or less, and no defects are generated in the wiring 51. When the conductive film 54 is formed on the film 55, the conductive film 54 begins to grow from a state where the thickness of the conductive film 54 is reset to zero nm (the horizontal axis of the figure). In this way, even if the total thickness of the conductive film 54 increases, the surface roughness of the wiring member 52 can be suppressed.

[0042] Secondly, the defects are explained.

[0043] Figures 6A to 6E are cross-sectional views showing one example of a method for manufacturing a semiconductor device according to the first comparative example.

[0044] FIG6A shows the wiring member 52 described with reference to FIG4. As shown in FIG6A, a local protrusion 52a is formed on the upper surface of the wiring member 52 due to the surface roughness. Because of the protrusion 52a, the upper surfaces of the insulating film 90 and the semiconductor film 100 above the protrusion 52a also have protrusions.

[0045] First, as shown in FIG6A, an insulating film 90, a semiconductor film 100 serving as a masking film, a masking film 110, and an insulating film 120 are sequentially formed on the wiring member 52. A photoresist 130 is formed in a specific area on the insulating film 120, and a spacer 140 is formed on the insulating film and the photoresist 130.

[0046] The insulating film 120 is, for example, an SOG (Spin On Glass) film. The spacer 140 contains, for example, SiO2.

[0047] Next, as shown in FIG6B, the masking film 110, the insulating film 120, the photoresist 130, and the spacer 140 are processed until the semiconductor film 100 is exposed, and the spacer 150 is formed. The processing is performed, for example, using a RIE.

[0048] Next, as shown in FIG6C, the masking film 110, the insulating film 120, and the spacer 150 are processed. The processing is performed, for example, using a RIE / WET. As shown in FIG6C, the spacer 150 provided above the protrusion 52a is thinner than the spacers 150 provided at other locations.

[0049] Next, as shown in FIG6D, the spacer 150 is used as a mask to process the semiconductor film 100. The processing of the semiconductor film 100 is performed, for example, using a resonant interconnect (RIE). As shown in FIG6D, the spacer 150 provided above the protrusion 52a completely disappears during processing. Since the spacer 150, which serves as a mask, disappears, the semiconductor film 100 above the protrusion 52a also disappears.

[0050] Next, as shown in FIG6E, the spacer 150 is used as a mask to process the wiring member 52. By processing the wiring member 52, wiring 51 with a specific pattern such as line and gap patterns is formed. Furthermore, the steps shown in FIG6D to FIG6E are continued. As shown in FIG6E, because the spacer 150 acting as a mask disappears, wiring 51 is not formed at the position where the protrusion 52a is formed. That is, wiring 51 has a recessed defect.

[0051] In contrast, in the first embodiment, by cyclically forming the conductive film 54 and the film 55, the large particle size of the conductive film 54 can be suppressed, thereby improving the surface roughness of the wiring member 52. As a result, the formation of protrusions 52a can be suppressed, thereby suppressing defects in the wiring 51.

[0052] Furthermore, for example, the thickness of the conductive film 54 can be determined by experimentally obtaining the relationship between the thickness of the conductive film 54 shown in Figure 5 and the defects generated in the wiring 51.

[0053] (Second Comparative Example) FIG7 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second comparative example. The second comparative example differs from the first embodiment in that the wiring member 52 is entirely a nucleation layer 53.

[0054] In the second comparative example, the steps shown in FIG. 3A of the first embodiment were continued. The nucleation layer 53 was amorphous. Therefore, the surface roughness of the wiring member 52 was improved compared to the first comparative example. However, the resistivity of the wiring 51 increased. As a result, the wiring resistance of the wiring 51 increased.

[0055] In contrast, in the first embodiment, a plurality of conductive films 54 with a certain particle size are formed. This reduces the specific resistance of the wiring 51. As a result, a wiring component 52 with low resistance and improved surface roughness can be formed.

[0056] (Second Embodiment) The second embodiment differs from the first embodiment in that the film 55 is an oxide film.

[0057] The main component of the membrane 55 is the oxide of the metal element that is the main component of the conductive membrane 54.

[0058] The oxide film 55 is formed, for example, by oxidizing the surface of the conductive film 54. The conductive film 54 contains tungsten (W), therefore the film 55 contains WOx as the main component. Furthermore, the film 55 is an amorphous film.

[0059] Since film 55 is an oxide film, it is easier to form film 55.

[0060] Furthermore, there exists a situation where, if tungsten hexafluoride and hydrogen gas are supplied to WOx, the WOx will be reduced, causing the film 55 to become thinner. In this case, the ratio of the thickness of the conductive film 54 to the overall thickness of the wiring component 52 can be increased. As a result, the wiring resistance of the wiring 51 can be further reduced.

[0061] As in the second embodiment, the film 55 can be an oxide film. In this case, the same effect as in the first embodiment can also be obtained.

[0062] (Third Embodiment) The third embodiment differs from the first embodiment in that the film 55 is the nucleus forming layer of the conductive film 54.

[0063] The main components of film 55 are the same as those of conductive film 54. More specifically, film 55 is the nucleation layer of conductive film 54.

[0064] The film 55, which serves as the nucleation layer, is formed, for example, in the same manner as the nucleation layer 53 shown in FIG. 3A. In this case, the film 55 is a tungsten film containing more of the material gas used to form the nucleation layer, namely diborane. Therefore, the film 55 contains boron (B) based on diborane. Furthermore, the film 55 is an amorphous film.

[0065] Since the film 55 is a metal film, its resistance is relatively low. This allows for a further reduction in the wiring resistance of the wiring 51.

[0066] As in the third embodiment, the membrane 55 can be a nucleation layer. In this case, the same effects as in the first embodiment can be obtained.

[0067] (Fourth Embodiment) FIG8 is a cross-sectional view showing an example of the structure of the semiconductor device according to the fourth embodiment. The semiconductor device shown in FIG8 is a three-dimensional memory formed by bonding an array chip C1 and a circuit chip C2.

[0068] The array chip C1 includes a memory cell array 11 comprising a plurality of memory cells arranged in three dimensions, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film, or a laminated film comprising a silicon oxide film and other insulating films.

[0069] Circuit chip C2 is disposed under array chip C1. The symbol S indicates the bonding surface between array chip C1 and circuit chip C2. Circuit chip C2 includes an interlayer insulating film 14 and a substrate 15 under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film, or a laminated film including a silicon oxide film and other insulating films. The substrate 15 is an example of a first substrate, such as a semiconductor substrate like a silicon substrate. FIG8 shows the X and Y directions parallel and perpendicular to the surface, i.e., the upper surface, of the substrate 15, and the Z direction perpendicular to the surface of the substrate 15. The Y direction is an example of the first direction, the X direction is an example of the second direction intersecting the first direction, and the Z direction is an example of the third direction intersecting the first and second directions.

[0070] The array chip C1 has a plurality of word lines WL and source lines SL as a plurality of electrode layers within the memory cell array 11. Figure 8 shows the stepped structure 21 of the memory cell array 11. Each word line WL is electrically connected to the word wiring layer 23 via a contact plug 22. Each columnar portion CL passing through the plurality of word lines WL is electrically connected to the bit line BL via a through-hole plug 24, and is also electrically connected to the source line SL. The source line SL includes a first layer SL1 as a semiconductor layer and a second layer SL2 as a metal layer. The symbol V indicates a through-hole plug disposed under the bit line BL.

[0071] The circuit chip C2 includes a plurality of transistors 31. Each transistor 31 has a gate electrode 32 disposed on a substrate 15 through a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 15. Furthermore, the circuit chip C2 includes: a plurality of contact plugs 33 disposed on the source diffusion layer or drain diffusion layer of the transistors 31; a wiring layer 34 disposed on the contact plugs 33, comprising a plurality of wirings; and a wiring layer 35 disposed on the wiring layer 34, comprising a plurality of wirings.

[0072] The circuit chip C2 further includes: a wiring layer 36 disposed on the wiring layer 35, comprising a plurality of wirings; a plurality of via plugs 37 disposed on the wiring layer 36; and a plurality of metal pads 38 disposed on the via plugs 37. The metal pads 38 are, for example, Cu (copper) layers or Al (aluminum) layers. The circuit chip C2 functions as a control circuit (logic circuit) for controlling the operation of the array chip C1. The control circuit includes transistors 31, etc., electrically connected to the metal pads 38.

[0073] The array chip C1 includes a plurality of metal pads 41 disposed on metal pads 38, and a plurality of via plugs 42 disposed on the metal pads 41. Furthermore, the array chip C1 includes: a wiring layer 43 disposed on the via plugs 42, comprising a plurality of wirings; and a wiring layer 44 disposed on the wiring layer 43, comprising a plurality of wirings including bit lines BL. The metal pads 41 are, for example, Cu layers or Al layers. The via plugs 42 are connected to the wiring layer 43 and the bit lines BL.

[0074] The array chip C1 further includes a plurality of through-hole plugs 45 disposed on the wiring layer 44, metal pads 46 disposed on the through-hole plugs 45 or on the insulating film 12, and a passivation film 47 disposed on the metal pads 46 or on the insulating film 12. The metal pads 46 are, for example, Cu layers or Al layers, and function as external connection pads (bonding pads) of the semiconductor device in FIG8. The passivation film 47 is, for example, an insulating film such as a silicon oxide film, and has an opening P that exposes the upper surface of the metal pads 46. The metal pads 46 can be connected to a mounting substrate or other device through the opening P by bonding wires, solder balls, metal bumps, etc.

[0075] Here, the wiring 51 in the wiring layer 50 described in the first to third embodiments is, for example, equivalent to the wiring in the wiring layer 44. Furthermore, the vertical direction of FIG8 is reversed relative to FIG1.

[0076] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0005] Figure 1 is a cross-sectional view showing an example of the configuration of the semiconductor device according to the first embodiment. Figure 2A is a cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. Figure 2B is a cross-sectional view showing an example of the manufacturing method of the semiconductor device following Figure 2A. Figure 3A is a cross-sectional view showing an example of the manufacturing method of the semiconductor device according to the first embodiment. Figure 3B is a cross-sectional view showing an example of the manufacturing method of the semiconductor device following Figure 3A. Figure 3C is a cross-sectional view showing an example of the manufacturing method of the semiconductor device following Figure 3B. Figure 3D is a cross-sectional view showing an example of the manufacturing method of the semiconductor device following Figure 3C. Figure 3E is a cross-sectional view showing an example of the manufacturing method of the semiconductor device following Figure 3D. Figure 4 is a cross-sectional view showing an example of the manufacturing method of the semiconductor device of the first comparative example. Figure 5 is a diagram showing an example of the relationship between the film thickness of the conductive film and the wiring defects in the first embodiment and the first comparative example. Figure 6A is a cross-sectional view showing an example of the manufacturing method of the semiconductor device of the first comparative example. Figure 6B is a cross-sectional view following Figure 6A, showing one example of a method for manufacturing a semiconductor device. Figure 6C is a cross-sectional view following Figure 6B, showing one example of a method for manufacturing a semiconductor device. Figure 6D is a cross-sectional view following Figure 6C, showing one example of a method for manufacturing a semiconductor device. Figure 6E is a cross-sectional view following Figure 6D, showing one example of a method for manufacturing a semiconductor device. Figure 7 is a cross-sectional view showing one example of a method for manufacturing a semiconductor device according to the second comparative example. Figure 8 is a cross-sectional view showing one example of the structure of the semiconductor device according to the fourth embodiment.

Claims

1. A semiconductor device comprising: a wiring layer including a plurality of wirings; and a pillar electrode integrally disposed with the wirings and extending from the bottom of the wirings in a direction substantially perpendicular to the wiring layer; wherein the wirings have conductive films alternately deposited in a direction substantially perpendicular to the wiring layer and a first film different from the conductive films, wherein the main component of the first film is boron (B), an oxide of a metal element that is the main component of the conductive films, or a nucleation layer of the conductive films.

2. The semiconductor device of claim 1, wherein the first film is provided in such a way that the grains of the conductive film are separated between the two conductive films sandwiching the first film.

3. The semiconductor device of claim 1, wherein the first film comprises boron (B) when the main component of the first film is the nucleation layer of the conductive film.

4. The semiconductor device of claim 1, wherein the first film is an amorphous film.

5. The semiconductor device of claim 1, wherein the main component of the conductive film is tungsten (W).

6. The semiconductor device of claim 1, wherein the number of layers of the conductive film and the first film is 2 or more.

7. The semiconductor device of claim 1, wherein the thickness of the conductive film in a direction substantially perpendicular to the wiring layer is 15 nm or less.

8. The semiconductor device of claim 1, further comprising an insulating film disposed on a plurality of the aforementioned wirings, wherein the insulating film is configured according to the shape of the plurality of the aforementioned wirings as viewed from a direction substantially perpendicular to the aforementioned wiring layer.

9. The semiconductor device of claim 1 further comprises: a memory cell array; and a plurality of columnar portions passing through the memory cell array; and the plurality of the aforementioned wirings being electrically connected to the plurality of the aforementioned columnar portions respectively.

10. The semiconductor device of claim 9 further comprises: a substrate; and the wiring layer is disposed between the substrate and the memory cell array.

11. A semiconductor device comprising: a wiring layer including a plurality of wirings; wherein the wirings have conductive films alternately deposited in a direction substantially perpendicular to the wiring layer and a first film different from the conductive films, wherein the main component of the first film is boron (B), or an oxide of a metal element that is the main component of the conductive films, or the first film is an amorphous film, and the number of layers of the conductive films and the first film is 5 or more.

12. The semiconductor device of claim 11 further comprises: a memory cell array; and a plurality of columnar portions, which pass through the memory cell array; and the plurality of the aforementioned wirings are electrically connected to the plurality of the aforementioned columnar portions respectively.

13. The semiconductor device of claim 12 further comprises: a substrate; and the wiring layer is disposed between the substrate and the memory cell array.

14. The semiconductor device of claim 11, wherein the thickness of the conductive film in a direction substantially perpendicular to the wiring layer is 15 nm or less.

15. A semiconductor device comprising: a wiring layer including a plurality of wirings; and a pillar electrode integrally disposed with the wirings and extending from the bottom of the wirings in a direction substantially perpendicular to the wiring layer; wherein the wirings have conductive films alternately deposited in a direction substantially perpendicular to the wiring layer and a first film different from the conductive films, and the main component of the first film is the same as the main component of the conductive films, or the first film is an amorphous film, and when the main component of the first film is the same as that of the conductive films, the first film is a nucleation layer of the conductive films.

16. The semiconductor device of claim 15, wherein the first film comprises boron (B) when the main component of the first film is the nucleation layer of the conductive film.

17. The semiconductor device of claim 15 further comprises: a memory cell array; and a plurality of columnar portions, which pass through the memory cell array; and the plurality of the aforementioned wirings are electrically connected to the plurality of the aforementioned columnar portions respectively.

18. The semiconductor device of claim 17 further comprises: a substrate; and the wiring layer is disposed between the substrate and the memory cell array.

19. The semiconductor device of claim 15, wherein the number of layers of the conductive film and the first film is 2 or more.

20. The semiconductor device of claim 15, wherein the thickness of the conductive film in a direction substantially perpendicular to the wiring layer is 15 nm or less.

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