Light-emitting diode chip structures with electrode extensions and gradient vias

Abstract

The solid-state light-emitting device includes a light-emitting diode (LED) chip and, more specifically, an LED chip structure with electrode extensions and a gradient via arrangement as disclosed. The electrode extensions and vias are formed on opposite sides of the active light-emitting diode structure as connection portions between the anode and cathode. The gradient via arrangement includes a variable diameter and / or a variable via spacing relative to the electrode extensions and electrode pads. Additional structures include electrode extensions of variable width relative to the vias and / or electrode pads. The layout of the gradient vias and corresponding electrode extensions is intended to increase the uniformity of re-bonding efficiency throughout the LED chip area and to provide the disclosed improvements in current injection, current droop, and overall emission efficiency.

Description

[Technical Field]

[0001] The present invention relates to a solid-state light-emitting device comprising a light-emitting diode chip, and more particularly to an LED chip structure having electrode extensions and gradient vias. [Previous Technology]

[0002] Solid-state light-emitting devices, such as light-emitting diodes (LEDs), are increasingly used in both consumer and commercial applications. Advances in LED technology have resulted in highly efficient and mechanically robust light sources with long lifespans. As a result, modern LEDs have enabled a variety of new display applications and are increasingly used in general lighting applications, often replacing incandescent and fluorescent light sources.

[0003] A light-emitting diode (LED) is a solid-state device that converts electrical energy into light, and typically comprises one or more active layers (or active regions) of semiconductor material disposed between oppositely doped n-type and p-type layers. When a bias voltage is applied across the doped layers, holes and electrons are injected into one or more active layers, where the holes and electrons recombine to produce emission, such as visible light or ultraviolet light emission. The active regions can be made of, for example, gallium nitride, gallium phosphide, aluminum nitride, and / or gallium arsenide-based materials and / or organic semiconductor materials, etc. Photons generated by the active regions are emitted in all directions.

[0004] Typically, the desired outcome is operation with the highest possible light-emitting efficiency (LED), which can be measured by the emission intensity relative to the output power (e.g., in watt-lumen). The practical goal for enhancing emission efficiency is to maximize the extraction of emitted light from the active region in the desired direction of light transmission. The light extraction and external quantum efficiency of an LED are limited by how well the current can be distributed within the LED. To increase current distribution in LEDs, and particularly for large-area LEDs, it has been found useful to add a high-conductivity layer to one or more epitaxial layers of the LED. Electrodes for LEDs can have a large surface area and can include electrode extensions or fingers with various configuration routes and distributions throughout the LED current.

[0005] With the advancement of modern LED technology, the technology continues to seek LEDs and solid-state light-emitting devices with improved lighting characteristics that can overcome the challenges associated with traditional light-emitting devices. [Summary of the Invention]

[0006] This invention relates to a solid-state light-emitting device comprising a light-emitting diode (LED) wafer and, more particularly, an LED wafer structure having electrode extensions and a gradient via arrangement. The electrode extensions and vias are formed on opposite sides of the active LED structure as connection portions of the anode and cathode. The gradient via arrangement includes a variable diameter and / or a variable via spacing relative to the electrode extensions and electrode pads. Additional structures include electrode extensions of variable width relative to the vias and / or electrode pads. The arrangement of the gradient vias and corresponding electrode extensions is intended to increase the uniformity of re-bonding efficiency throughout the LED wafer area and to provide the disclosed parameters for current injection, current droop, and overall emission efficiency.

[0007] In one embodiment, the LED chip includes: an active light-emitting diode (LED) structure comprising a first layer of a first conductor type, a second layer of a second conductor type opposite to the first conductor type, and an active layer between the first and second layers; a first electrode pad on a first side of the LED structure, a first electrode extension and a second electrode extension on the first side of the LED structure, the first electrode extension and the second electrode extension being electrically connected to the first electrode pad; and a plurality of vias on a second side of the LED structure opposite to the first side, the plurality of vias being located between portions of the LED structure, the plurality of vias being perpendicularly aligned with the first electrode extension and the second electrode extension, and the diameter of each via varying with distance from the first electrode pad. In some embodiments, the plurality of vias are arranged in rows throughout the second side of the LED structure. In some embodiments, the diameter of each via gradually decreases with increasing distance from the first electrode pad. In some embodiments, the diameter of an individual via of the plurality of vias gradually increases with increasing distance from the first electrode pad. The LED chip may further include a second electrode pad on a first side of the active-emitting diode (EVD) structure, wherein the first electrode pad is arranged close to a first edge of the EPD structure, and the second electrode pad is arranged close to a second edge of the EPD structure, with the second edge opposite the first edge. In some embodiments, the diameter of an individual via of the plurality of vias gradually decreases with increasing distance from the first and second electrode pads toward the center of the EPD structure. In some embodiments, the diameter of an individual via of the plurality of vias gradually increases with increasing distance from the first and second electrode pads toward the center of the EPD structure.

[0008] The LED chip may further include: a second electrode pad, a third electrode pad, and a fourth electrode pad, all three being located on a first side of the active light-emitting diode structure; wherein the first and second electrode pads are arranged close to the first edge of the active light-emitting diode structure, and the third and fourth electrode pads are arranged close to the second edge of the active light-emitting diode structure, with the second edge opposite to the first edge. In some embodiments, the first electrode pad is an electrode strip arranged close to the first edge of the active light-emitting diode structure.

[0009] In some embodiments: the active light-emitting diode structure includes a first edge and a second edge opposite to each other, and a third edge and a fourth edge opposite to each other; a plurality of through holes are arranged in a first row of through holes and a second row of through holes, both the first row of through holes and the second row of through holes extending between the first edge and the second edge of the active light-emitting diode structure; and in the direction from the third edge to the fourth edge, the position of the through holes in the first row of through holes is offset relative to the position of the through holes in the second row of through holes.

[0010] In some embodiments: a plurality of through holes are arranged in the first row of through holes and the second row of through holes; and the total number of through holes in the first row of through holes is different from the total number of through holes in the second row of through holes.

[0011] In another embodiment, the LED chip includes: an active light-emitting diode (LED) structure comprising a first layer of a first conductor type, a second layer of a second conductor type opposite to the first conductor type, and an active layer between the first and second layers; a first electrode pad, a first electrode extension, and a second electrode extension on a first side of the LED structure, the first and second electrode extensions being electrically connected to the first electrode pad; and a plurality of vias on a second side of the LED structure opposite to the first side, the plurality of vias being located between portions of the LED structure, the plurality of vias being perpendicularly aligned with the first and second electrode extensions, and the spacing between adjacent vias varying with distance from the first electrode pad. In some embodiments, the plurality of vias are arranged in rows throughout the second side of the LED structure, and the spacing increases with increasing distance from the first electrode pad. In some embodiments, the diameter of an individual through-hole of the plurality of vias increases with increasing distance from the first electrode pad. The LED chip may further include a second electrode pad on a first side of the active-emitting diode (EVD) structure, wherein the first electrode pad is arranged close to a first edge of the EPD structure, and the second electrode pad is arranged close to a second edge of the EPD structure, with the second edge opposite the first edge; wherein the spacing between adjacent vias of the plurality of vias is at the center of the first side closest to the EPD structure. In some embodiments, the plurality of vias are arranged in a plurality of rows between a first electrode extension and a second electrode extension close to the first electrode pad; and the plurality of vias are arranged in a single row at a position between the first electrode extension and the second electrode extension, positioned further away from the first electrode pad than the plurality of rows. In some embodiments, the diameter of an individual through-hole of the plurality of vias increases with increasing distance from the first electrode pad. In some embodiments, the first electrode pad is an electrode strip arranged close to the first edge of the EPD structure. In some embodiments: the active light-emitting diode (ALD) structure includes a first edge and a second edge opposite to each other, and a third edge and a fourth edge opposite to each other; a plurality of through-holes are arranged in a first row of through-holes and a second row of through-holes, the first row of through-holes and the second row of through-holes extending between the first edge and the second edge of the ALD structure; and in the direction from the third edge to the fourth edge, the position of the through-holes in the first row of through-holes is offset relative to the position of the through-holes in the second row of through-holes. In some embodiments: the plurality of through-holes are arranged in the first row of through-holes and the second row of through-holes; and the total number of through-holes in the first row of through-holes is different from the total number of through-holes in the second row of through-holes.

[0012] In another embodiment, the LED chip includes: an active light-emitting diode (LED) structure comprising a first layer of a first conductor type, a second layer of a second conductor type opposite to the first conductor type, and an active layer between the first and second layers; an electrode pad on a first side of the LED structure, and a plurality of through-holes on a second side of the LED structure opposite to the first side, wherein the diameter of each individual through-hole varies with distance from the electrode pad; and a first electrode extension on the first side of the LED structure, electrically connected to the electrode pad, wherein the width of the first electrode extension varies with distance from the electrode pad. In some embodiments, the width of the first electrode extension gradually decreases with increasing distance from the electrode pad. The LED chip may further include a second electrode extension on the first side of the LED structure, electrically connected to the electrode pad, wherein the width of the second electrode extension gradually decreases with increasing distance from the electrode pad. In some embodiments, a plurality of through-holes are arranged in rows along a second side of the active light-emitting diode (EVD) structure, between portions of the EPD structure, and the plurality of through-holes are perpendicularly aligned with first and second electrode extensions. In some embodiments, the spacing between adjacent through-holes of the plurality of through-holes increases with increasing distance from the electrode pad. In some embodiments, the diameter of an individual through-hole of the plurality of through-holes increases with increasing distance from the electrode pad along the row. In some embodiments, the electrode pad is an electrode strip arranged close to a first edge of the EPD structure. In some embodiments: the EPD structure includes a first edge and a second edge opposite to each other, and a third edge and a fourth edge opposite to each other; the plurality of through-holes are arranged in a first row of through-holes and a second row of through-holes, both extending between the first and second edges of the EPD structure; and in the direction from the third edge to the fourth edge, the position of the through-holes in the first row of through-holes is offset relative to the position of the through-holes in the second row of through-holes. In some embodiments: a plurality of through holes are arranged in the first row of through holes and the second row of through holes; and the total number of through holes in the first row of through holes is different from the total number of through holes in the second row of through holes.

[0013] In another configuration, any of the aforementioned configurations and / or various independent configurations and features described herein may be combined individually or together to obtain additional advantages. Any of the various features and elements disclosed herein may be combined with one or more other features and elements disclosed herein, unless otherwise indicated herein.

[0014] Those skilled in the art will understand the scope of the invention and will recognize additional features of the invention after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings.

Implementation Method

[0028] The embodiments described below illustrate the information necessary for those skilled in the art to practice the embodiments, and depict the best mode of practicing the embodiments. Those skilled in the art will understand the concept of the invention and recognize the application of the concepts not specifically presented herein after reading the following illustrations in conjunction with the accompanying drawings. It should be understood that the concepts and applications described are within the scope of the present invention and the appended patent applications.

[0029] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, the elements should not be limited by the terms. The terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of the invention, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another component, it can be directly on or directly extending to the other component, or an intervening component may also be present. In contrast, when a component is referred to as "directly located on" or "directly extending to" another component, no intervening component is present. Similarly, it should be understood that when a component, such as a layer, region, or substrate, is referred to as "located above" or "extending above" another component, it can be directly located above or directly extending above the other component, or an intervening component may also be present. In contrast, when a component is referred to as "directly located above" or "directly extending above" another component, no intervening component is present. It should also be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or an intervening component may be present. In contrast, when a component is referred to as "directly connected" or "directly coupled" to another component, no intervening component is present.

[0031] Relative terms such as “below” or “above”, or “upper” or “lower”, or “horizontal” or “vertical” may be used herein to describe the relationship between one element, layer or region and another element, layer or region as illustrated in the figures. It should be understood that the terms mentioned above, as well as the terms discussed above, are intended to cover different device orientations other than those depicted in the figures.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a" and "the" are intended to include the plural forms as well. It should be further understood that the terms "comprising" and / or "including" as used herein specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should be further understood that the terms used herein should be interpreted as having the meaning appropriate to their meaning in the context of this specification and in the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0034] Embodiments are described herein with reference to illustrative drawings of embodiments of the invention. Therefore, the actual dimensions of layers and elements may differ, and variations in the shape of the drawings are anticipated due to, for example, manufacturing techniques and / or tolerances. For instance, areas illustrated or described as squares or rectangles may have circular or curved features, and areas shown as straight lines may have some irregularity. Therefore, the areas illustrated in the figures are illustrative, and their shapes are not intended to depict the precise shape of the areas of the device, nor are they intended to limit the scope of the invention. Furthermore, for illustrative purposes, the dimensions of structures or areas may be enlarged relative to other structures or areas, and thus, a general structure for illustrating the subject matter of the invention may be provided and may or may not be drawn to scale. Common elements between the figures may be shown herein with common element symbols and may not be described again subsequently.

[0035] This invention relates to a solid-state light-emitting device comprising a light-emitting diode (LED) chip, and more specifically to an LED chip structure having electrode extensions and a gradient via arrangement. The electrode extensions and vias are formed on opposite sides of the active LED structure as portions connecting the anode and cathode. The gradient via arrangement includes a variable diameter and / or variable via spacing relative to the electrode extensions and electrode pads. Additional structures include electrode extensions of variable width relative to the vias and / or electrode pads. The arrangement of gradient vias and corresponding electrode extensions is disclosed to increase the uniformity of re-bonding efficiency throughout the entire LED chip area and to provide improvements in current injection, current droop, and overall emission efficiency.

[0036] A light-emitting diode (LED) wafer can include an active light-emitting diode (ALD) structure or region having a number of different semiconductor layers arranged in different ways. The fabrication and operation of LEDs and their active structures are generally known in the art and are only briefly discussed herein. The layers of the ALD structure can be fabricated using known processes with suitable processing techniques using metal-organic chemical vapor deposition (MOCVD). The layers of the ALD structure can include a number of different layers and typically include an active layer sandwiched between n-type and p-type oppositely doped epitaxial layers, all continuously formed on a growth substrate. It should be understood that additional layers and elements can also be included in the ALD structure, including (but not limited to) buffer layers, nucleation layers, superlattice structures, undoped layers, cladding layers, contact layers, current-dispersing layers, light-extracting layers, and elements. The active layer can include single-quantum-well, multi-quantum-well, dual-heterogeneous structures, or superlattice structures.

[0037] Active light-emitting diode (ALD) structures can be fabricated from various material systems, some of which are based on group III nitrides. Group III nitrides refer to semiconductor compounds formed between nitrogen (N) and elements in group III of the periodic table, typically aluminum (Al), gallium (Ga), and indium (In). Gallium nitride (GaN) is a common binary compound. Group III nitrides also refer to ternary and quaternary compounds, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). For group III nitrides, silicon (Si) is a common n-type dopant and magnesium (Mg) is a common p-type dopant. Therefore, the active layer, n-type layer, and p-type layer can comprise one or more layers of GaN, AlGaN, InGaN, and AlInGaN that are undoped or doped with Si or Mg for III-nitride-based material systems. Other material systems include organic semiconductor materials and other III-V systems and related compounds such as gallium phosphide (GaP), gallium arsenide (GaAs), and indium phosphide (InP). Active light-emitting diode structures can be grown on a substrate that can contain many materials, such as sapphire, silicon carbide (SiC), aluminum nitride (AlN), and GaN.

[0038] Different embodiments of the active light-emitting diode (ALD) structure can emit light of different wavelengths depending on the composition of the active layer and the n-type and p-type layers. In some embodiments, the ALD structure can emit blue light with a peak wavelength range of approximately 430 nanometers (nm) to 480 nm. In other embodiments, the ALD structure can emit green light with a peak wavelength range of 500 nm to 570 nm. In other embodiments, the ALD structure can emit red or yellow light with a peak wavelength range of 600 nm to 700 nm. Some embodiments described herein are well adapted to various sub-ranges within 600 nm to 700 nm, such as peak wavelength ranges from 650 nm to 670 nm and / or from 610 nm to 630 nm, depending on the application. In some embodiments, the present invention can be applied to ALD structures that emit light with peak wavelengths in any region of the visible spectrum, for example, with peak wavelengths primarily in the range of 400 nm to 700 nm.

[0039] In other embodiments, the active light-emitting diode (LED) structure can be configured to emit light beyond the visible spectrum, including one or more portions of the ultraviolet (UV) spectrum, infrared (IR) spectrum, or near-infrared spectrum. The UV spectrum is typically divided into three wavelength range categories denoted by the letters A, B, and C. In this manner, UV-A light is typically defined as having a peak wavelength in the range of 315 nm to 400 nm, UV-B is typically defined as having a peak wavelength in the range of 280 nm to 315 nm, and UV-C is typically defined as having a peak wavelength in the range of 100 nm to 280 nm. UV LEDs are particularly suitable for applications related to the disinfection of microorganisms in air, water, and surfaces, as well as other applications. In other applications, the UV LED may also incorporate one or more luminescent materials to provide the LED package with dense emission having a broad spectrum and improved color quality for visible light applications. The near-infrared and / or infrared wavelengths of the LED structure of the present invention may have a wavelength of approximately 700 nm, such as in the range of 750 nm to 1100 nm or greater.

[0040] Light emitted from the active layer or region of an LED chip typically travels in multiple directions. For directional applications, internal mirrors or external reflective surfaces can be used to redirect more light as far as possible toward the desired emission direction. Internal mirrors may comprise single or multiple layers. Some multilayer mirrors comprise a metal reflector layer and a dielectric reflector layer, wherein the dielectric reflector layer is disposed between the metal reflector layer and a plurality of semiconductor layers. A passivation layer is disposed between the metal reflector layer and first and second electrical contacts, wherein the first electrical contact is disposed to be electrically connected to a first semiconductor layer, and the second electrical contact is disposed to be electrically connected to a second semiconductor layer. For single or multilayer mirrors containing surfaces with a reflectivity of less than 100%, some light may be absorbed by the mirror. Additionally, light redirected through the active light-emitting diode structure may be absorbed by other layers or elements within the LED chip.

[0041] As used herein, a layer or region may be considered "transparent" when at least 80% of the emitted radiation impinging on a layer or region of the light-emitting device passes through the layer or region. Furthermore, as used herein, a layer or region may be considered "reflective" or embody as a "mirror" or "reflector" when at least 80% of the emitted radiation impinging on a layer or region of a light-emitting diode is reflected. In some embodiments, the emitted radiation includes visible light, such as blue and / or green light-emitting diodes with or without luminescent material. In other embodiments, the emitted radiation may include non-visible light. In some embodiments, a "light-transmitting" material may be configured to transmit at least 50% of the emitted radiation of the desired wavelength.

[0042] This invention is useful for LED chips with geometric variations, including vertical geometry. Vertical geometry LED chips typically include anode and cathode connections on opposite sides of the LED chip or facing the LED chip. In some embodiments, vertical geometry LED chips may also include a growth substrate disposed between the anode and cathode connections. In other embodiments, the LED chip structure may include a carrier base and the growth substrate is removed. In yet another embodiment, any of the principles described herein can be applied to flip-chip structures, in which the anode and cathode connections are configured from the same side of the LED chip for mounting the flip-chip to another surface.

[0043] This invention is useful for LED chips with a current-dispersing structure that distributes current throughout the active light-emitting diode (EVD) structure region. The current-dispersing structure may include a conductive layer, contacts, electrode extensions or fingers, and / or vias that effectively route current throughout the LED chip to reduce variations in current congestion. In a vertical LED chip structure, n-type and p-type contacts are typically formed from opposite sides of the EPD structure. For larger area LED chips, contacts and corresponding electrode extensions may be arranged along the top of the EPD structure to contact one side of the EPD structure, while bottom contacts and corresponding vias may be arranged to contact the opposite side of the EPD structure. As used herein, an electrode extension may refer to an elongated conductive material continuous with and extending from an electrode pad or contact pad of the LED chip. The electrode pad may accept external electrical connections, such as wire bonding, and the electrode extension extends from the electrode pad used for current dispersion. As used herein, the terms electrode extension, contact extension, electrode finger, and contact finger may be used interchangeably.

[0044] As noted above, the principles of the present invention can be applied to active light emitting diode (ALD) structures that emit peak wavelengths spanning both visible and invisible ranges. In some embodiments, the present invention is particularly useful for ALD structures configured to emit red or yellow light with peak wavelengths typically ranging from 600 nm to 700 nm. As disclosed herein, certain embodiments may be well suited to various sub-ranges within the 600 nm to 700 nm range, such as peak wavelength ranges from 650 nm to 670 nm and / or from 610 nm to 630 nm, depending on the application. Such ALD structures may include GaP and / or GaAs-based materials, such as AlInGaP materials for any of the n-type, p-type, and active layers.

[0045] FIG1 is a cross-section illustrating an electrode extension 12 and a via 14 of a portion of a light-emitting diode wafer 10 according to the principles of the present invention, the electrode extension and the via being arranged on opposite sides of an active light-emitting diode structure 16. In FIG1, the active light-emitting diode structure 16 is shown in general as a p-type layer 18, an n-type layer 22 and an active layer 20 therebetween. It is understood that the active light-emitting diode structure 16 may include additional layers and each of the p-type layer 18, the n-type layer 22 and the active layer 20 may include multiple sublayers. The active light-emitting diode structure 16 may be formed on a substrate 24. In some embodiments, the substrate 24 is embodied as the active light-emitting diode structure 16 being supported on a carrier substrate. In such an embodiment, the active light-emitting diode structure 16 may first be grown on a growth substrate, then the substrate 24 (e.g., a carrier substrate) is joined to the side of the active light-emitting diode structure opposite the growth substrate, and then the growth substrate is removed. In some embodiments, the p-type layer 18, as illustrated in FIG. 1, is located between the active layer 20 and the carrier substrate 24. In other embodiments, it is understood that the doping or conductor order can be reversed, such that the n-type layer 22 is located between the active layer 20 and the carrier substrate 24. The discussion in FIG. 1 below is in the case where the p-type layer 18 is closer to the carrier substrate 24 than the n-type layer 22. However, it is understood that the same principle applies to embodiments where the conductor type is reversed. The substrate 24 may comprise many different materials, with silicon or other conductive materials being well-suited for vertical wafer structures.

[0046] In FIG. 1, the electrode extension 12 is on the first side 16' (or top side) of the active light-emitting diode structure 16 relative to the carrier substrate 24. As will be shown in the following figures, the electrode extension 12 may extend from a top electrode pad, which is also on the first side 16'. The electrode extension 12 provides a portion of an n-contact connected to the n-type layer 22. The LED chip 10 may include one or more electrically insulating layers 26 between the active light-emitting diode structure 16 and the carrier substrate 24. In one example, the insulating layer 26 may form part of a mirror or reflective layer positioned to redirect downward-propagating light back through the active light-emitting diode structure 16 and out from the top side of the LED chip 10. In this case, a via 14 is arranged on the second side 16'' (or bottom side) of the active light-emitting diode structure 16 relative to the first side 16' to provide a conductive path through the insulating layer 26 between the carrier substrate 24 and the active light-emitting diode structure 16. The bottom electrode pad 27 may be formed on the bottom of the carrier substrate 24. By way of example, the via 14 provides a portion of the p-contact connection between the bottom electrode pad 27 and the p-type layer 18.

[0047] As illustrated in Figure 1, distance D can be defined as the lateral distance or interval between the electrode extension 12 and the via 14, as measured in the horizontal plane between the peripheral edge closest to the electrode extension 12 and the via 14. Since the electrode extension 12 and the via 14 are on opposite sides of the active light-emitting diode structure 16, distance D is measured between a first plane P1 perpendicularly aligned to the edge of the electrode extension 12 and a second plane P2 perpendicularly aligned to the edge of the via 14 closest to the electrode extension 12. Upon electrical activation, the active light-emitting diode structure 16 generates light by recombination of electrons and holes approaching the active layer 20. Increased recombination efficiency is achieved in the portion of the active light-emitting diode structure 16 between the electrode extension 12 and the via 14. As illustrated, to reduce the amount of light loss absorbed by the electrode extension 12, the via 14 can be laterally spaced from the electrode extension 12 by distance D. For example, electrode extension 12 may include a conductive metal, such as gold (Au) or an alloy thereof, which may reflect and / or absorb light generated in active light-emitting diode structure 16. The increased amount of light emitted by positioning the via 14 at a lateral distance (the lateral distance being offset by a distance D from a position directly below electrode extension 12) can escape without interacting with electrode extension 12. However, the electrostatic potential decreases with increasing distance D; therefore, if distance D is too large, the gap between via 14 and electrode extension 12 may contain regions with significantly reduced field strength, thereby reducing re-bonding efficiency.

[0048] FIG2 is a top view of an LED wafer 28 similar to an LED wafer 10, arranged with electrode extensions 12 and through-holes 14 of variable diameter, according to the principles of the present invention. Since the view is from the top of the LED wafer 28, the electrode extensions 12 are visible on the top surface of the LED wafer 28. Although the through-holes 14 are below the top surface of the LED wafer 28, they are still visible in perspective as shown in FIG2. The electrode extensions 12 are interconnected in a continuous manner with one or more top electrode pads 30 on the top surface. In this way, the electrode pads 30 can accept external electrical connections, such as wire bonding, and the electrode extensions 12 distribute current along the region of the LED wafer 28. In FIG2, the electrode pads 30 are arranged close to the same edge of the LED wafer 28, and the electrode extensions 12 extend linearly toward the opposite edge of the LED wafer 28. In some embodiments, the electrode extensions 12 and through-holes 14 are arranged in alternating linear rows when viewed from the top. This arrangement provides a variable distance between each point on each electrode extension 12 and the nearest via or vias 14. Therefore, certain regions between the electrode extension 12 and the nearest via 14 can be located in areas of reduced field strength, exhibiting reduced rebonding efficiency. As illustrated, the diameter of the via 14 varies with its distance from the electrode pad 30 to improve rebonding efficiency. For example, the diameter of the via 14 can decrease from larger to smaller within each row and gradually decrease with increasing distance from one or more of the electrode pads 30. In this way, vias 14 with larger diameters are positioned closer to the electrode pad 30, where current injection and / or potential can be highest.

[0049] Similar to the LED chip 28 in FIG. 2, FIG. 3 is a top view of the LED chip 32, except that the diameter of the via 14 increases with increasing distance from the electrode pad 30. As illustrated, vias 14 with smaller diameters are positioned closer to the electrode pad 30, and vias 14 with the largest diameters are located at or near the distal end of the electrode extension 12, which is close to the opposite edge of the LED chip 32. In such an embodiment, vias 14 with larger diameters are located at the furthest point from the electrode pad 30, where current injection can be minimized. The gradient of via 14 having a larger to smaller diameter with distance from the electrode pad 30 (e.g., FIG. 2) or a smaller to larger diameter with distance from the electrode pad 30 (e.g., FIG. 3) can be determined by a variation factor. Such a factor may include electrostatic field differences related to variations in the LED chip structure, material system, and / or the current dissipation capability of the electrode extension 12. Other factors and / or benefits include helping to drive a more uniform distribution of carriers (i.e., holes and electrons), which leads to improved recombination efficiency for light generation and reduced localized heating from localized carrier concentration.

[0050] Similar to the LED chip 28 in FIG. 2, FIG. 4 is a top view of the LED chip 34, except that the diameter of the vias 14 decreases and then increases along each row of vias 14. In some embodiments, the electrode pads 30 may be arranged close to the opposite sides of the LED chip 34. Therefore, the diameter of the vias 14 in each row may decrease with increasing distance from each opposite electrode pad 30. In this way, the vias 14 with smaller diameters are arranged along the central portion of the LED chip 34, which is between the opposite electrode pads 30. In some embodiments, one or more, or even all, of the electrode extensions 12 may form a continuous structure with two electrode pads 30.

[0051] Similar to the LED chip 34 in FIG. 4, FIG. 5 is a top view of the LED chip 36, except that the diameter of the vias 14 increases and then decreases along each row of vias 14. In some embodiments, the electrode pads 30 may be arranged close to the opposite sides of the LED chip 36. Therefore, the diameter of each row of vias 14 may increase with the increasing distance from each opposite electrode pad 30 toward the center of the LED chip 36. In this way, vias 14 with larger diameters are arranged along the central portion of the LED chip 36, which lies between the opposite electrode pads 30.

[0052] Similar to the LED chip 36 in FIG. 5, FIG. 6 is a top view of the LED chip 38 and further includes a plurality of electrode pads 30 close to each opposite edge of the LED chip 38. As illustrated, the diameter of the via 14 in each row increases with increasing distance from each opposite electrode pad 30 toward the center of the LED chip 38, similar to FIG. 5. By having a plurality of electrode pads 30 close to each opposite edge, further improvements in current injection, current droop, and efficiency can be achieved. As in the previous embodiment, one or more, or even all, of the electrode extensions 12 can be formed into a continuous structure having all the electrode pads 30.

[0053] Similar to the LED chip 32 in FIG3, FIG7 is a top view of the LED chip 40. In this embodiment, the spacing of the vias 14 varies with the distance from the electrode pads 30. As used herein, spacing may refer to the distance between adjacent or next-to-next-adjacent vias 14 measured between the center points of adjacent vias 14. As illustrated, the spacing between adjacent vias 14 is smaller at the edge of the LED chip 40 near the electrode pads 30. In this way, an increased number of vias 14 can be located close to the electrode pads 30, where current injection can be highest. Within each row of vias 14, the spacing may increase with increasing distance from the electrode pads 30. In some embodiments, the diameter of the vias 14 may also increase within each row of vias 14 with increasing distance from the electrode pads 30. For example, in FIG7, vias 14 with larger diameters are located near the edge of the LED chip 40 opposite the electrode pads 30.

[0054] Similar to the LED chip 40 in FIG. 7, FIG. 8 is a top view of the LED chip 42, except that the electrode pads 30 are positioned near the opposite edges of the LED chip 42. This arrangement allows the spacing between adjacent vias 14 in each row to increase with increasing distance from each electrode pad 30 toward the center of the LED chip 42. Therefore, the maximum spacing between adjacent vias 14 is formed at or near the center of each row of vias 14. As illustrated, the diameter of the vias 14 can first increase and then decrease along each row of vias 14. In this way, the diameter of the vias 14 in each row can increase with increasing distance from each opposite electrode pad 30 toward the central portion of the LED chip 42, so that vias 14 with larger diameters are arranged along the central portion of the LED chip 42.

[0055] Similar to the LED chip 40 in FIG. 7, the embodiment in FIG. 9 is a top view of the LED chip 44, which forms multiple rows of through holes 14 between portions adjacent to the electrode extensions 12. As described with reference to FIG. 7, the spacing and diameter of the through holes 14 closest to the electrode pads 30 can be smaller than the spacing and diameter of the through holes 14 further away from the electrode pads 30. In this configuration, the smaller spacing and diameter of the through holes 14 closer to the electrode pads 30 allow for multiple rows of through holes 14 at these locations. With increasing distance from the electrode pads 30, the spacing and diameter of the through holes 14 can be increased so that the through holes 14 are arranged in a single row between adjacent electrode extensions 12.

[0056] Similar to the LED chip 40 of FIG. 7, the embodiment of FIG. 10 is a top view of the LED chip 46, wherein the width of one or more of the electrode extensions 12 varies with distance from one or more of the electrode pads 30. For example, the width of one or more electrode extensions 12 is larger near the electrode pads 30 and narrower near the edge of the LED chip 46 opposite to the electrode pads 30. In this way, the electrode extensions 12 are formed to cover an increased surface area of ​​the LED chip 46 near the electrode pads 30, where current injection can be highest near the electrode pads 30. As illustrated, the vias 14 in each row may have a diameter and / or spacing that increases with increasing distance from the electrode pads 30. Thus, the largest diameter via with the largest spacing may be located furthest from the electrode pads 30 and narrowest near the electrode extensions 12. The relative nature of the decreasing width of the electrode extensions 12, and the increasing spacing and / or diameter of the vias 14, can increase the uniformity of the lateral spacing between each via 14 and one or more of the nearest electrode extensions 12. In this context, the lateral spacing can be measured perpendicular to the direction of each row of vias 14. Thus, the position of each via 14 can be set in a region with a higher potential to increase emission efficiency, while also improving the current distribution across the LED chip 46.

[0057] Similar to the LED chip 32 of FIG. 3, FIG. 11 is a top view of the LED chip 48, wherein the electrode pad 30 is an electrode strip near the edge of the LED chip 32. As illustrated, each of the electrode extensions 12 is connected to the electrode pad 30 near the edge of the LED chip 48. In some embodiments, the electrode pad 30 is a single electrode pad that extends continuously between each of the electrode extensions 12. In yet another embodiment, the electrode pad 30 has a length along the edge of the LED chip 48, and the length is greater than the distance between the outermost rows of vias measured in the array of vias 14. The single electrode pad 30 in the strip form as illustrated in FIG. 11 is advantageous for high-current applications. In this case, multiple wire connections can be electrically coupled to the single electrode pad 30. The diameter within each row and / or the spacing of the vias 14 can also vary as previously described. The electrode pad 30 as illustrated in FIG. 11 can be implemented as any of the previous embodiments of FIG. 2 to FIG. 10.

[0058] Similar to the LED wafer 48 of FIG. 11, FIG. 12 is a top view of the LED wafer 50, in which the position of the vias 14 in each row is offset from the position of the vias 14 in adjacent rows. The rows of vias 14 extend between opposite edges of the LED wafer 50. As illustrated, the offset position of the vias 14 in each row avoids forming a row of vias 14 in a direction between other opposite edges of the LED wafer 50 or perpendicular to the row. Such an arrangement can provide improved uniformity of the vias 14 relative to the electrode extension 12, thereby increasing carrier distribution uniformity. In some embodiments, the offset of the vias 14 inherently provides a different total number of vias in adjacent rows. The diameter and / or spacing of the vias 14 in each row may also vary as previously described. The arrangement of vias 14 as illustrated in FIG. 12 can be implemented in any of the previous embodiments of FIG. 2 through 11.

[0059] As described above, the principles of the present invention provide a varied layout of vias, electrode extensions, and / or electrode pads, which are customized to localize electrostatic field differences in various LED chip structures. Such a layout can provide a carrier (i.e., holes and electrons) distribution with improved uniformity, thereby improving the recombination efficiency for light generation while reducing localized heating from local carrier concentration.

[0060] It is conceivable that any of the foregoing configurations and / or the various individual configurations and features described herein can be combined to obtain additional advantages. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0061] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims. [Simplified Explanation of the Diagram]

[0015] The accompanying drawings, together with the accompanying drawings, form part of this specification illustrating several aspects of the present invention, and together with the description serve to explain the principles of the present invention.

[0016] [Figure 1] is a cross-section of an electrode extension and a through hole of a portion of a light-emitting diode (LED) chip according to the principle of the present invention, wherein the electrode extension and the through hole are arranged on opposite sides of the active light-emitting diode structure.

[0017] [Figure 2] is a top view of an LED chip based on the principle of the present invention, which is similar to the layout of the electrode extension with variable diameter and through hole in Figure 1.

[0018] [Figure 3] is a top view of an LED chip, which is similar to the LED chip in Figure 2, except that the diameter of the through hole increases with the increasing distance from the electrode pad.

[0019] [Figure 4] is a top view of an LED chip, which is similar to the LED chip in Figure 2, except that the diameter of the through holes decreases and then increases along each row of through holes.

[0020] [Figure 5] is a top view of an LED chip, which is similar to the LED chip in Figure 4, except that the diameter of the through holes increases and then decreases along each row of through holes.

[0021] [Figure 6] is a top view of an LED chip, which is similar to the LED chip in Figure 5, and further includes multiple electrode pads near each opposite edge of the LED chip.

[0022] [Figure 7] is a top view of an LED chip similar to that in Figure 3. In this embodiment, the spacing of the through holes varies with the distance from the electrode pad.

[0023] [Figure 8] is a top view of an LED chip similar to that in Figure 7, except that the electrode pads are positioned close to the relative edges of the LED chip.

[0024] [Figure 9] is a top view of an LED chip similar to that in Figure 7, wherein multiple rows of through holes are formed between portions of the adjacent electrode extension.

[0025] [Figure 10] is a top view of an LED chip similar to that in Figure 7, wherein the width of one or more of the electrode extensions varies with the distance from one or more of the electrode pads.

[0026] [Figure 11] is a top view of an LED chip similar to that in Figure 3. In this embodiment, the electrode pad is an electrode strip close to the edge of the LED chip.

[0027] [Figure 12] is a top view of an LED chip similar to that in Figure 11, in which the position of the through hole in each row is offset from the position of the through hole in the adjacent row.

Claims

1. A light-emitting diode chip, comprising: An active light-emitting diode (ALD) structure includes a first layer of a first conductor type, a second layer of a second conductor type relative to the first conductor type, and an active layer between the first layer and the second layer; a first electrode pad on a first side of the ALD structure; a first electrode extension and a second electrode extension arranged parallel to each other on the first side of the ALD structure, wherein the first electrode extension and the second electrode extension are electrically connected to the first electrode pad; and a plurality of through holes on a second side of the ALD structure relative to the first side, the plurality of through holes being located between portions of the ALD structure perpendicularly aligned with the first electrode extension and the second electrode extension, and the diameter of each individual through hole varying with distance from the first electrode pad.

2. The light-emitting diode wafer as claimed in claim 1, wherein the plurality of vias are arranged in rows throughout the second side of the active light-emitting diode structure.

3. The light-emitting diode wafer as claimed in claim 1, wherein the diameter of each of the plurality of vias gradually decreases with increasing distance from the first electrode pad.

4. The light-emitting diode wafer as claimed in claim 1, wherein the diameter of each of the plurality of vias gradually increases with increasing distance from the first electrode pad.

5. The light-emitting diode chip as claimed in claim 1, further comprising a second electrode pad on the first side of the active light-emitting diode structure, wherein the first electrode pad is arranged close to a first edge of the active light-emitting diode structure, the second electrode pad is arranged close to a second edge of the active light-emitting diode structure, and the second edge is opposite to the first edge.

6. The light-emitting diode wafer as claimed in claim 5, wherein the diameter of each of the plurality of vias gradually decreases with increasing distance from the first electrode pad and the second electrode pad toward the center of the active light-emitting diode structure.

7. The light-emitting diode wafer as claimed in claim 5, wherein the diameter of each of the plurality of vias gradually increases with increasing distance from the first electrode pad and the second electrode pad toward the center of the active light-emitting diode structure.

8. The light-emitting diode chip as described in claim 1, further comprising: The second electrode pad, the third electrode pad, and the fourth electrode pad are located on the first side of the active light-emitting diode structure; wherein the first electrode pad and the second electrode pad are arranged close to the first edge of the active light-emitting diode structure, and the third electrode pad and the fourth electrode pad are arranged close to the second edge of the active light-emitting diode structure, with the second edge opposite to the first edge.

9. The light-emitting diode wafer as claimed in claim 1, wherein the first electrode pad is an electrode strip arranged close to a first edge of the active light-emitting diode structure.

10. The light-emitting diode chip as described in claim 1, wherein: The active light-emitting diode structure includes a first edge and a second edge opposite to each other, and a third edge and a fourth edge opposite to each other; the plurality of through holes are arranged in a first row of through holes and a second row of through holes, both the first row of through holes and the second row of through holes extending between the first edge and the second edge of the active light-emitting diode structure; and in the direction from the third edge to the fourth edge, the position of the through holes in the first row of through holes is offset relative to the position of the through holes in the second row of through holes.

11. The light-emitting diode chip as described in claim 1, wherein: The plurality of through holes are arranged in the first row of through holes and the second row of through holes; and the total number of through holes in the first row of through holes is different from the total number of through holes in the second row of through holes.

12. A light-emitting diode chip, comprising: An active light-emitting diode (ALD) structure includes a first layer of a first conductor type, a second layer of a second conductor type relative to the first conductor type, and an active layer between the first layer and the second layer; a first electrode pad on a first side of the ALD structure; a first electrode extension and a second electrode extension arranged parallel to each other on the first side of the ALD structure, wherein the first electrode extension and the second electrode extension are electrically connected to the first electrode pad; and a plurality of through holes on a second side of the ALD structure relative to the first side, the plurality of through holes being located between portions of the ALD structure perpendicularly aligned with the first electrode extension and the second electrode extension, wherein the spacing between adjacent through holes varies with distance from the first electrode pad, and the diameter of individual through holes varies with distance from the first electrode pad.

13. The light-emitting diode wafer as claimed in claim 12, wherein the plurality of vias are arranged in rows throughout the second side of the active light-emitting diode structure, and the spacing increases with increasing distance from the first electrode pad.

14. The light-emitting diode wafer as claimed in claim 13, wherein the diameter of each of the plurality of vias increases with increasing distance from the first electrode pad along the row.

15. The light-emitting diode chip as described in claim 12, further comprising: A second electrode pad is disposed on the first side of the active light-emitting diode structure, wherein the first electrode pad is arranged close to the first edge of the active light-emitting diode structure, and the second electrode pad is arranged close to the second edge of the active light-emitting diode structure, with the second edge opposite to the first edge; wherein the spacing between adjacent through holes of the plurality of through holes is at the center of the first side closest to the active light-emitting diode structure.

16. The light-emitting diode chip as described in claim 12, wherein: The plurality of through holes are arranged in a plurality of rows between the first electrode extension and the second electrode extension near the first electrode pad; and the plurality of through holes are arranged in a single row at a position between the first electrode extension and the second electrode extension, the position being further away from the first electrode pad than the plurality of rows.

17. The light-emitting diode wafer as claimed in claim 16, wherein the diameter of each of the plurality of vias increases with increasing distance from the first electrode pad.

18. The light-emitting diode wafer as claimed in claim 12, wherein the first electrode pad is an electrode strip arranged close to a first edge of the active light-emitting diode structure.

19. The light-emitting diode chip as described in claim 12, wherein: The active light-emitting diode structure includes a first edge and a second edge opposite to each other, and a third edge and a fourth edge opposite to each other; the plurality of through holes are arranged in a first row of through holes and a second row of through holes, the first row of through holes and the second row of through holes extending between the first edge and the second edge of the active light-emitting diode structure; and in the direction from the third edge to the fourth edge, the position of the through holes in the first row of through holes is offset relative to the position of the through holes in the second row of through holes.

20. The light-emitting diode chip as described in claim 12, wherein: The plurality of through holes are arranged in the first row of through holes and the second row of through holes; and the total number of through holes in the first row of through holes is different from the total number of through holes in the second row of through holes.

21. A light-emitting diode chip, comprising: An active light-emitting diode (ALD) structure includes a first layer of a first conductor type, a second layer of a second conductor type opposite to the first conductor type, and an active layer between the first layer and the second layer; an electrode pad on a first side of the ALD structure, having a plurality of through holes on a second side of the ALD structure opposite to the first side, wherein the diameter of each of the plurality of through holes varies with distance from the electrode pad; and a first electrode extension on the first side of the ALD structure, the first electrode extension being electrically connected to the electrode pad, wherein the width of the first electrode extension varies with distance from the electrode pad, and the direction of the first electrode extension is parallel to the plurality of through holes.

22. The light-emitting diode wafer as claimed in claim 21, wherein the width of the first electrode extension gradually decreases with increasing distance from the electrode pad.

23. The light-emitting diode wafer as claimed in claim 22, further comprising a second electrode extension on the first side of the active light-emitting diode structure, the second electrode extension being electrically connected to the electrode pad, wherein the width of the second electrode extension gradually decreases with increasing distance from the electrode pad.

24. The light-emitting diode wafer as claimed in claim 23, wherein the plurality of vias are arranged in a row throughout the second side of the active light-emitting diode structure, the row being between portions of the active light-emitting diode structure in which the plurality of vias are perpendicularly aligned with the first electrode extension and the second electrode extension.

25. The light-emitting diode wafer as claimed in claim 24, wherein the spacing between adjacent vias of the plurality of vias increases with increasing distance from the electrode pad.

26. The light-emitting diode wafer as claimed in claim 24, wherein the diameter of each of the plurality of vias increases with increasing distance from the electrode pad along the row.

27. The light-emitting diode wafer as claimed in claim 21, wherein the electrode pad is an electrode strip arranged close to a first edge of the active light-emitting diode structure.

28. The light-emitting diode chip as described in claim 21, wherein: The active light-emitting diode structure includes a first edge and a second edge opposite to each other, and a third edge and a fourth edge opposite to each other; the plurality of through holes are arranged in a first row of through holes and a second row of through holes, the first row of through holes and the second row of through holes extending between the first edge and the second edge of the active light-emitting diode structure; and in the direction from the third edge to the fourth edge, the position of the through holes in the first row of through holes is offset relative to the position of the through holes in the second row of through holes.

29. The light-emitting diode chip as described in claim 21, wherein: The plurality of through holes are arranged in the first row of through holes and the second row of through holes; and the total number of through holes in the first row of through holes is different from the total number of through holes in the second row of through holes.

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