Integrated circuit packages and forming method thereof

Abstract

This disclosure provides an integrated circuit package and a method for forming the same. The integrated circuit package may include an integrated circuit die and a dielectric material on the sidewalls of the integrated circuit die. The integrated circuit die may include a substrate, a protective structure in the substrate, an interconnect structure on the substrate, and a sealing ring structure in the interconnect structure that contacts the protective structure. The protective structure and the substrate may contain the same semiconductor material, and the protective structure may include a first dopant and a second dopant different from the first dopant. The interconnect structure may include a dielectric layer and conductive features in the dielectric layer. The sealing ring structure may surround the conductive features of the interconnect structure in a top-down view.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, improvements in integrated density are due to iterative reductions in the minimum feature size, which allows more electronic components to be integrated into a given area. As the demand for miniaturized electronic devices continues to increase, the need for smaller and more innovative semiconductor die packaging technologies has also emerged. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides many different implementations or embodiments to implement the different features of this disclosure. The specific implementations or embodiments of the composition or arrangement described below are used to simplify this disclosure. Of course, these are merely embodiments and are not intended to limit this disclosure. For example, in the description below, a first feature is formed on or above a second feature, which may include an implementation where the formed first feature and the second feature are in direct contact, and may also include an implementation where an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplification and clarity, and does not in itself specify the relationship between the various implementations and / or configurations.

[0006] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower," "above," and "upper" may be used in this disclosure to describe the relationship between an element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device during use or operation. The device may also be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptive symbols used in this disclosure may be interpreted accordingly.

[0007] According to some embodiments, an integrated circuit package includes an integrated circuit die in one layer and another integrated circuit die and inactive die in another layer. A gap-filling dielectric may be formed around the integrated circuit die and inactive die. The integrated circuit die and inactive die may include a protective structure that separates the sealing ring structure from the substrate. The protective structure can reduce or prevent the release of static charge generated on the substrate through the sealing ring structure, thereby reducing or preventing cracks formed by electrostatic discharge in the integrated circuit die, inactive die, and / or gap-filling dielectric. Therefore, the reliability of the integrated circuit package can be improved.

[0008] Figures 1 through 5A are views illustrating various intermediate steps in the process of forming an integrated circuit die 50 according to a partial embodiment. As shown in Figure 1, a protective structure 51 is formed in a wafer 52. Features that may be formed on the wafer 52 may subsequently be singulated to form discrete integrated circuit dies 50, as described in more detail below. For illustrative purposes, the area of ​​the wafer 52 where the integrated circuit die 50 may be formed is shown as the integrated circuit die 50. After the singulation process, a substrate 52 may be formed on the wafer 52, which may be part of the integrated circuit die 50. The protective structure 51 may include a pn junction and may be referred to as a diode. The protective structure 51 may reduce or prevent cracks formed in or around the integrated circuit die 50 due to electrostatic discharge, as described in more detail below.

[0009] Wafer 52 may contain semiconductor materials, such as silicon, germanium, etc. Wafer 52 and subsequently formed substrate 52 may have active surfaces (e.g., the upward-facing surface in Figure 1), sometimes referred to as the front side, and inactive surfaces (e.g., the downward-facing surface in Figure 1), sometimes referred to as the back side. Components (not shown separately) may be disposed on the active surfaces of wafer 52. Components may be transistors, capacitors, resistors, etc., and may be part of the integrated circuit die 50 after a subsequent die-cutting process.

[0010] In the embodiment illustrated in Figure 1, the protective structure 51 includes a first portion 51A and a second portion 51B. The surface of the first portion 51A is exposed and can be coplanar with the active surface of the wafer 52. The first portion 51A may contain a first dopant and the second portion 51B may contain a second dopant. The first dopant may be different from the second dopant. The first dopant and the second dopant may be of different conductivity types, and a pn junction may be formed at the interface between the first portion 51A and the second portion 51B. In some embodiments, the first dopant may be an n-type dopant, such as phosphorus, arsenic, etc., and the second dopant may be a p-type dopant, such as boron, aluminum, gallium, indium, etc. In some embodiments, the first dopant may be a p-type dopant, such as boron, aluminum, gallium, indium, etc., and the second dopant may be an n-type dopant, such as phosphorus, arsenic, etc.

[0011] The protective structure 51 can be formed in the wafer 52 through a portion of the doped wafer 52. Therefore, the protective structure 51 can contain the same material as the wafer 52. The protective structure 51 can be formed through a masking step and two doping steps. The mask can be formed on the active surface of the wafer 52 using a suitable lithography process. The pattern of the mask may expose portions in the wafer 52, where the protective structure 51 can be formed and cover the remaining portions of the wafer 52. The first doping step can be performed using a suitable ion implantation process to form a second portion 51B having a second dopant. An annealing process can be performed after the ion implantation process. The dopant concentration of the second dopant in the second portion 51B can be in the range of approximately 1 x 10¹⁵ cm⁻³ to approximately 1 x 10²⁰ cm⁻³. The second doping step can be performed using a suitable ion implantation process to form a first portion 51A having a first dopant. An annealing process can be performed after the ion implantation process. The dopant concentration of the first dopant in the first part 51A can be in the range of about 1 x 10¹⁵ cm⁻³ to about 1 x 10²⁰ cm⁻³.

[0012] In Figure 2, an interconnect structure 54 is formed on the active surface of the wafer 52, a sealing ring structure 55 is formed in the interconnect structure 54, a dielectric layer 56 is formed on the interconnect structure 54, and a die connector 58 is formed in the dielectric layer 56. The interconnect structure 54 interconnects elements on the active surface of the wafer 52 (e.g., substrate 52) to form a circuit in the subsequently formed integrated circuit die 50. The interconnect structure 54 may include a dielectric layer 54A and conductive features 54B in the dielectric layer 54A. The dielectric layer 54A may be formed by a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, etc. The conductive features 54B may include metal lines and vias, which may be formed in the dielectric layer 54A by a damascene process, such as a single damascene process, a dual damascene process, etc. The conductive features 54B may be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, etc. The conductive feature 54B can be electrically coupled to elements on the active surface of the wafer 52. The sealing ring structure 55 may include conductive lines or vias, which may be formed through the same or similar processes as the conductive feature 54B and made of the same or similar materials. The sealing ring structure 55 can be electrically isolated from the conductive feature 54B and elements on the active surface of the wafer 52. The sealing ring structure 55 may extend through the interconnect structure 54 and contact the protective structure 51.

[0013] The dielectric layer 56 can be formed on the interconnect structure 54 through a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, etc. The dielectric layer 56 may contain silicon oxide, silicon nitride, etc. The die connector 58 can be formed in the dielectric layer 56 through a damascene process, such as a single damascene process, dual damascene process, etc. The die connector 58 may extend through the dielectric layer 56. The die connector 58 may be formed of a conductive material, such as copper, aluminum, etc. The dielectric layer 56 and the die connector 58 can be used in subsequent bonding processes to bond the integrated circuit die 50 to other features.

[0014] In Figure 3, a photomask 66 is formed on the dielectric layer 56 and the die connector 58, and an opening 70 passes through the portion of the wafer 52 exposed by the photomask 66. The photomask 66 can be a photoresist and can be formed by spin coating or the like, and patterned by a suitable lithography process. The opening 70 can pass through the portion of the wafer 52 exposed by the photomask 66 by a suitable dicing process. In some embodiments, the dicing process is a mechanical dicing process using a saw or the like. In some embodiments, the dicing process is a chemical dicing process using a suitable plasma source. After the dicing process, the photomask 66 can be removed using an acceptable ashing or stripping process.

[0015] In Figure 4, the structure shown in Figure 3 is attached to the carrier 74 via an adhesive 75, and the wafer 52 is thinned on the inactive surface. The carrier 74 can be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 74 can be a wafer. In some embodiments, the adhesive 75 is a heat-release layer, such as an epoxy-based photothermal conversion release material, which loses its adhesive properties when heated. In some embodiments, the adhesive 75 is a UV adhesive, which loses its adhesive properties when exposed to ultraviolet light. A thinning process is then performed on the inactive surface of the wafer 52, resulting in the dicing of the structure shown in Figure 3 and the formation of the integrated circuit die 50. The thinning process can be performed using chemical mechanical polishing, polishing processes, etch-back processes, or combinations thereof, which can remove portions of the wafer 52 until the opening 70 is exposed on the inactive surface of the wafer 52. Therefore, the wafer 52 can be diced into discrete substrates 52, which can be part of the integrated circuit die 50. The cleaning or rinsing process can be performed after the thinning process. Then the integrated circuit die 50 can be separated from the carrier 74.

[0016] Figures 5A and 5B illustrate all individual integrated circuit chips 50. Figure 5A is a cross-sectional view and Figure 5B is a top view. The cross-sectional view of Figure 5A may be along the reference cross section A-A' shown in the top view of Figure 5B. The conductivity features 54B of the interconnect structure 54 and the protection structure 51 are shown in dashed lines in Figure 5B for illustrative purposes. The portion of the integrated circuit chip 50 circled in dashed lines is enlarged in Figure 5A to show more structural details. The integrated circuit chip 50 may be a logic chip (e.g., a central processing unit, a graphics processing unit, a system chip, an application processor, a microcontroller, etc.), a memory chip (dynamic random access memory chip, static random access memory chip, etc.), a power management chip (e.g., a power management integrated circuit chip), a radio frequency chip, a sensing chip, a microelectromechanical system chip, a signal processing chip (e.g., a digital signal processing chip), a front-end chip (e.g., an analog front-end chip), or a combination thereof.

[0017] The integrated circuit die 50 may include a substrate 52, an interconnect structure 54 on the active surface of the substrate 52, a dielectric layer 54A on the interconnect structure 54, and a die connector 58 in the dielectric layer 54A. A protective structure 51 may be disposed in the substrate 52, and the surface of a first portion 51A of the protective structure 51 may be coplanar with the active surface of the substrate 52. The interconnect structure 54 may include the dielectric layer 54A and a conductive feature 54B in the dielectric layer 54A. A sealing ring structure 55 may be disposed in the interconnect structure 54. The sealing ring structure 55 may extend through the dielectric layer 54A and contact the first portion 51A of the protective structure 51. The first portion 51A may be located between the sealing ring structure 55 and the second portion 51B of the protective structure 51. The first portion 51A may separate the sealing ring structure 55 from the second portion 51B. In the embodiment shown in Figure 5B, from a top-down perspective, the sealing ring structure 55 is a continuous ring surrounding the conductive feature 54B, and the protective structure 51 is a continuous ring surrounding the conductive feature 54B. The sealing ring structure 55 and the protective structure 51 are circuit-isolated from the integrated circuit die 50.

[0018] The surface of the sealing ring structure 55 may contact the surface of the first portion 51A, and the surface of the sealing ring structure 55 may be narrower than the surface of the first portion 51A. The surface of the first portion 51A may contact the dielectric layer 54A. Therefore, the surface of the sealing ring structure 55 in contact with the protective structure 51 may be completely covered by the first portion 51A of the protective structure 51 and separated from the substrate 52. Static charge may be generated during the formation of the integrated circuit die 50 and in subsequent processes in which the integrated circuit die 50 may be used to form an integrated circuit package. The protective structure 51 may include a pn junction at the interface between the first portion 51A and the second portion 51B, which may reduce or prevent the release of static charge through the conductive sealing ring structure 55, thereby reducing or preventing cracks formed in or around the integrated circuit die 50 due to electrostatic discharge.

[0019] The first portion 51A may have a width W1 ranging from approximately 0.1 µm to approximately 50 µm. The second portion 51B may have a width W2 ranging from approximately 0.1 µm to approximately 50 µm. In some embodiments, the width W1 is equal to the width W2. The sealing ring structure 55 may have a width W3 ranging from approximately 0.1 µm to approximately 45 µm. In some embodiments, the widths W1 and W2 are greater than the width W3. The first portion 51A may have a thickness T1 ranging from approximately 0.1 µm to approximately 20 µm. The second portion 51B may have a thickness T2 ranging from approximately 0.1 µm to approximately 20 µm. In some embodiments, the thickness T1 is equal to the thickness T2. The substrate 52 below the second portion 51B may have a thickness T3 ranging from approximately 1 µm to approximately 200 µm. The first portion 51A may be spaced from the sidewall of the substrate 52 by a horizontal distance D1 ranging from approximately 0.1 µm to approximately 100 µm. The first portion 51A may be spaced from the conductive feature 54B by a horizontal distance D2 ranging from approximately 0.1 µm to approximately 100 µm. The second portion 51B may be spaced from the sidewall of the substrate 52 by a horizontal distance D3 ranging from approximately 0.1 µm to approximately 100 µm. The second portion 51B may be spaced from the conductive feature 54B by a horizontal distance D4 ranging from approximately 0.1 µm to approximately 100 µm.

[0020] Figure 5C is a top view of an integrated circuit die 50 according to a partial embodiment. The embodiment of the integrated circuit die 50 shown in Figure 5C may be similar to the embodiment of the integrated circuit die 50 shown in Figure 5B, wherein similar reference numerals refer to similar features formed by similar processes. The cross-sectional view shown in Figure 5A may be along the reference cross section A-A' shown in the top view of Figure 5C. The conductive feature 54B of the interconnect structure 54 and the protective structure 51 are shown in dashed lines in Figure 5C for illustrative purposes. In the embodiment shown in Figure 5C, in a top-down view, the sealing ring structure 55 includes a segmented ring surrounding the conductive feature 54B, and the protective structure 51 includes a segmented ring surrounding the conductive feature 54B.

[0021] Figures 6A and 6B illustrate the integrated circuit die 100. Figure 6A is a cross-sectional view and Figure 6B is a top view. The cross-sectional view shown in Figure 6A may be along the reference cross section A-A' shown in the top view of Figure 6B. The portion of the integrated circuit die 100 circled by dashed lines is enlarged in Figure 6A to show more structural details. The integrated circuit die 100 may be a logic die (e.g., a central processing unit, graphics processing unit, system chip, application processor, microcontroller, etc.), a memory die (dynamic random access memory die, static random access memory die, etc.), a power management die (e.g., a power management integrated circuit die), a radio frequency die, a sensing die, a microelectromechanical system die, a signal processing die (e.g., a digital signal processing die), a front-end die (e.g., an analog front-end die), or a combination thereof.

[0022] The materials and fabrication processes of the features in the integrated circuit die 100 can be found by referring to similar features in the integrated circuit die 50. The integrated circuit die 100 may include a substrate 102, which may have an active surface (e.g., the upward-facing surface in Figure 6A), sometimes referred to as the front side, and an inactive surface (e.g., the downward-facing surface in Figure 6A), sometimes referred to as the back side. Components (not shown separately) may be disposed on the active surface of the substrate 102. Components may be transistors, capacitors, resistors, etc. A protective structure 101 may be disposed in the substrate 102.

[0023] In the embodiment illustrated in Figure 6A, the protective structure 101 includes a first portion 101A and a second portion 101B. The surface of the first portion 101A of the protective structure 101 may be coplanar with the active surface of the substrate 102. The first portion 101A may contain a third dopant, and the second portion 101B may contain a fourth dopant. The third dopant may be different from the fourth dopant. The third dopant and the fourth dopant may be of different conductivity types, and a pn junction may be formed at the interface between the first portion 101A and the second portion 101B. In some embodiments, the third dopant may be an n-type dopant, such as phosphorus, arsenic, etc., and the fourth dopant may be a p-type dopant, such as boron, aluminum, gallium, indium, etc. In some embodiments, the third dopant may be a p-type dopant, such as boron, aluminum, gallium, indium, etc., and the fourth dopant may be an n-type dopant, such as phosphorus, arsenic, etc. The dopant concentration of the third dopant in the first region 101A can be in the range of approximately 1 x 10¹⁵ cm⁻³ to approximately 1 x 10²⁰ cm⁻³. The dopant concentration of the fourth dopant in the second region 101B can be in the range of approximately 1 x 10¹⁵ cm⁻³ to approximately 1 x 10²⁰ cm⁻³.

[0024] Interconnect structure 104 may be on the active surface of substrate 102. Interconnect structure 104 may interconnect elements on the active surface of substrate 102 to form a circuit in integrated circuit die 100. Interconnect structure 104 may include dielectric layer 104A and conductive feature 104B in dielectric layer 104A. Sealing ring structure 105 may be disposed in interconnect structure 104. Sealing ring structure 105 may extend through dielectric layer 104A and contact a first portion 101A of protective structure 101. First portion 101A may be between sealing ring structure 105 and a second portion 101B of protective structure 101. First portion 101A may separate sealing ring structure 105 from second portion 101B. In the embodiment shown in Figure 6B, in a top-down view, sealing ring structure 105 is a continuous ring around conductive feature 104B, and protective structure 101 is a continuous ring around conductive feature 104B. The conductivity features 104B of the interconnect structure 104 and the protection structure 101 are shown in dashed lines in Figure 6B for illustrative purposes. The sealing ring structure 105 and the protection structure 101 can isolate the circuitry from the integrated circuit die 100.

[0025] The surface of the sealing ring structure 105 may contact the surface of the first portion 101A, and the surface of the sealing ring structure 105 may be narrower than the surface of the first portion 101A. The surface of the first portion 101A may contact the dielectric layer 104A. Therefore, the surface of the sealing ring structure 105 in contact with the protective structure 101 may be completely covered by the first portion 101A of the protective structure 101 and separated from the substrate 102. Static charge may be generated during the formation of the integrated circuit die 100 and in subsequent processes in which the integrated circuit die 100 may be used to form an integrated circuit package. The protective structure 101 may include a pn junction at the interface between the first portion 101A and the second portion 101B, which may reduce or prevent the release of static charge through the conductive sealing ring structure 105, thereby reducing or preventing cracks formed in or around the integrated circuit die 100 due to electrostatic discharge.

[0026] The first portion 101A may have a width W5 ranging from approximately 0.1 µm to approximately 50 µm. The second portion 101B may have a width W6 ranging from approximately 0.1 µm to approximately 50 µm. In some embodiments, the width W5 is equal to the width W6. The sealing ring structure 105 may have a width W7 ranging from approximately 0.1 µm to approximately 45 µm. In some embodiments, the widths W5 and W6 are greater than the width W7. The first portion 101A may have a thickness T5 ranging from approximately 0.1 µm to approximately 20 µm. The second portion 101B may have a thickness T6 ranging from approximately 0.1 µm to approximately 20 µm. In some embodiments, the thickness T5 is equal to the thickness T6. The substrate 102 below the second portion 101B may have a thickness T7 ranging from approximately 1 µm to approximately 200 µm. The first portion 101A may be spaced from the sidewall of the substrate 102 by a horizontal distance D5 ranging from approximately 0.1 µm to approximately 100 µm. The first portion 101A may be spaced from the conductive feature 104B by a horizontal distance D6 ranging from approximately 0.1 µm to approximately 100 µm. The second portion 101B may be spaced from the sidewall of the substrate 102 by a horizontal distance D7 ranging from approximately 0.1 µm to approximately 100 µm. The second portion 101B may be spaced from the conductive feature 104B by a horizontal distance D8 ranging from approximately 0.1 µm to approximately 100 µm.

[0027] The integrated circuit die 100 may be included in a dielectric layer 106 on the interconnect structure 104 and a die connector 108 in the dielectric layer 106. The integrated circuit die 100 may further include a conductive via 107 in a substrate 102. The conductive via 107 may be electrically coupled to a conductive feature 104B of the interconnect structure 104. The substrate 102 may be thinned in a subsequent process to expose the conductive via 107 on the inactive surface of the substrate 102. After the thinning process, the conductive via 107 may be referred to as a through-substrate via (TSV).

[0028] Figure 6C is a top view of an integrated circuit die 100 according to a partial embodiment. The embodiment of the integrated circuit die 100 shown in Figure 6C may be similar to the embodiment of the integrated circuit die 100 shown in Figure 6B, wherein similar reference numerals refer to similar features formed by similar processes. The cross-sectional view shown in Figure 6A may be along the reference cross section A-A' shown in the top view of Figure 6C. The conductive feature 104B of the interconnect structure 104 and the protective structure 101 are shown in dashed lines in Figure 6C for illustrative purposes. In the embodiment shown in Figure 6C, in a top-down view, the sealing ring structure 105 includes a segment ring surrounding the conductive feature 104B, and the protective structure 101 includes a segment ring surrounding the conductive feature 104B.

[0029] Figures 7A and 7B illustrate inactive die 150. Figure 7A is a cross-sectional view and Figure 7B is a top view. The cross-sectional view of Figure 7A may be along the reference cross section A-A' shown in the top view of Figure 7B. The portion of inactive die 150 circled by dashed lines is enlarged in Figure 7A to show more structural details. Inactive die 150 may also be referred to as a virtual die. The material and forming process of features in inactive die 150 can be found by referring to similar features in integrated circuit die 50. Inactive die 150 may include a substrate 152, which may have a front surface (e.g., the upward-facing surface in Figure 7A), sometimes referred to as the front side, and a rear surface (e.g., the downward-facing surface in Figure 7A), sometimes referred to as the rear side.

[0030] In the embodiment illustrated in Figure 7A, the protective structure 151 includes a first portion 151A and a second portion 151B. The surface of the first portion 151A of the protective structure 151 may be coplanar with the front surface of the substrate 152. The first portion 151A may contain a fifth dopant, and the second portion 151B may contain a sixth dopant. The fifth dopant may be different from the sixth dopant. The fifth and sixth dopants may be of different conductivity types, and a pn junction may be formed at the interface between the first portion 151A and the second portion 151B. In some embodiments, the fifth dopant may be an n-type dopant, such as phosphorus, arsenic, etc., and the sixth dopant may be a p-type dopant, such as boron, aluminum, gallium, indium, etc. In some embodiments, the fifth dopant may be a p-type dopant, such as boron, aluminum, gallium, indium, etc., and the second dopant may be an n-type dopant, such as phosphorus, arsenic, etc. The dopant concentration of the fifth dopant in the first site 151A can be in the range of approximately 1 x 10¹⁵ cm⁻³ to approximately 1 x 10²⁰ cm⁻³. The dopant concentration of the sixth dopant in the second site 151B can be in the range of approximately 1 x 10¹⁵ cm⁻³ to approximately 1 x 10²⁰ cm⁻³.

[0031] A dielectric layer 154 may be on the front surface of a substrate 152. A sealing ring structure 155 may be disposed in the dielectric layer 154. The sealing ring structure 155 may extend through the dielectric layer 154 and contact a first portion 151A of a protective structure 151. The first portion 151A may be located between the sealing ring structure 155 and a second portion 151B of the protective structure 151. The first portion 151A may separate the sealing ring structure 155 from the second portion 151B. In the embodiment shown in Figure 7B, the sealing ring structure 155 is a continuous ring in a top-down view, and the protective structure 151 is a continuous ring. The protective structure 151 is shown in dashed lines in Figure 7B for illustrative purposes.

[0032] The surface of the sealing ring structure 155 may contact the surface of the first portion 151A, and the surface of the sealing ring structure 155 may be narrower than the surface of the first portion 151A. The surface of the first portion 151A may contact the dielectric layer 154. Therefore, the surface of the sealing ring structure 155 in contact with the protective structure 151 may be completely covered by the first portion 151A of the protective structure 151 and separated from the substrate 152. Static charge may be generated during the formation of the inactive die 150 and in subsequent processes in which the inactive die 150 may be used to form an integrated circuit package. The protective structure 151 may include a pn junction at the interface between the first portion 151A and the second portion 151B, which may reduce or prevent the release of static charge through the conductive sealing ring structure 155, thereby reducing or preventing cracks formed in or around the inactive die 150 due to electrostatic discharge.

[0033] The first portion 151A may have a width W11 ranging from approximately 0.1 µm to approximately 50 µm. The second portion 151B may have a width W12 ranging from approximately 0.1 µm to approximately 50 µm. In some embodiments, the width W11 is equal to the width W12. The sealing ring structure 155 may have a width W13 ranging from approximately 0.1 µm to approximately 45 µm. In some embodiments, the widths W11 and W12 are greater than the width W13. The first portion 151A may have a thickness T11 ranging from approximately 0.1 µm to approximately 20 µm. The second portion 151B may have a thickness T12 ranging from approximately 0.1 µm to approximately 20 µm. In some embodiments, the thickness T11 is equal to the thickness T12. The substrate 152 below the second portion 151B may have a thickness T13 ranging from approximately 1 µm to approximately 200 µm. The first portion 151A may be spaced from the sidewall of the substrate 152 by a horizontal distance D11 ranging from approximately 0.1 µm to approximately 100 µm. The second portion 151B may be spaced from the sidewall of the substrate 152 by a horizontal distance D12 ranging from approximately 0.1 µm to approximately 100 µm.

[0034] Figure 7C is a top view of the inactive grain 150 according to a partial embodiment. The embodiment of the inactive grain 150 shown in Figure 7C may be similar to the embodiment of the inactive grain 150 shown in Figure 7B, wherein similar reference numerals refer to similar features formed by similar processes. The cross-sectional view shown in Figure 7A may be along the reference cross section A-A' shown in the top view of Figure 7C. The protective structure 151 is shown in dashed lines in Figure 7C for illustrative purposes. In the embodiment shown in Figure 7C, the sealing ring structure 155 includes a segment ring in a top-down view, and the protective structure 151 includes a segment ring.

[0035] Figures 8 to 16 are views of intermediate steps in the process of forming an integrated circuit package 300. In Figure 8, an integrated circuit die 100 is bonded to a carrier 116. The carrier 116 can be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 116 can be a wafer. Figure 8 illustrates one integrated circuit die 100 bonded to a carrier as an example. Two or more integrated circuit dies 100 can be bonded to a carrier and processed together during subsequent manufacturing steps until they are cut into a single package element. An adhesive layer 118 can be disposed on the carrier 116. The adhesive layer 118 can contain a dielectric material, such as silicon dioxide, silicon oxynitride, etc.

[0036] The integrated circuit die 100 can be placed on the adhesive layer 118 through a pick-and-place process, and then the integrated circuit die 100 is bonded to the adhesive layer 118, thereby bonding the integrated circuit die 100 to the adhesive layer 118. During the pick-and-place process, static charge may be generated in the substrate 102. The protective structure 101 can reduce or prevent the release of static charge through the conductive sealing ring structure 105, thereby reducing or preventing cracks caused by electrostatic discharge in the integrated circuit die 100 and / or gap-filling dielectric formed around the integrated circuit die 100 in subsequent processes. Therefore, the reliability of the integrated circuit package 300 can be improved.

[0037] As an example of the bonding process, the integrated circuit die 100 can be bonded to the adhesive layer 118 by dielectric bonding without using any adhesive material (e.g., a die-attach film). The bonding process may include a pressing step and an annealing step. During the pressing step, a small pressure can be applied to press the integrated circuit die 100 against the adhesive layer 118. The pressing step can be performed at a low temperature, such as room temperature. After the pressing step, the dielectric layer 106 can be bonded to the adhesive layer 118 by direct bonding, such as fusion bonding, covalent bonding, etc. The bond strength can then be improved in a subsequent annealing step, wherein the dielectric layer 106 and the adhesive layer 118 can be annealed at a higher temperature.

[0038] In Figure 9, an interstitial dielectric 122 is formed around the integrated circuit die 100 and between adjacent integrated circuit dies 100 above the carrier 116, and the substrate 102 is thinned to expose the conductive vias 107. The interstitial dielectric 122 can be formed from a dielectric material, such as silica, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), or terephthalamide-based oxides (TEOS), and can be formed through a suitable deposition process, such as chemical vapor deposition or atomic layer deposition. Initially, the interstitial dielectric 122 can bury or cover the back side of the integrated circuit die 100. Thinning processes, such as chemical mechanical polishing, polishing processes, etch-back processes, or combinations thereof, can be performed to make the surface of the interstitial dielectric 122 flush with the back surface of the integrated circuit die 100. The substrate 102 can then be thinned to expose the conductive vias 107. The portions of the gap-filling dielectric 122 can also be removed through the thinning process. The thinning process can be chemical mechanical polishing, polishing, etch-back, or a combination thereof, performed on the back side of the integrated circuit die 100. After the thinning process, the surface of the gap-filling dielectric 122 and the integrated circuit die 100 (including the substrate 102 and the conductive vias 107) can be substantially coplanar (within the range of process variations).

[0039] In Figure 10, a dielectric layer 124 is formed on the gap-filling dielectric 122 and behind the integrated circuit die 100, and a die connector 126 is formed in the dielectric layer 124. The die connector 126 extends through the dielectric layer 124 and connects to the conductive via 107. The dielectric layer 124 electrically isolates the conductive vias 107 from each other to prevent short circuits and can be used in subsequent bonding processes. The dielectric layer 124 can be formed of oxides, such as silica, phosphosilicate glass, borosilicate glass, borosilicate glass, amide-based oxides, etc., and can be formed by a suitable deposition process, such as chemical vapor deposition. The die connector 126 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The die connector 126 can be formed of a metal, such as copper, aluminum, etc., by electroplating, etc. In some embodiments, planarization processes, such as chemical mechanical polishing, polishing, etch-back processes, or combinations thereof, are performed on the dielectric layer 124 and the die connector 126. After the thinning process, the surfaces of the dielectric layer 124 and the die connector 126 may be substantially coplanar (within the range of process variations).

[0040] In Figure 11, integrated circuit die 50 is bonded to dielectric layer 124 and die connector 126, and inactive die 150 is bonded to dielectric layer 124. Die connector 126 electrically couples integrated circuit die 50 and integrated circuit die 100. The arrangement of integrated circuit die 50 and inactive die 150 on integrated circuit die 100 shown in Figure 11 is an example; other arrangements with more integrated circuit dies 50 and no or more inactive dies 150 may be considered.

[0041] The integrated circuit die 50 can be placed on the dielectric layer 124 and the die connector 126 through a die bonding process, and then the integrated circuit die 50 is bonded to the dielectric layer 124 and the die connector 126, thereby bonding the integrated circuit die 50 to the dielectric layer 124 and the die connector 126. During the die bonding process, static charge may be generated in the substrate 52. The protective structure 51 can reduce or prevent the release of static charge through the conductive sealing ring structure 55, thereby reducing or preventing cracks caused by electrostatic discharge in the integrated circuit die 50 and / or the filling dielectric material for gaps formed around the integrated circuit die 50 in subsequent processes. Therefore, the reliability of the integrated circuit package 300 can be improved.

[0042] The inactive die 150 can be placed on the dielectric layer 124 through a die bonding process, and then the inactive die 150 is bonded to the dielectric layer 124, thereby bonding the inactive die 150 to the dielectric layer 124. During the die bonding process, static charge may be generated in the substrate 152. The protective structure 151 can reduce or prevent the release of static charge through the conductive sealing ring structure 155, thereby reducing or preventing cracks caused by electrostatic discharge in the inactive die 150 and / or the filling dielectric material for gaps formed around the inactive die 150 in subsequent processes. Therefore, the reliability of the integrated circuit package 300 can be improved.

[0043] The dielectric layer 56 of the integrated circuit die 50 can be directly bonded to the dielectric layer 124 via dielectric-to-dielectric bonding without using any adhesive material (e.g., die-attach film). The die connector 58 of the integrated circuit die 50 is directly bonded to the corresponding die connector 126 via metal-to-metal bonding without using any eutectic material (e.g., solder). The bonding process may include a pressing step and an annealing step. During the pressing step, a small pressure may be applied to press the integrated circuit die 50 against the dielectric layer 124 and the die connector 126. The pressing step may be performed at a low temperature, such as room temperature. After the pressing step, the dielectric layer 56 can be bonded to the dielectric layer 124 via direct bonding, such as fusion bonding, covalent bonding, etc. The bonding strength can then be improved in a subsequent annealing step, wherein the dielectric layer 124, die connector 126, dielectric layer 56, and die connector 58 are annealed at a higher temperature. Die connectors 126 and 58 can make physical contact after the pressing step, or they can expand during the annealing step to make physical contact. Furthermore, during the annealing step, the materials of die connectors 126 and 58 can be mixed to form metal-to-metal bonds. Die connectors 126 and 58 can correspond one-to-one. The dielectric layer 156 of the inactive die 150 can be bonded to the dielectric layer 124 via dielectric-to-dielectric bonding without using any adhesive material (e.g., die-attach film). The bonding process can be the same as or similar to the bonding process between the dielectric layer 56 and dielectric layer 124 of the integrated circuit die 50 described above.

[0044] In Figure 12, interstitial dielectric 157 is formed around the integrated circuit die 50 above the dielectric layer 124, around the inactive die 150, and between adjacent integrated circuit dies 50 and inactive dies 150. The interstitial dielectric 157 may be formed of a dielectric material, such as silica, phosphosilicate glass, borosilicate glass, borosilicate glass, amide-based oxides, etc. In some embodiments, the interstitial dielectric 157 is formed of the same dielectric material as the interstitial dielectric 122. The interstitial dielectric 122 may be formed by the same or similar methods as the interstitial dielectric 122. A thinning process may be performed to remove portions of the substrate 52, the substrate 152, and the interstitial dielectric 157. The thinning process may be chemical mechanical polishing, polishing, etch-back, etc., or a combination thereof, performed on the back side of the integrated circuit die 50. After the thinning process, the surface of the gap filling dielectric 157, the integrated circuit die 50 (including the substrate 102), and the inactive die 150 (including the substrate 152) can be substantially coplanar (within the range of process variations).

[0045] In Figure 13, an adhesive layer 158 is formed on the substrate 102, the substrate 152, and the gap-filling dielectric 157, and the structure above the carrier 116 (see Figure 12) is bonded to the carrier 160. The carrier 116 and the adhesive layer 118 are then removed. The adhesive layer 158 may contain a dielectric material, such as silicon oxide, and may be formed through a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, etc. The carrier 160 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 160 may be a wafer with the same or similar dimensions as the carrier 116. An adhesive layer 159 may be disposed on the carrier 160. The adhesive layer 159 may contain a dielectric material, such as silicon oxide, etc. The adhesive layers 158 and 159 can be bonded using the same or similar processes used to bond the dielectric layer 106 and the adhesive layer 118, thereby bonding the structure of the carrier 116 to the carrier 160. The carrier 116 and the adhesive layer 118 can then be removed through a thinning process. The portions of the interstitial dielectric 122 can also be removed. The thinning process can be chemical mechanical polishing, polishing, etch-back, or a combination thereof. After the thinning process, the surface of the dielectric layer 106 and the interstitial dielectric 122 can be substantially coplanar (within the range of process variations).

[0046] In Figure 14, a dielectric layer 166 is formed on the dielectric layer 106 and the gap-filling dielectric 122, a metallized bump 167 is formed on and through the dielectric layer 166, and an electrical connector 168 is formed on the metallized bump 167. The dielectric layer 166 may comprise silicon oxide, silicon nitride, etc., and may be formed through a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, etc. The dielectric layer 166 may be a protective layer. The metallized bump 167 has bump portions extending on and along the surface of the dielectric layer 166, and has via portions extending through the dielectric layer 166 and the dielectric layer 106, for physical and electrical coupling to the die connector 108. Therefore, the metallized bump 167 is electrically coupled to the integrated circuit die 100.

[0047] As an example of forming the metallization bump 167, the dielectric layer 166 and the dielectric layer 106 can be patterned to form openings exposing the underlying die connector 108. Patterning can be performed through an acceptable lithography or etching process, such as forming a photomask and then performing anisotropic etching. The photomask can be removed after patterning. A seed layer (not shown separately) can be formed on the dielectric layer 166, in the openings through the dielectric layer 166 and the dielectric layer 106, and on the exposed portions of the die connector 108. The seed layer can be formed through a deposition process, such as physical vapor deposition. Then, a photoresist can be formed and patterned on the seed layer. The pattern of the photoresist can correspond to the metallization bump 167. Patterning forms openings through the photoresist to expose the seed layer. A conductive material can be formed in the openings of the photoresist and on the exposed portions of the seed layer through electroplating, such as electroless plating or electroplating. The conductive material may comprise a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or combinations thereof. The photoresist and areas on the seed layer where no conductive material has formed can then be removed using an acceptable ashing or stripping process. Once the photoresist is removed, the exposed areas of the seed layer can be removed using an acceptable etching process, such as wet etching or dry etching. The remaining areas of the seed layer and conductive material may be referred to as metallized bumps 167.

[0048] The electrical connector 168 may be formed on the metallized bump 167. The electrical connector 168 may be a ball gate array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, etc. The electrical connector 168 may contain conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the electrical connector 168 is initially formed by forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In some embodiments, the electrical connector 168 includes metal pillars (e.g., copper pillars) formed through sputtering, printing, electroplating, electroless plating, chemical vapor deposition, etc. The structure shown in Figure 14 can be referred to as wafer structure 200.

[0049] In Figure 15, the wafer structure 200 is diced. The wafer structure 200 can be placed on the strip 169 supported by the frame 170. Then the wafer structure 200 can be diced along the scribing line 173, so that the wafer structure 200 is divided into discrete integrated circuit package elements 200'. The dicing process may include a dicing process, a laser dicing process, etc. A cleaning process or a washing process may be performed after the dicing process.

[0050] In Figure 16, an integrated circuit package element 200' is bonded to a package substrate 202, and a filler material 208 is formed between the integrated circuit package element 200' and the package substrate 202. The resulting structure may be referred to as an integrated circuit package 300. The package substrate 202 may include a conductive pad 206. In some embodiments, the package substrate 202 includes materials such as glass fiber reinforced resin, bismaleimide-triazine (BT) resin, other printed circuit board materials, etc. In some embodiments, the package substrate 202 includes materials such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, etc.

[0051] The packaging substrate 202 may include active and passive components (not shown separately), such as transistors, capacitors, resistors, etc., or combinations thereof. Components may be formed using any suitable method. The packaging substrate 202 may include a metallization layer and vias (not shown separately) physically and electrically coupled to the conductive pad 206. The metallization layer may be formed on the active or passive component and may connect various components to form a functional circuit. The metallization layer may be an alternating layer of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), with vias interconnecting the conductive material layers. In some embodiments, the packaging substrate 202 does not have active and passive components.

[0052] During the bonding process, the electrical connector 220 may be reflowed to bond the integrated circuit package element 250' to the conductive pad 206. The electrical connector 220 may electrically and physically couple the package substrate 202 to the integrated circuit package element 250'. In some embodiments, solder photoresist (not shown separately) is formed on the package substrate 202. The electrical connector 220 may be disposed in an opening in the solder photoresist to electrically and physically couple to the conductive pad 206. The solder photoresist may be used to protect areas of the package substrate 202 from external damage.

[0053] A filler material 208 may be formed between the integrated circuit package element 200' and the package substrate 202, surrounding the electrical connector 168. The filler material 208 can reduce pressure and protect the seam caused by backflow from the electrical connector 168. The filler material 208 may be formed by a capillary process after attachment of the integrated circuit package element 200', or by a suitable deposition method before attachment of the integrated circuit package element 200'. The filler material 208 may then be cured.

[0054] In Figures 17A and 17B, the integrated circuit die 50 is illustrated according to a partial embodiment. The embodiments of the integrated circuit die 50 shown in Figures 17A and 17B may be approximations of the integrated circuit die 50 shown in Figures 5A and 5B, wherein similar reference numerals refer to similar features formed by similar processes. Figure 17A is a cross-sectional view and Figure 17B is a top view. The cross-sectional view of Figure 17A may be along the reference cross section A-A' shown in the top view of Figure 17B. The conductive feature 54B of the interconnect structure 54 and the protective structure 51 are shown in dashed lines in Figure 17B for illustrative purposes. In the embodiment shown in Figure 17B, in a top-down view, the sealing ring structure 55 includes two concentric continuous rings surrounding the conductive feature 54B, and the protective structure 51 includes two concentric continuous rings surrounding the conductive feature 54B. The inner continuous ring of the sealing ring structure 55 can be separated from the substrate 52 through the inner continuous ring of the protective structure 51. The outer continuous ring of the sealing ring structure 55 can be separated from the substrate 52 through the outer continuous ring of the protective structure 51.

[0055] Figure 17C is a top view of an integrated circuit die 50 according to a partial embodiment. The embodiment of the integrated circuit die 50 shown in Figure 17C can be approximated by the embodiment of the integrated circuit die 50 shown in Figure 17B, wherein similar reference numerals refer to similar features formed by similar processes. The cross-sectional view of Figure 17A can be along the reference cross section A-A' shown in the top view of Figure 17C. The conductive feature 54B of the interconnect structure 54 and the protective structure 51 are shown in dashed lines in Figure 17C for illustrative purposes. In the embodiment shown in Figure 17C, in a top-down view, the sealing ring structure 55 includes two concentric segment rings surrounding the conductive feature 54B, and the protective structure 51 includes two concentric segment rings surrounding the conductive feature 54B. The inner segment ring of the sealing ring structure 55 can separate the inner segment ring of the protective structure 51 from the substrate 52. The outer segment ring of the sealing ring structure 55 can separate the outer segment ring of the protective structure 51 from the substrate 52.

[0056] Figure 18 illustrates an integrated circuit package 300 according to a partial embodiment. The embodiment of the integrated circuit package 300 shown in Figure 18 is approximately similar to the embodiment of the integrated circuit package 300 shown in Figure 16, wherein similar reference numerals refer to similar features formed by similar processes. In the embodiment shown in Figure 18, the integrated circuit package 300 includes an integrated circuit die 50 as shown in Figures 17A, 17B, and 17C. The integrated circuit package 300 may include an integrated circuit die 100 having a sealing ring structure 55 and a protective structure 101 that are respectively similar to those in Figures 17A, 17B, and 17C. The integrated circuit package 300 may include an inactive die 150, the inactive die 150 having a sealing ring structure 155 and a protective structure 51 that are respectively approximated to those in Figures 17A, 17B and 17C.

[0057] Figures 19A and 19B illustrate an integrated circuit die 50 according to a partial embodiment. The embodiment of the integrated circuit die 50 shown in Figures 19A and 19B may be approximated to the embodiment of the integrated circuit die 50 shown in Figures 17A and 17B, wherein similar reference numerals refer to similar features formed by similar processes. Figure 19A is a cross-sectional view and Figure 19B is a top view. The cross-sectional view of Figure 19A may be along the reference cross section A-A' shown in the top view of Figure 19B. The conductive feature 54B of the interconnect structure 54 and the protective structure 51 are shown in dashed lines in Figure 19B for illustrative purposes. In the embodiment shown in Figure 19B, in a top-down view, the sealing ring structure 55 includes two concentric continuous rings surrounding the conductive feature 54B, and the protective structure 51 includes a continuous ring surrounding the conductive feature 54B. The two concentric continuous rings of the sealing ring structure 55 can be separated from the substrate 52 through the continuous rings of the protective structure 51.

[0058] Figure 19C is a top view of an integrated circuit die 50 according to a partial embodiment. The embodiment of the integrated circuit die 50 shown in Figure 19C can be approximated by the embodiment of the integrated circuit die 50 shown in Figure 19B, wherein similar reference numerals refer to similar features formed by similar processes. The cross-sectional view of Figure 19A can be along the reference cross section A-A' shown in the top view of Figure 19C. The conductive feature 54B of the interconnect structure 54 and the protective structure 51 are shown in dashed lines in Figure 19C for illustrative purposes. In the embodiment shown in Figure 19C, in a top-down view, the sealing ring structure 55 includes two concentric segment rings surrounding the conductive feature 54B, and the protective structure 51 includes segment rings surrounding the conductive feature 54B. The two concentric segment rings of the sealing ring structure 55 are separable from the substrate 52 through the segment rings of the protective structure 51.

[0059] Figure 20 illustrates an integrated circuit package 300 according to a partial embodiment. The embodiment of the integrated circuit package 300 shown in Figure 20 is approximately similar to the embodiment of the integrated circuit package 300 shown in Figure 18, wherein similar reference numerals refer to similar features formed by similar processes. In the embodiment shown in Figure 20, the integrated circuit package 300 includes an integrated circuit die 50 as shown in Figures 19A, 19B, and 19C. The integrated circuit package 300 may include an integrated circuit die 100 having a sealing ring structure 55 and a protective structure 101 that are respectively similar to those in Figures 19A, 19B, and 19C. The integrated circuit package 300 may include an inactive die 150, the inactive die 150 having a sealing ring structure 155 and a protective structure 151 that are respectively approximated to those in Figures 19A, 19B and 19C.

[0060] Figures 21A and 21B illustrate an integrated circuit die 50 according to a partial embodiment. The embodiment of the integrated circuit die 50 shown in Figures 21A and 21B may be similar to the embodiment of the integrated circuit die 50 shown in Figures 5A and 5B, wherein similar reference numerals refer to similar features formed by similar processes. Figure 21A is a cross-sectional view and Figure 21B is a top view. The cross-sectional view of Figure 21A may be along the reference cross section A-A' shown in the top view of Figure 21B. The conductivity feature 54B of the interconnect structure 54 and the protection structure 51 are shown in dashed lines in Figure 21B for illustrative purposes.

[0061] In the embodiment shown in Figure 21A, the protective structure 51, in addition to the first portion 51A and the second portion 51B, further includes a third portion 51C. The second portion 51B may be located between the first portion 51A and the third portion 51C. The second portion 51B can separate the first portion 51A and the third portion 51C. The third portion 51C may include a seventh dopant. The seventh dopant may be different from the second dopant. The seventh dopant and the second dopant may be of different conductivity types, and a pn junction may be formed at the interface between the third portion 51C and the second portion 51B. The seventh dopant and the first dopant may be of the same conductivity type. In some embodiments, the seventh dopant and the first dopant are the same. In some embodiments, the first dopant and the seventh dopant may be n-type dopants, such as phosphorus, arsenic, etc., and the second dopant may be p-type dopants, such as boron, aluminum, gallium, indium, etc. In some embodiments, the first dopant and the seventh dopant can be p-type dopants, such as boron, aluminum, gallium, indium, etc., and the second dopant can be n-type dopants, such as phosphorus, arsenic, etc.

[0062] Figure 21C is a top view of an integrated circuit die 50 according to a partial embodiment. The embodiment of the integrated circuit die 50 shown in Figure 21C may be approximated by the embodiment of the integrated circuit die 50 shown in Figure 21B, wherein similar reference numerals refer to similar features formed by similar processes. The cross-sectional view of Figure 21A may be along the reference cross section A-A' shown in the top view of Figure 21C. The conductive feature 54B of the interconnect structure 54 and the protective structure 51 are shown in dashed lines in Figure 21C for illustrative purposes. In the embodiment shown in Figure 21C, in a top-down view, the sealing ring structure 55 includes a segmented ring surrounding the conductive feature 54B, and the protective structure 51 includes a segmented ring surrounding the conductive feature 54B.

[0063] Figure 22 illustrates an integrated circuit package 300 according to a partial embodiment. The embodiment of the integrated circuit package 300 shown in Figure 22 is similar to the embodiment of the integrated circuit package 300 shown in Figure 16, wherein similar reference numerals refer to similar features formed by similar processes. In the embodiment shown in Figure 22, the integrated circuit package 300 includes an integrated circuit die 50 as shown in Figures 21A, 21B, and 21C. The integrated circuit package 300 may include an integrated circuit die 100 having a sealing ring structure 105 and a protective structure 101 that are respectively similar to the sealing ring structure 55 and protective structure 51 in Figures 21A, 21B, and 21C. The integrated circuit package 300 may include an inactive die 150, the inactive die 150 having a sealing ring structure 155 and a protective structure 151 that are respectively approximated to those in Figures 21A, 21B and 21C.

[0064] The embodiments disclosed herein have several advantageous features. By forming a protective structure 51 in the integrated circuit die 50, a protective structure 101 in the integrated circuit die 100, and a protective structure 151 in the inactive die 150, cracks formed due to electrostatic discharge in the integrated circuit die 50, the integrated circuit die 100, the inactive die 150, the gap-filling dielectric 122, and / or the gap-filling dielectric 157 can be reduced or prevented. Therefore, the reliability of the integrated circuit package 300 can be improved.

[0065] In one embodiment, an integrated circuit package includes an integrated circuit die and a dielectric material. The integrated circuit die includes a substrate, a protective structure, an interconnect structure, and a sealing ring structure. The protective structure is in the substrate, wherein the protective structure and the substrate contain the same semiconductor material, and wherein the protective structure includes a first dopant and a second dopant different from the first dopant. The interconnect structure is on the substrate, and the interconnect structure includes a dielectric layer and conductive features in the dielectric layer. The sealing ring structure is in the dielectric layer of the interconnect structure, wherein the sealing ring structure surrounds the conductive features of the interconnect structure from a top-down perspective, and wherein the sealing ring structure contacts the protective structure. The dielectric material is on the sidewalls of the integrated circuit die. In one embodiment, the protective structure includes a pn junction. In one embodiment, the protective structure includes a first portion containing the first dopant and a second portion containing the second dopant, wherein the first portion of the protective structure contacts the protective structure, and wherein the second portion of the protective structure is separated from the sealing ring structure through the first portion of the protective structure. In one embodiment, the first dopant and the second dopant are of different conductivity types. In one embodiment, the protective structure includes a first portion containing a first dopant, a second portion containing a second dopant, and a third portion containing a third dopant different from the second dopant. In one embodiment, the first portion of the protective structure contacts the protective structure, wherein the second portion of the protective structure is separated from the sealing ring structure through the first portion of the protective structure, and wherein the third portion of the protective structure is separated from the first portion of the protective structure through the second portion of the protective structure. In one embodiment, the first dopant and the second dopant are of different conductivity types, and wherein the first dopant and the third dopant are of the same conductivity type. In one embodiment, the sealing ring structure is separated from the substrate through the protective structure.

[0066] In one embodiment, an integrated circuit package includes an integrated circuit die and a dielectric material. The integrated circuit die includes a substrate, a protective structure, an interconnect structure, and a sealing ring structure. The substrate includes a first semiconductor material. The protective structure is in the substrate, wherein the protective structure includes the first semiconductor material, wherein a first portion of the protective structure is doped with a first dopant, and a second portion of the protective structure is doped with a second dopant, wherein the first dopant and the second dopant are of different conductivity types. The interconnect structure is on the substrate, wherein the interconnect structure includes a dielectric layer and conductive features in the dielectric layer. The sealing ring structure is in the dielectric layer of the interconnect structure, wherein the sealing ring structure contacts the first portion of the protective structure. The dielectric material is on the sidewalls of the integrated circuit die. In one embodiment, the sealing ring structure is separated from the second portion of the protective structure through the first portion of the protective structure. In one embodiment, the sealing ring structure is narrower than the first portion of the protective structure. In one embodiment, the sealing ring structure is a continuous ring surrounding the conductive features of the interconnect structure in a top-down view, and wherein the protective structure is a continuous ring surrounding the conductive features of the interconnect structure in a top-down view. In one embodiment, the sealing ring structure is a segment ring surrounding the conductive features of the interconnect structure in a top-down view, and the protective structure is also a segment ring surrounding the conductive features of the interconnect structure in a top-down view. In one embodiment, the protective structure further includes a third portion doped with the first dopant, and a second portion of the protective structure is located between the first portion and the third portion of the protective structure.

[0067] In one embodiment, a method includes forming a protective structure in a substrate by sequentially doping a first dopant and a second dopant, wherein the second dopant is different from the first dopant, and wherein the protective structure includes a first portion containing the first dopant and a second portion containing the second dopant. An interconnect structure is formed on the first portion of the substrate, wherein the interconnect structure includes a dielectric layer and conductive features in the dielectric layer. A sealing ring structure is formed in the dielectric layer of the interconnect structure, wherein the sealing ring structure surrounds the conductive features of the interconnect structure in a top-down view, wherein the sealing ring structure contacts the second portion of the protective structure, and wherein the sealing ring structure is separated from the first portion of the substrate through the second portion of the protective structure. A single substrate is diced to form an integrated circuit die, wherein the integrated circuit die includes the first portion of the substrate, the protective structure, the interconnect structure, and the sealing ring structure. An integrated circuit package having the integrated circuit die is formed. In one embodiment, the first portion of the protective structure is separated from the sealing ring structure through the second portion of the protective structure. In one embodiment, the first portion of the protective structure contacts the dielectric layer of the interconnect structure. In one embodiment, the protective structure includes a pn junction at the interface between a first portion and a second portion of the protective structure. In one embodiment, the protective structure is spaced apart from the sidewall of the first portion of the substrate. In one embodiment, the protective structure is circuit-isolated from the integrated circuit die.

[0068] The features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] This disclosure can be best understood by reading the following embodiments in conjunction with the accompanying drawings. It should be emphasized that, according to industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased. Figures 1 to 5C are views illustrating various intermediate steps in the process of forming an integrated circuit die according to some embodiments. Figures 6A to 6C are views illustrating various integrated circuit dies according to some embodiments. Figures 7A to 7C are views illustrating various dummy dies according to some embodiments. Figures 8 to 16 are views illustrating various intermediate steps in the process of forming an integrated circuit package according to some embodiments. Figures 17A to 18 are views illustrating an integrated circuit die and an integrated circuit package containing the integrated circuit die according to some embodiments. Figures 19A to 20 are views illustrating an integrated circuit die and an integrated circuit package containing the integrated circuit die according to some embodiments. Figures 21A and 22 are various views illustrating an integrated circuit die and an integrated circuit package containing the integrated circuit die according to some embodiments. [Biomaterial Storage]

[0070] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. An integrated circuit package comprising: an integrated circuit die comprising: a substrate; a protective structure in the substrate, wherein the protective structure and the substrate comprise the same semiconductor material, and wherein the protective structure comprises a first dopant and a second dopant different from the first dopant, wherein the protective structure comprises a first portion containing the first dopant and a second portion containing the second dopant; an interconnect structure on the substrate, wherein the interconnect structure comprises dielectric layers and conductive features in the dielectric layers; and a sealing ring structure in the dielectric layers of the interconnect structure, wherein the sealing ring structure surrounds the conductive features of the interconnect structure in a top-down view, and wherein the sealing ring structure contacts the protective structure, wherein the first portion of the protective structure contacts the sealing ring structure, and wherein the second portion of the protective structure is separated from the sealing ring structure through the first portion of the protective structure; and a dielectric material on the sidewalls of the integrated circuit die.

2. The integrated circuit package as described in claim 1, wherein the protection structure includes a pn junction.

3. The integrated circuit package as described in claim 1, wherein the first dopant and the second dopant are of different conductivity types.

4. The integrated circuit package as claimed in claim 1, wherein the protection structure further includes a third portion containing a third dopant different from the second dopant.

5. An integrated circuit package comprising: an integrated circuit die comprising: a substrate, wherein the substrate comprises a first semiconductor material; a protective structure in the substrate, wherein the protective structure comprises the first semiconductor material, wherein a first portion of the protective structure is doped with a first dopant, and a second portion of the protective structure is doped with a second dopant, wherein the first dopant and the second dopant are of different conductivity types; an interconnect structure on the substrate, wherein the interconnect structure comprises dielectric layers and conductive features in the dielectric layers; and a sealing ring structure in the dielectric layers of the interconnect structure, wherein the sealing ring structure contacts the first portion of the protective structure, and wherein the second portion of the protective structure is separated from the sealing ring structure through the first portion of the protective structure; and a dielectric material on the sidewalls of the integrated circuit die.

6. The integrated circuit package as described in claim 5, wherein one surface of the sealing ring structure is narrower than one surface of the first portion of the protective structure.

7. The integrated circuit package as claimed in claim 5, wherein the sealing ring structure is a continuous ring surrounding the conductive features of the interconnect structure in a top-down view, and wherein the protective structure is a continuous ring surrounding the conductive features of the interconnect structure in a top-down view.

8. The integrated circuit package as claimed in claim 5, wherein the sealing ring structure is a segment ring surrounding the conductive features of the interconnect structure in a top-down view, and wherein the protective structure is a segment ring surrounding the conductive features of the interconnect structure in a top-down view.

9. The integrated circuit package as claimed in claim 5, wherein the protection structure further includes a third portion doped with the first dopant, and wherein the second portion of the protection structure is located between the first portion of the protection structure and the third portion of the protection structure.

10. A method of forming an integrated circuit package, comprising: sequentially doping a substrate with a first dopant and a second dopant to form a protective structure in the substrate, wherein the second dopant is different from the first dopant, and wherein the protective structure includes a first portion containing the first dopant and a second portion containing the second dopant; forming an interconnect structure on the first portion of the substrate, wherein the interconnect structure includes dielectric layers and conductive features in the dielectric layers; forming a sealing ring structure in the dielectric layers of the interconnect structure, wherein the sealing ring structure surrounds the conductive features of the interconnect structure in a top-down view, wherein the sealing ring structure contacts the second portion of the protective structure, wherein the first portion of the protective structure is separated from the sealing ring structure through the second portion of the protective structure, and wherein the sealing ring structure is separated from the first portion of the substrate through the second portion of the protective structure; The substrate is diced to form an integrated circuit die, wherein the integrated circuit die includes the first portion of the substrate, the protective structure, the interconnect structure, and the sealing ring structure; and an integrated circuit package having the integrated circuit die is formed.

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