Low power and low cost active cable architecture

Abstract

This invention relates to an active transmission cable architecture. The active transmission cable architecture connects a first and a second electronic device. The active transmission cable architecture includes first and second connectors, first and second adapter chips, a plurality of high-speed transmission lines, and a main communication processor. The first and second adapter chips are respectively disposed within the first and second connectors. The plurality of high-speed transmission lines connect the first and second adapter chips. The main communication processor is disposed within one of the first or second connectors to connect to one of the first or second adapter chips and to another adapter chip within the other connector; thereby, the main communication processor controls the synchronous communication function of the first and second adapter chips.

Claims

1. An active transmission cable architecture for connecting a first electronic device and a second electronic device; This active transmission cable architecture includes: First connection port; A second connection port, wherein the first connection port or the second connection port can be respectively connected to the first electronic device or the second electronic device; a first adapter chip disposed in the first connection port; a second adapter chip disposed in the second connection port; a plurality of high-speed transmission lines connected between the first adapter chip and the second adapter chip, thereby enabling the first electronic device and the second electronic device to transmit a signal via the first connection port, the second connection port and the plurality of high-speed transmission lines; and a main communication processor disposed inside one of the first connection port or the second connection port, for electrically connecting one of the first adapter chip or the second adapter chip via a non-high-speed transmission line, and electrically connecting to another adapter chip inside another connection port via the non-high-speed transmission line; thereby the main communication processor can control the synchronous communication function of the first adapter chip and the second adapter chip.

2. The active transmission cable architecture as described in claim 1, wherein the communication addresses of the first adapter chip and the second adapter chip are different.

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