Package structure and manufacturing method thereof

Abstract

An encapsulation structure includes an encapsulation substrate and first and second terminal structures disposed on a first side of the encapsulation structure. Each first terminal structure includes a first conductive core, a first conductive coating surrounding the first conductive core, and a first conductive shell surrounding the first conductive coating. Each second terminal structure includes a second conductive core, a second conductive coating surrounding the second conductive core, and a second conductive shell surrounding the second conductive coating. The second conductive coating comprises a material different from the material of the first conductive coating.

Description

Prior Technology

[0001] In recent years, the semiconductor industry has experienced rapid growth due to continuous improvements in the packing density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). To a large extent, this increased packing density stems from the continuous reduction in minimum feature size, allowing more components to be integrated into a given area. These smaller electronic components also require smaller packages, occupying less area than previous packages. Therefore, new packaging technologies have begun to be developed. For example, some packages rely on solder bumps for electrical connections, and the different layers forming the interconnects within the package have different coefficients of thermal expansion (CTE). As a result, relatively large stresses due to this difference are manifested in the bonding areas, leading to the risk of delamination and / or cold solder joints. These relatively new semiconductor device packaging technologies face manufacturing challenges. Simple Explanation of the Diagram

[0002] The best understanding of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1 to 4A, 5A and 6 are schematic cross-sectional views of various stages of manufacturing the packaging structure according to some embodiments. Figure 4B is a schematic plan view of a canopy structure according to some embodiments. Figure 5B is a schematic plan view of the structure shown in Figure 5A according to some embodiments. Figure 7 is a schematic cross-sectional view of another embodiment of the packaging structure according to some embodiments. Figures 8 and 9 are schematic cross-sectional views of various stages of manufacturing the packaging structure according to some embodiments. Figures 10A to 10D are schematic enlarged cross-sectional views of a first terminal structure according to some embodiments. Figures 11A to 11C are schematic enlarged cross-sectional views of a second terminal structure according to some embodiments. Figures 12A and 12B are schematic cross-sectional views of another embodiment of the packaging structure according to some embodiments. Implementation

[0003] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0005] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on redistribution layers or substrates, which allow for testing of 3D packages or 3DICs, probes and / or probe cards, etc. Verification testing can be performed on intermediate and final structures. In addition, the structures and methods disclosed herein can be combined with intermediate verification test methods incorporated into known good dies to increase yield and reduce costs.

[0006] According to some embodiments, Figures 1 to 4A, 5A and 6 are schematic cross-sectional views of various stages of manufacturing the packaging structure, Figure 4B is a schematic plan view of the cover structure, and Figure 5B is a schematic plan view of the structure shown in Figure 5A.

[0007] Referring to FIG1, a first encapsulation assembly 100 and a second encapsulation assembly 200 electrically coupled to the first encapsulation assembly 100 may be provided. In some embodiments, the first encapsulation assembly 100 and the second encapsulation assembly 200 are collectively referred to as device packages 10. A plurality of device packages 10 may be disposed on a frame 51. In some embodiments, the frame 51 includes a carrier on which a temporary adhesive is coated. For example, the first encapsulation assembly 100 is attached to the frame 51, and the second encapsulation assembly 200 is disposed on the first encapsulation assembly 100. In some embodiments, the device packages 10 are provided in wafer form and mounted on the frame 51, and then a dicing process is performed on the wafer to separate the device packages 10 from each other. In some embodiments, after the dicing process, the outer sidewalls of the first encapsulation assembly 100 and the outer sidewalls of the second encapsulation assembly 200 are substantially flush (or coplanar) within a process variation range. The frame 51 may be referred to as a diced frame. In alternative embodiments, the frame 51 is replaced by another suitable type of temporary carrier.

[0008] Referring again to FIG1, the corresponding first package assembly 100 may include at least one semiconductor die 110 encapsulated by an insulating encapsulator 120. The corresponding semiconductor die 110 may include a first side 110a, a second side 110b opposite to the first side 110a, and sidewalls 110s connected to the first side 110a and the second side 110b. In some embodiments, the semiconductor die 110 includes die connectors 112 (e.g., microbumps, capped or uncovered metal pillars, controlled collapse chip connection (C4) bumps, or the like) distributed on the first side 110a for electrically connecting the second package assembly 200. The corresponding semiconductor die 110 may (or may not) include an interconnect layer 114 for connecting active / passive elements (not shown) formed on / in a semiconductor substrate 116 to the die connectors 112. The semiconductor substrate 116 may be a semiconductor material, including but not limited to bulk silicon, semiconductor wafers, silicon-germanium substrates, silicon-on-insulator (SOI) substrates, etc. Other semiconductor material elements including those from Group III, Group IV, and Group V may be used. In some embodiments, the interconnect layer 114 includes a plurality of dielectric layers, metal lines formed in the dielectric layers, and vias formed between the upper and lower metal lines. It should be noted that the configuration and number of semiconductor dies 110 shown herein are for illustrative purposes only, and any other configuration and number of semiconductor dies 110 may be used according to product requirements.

[0009] Referring again to Figure 1, the corresponding semiconductor die 110 may have a single function (e.g., a logic die, a processor die (e.g., a central processing unit (CPU) die, a graphics processing unit (GPU) die, an application-specific integrated circuit (ASIC) die, etc.), a memory die (e.g., a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, a stacked memory module, a high-bandwidth memory (HBM) die, etc.), an RF die, a mixed-signal die, an I / O die, a combination thereof, and / or similar). For example, the semiconductor die 110 is formed in a device wafer (not shown), which includes different die regions divided to form a plurality of semiconductor dies 110. After dicing, the semiconductor dies 110 are mounted to predetermined locations in the second package assembly 200. In some embodiments, the semiconductor die 110 may have different sizes (e.g., occupying different areas) and different functions. Alternatively, the semiconductor die 110 may be of the same / similar size. Other types of semiconductor dies 110 may be used depending on product requirements.

[0010] Referring again to FIG1, the insulating encapsulation 120 may extend at least along the sidewalls 110s of the semiconductor die 110 for protection. The insulating encapsulation 120 may be or may include molding compounds, epoxy resins, molding underfills, and / or the like, and may be applied by compression molding, transfer molding, etc. For example, the insulating encapsulation 120 is formed on the second package assembly 200, and the semiconductor die 110 is buried or covered by the insulating encapsulation 120. In some embodiments, the insulating encapsulation 120 is thinned to expose the second side 110b of the semiconductor die 110. The thinning process may be performed by chemical-mechanical polishing (CMP), grinding, etching, or combinations thereof. In some embodiments, after the thinning process, the first surface 120a of the insulating encapsulation 120 and the second side 110b of the semiconductor die 110 are substantially flush (or coplanar) within the range of process variations.

[0011] Referring again to FIG1, an underfill layer UF1 may optionally be formed in the gap between the respective semiconductor die 110 and the second package assembly 200 to laterally cover the electrical connection between the die connector 112 and the second package assembly 200. In some embodiments, a portion of the underfill layer UF1 rises upward to at least partially cover the sidewalls 110s of the semiconductor die 110. An insulating encapsulation 120 may be formed after the underfill layer UF1 is formed, such that the remaining sidewalls 110s of the semiconductor die 110 not covered by the underfill layer UF1 may be covered by the insulating encapsulation 120. Alternatively, the underfill layer UF1 may be omitted, and the gap between the semiconductor die 110 and the second package assembly 200 may be covered by the insulating encapsulation 120 (e.g., a molded underfill).

[0012] Referring again to FIG. 1, the second package assembly 200 may (or may not) include active and / or passive elements. In some embodiments, the second package assembly 200 serves as an intermediary. Semiconductor dies 110 may be electrically coupled to each other via the second package assembly 200. For example, the second package assembly 200 includes an interconnect structure 212 on a first side 200a of the second package assembly 200. The interconnect structure 212 may include a plurality of dielectric layers, conductive patterns embedded in the dielectric layers, and vias interconnecting two vertically adjacent layers of the conductive patterns. In some embodiments, an additional interconnect structure is formed on a second side 200b opposite to the first side 200a for electrically connecting the semiconductor dies 110. In some embodiments, the second package assembly 200 includes a plurality of conductive terminals 211 distributed on the first side 200a and connected to the interconnect structure 212. The conductive terminal 211 may be or may include C4 bumps, metal pillars, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, solder balls, ball-grid-array (BGA) connectors and / or the like.

[0013] Referring again to FIG. 1, the interconnect structure 212 may be formed on the semiconductor substrate 214. The semiconductor substrate 214 may be made of a material similar to that of the semiconductor substrate 116 or may be formed of other suitable materials. For example, after a dicing process, the device package 10 has an edge formed by the interconnect structure 212, the semiconductor substrate 214, and the continuous sidewalls 10W of the insulating encapsulation 120. The second package assembly 200 may include a plurality of conductive vias 216 penetrating the semiconductor substrate 214 to provide a vertical and electrical connection between opposite sides of the semiconductor substrate 214. For example, the conductive vias 216 are electrically connected to the conductive pattern of the interconnect structure 212 and extend into the first package assembly 100 to connect to the conductive pattern 218 (e.g., a contact pad) at a second side 200b of the second package assembly 200. The die connector 112 of the semiconductor die 110 may be in physical and electrical contact with one side of the conductive pattern 218, and the conductive vias 216 connect to the other side of the conductive pattern 218. The second packaging component 200 may optionally include a dielectric layer formed on a semiconductor substrate 214 to cover a conductive pattern 218 (e.g., a contact pad) for protection, and an insulating encapsulator 120 (and an underfill layer UF1, if present) may be formed on the dielectric layer.

[0014] In an alternative embodiment, the second package assembly 200 is formed as a fan-out redistribution structure, wherein the semiconductor substrate 214 and conductive vias 216 are omitted or can be replaced by other interconnect layers. In such an embodiment, the first and second package assemblies are collectively referred to as integrated fan-out (InFO) packages. It should be noted that the second package assembly 200 shown herein is for illustrative purposes only, and the second package assembly 200 may contain additional or fewer components.

[0015] Referring to Figures 2-3 and Figure 1, the corresponding device package 10 can be disposed on and connected to the first side 300a of the third package assembly 300 by, for example, immersing the conductive terminals 211 sequentially in flux material 522, and then using a pick-and-place tool (not shown) to substantially align the corresponding device package 10 with the corresponding area of ​​the third package assembly 300. In some embodiments, the flux material 522 comprises a liquid poured into a tray 52, and a portion of the device package 10 can be placed near the tray 52 and lowered toward the flux material 522 until the conductive terminals 211 are at least partially immersed in the flux material 522. A portion of the flux material 522 can adhere to the conductive terminals 211. Alternatively, the flux material 522 can be sprayed onto the conductive terminals 211. Other suitable methods can also be used to form the flux material 522 on the conductive terminals 211.

[0016] Referring again to FIG3, the device package 10 may be disposed on the third package assembly 300, and a reflow process may be performed on the conductive terminals 211 to bond the conductive terminals 211 to the third package assembly 300. In some embodiments, an underfill layer UF2 is formed between the gap between the second package assembly 200 and the third package assembly 300 to protect the conductive terminals 211. In some embodiments, a sufficient amount of underfill material is dispensed, and a portion of the underfill layer UF2 rises upward to at least partially cover the continuous sidewalls 10W of the device package 10. Alternatively, the underfill layer UF2 may be omitted.

[0017] Referring again to FIG3, a first side 300a of the third package assembly 300 may physically and electrically contact the conductive terminals 211 of the second package assembly 200, wherein the second package assembly 200 is interposed between the first package assembly 100 and the first side 300a of the third package assembly 300. In some embodiments, the third package assembly 300 includes a contact pad 311A ​​on the first side 300a so that the conductive terminals 211 rest thereon. A mask layer 305A (e.g., a solder mask or the like) may be selectively formed to partially cover the contact pad 311A ​​to prevent bridging and protect the underlying trace layer. In some embodiments, the third package assembly 300 is a laminated package substrate in which conductive patterns are embedded in a laminated dielectric layer. In some embodiments, the third packaging component 300 is an added-layer packaging substrate, including a core layer 310 (e.g., BT resin, FR-4, ceramic, glass, plastic, or other support material), trace layers (312A and 312B) respectively constructed on opposite sides of the core layer 310, dielectric layers (314A and 314B) respectively covering the trace layers (312A and 312B), and vias 316 passing through the core layer 310 to connect to the trace layers (312A and 312B) on opposite sides of the core layer 310. For example, a contact pad 311A ​​is formed on the trace layer 312A, wherein each trace layer (312A and 312B) includes a conductive pad, vias, and wires, etc. In some embodiments, the packaging substrate is a multilayer circuit board (e.g., a printed circuit board (PCB)) or other types of packaging substrates depending on product requirements.

[0018] Referring again to FIG. 3, the device package 10 may be arranged in a first region R1 of the third package assembly 300. In some embodiments, one or more fourth package assemblies 40 are attached to a first side 300a of the third package assembly 300 and arranged within a second region R2. For example, the first region R1 is surrounded by the second region R2. It should be understood that warping may occur due to differences between the different materials of the plurality of package assemblies. For example, different coefficients of thermal expansion (CTE) between the elements of the device package 10 and the elements of the third package assembly 300 may cause warping. In some embodiments, the device package 10 in the first region R1 dominates the warping of the resulting package structure compared to the fourth package assembly 40 in the second region R2. The fourth package assembly 40 may be or may include an integrated passive device (IPD), an integrated voltage regulator (IVR), an active element, and / or the like. In some embodiments, the corresponding fourth encapsulation component 40 is mounted on the third encapsulation component 300 via a device connector 45 resting on the contact pad 311A ​​of the third encapsulation component 300. Other types of connections between the third and fourth encapsulation components may be used. It should be noted that the two fourth encapsulation components 40 shown in FIG3 are for illustrative purposes only, and this disclosure does not constitute a limitation on the number and configuration of the fourth encapsulation components 40.

[0019] Referring to Figures 4A-4B and Figure 3, the structure of Figure 3 can be flipped over and placed on a temporary carrier 53. The material of the temporary carrier 53 may include glass, metal, ceramic, silicon, plastic, combinations thereof, multilayers thereof, or other suitable materials that can provide structural support for the structure above in subsequent processing. In some embodiments, attaching the device package 10 to the temporary carrier 53 by means of the temporary adhesive layer DF1 includes bonding the first surface 120a of the insulating encapsulation 120 and the second side 110b of the semiconductor die 110 to the temporary carrier 53. The temporary adhesive layer DF1 may be or may include a polymer layer, a UV-curable layer, and / or other suitable temporary adhesive. Alternatively, the temporary adhesive layer DF1 may be omitted.

[0020] Referring again to Figures 4A, 4B, and 3, the dome structure 54 can be placed on the second side 300b of the third encapsulation assembly 300, opposite the first side 300a. In some embodiments, the dome structure 54 is a screen and includes a first opening OP1 and a second opening OP2, wherein the first opening OP1 and the second opening OP2 have different dimensions. For example, the lateral dimension OD1 of the corresponding first opening OP1 is larger than the lateral dimension OD2 of the corresponding second opening OP2. In some embodiments, the first openings OP1 are arranged in an array within the central region CR1 of the dome structure 54, while the second openings OP2 are distributed around the central region CR1 within the peripheral region CR2 of the dome structure 54, as shown in the plan view of Figure 4B. Since the mask structure 54 is placed on top of the third encapsulation assembly 300, the central region CR1 of the mask structure 54 with the first opening OP1 can overlap with the first region R1 of the third encapsulation assembly 300 (or directly above the first region R1 of the third encapsulation assembly 300), and the peripheral region CR2 of the mask structure 54 with the second opening OP2 can overlap with the second region R2 of the third encapsulation assembly 300 (or directly above the second region R2 of the third encapsulation assembly 300).

[0021] Referring again to FIG4A, the first opening OP1 and the second opening OP2 of the cover structure 54 are substantially aligned with the contact pad 311B, such that the first conductive ball 321' and the second conductive ball 322' can be accurately placed on the portion of the contact pad 311B exposed by the cover layer 305B. After the cover structure 54 is placed above the second side 300b of the third encapsulation assembly 300, the first conductive ball 321' and the second conductive ball 322' can fall into the first opening OP1 and the second opening OP2, respectively. In some embodiments, the first conductive ball 321' passes through the first opening OP1 before the second conductive ball 322' passes through the second opening OP2.

[0022] Referring again to Figure 4A, the size and volume of the corresponding first conductive sphere 321' may be larger than the size and volume of the corresponding second conductive sphere 322'. In some embodiments, the cross-sectional profiles of the corresponding first conductive sphere 321' and the corresponding second conductive sphere 322' are different. For example, the corresponding second conductive sphere 322' has a substantially circular cross-section, and the corresponding first conductive sphere 321' has an arcuate non-circular cross-section (e.g., an oval cross-section, an elliptical cross-section, a spherical cross-section, etc.). Each of the first conductive sphere 321' and the second conductive sphere 322' may include two equatorial radii along the x-axis and y-axis and a polar radius along the z-axis. The polar radius of the corresponding first conductive sphere 321' may be larger than the two equatorial radii of the corresponding first conductive sphere 321'. All radii of the second conductive sphere 322' may be substantially the same.

[0023] As shown in Figure 4A, the cross-section of the corresponding first conductive sphere 321' includes a first axis (e.g., a major axis or principal axis) along the Z direction and a second axis (e.g., a minor axis or secondary axis) along the X direction, wherein the diameter BH1 along the major axis is larger than the diameter BD1 along the minor axis. For example, the corresponding first conductive sphere 321' is oval, ellipsoidal, oblate, or similar. The diameter BD1 of the corresponding first conductive sphere 321' may be smaller than the lateral dimension OD1 of the first opening OP1, such that the corresponding first conductive sphere 321' can pass through the first opening OP1. For example, the ratio of the lateral dimension OD1 to the diameter BD1 is in the range of about 5% to about 10%. The cross-section of the corresponding second conductive sphere 322' includes a first axis along the Z direction and a second axis along the X or Y direction, wherein the diameter BH2 ​​along the first axis is substantially equal to the diameter BD2 along the second axis. The diameter (BD2 or BH2) of the corresponding second conductive sphere 322' can be smaller than the lateral dimension OD2 of the second opening OP2, so that the corresponding second conductive sphere 322' can pass through the second opening OP2. For example, the ratio of the lateral dimension OD2 to the diameter BD2 is in the range of about 5% to about 10%.

[0024] Referring again to Figure 4A, the corresponding first conductive ball 321' may include a conductive core 3211, a conductive coating 3212 surrounding the conductive core 3211, and a conductive shell 3213 surrounding the conductive coating 3212, wherein the conductive core 3211, the conductive coating 3212, and the conductive shell 3213 are made of different materials. The conductive core 3211 may include copper, its alloys, or the like. The conductive coating 3212 may include silver, cobalt, bismuth, zinc, nickel, their alloys, combinations thereof, etc. The conductive coating 3212 may be a single layer or a composite layer including different materials. The conductive shell 3213 may include solder materials made of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-lead, tin-copper, tin-zinc-indium, tin-silver-antimony, etc.

[0025] Referring again to Figure 4A, the corresponding second conductive ball 322' may include a conductive core 3221, a conductive coating 3222 surrounding the conductive core 3221, and a conductive shell 3223 surrounding the conductive coating 3222, wherein the conductive core 3221, the conductive coating 3222, and the conductive shell 3223 are made of different materials. The conductive core 3221 may contain copper, its alloys, or the like. In some embodiments, the conductive cores (3211 and 3221) are made of the same / similar metallic material. The conductive coating 3222 may include nickel, its alloys, combinations thereof, etc. The conductive coating 3222 may be a single layer or a composite layer comprising different materials. For example, the material of the conductive coating 3222 of the second conductive ball 322' is different from the material of the conductive coating 3212 of the corresponding first conductive ball 321'. The conductive housing 3223 may include solder materials made of tin, tin silver, tin-lead, tin silver copper, tin silver zinc, tin zinc, tin bismuth-indium, tin-indium, tin-gold, tin lead, tin copper, tin zinc indium, tin silver antimony, etc.

[0026] Referring to Figures 5A and 5B and Figures 4A and 4B, after the first conductive ball 321' and the second conductive ball 322' land on the contact pad 311B, a reflow process can be performed on the first conductive ball 321' and the second conductive ball 322' to form the first terminal structure 321 and the second terminal structure 322, respectively. Physical and electrical connections can be made between the respective terminal structures (e.g., the first terminal structure 321 and the second terminal structure 322) and the respective contact pads 311B of the third package assembly 300. During the reflow process, the conductive housings (3213 and 3223) can be reflowed. In some embodiments, the reflow temperature is in the range of about 150°C to about 250°C, for example, about 200°C. The reflow temperature and process parameters may vary depending on the material of the first conductive ball 321' and the second conductive ball 322'. Because the reflow temperature is close to (or exceeds) the melting temperature of the solder material, the reflow process can alter the cross-sectional profile of the conductive housings (3213 and 3223). In some embodiments, after the reflow process, the temporary carrier 53 is removed from the device package 10 by, for example, peeling off the temporary adhesive layer DF1 or using any suitable removal technique to expose the first surface 120a of the insulating encapsulation 120 and the second side 110b of the semiconductor die 110.

[0027] As shown in the enlarged cross-sectional view (i.e., dashed box A) in Figure 5A, the first terminal structure 321 may include a conductive core 3211, a conductive coating 3212 surrounding the conductive core 3211, and a conductive shell 3213 surrounding the conductive coating 3212 and connected to the contact pad 311B, wherein an intermetallic compound (IMC) layer C1 is formed at the interface between the conductive coating 3212 and the conductive shell 3213. The contact pad 311B may be physically separated from the conductive coating 3212 by a portion of the conductive shell 3213 (and the IMC layer C1, if present). A portion of the conductive shell 3213 may include a non-zero thickness Tc1. For example, the conductive core 3211 is suspended in a solder layer (e.g., the conductive shell 3213). The conductive core 3211 may have an arcuate non-circular cross-section (e.g., an oval cross-section, an elliptical cross-section, a spherical cross-section, etc.). For example, the conductive core 3211 is oval, ellipsoidal, or oblate. The cross-section of the conductive core 3211 may include a first axis (e.g., a major axis or principal axis) along the Z direction and a second axis (e.g., a minor axis or secondary axis) along the X direction, wherein the diameter DC1 along the major axis is greater than the diameter DB1 along the minor axis. The ratio of diameter DB1 to diameter DC1 is greater than 0 and less than 1. The conductive coating 3212 may have a non-zero thickness Tb. For example, the thickness Tb is substantially equal to or greater than 10 nm.

[0028] As shown in the enlarged cross-sectional view (i.e., dashed box B) in Figure 5A, the second terminal structure 322 may include a conductive core 3221, a conductive coating 3222 surrounding the conductive core 3221, a conductive shell 3223 surrounding the conductive coating 3222 and connected to the contact pad 311B, and an intermetallic compound (IMC) layer C2 formed at the interface between the conductive coating 3222 and the conductive shell 3223. The contact pad 311B may be physically separated from the conductive coating 3222 by a portion of the conductive shell 3223 (and the IMC layer C2, if present). The portion of the conductive shell 3223 may include a non-zero thickness Tc2. For example, the conductive core 3221 is suspended in a solder layer (e.g., the conductive shell 3223). The conductive core 3221 may have a substantially circular cross-section. For example, the conductive core 3221 is a substantially sphere with a spherical shape. The cross-section of the conductive core 3211 may include a first axis along the Z direction and a second axis along the X or Y direction, wherein the diameter DD1 along the first axis is substantially equal to the diameter DD1 along the second axis. The ratio of diameter DD1 to diameter DD2 is substantially equal to 1. The conductive coating 3222 may have a non-zero thickness Ts. For example, the thickness Ts is substantially equal to or greater than 10 nm.

[0029] Referring again to dashed boxes A and B in Figure 5A, the overall size and volume of the first terminal structure 321 may be larger than the overall size and volume of the second terminal structure 322. The first terminal structure 321 can be considered a large terminal, while the second terminal structure 322 can be considered a small terminal. The cross-sectional area of ​​the conductive core 3211 of the first terminal structure 321 may be larger than the cross-sectional area of ​​the conductive core 3221 of the second terminal structure 322. For example, along the Z-direction, the diameter DC1 of the conductive core 3211 of the first terminal structure 321 is larger than the diameter DD1 of the conductive core 3221 of the second terminal structure 322. Along the X or Y direction, the diameter DB1 of the conductive core 3211 of the first terminal structure 321 may be larger than or substantially equal to the diameter DD1 of the conductive core 3211 of the second terminal structure 322. In some embodiments, the ratio (DC / DB1) is greater than the ratio (DD1 / DD1).

[0030] Referring again to Figure 5A, during the reflow process, tin in the conductive housing (e.g., 3213 and 3223) may tend to migrate and react with the conductive coating (e.g., 3212 and 3222) to form IMC layers (e.g., C1 and C2). The conductive coating (e.g., 3212 and 3222) may be consumed during IMC formation. For example, the reflow process results in the formation of IMC layer C1 at the interface between conductive housing 3213 and conductive coating 3212, and IMC layer C2 at the interface between conductive housing 3223 and conductive coating 3222. The IMC layers (C1 and C2) may each be materials formed by the reaction between the material of the conductive housing (e.g., solder material) and the material of the conductive coating (e.g., silver, cobalt, zinc, bismuth, nickel, etc.). The IMC layer C1 in the corresponding first terminal structure 321 and the IMC layer C2 in the corresponding second terminal structure 322 may include different compositions.

[0031] In some embodiments, the conductive coating 3222 is made of nickel and the conductive housing 3223 is made of solder, and the IMC layer C2 in the corresponding second terminal structure 322 is a tin-nickel alloy such as Ni3Sn4. In some embodiments, the conductive coating 3212 is made of silver and the conductive housing 3213 is made of solder, and the IMC layer C1 in the corresponding first terminal structure 321 is a tin-silver alloy such as Ag3Sn. When the conductive coating 3212 is made of cobalt, the IMC layer C1 may be CoSn3. When the conductive coating 3212 is made of zinc, the IMC layer C1 may be zinc. When the conductive coating 3212 is made of bismuth, the IMC layer C1 may be bismuth. The conductive coatings (e.g., 3212 and 3222) may be made of any suitable metallic material capable of reacting with the conductive housings (e.g., 3213 and 3223) to form an IMC layer, and such IMC layers may be configured to reduce or suppress the diffusion of copper from the contact pad 311B to the corresponding conductive housings (e.g., 3213 and 3223). If the copper in contact pad 311B is consumed too quickly, an open-circuit fault may occur. By configuring a conductive coating between the conductive shell and the conductive core to form an IMC layer at the interface between the conductive shell and the conductive coating, the diffusion of copper from contact pad 311B to the conductive shell can be effectively suppressed.

[0032] Referring again to FIG. 5B, a first terminal structure 321 may be arranged within a first region R1, while a second terminal structure 322 may be distributed within a second region R2. For example, in a top view, the maximum length LA1 of the first region R1 is less than the maximum length LA2 of the second region R2. The ratio of the maximum length LA1 to the maximum length LA2 may be greater than 0 and less than 1. In some embodiments, the maximum length LA2 of the second region R2 is substantially equal to the length of the second side 300b of the third encapsulation assembly 300. In a top view, the maximum width WA1 of the first region R1 may be less than the maximum width WA2 of the second region R2. The ratio of the maximum width WA1 to the maximum width WA2 may be greater than 0 and less than 1. In some embodiments, the maximum width WA2 of the second region R2 is substantially equal to the width of the second side 300b of the third encapsulation assembly 300. It should be noted that the number of first terminal structures 321 in the first region R1 and the number of second terminal structures 322 in the second region R2 shown in FIG. 5B are merely examples and do not constitute a limitation of this disclosure.

[0033] Referring to Figure 6 and Figure 5A, after the reflow process, the structure shown in Figure 5A can be flipped upside down, and the cover 420 can be attached to the third package assembly 300 and the device package 10 via the first adhesive layer 411 and the second adhesive layer 412, respectively. For example, the first adhesive layer 411 formed on the first side 300a of the third package assembly 300 includes any suitable adhesive material, including viscous gels or liquid materials, such as thermal paste, silver solder paste, polymer adhesives, or the like. The material of the first adhesive layer 411 may or may not have high thermal conductivity. The second adhesive layer 412 formed on the first surface 120a of the insulating encapsulation 120 and the second side 110b of the semiconductor die 110 may include any suitable material having high thermal conductivity to effectively dissipate the heat generated by the semiconductor die 110 into the cover 420. In some embodiments, the second adhesive layer 412 is a thermal interface material (TIM) layer designed with specific characteristics to meet specific requirements. In some cases, the second adhesive layer 412 may have higher thermal conductivity, while in alternative embodiments, the second adhesive layer 412 may have better adhesion.

[0034] Referring again to Figure 6, after attaching the cover 420 to the first side 300a of the third packaging assembly 300, the third packaging assembly 300 and the cover 420 define a cavity containing the device package 10 therein. The rigidity of the cover 420 is sufficient to protect the device package 10 and the third packaging assembly 300. In some embodiments, the cover 420 counteracts forces arising from mismatch caused by CTE between the device package 10 and the third packaging assembly 300. It should be noted that the cover 420 may have various feasible shapes and sizes depending on product requirements. The cover 420 may be configured to transfer heat generated from the device package 10 to a larger area and / or dissipate heat from the device package 10. The cover 420 may be a heat dissipation component (e.g., a heat sink, vapor chamber, or the like) placed above the device package 10, for example, by placing a process-placed heat dissipation component above the device package 10. The material of the cover 420 may be or may include copper, aluminum, silver, steel, stainless steel, metal alloys, combinations thereof, and / or other suitable materials with high thermal conductivity. In some embodiments, the cover 420 is a one-piece molded component. Alternatively, the cover 420 may include more than one component, which may be made of the same or different materials. For example, the cover may include a reinforcement attached to a third encapsulation assembly and an upper plate attached to the reinforcement.

[0035] Referring again to FIG. 6, a package structure 10_1 is provided. Package structure 10_1 may include a device package 10 stacked and bonded to a first side 300a of a third package assembly 300, a first terminal structure 321 and a second terminal structure 322 disposed at a second side 300b of the third package assembly 300 for further electrical connection, and a cover 420 attached to the first side 300a and the device package 10 of the third package assembly 300 to dissipate heat generated from the semiconductor die 110 of the device package 10. In some embodiments, the device package 10 and the third package assembly 300 are collectively referred to as a chip-on-wafer-on-substrate (CWB) structure. It should be noted that the CWB structure can be replaced by any suitable type of three-dimensional integrated circuit structure. Package structure 10_1 may include a larger terminal (e.g., the first terminal structure 321) disposed directly below the device package 10 and smaller terminals (e.g., the second terminal structure 322) distributed around the larger terminal.

[0036] Referring again to Figure 6, for the corresponding first terminal structure 321, the conductive core 3211 may be surrounded by a conductive shell 3213 with a conductive coating 3212 inserted between them, and an IMC layer C1 may be formed at the interface between the conductive shell 3213 and the conductive coating 3212. Similarly, for the corresponding second terminal structure 322, the conductive core 3221 may be surrounded by a conductive shell 3223 with a conductive coating 3222 inserted between them, and an IMC layer C2 may be formed at the interface between the conductive shell 3223 and the conductive coating 3222. Compared to solder terminals coupled to contact pad 311B (e.g., those excluding a copper core), coupling terminal structures (e.g., the first terminal structure 321 and the second terminal structure 322) to contact pad 311B can alleviate the local crowding effect, thereby improving electromigration performance. In some instances where solder terminals are coupled to contact pad 311B, the current density in the solder terminal may increase at the periphery of the interface between the solder terminal and the contact pad. This can lead to electromigration, which may be caused by localized current congestion. Due to the current congestion effect, electrical stress may be generated at the solder interface, leading to circuit failure. It should be understood that copper has a lower resistivity than solder material. By providing copper cores (e.g., conductive cores 3211 and 3221) in the terminal structures (e.g., 321, 322), electron flow can tend to travel along the middle portion of the respective conductive cores (3211, 3221), thereby mitigating the localized congestion effect and improving electromigration performance.

[0037] Referring again to Figure 6, the corresponding first terminal structure 321 may include a conductive core 3211 that is larger than the conductive core 3221 of the corresponding second terminal structure 322. For example, the cross-sectional area of ​​the conductive core 3211 of the corresponding first terminal structure 321 is larger than the cross-sectional area of ​​the conductive core 3221 of the corresponding second terminal structure 322. The larger the cross-sectional area of ​​the conductive core, the smaller the local congestion effect on the terminal structure and contact pad. By arranging the first terminal structure 321 including the larger conductive core 3211 in the first region R1 overlapping with the device package 10, not only can cold soldering problems caused by warpage be advantageously minimized or substantially eliminated, but the electromigration performance of the package structure can also be improved.

[0038] Referring again to FIG. 6, the conductive coating 3212 of the corresponding first terminal structure 321 may have a different metal material than the conductive coating 3222 of the corresponding second terminal structure 322. The IMC layer C1 in the corresponding first terminal structure 321 may have a different composition than the IMC layer C2 in the corresponding second terminal structure 322. By configuring the conductive coating between the conductive housing and the conductive core, the current carrying capacity of the IMC can be improved. The metal material of the conductive coating 3212 can be selected to reduce or suppress the reaction that could form an IMC between the conductive housing 3213 and the contact pad 311B. In some embodiments, the conductive coating 3212 is configured to reduce solder sources and interrupt solder diffusion paths. In this way, a more robust connection can be provided between the first terminal structure 321 and the contact pad 311B in the first region R1 (e.g., a warp-dominated region), and the performance and reliability of the package structure 10_1 can be improved.

[0039] Figure 7 is a schematic cross-sectional view of another embodiment of the packaging structure according to some embodiments. The packaging structure 20 in Figure 7 may be similar to the packaging structure 10_1 described with reference to Figure 6. Only the differences between them will be discussed; similar or identical parts will not be repeated, and similar reference numerals indicate similar elements. Referring to Figure 7 and Figure 6, the difference between packaging structure 20 and packaging structure 10_1 lies in the third packaging component. For example, the third packaging component 300' of packaging structure 20 is a coreless substrate.

[0040] Referring again to Figure 7, the third package assembly 300' includes a primary conductive pad 315, which includes a first side 315a and a second side 315b opposite to the first side 315a. The bottom layer of trace layer 312A is in physical and electrical contact with the first side 315a of the primary conductive pad 315, and the bottom layer of trace layer 312B is in physical and electrical contact with the second side 315b of the primary conductive pad 315. For example, the vias of the bottom layer of trace layer 312A falling on the primary conductive pad 315 taper in the direction from the first side 315a toward the second side 315b, while the vias of the bottom layer of trace layer 312B falling on the primary conductive pad 315 taper in the opposite direction. For the third package assembly 300', the core layer and the through-holes through the core layer are omitted (as shown in Figure 6).

[0041] Figures 8 and 9 are schematic cross-sectional views of various stages of manufacturing the package structure according to some embodiments. The manufacturing process of the package structure 30 in Figures 8 and 9 may be similar to that of the package structure 10_1 described with reference to Figures 1 to 6. Only the differences between them will be discussed; similar or identical parts will not be repeated, and similar reference numerals indicate similar elements.

[0042] Referring to FIG8 and FIG4A, the structure shown in FIG8 is similar to that shown in FIG4A, except that more than one conductive ball (e.g., 321', 322') passes through the corresponding opening (e.g., OP1, OP2) of the cover structure 54. For example, two (or more) first conductive balls 321' pass through the corresponding first opening OP1 to land on the same contact pad 311B. Similarly, two (or more) second conductive balls 322' may pass through the corresponding second opening OP2 to land on the same contact pad 311B. In some embodiments, the two (or more) first conductive balls 321' are substantially identical. The two (or more) second conductive balls 322' may be substantially identical. In alternative embodiments, conductive balls of different sizes / structures fall into the same opening (e.g., OP1, OP2) to land on the same contact pad 311B, as will be described later in conjunction with FIG10C-10D and FIG11B-11C.

[0043] Referring to FIG9 and FIG8 and 6, after the ball-mounting process, a reflow process can be performed as shown in FIG5A to form the first terminal structure 321A and the second terminal structure 322A, respectively. After forming the first terminal structure 321A and the second terminal structure 322A, the temporary carrier 53 can be removed from the device package 10 by, for example, peeling off the temporary adhesive layer DF1 or using any suitable removal technique to expose the first surface 120a of the insulating encapsulant 120 and the second side 110b of the semiconductor die 110. Next, the cover 420 can be attached to the third package assembly 300 and the device package 10 by means of the first adhesive layer 411 and the second adhesive layer 412, respectively, as shown in FIG6.

[0044] Referring again to Figures 9 and 6, a package structure 30 can be provided. Package structure 30 is similar to package structure 10_1 described in Figure 6, except that each terminal structure (e.g., 321A, 322A) includes multiple conductive cores (e.g., 3211, 3221) suspended in a solder layer (e.g., a corresponding conductive shell), wherein each conductive core (e.g., 3211, 3221) is coated with a corresponding conductive coating (e.g., 3212, 3222). For the corresponding first terminal structure 321A, two conductive cores 3211 may be enclosed by a conductive shell 3213, the two conductive cores 3211 being separate from each other and each conductive core 3211 being coated with a conductive coating 3212. Similarly, two conductive cores 3221 may be enclosed by a conductive shell 3223, the two conductive cores 3221 being separate from each other and each conductive core 3221 being coated with a conductive coating 3222. Conductive cores (e.g., 3211, 3221) encased in the same conductive shell (e.g., 3213, 3223) may be substantially identical (e.g., having the same dimensions / volume / weight, etc.). Alternatively, conductive cores of different dimensions may be encased in the same conductive shell, as will be described later in conjunction with Figures 10C-10D and 11B-11C.

[0045] Figures 10A to 10D are schematic enlarged cross-sectional views of a first terminal structure according to some embodiments. The first terminal structures in Figures 10A to 10D may be similar to the first terminal structures 321 and 321A described with reference to Figures 5A and 9. One or more of the first terminal structures of the package structures shown in Figures 5A and / or 9 may be replaced by the first terminal structures described in Figures 10A to 10D. Only the differences between them will be discussed; similar or identical parts will not be repeated, and similar reference numerals indicate similar elements.

[0046] Referring to Figure 10A and Figure 9, the first terminal structure 321B is similar to the first terminal structure 321A, except that the two conductive cores 3211A of the first terminal structure 321B are made of a different metal material than the conductive core 3211. In some embodiments, the conductive cores 3211A of the first terminal structure 321B are made of silver or its alloys. In some embodiments, the conductive cores 3211A have the same size / volume. Alternatively, the conductive cores 3211A may have different sizes and / or different materials. The conductive coating in the first terminal structure 321B may be omitted. For example, the conductive cores 3211A are surrounded by the conductive shell 3213 of the first terminal structure 321B, without any conductive coating inserted between them. In some embodiments, the first terminal structure 321B includes an IMC layer C1 formed at the interface between the conductive cores 3211A and the conductive shell 3213.

[0047] Referring to Figure 10B and Figure 10A, the first terminal structure 321C is similar to the first terminal structure 321B, except that each conductive core 3211A is coated with a conductive coating 3212A. The conductive coating 3212A and the corresponding conductive core 3211A can be made of different metallic materials. For example, the conductive core 3211A may be made of silver, its alloy, or the like, while the conductive coating 3212A may be made of cobalt, zinc, bismuth, nickel, etc. The first terminal structure 321C may include an IMC layer C1' formed at the interface between the conductive coating 3212A and the conductive shell 3213. Depending on the material of the conductive coating 3212A, the IMC layer C1' may include CoSn3, zinc, bismuth, Ni3Sn4, etc.

[0048] Referring to Figure 10C and Figure 9, the first terminal structure 321D is similar to the first terminal structure 321A, except that the first terminal structure 321D includes at least one primary conductive core 3211 and more than one secondary conductive core 3211B. Except that the secondary conductive core 3211B has a smaller size than the primary conductive core 3211, the corresponding secondary conductive core 3211B may be similar to the primary conductive core 3211. Each of the primary conductive core 3211 and the secondary conductive core 3211B may be coated with a conductive coating 3212. In some embodiments, the primary conductive core 3211 and the secondary conductive core 3211B are made of the same / similar metallic material, such as copper, its alloys, etc. In alternative embodiments, the primary conductive core 3211 and the secondary conductive core 3211B are made of silver, its alloys, etc. In some embodiments, the primary conductive core 3211 and the secondary conductive core 3211B are made of different metallic materials.

[0049] Referring to Figure 10D and Figure 10C, the first terminal structure 321E is similar to the first terminal structure 321D, except that the secondary conductive core 3211B is replaced by a metal bead 3211C. In some embodiments, the metal bead 3211C is not coated with any conductive coating. For example, the size of the primary conductive core 3211 is larger than the size of the corresponding metal bead 3211C. In some embodiments, the primary conductive core 3211 and the metal bead 3211C are made of the same / similar metallic material, such as copper, its alloys, etc. In alternative embodiments, the primary conductive core 3211 and the metal bead 3211C are made of silver, its alloys, etc. In some other embodiments, the primary conductive core 3211 and the metal bead 3211C are made of different metallic materials.

[0050] Referring again to Figures 9 and 10A through 10D, for the corresponding first terminal structures (e.g., 321A, 321B, 321C, 321D, and 321E), the ratio of the total volume of the conductive core (including primary and secondary conductive cores, or including primary conductive cores and metal beads) to the total volume of the first terminal structure can range from about 45% to about 95%. It should be noted that these values ​​are merely examples and can be adjusted according to various embodiments.

[0051] Figures 11A to 11C are schematic enlarged cross-sectional views of a second terminal structure according to some embodiments. The second terminal structures in Figures 11A to 11C may be similar to the second terminal structures 322 and 322A described with reference to Figures 5A and 9. One or more second terminal structures in the package structures shown in Figures 5A and / or 9 may be replaced by the second terminal structures described in Figures 11A to 11C. Only the differences between them will be discussed; similar or identical parts will not be repeated, and similar reference numerals indicate similar elements.

[0052] Referring to Figure 11A and Figure 9, the second terminal structure 322B is similar to the second terminal structure 322A, except that the two conductive cores 3221A of the second terminal structure 322B are made of a different metal material than the conductive core 3221. In some embodiments, the conductive cores 3221A of the second terminal structure 322B are made of silver, its alloys, or the like. In some embodiments, the conductive cores 3221A have substantially the same size / volume. Alternatively, the conductive cores 3221A may have different sizes and / or different materials. For example, the conductive cores 3221A are surrounded by the conductive shell 3213 of the first terminal structure 321B, and a conductive coating 3222 is inserted between them. The conductive coating 3222 may be made of nickel, cobalt, its alloys, etc. The second terminal structure 322B may include an IMC layer C2 formed at the interface between the conductive coating 3222 and the conductive shell 3223, and the composition of the IMC layer C2 may depend on the metal material of the corresponding conductive coating 3222.

[0053] Referring to Figure 11B and Figure 9, the second terminal structure 321C is similar to the first terminal structure 321A, except that the first terminal structure 322C includes at least one primary conductive core 3221 and more than one secondary conductive core 3221B. Except that the secondary conductive core 3221B has a smaller size than the primary conductive core 3221, the corresponding secondary conductive core 3221B may be similar to the primary conductive core 3221. Each of the primary conductive core 3221 and the secondary conductive core 3221B may be coated with a conductive coating 3222. In some embodiments, the primary conductive core 3221 and the secondary conductive core 3221B are made of the same / similar metallic material, such as copper, its alloys, etc. In alternative embodiments, the primary conductive core 3221 and the secondary conductive core 3221B are made of silver, its alloys, etc. In some other embodiments, the primary conductive core 3221 and the secondary conductive core 3221B are made of different metallic materials.

[0054] Referring to Figure 11C and Figure 11B, the second terminal structure 322D is similar to the first terminal structure 322C, except that the secondary conductive core 3221B is replaced by a metal bead 3221C. In some embodiments, the metal bead 3221C is not coated with any conductive coating. For example, the size of the primary conductive core 3221 is larger than the size of the corresponding metal bead 3221C. In some embodiments, the primary conductive core 3221 and the metal bead 3221C are made of the same / similar metallic material, such as copper, its alloys, etc. In alternative embodiments, the primary conductive core 3221 and the metal bead 3221C are made of silver, its alloys, etc. In some other embodiments, the primary conductive core 3221 and the metal bead 3221C are made of different metallic materials.

[0055] Referring again to Figures 9 and 11A-11C, for the corresponding second terminal structures (e.g., 322A, 322B, 322C, and 322D), the ratio of the total volume of the conductive core (including primary and secondary conductive cores, or including a primary conductive core and a metal bead) to the total volume of the second terminal structure can range from about 45% to about 95%. It should be noted that these values ​​are merely examples and can be adjusted according to various embodiments.

[0056] Figures 12A and 12B are schematic cross-sectional views of another embodiment of the package structure according to some embodiments. It should be noted that the package structures shown in Figures 12A and 12B are simplified; details of the package structure can be found in the package structures described in the preceding paragraphs (e.g., 10_1, 20, 30). The following discussion relating to Figures 12A and 12B focuses on the warpage of the package structure and the distribution of the first and second terminal structures.

[0057] Referring to Figure 12A, the encapsulation structure 40_1 shown in Figure 12A may be similar to the encapsulation structure 10_1 described in Figure 6, except that the cover and associated adhesive are not shown, and the encapsulation structure 40_1 is shown to have a protruding warp (e.g., a crying face profile). In some embodiments, the encapsulation structure 40_1 includes a first terminal structure 321 distributed in a central region of the encapsulation structure 40_1 and a second terminal structure 322 distributed in a peripheral region of the encapsulation structure 40_1. The distribution area of ​​the first terminal structure 321 on the third encapsulation assembly 300 may overlap with the orthogonal projection of the device package 10 on the third encapsulation assembly 300. The distribution area of ​​the second terminal structure 322 may surround the distribution area of ​​the first terminal structure 321. The encapsulation structure 40_1 heated at high temperatures may have some degree of warping. For example, the vertical distance WP1 between the highest point and the lowest point of the encapsulation structure 40_1 is in the range of about 50 micrometers to about 300 micrometers. Even if the package structure 40_1 is warped downwards, by arranging terminal structures of different sizes (e.g., 321 and 322) in the predetermined area, the coplanarity of the package structure 40_1 can be reduced and the flatness of the package structure 40_1 can be improved.

[0058] Referring to FIG12B and FIG12A, the package structure 50 may include a plurality of device packages 10' attached to the third package assembly 300. The corresponding device packages 10' may be similar to the device packages 10 described in the preceding embodiments. In some embodiments, the package structure 50 includes a first terminal structure 321 distributed in a peripheral region of the package structure 50 and a second terminal structure 322 distributed in a central region of the package structure 50 and surrounded by the first terminal structure 321. The package structure 50, when heated at high temperatures, may warp and exhibit concave warping (e.g., a smiley face profile). For example, the vertical distance WP2 between the highest point and the lowest point of the package structure 50 is in the range of approximately 50 micrometers to approximately 300 micrometers. Even if the package structure 50 warps upwards, by configuring terminal structures of different sizes (e.g., 321 and 322) in different regions, the coplanarity of the package structure 50 can be reduced, and the flatness of the package structure 50 can be improved.

[0059] According to some embodiments, a packaging structure includes a packaging substrate and first and second terminal structures disposed on a first side of the packaging structure. Each first terminal structure includes a first conductive core, a first conductive coating surrounding the first conductive core, and a first conductive shell surrounding the first conductive coating. Each second terminal structure includes a second conductive core, a second conductive coating surrounding the second conductive core, and a second conductive shell surrounding the second conductive coating. The second conductive coating includes a material different from the material of the first conductive coating.

[0060]

[0061] According to some embodiments, a packaging structure includes a packaging substrate, the packaging substrate including a first region and a second region, a device package disposed on one side of the packaging substrate and within the first region, a first terminal structure disposed on the opposite side of the packaging structure and within the first region, and a second terminal structure disposed on the opposite side of the packaging structure and within the second region. Each first terminal structure includes a first solder layer and a first conductive core suspended in the first solder layer. Each second terminal structure includes a second solder layer and a second conductive core suspended in the second solder layer, wherein the cross-sectional area of ​​the first conductive core is larger than the cross-sectional area of ​​the second conductive core.

[0062]

[0063] According to some embodiments, a method of manufacturing a package structure includes: coupling a device package to a first side of a package substrate; placing a first conductive ball on a second side of the package substrate, wherein a distribution area of ​​the first conductive ball on the package substrate overlaps with an orthogonal projection of the device package on the package substrate; placing a second conductive ball on a second side of the package substrate outside the distribution area of ​​the first conductive ball; and reflowing the first and second conductive balls to form a first terminal structure and a second terminal structure, respectively. Each first terminal structure includes a first conductive core suspended in a first solder layer, and each second terminal structure includes a second conductive core suspended in a second solder layer, wherein the cross-sectional area of ​​the first conductive core is larger than the cross-sectional area of ​​the second conductive core.

[0064]

[0065] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0066] 10, 10': Device package 10_1, 20, 30, 40_1, 50: Package structure 10W: Continuous sidewall 40: Fourth encapsulation component 45: Device connector 51: Framed 52: Pallet 53: Temporary carrier 54: Dome Structure 100: First encapsulation component 110: Semiconductor die 110a, 200a, 300a, 315a: First side 110b, 200b, 300b, 315b: Second side 110s: Sidewall 112: Grain connector 114: Interconnect layer 116, 214: Semiconductor substrate 120: Insulating Encapsulation 120a: First surface 200: Second encapsulation component 211: Conductive terminal 212: Internal Wiring Structure 216: Conductive Through-hole 218: Conductive Pattern 300, 300': Third encapsulation component 305A, 305B: Covering layer 310: Core Layer 311A, 311B: Contact pads 312A, 312B: Trace layer 314A, 314B: Dielectric layers 315: Main conductive pad 316: Perforation 321, 321A, 321B, 321C, 321D, 321E, 322C: First terminal structure 321': First conductive ball 322, 322A, 322B, 322D: Second terminal structure 322': Second conductive ball 411: First adhesive layer 412: Second adhesive layer 420: Cover 522: Flux Material 3211, 3221: Conductive core / Main conductive core 3211A, 3221A: Conductive core 3211B, 3221B: Secondary conductive core 3211C, 3221C: Metal beads 3212, 3212A, 3222: Conductive coating 3213, 3223: Conductive outer casing A, B: Dashed boxes BD1, BD2, BH1, BH2, DB1, DC1, DD1: Diameter C1, C1', C2: Intermetallic compound (IMC) layers CR1: Central District CR2: Outer Zone DF1: Temporary adhesive layer LA1, LA2: Maximum length OD1, OD2: Lateral dimensions OP1: First opening OP2: Second opening R1: Zone 1 R2: Second Zone Tb, Tc1, Tc2, Ts: Thickness UF1, UF2: Bottom filler layer WA1, WA2: Maximum width WP1, WP2: Vertical distance X, Y, Z: Direction

Claims

1. A packaging structure, comprising: Packaging substrate; A first terminal structure is disposed on a first side of the encapsulation structure, the first terminal structure comprising: a first conductive core; a first conductive coating surrounding the first conductive core; and a first conductive shell surrounding the first conductive coating; and a second terminal structure is disposed on the first side of the encapsulation structure, the second terminal structure comprising: a second conductive core; a second conductive coating surrounding the second conductive core and comprising a material different from the material of the first conductive coating; and a second conductive shell surrounding the second conductive coating.

2. The packaging structure as claimed in claim 1, wherein the volume of the first terminal structure is different from the volume of the second terminal structure.

3. The packaging structure as claimed in claim 1, wherein a first dimension of the first conductive core, measured along the long axis of the first conductive core, is different from a second dimension of the second conductive core, measured along the long axis of the second conductive core.

4. The packaging structure as claimed in claim 1, wherein a first ratio of a first dimension of the first conductive core measured along the long axis of the first conductive core to a second dimension of the first conductive core measured along the short axis of the first conductive core is greater than a second ratio of a third dimension of the second conductive core measured along the long axis of the second conductive core to a fourth dimension of the second conductive core measured along the short axis of the second conductive core.

5. The encapsulation structure as described in request item 1, wherein: The first terminal structure further includes a first intermetallic compound layer between the first conductive shell and the first conductive coating, and the second terminal structure further includes a second intermetallic compound layer between the second conductive shell and the second conductive coating, wherein the first intermetallic compound layer has a different composition from the second intermetallic compound layer.

6. The encapsulation structure as described in claim 1, further comprising: A device package is disposed on a second side of the package substrate opposite to the first side, wherein the distribution area of ​​the first terminal structure on the package substrate overlaps with the orthogonal projection of the device package on the package substrate.

7. The packaging structure as claimed in claim 1, wherein the first conductive core comprises a material different from the material of the first conductive coating, and the second conductive core comprises a material different from the material of the second conductive core.

8. The packaging structure as claimed in claim 1, wherein the first conductive core or the second conductive core comprises a plurality of conductive balls physically separated from each other.

9. A packaging structure, comprising: The packaging substrate includes a first region and a second region; A device package is disposed on one side of the package substrate and within the first region; A first terminal structure is disposed on the opposite side of the package structure and within the first region. The first terminal structure includes a first solder layer and a first conductive core suspended in the first solder layer. And a second terminal structure disposed on the opposite side of the package structure and within the second region, the second terminal structure including a second solder layer and a second conductive core suspended in the second solder layer, wherein the cross-sectional area of ​​the first conductive core is different from the cross-sectional area of ​​the second conductive core.

10. A method for manufacturing a packaging structure, comprising: Couple the device package to the first side of the package substrate; A first conductive ball is placed on the second side of the encapsulation substrate, wherein the distribution area of ​​the first conductive ball on the encapsulation substrate overlaps with the orthogonal projection of the device package on the encapsulation substrate; a second conductive ball is placed on the second side of the encapsulation substrate outside the distribution area of ​​the first conductive ball; and the first conductive ball and the second conductive ball are reflowed to form a first terminal structure and a second terminal structure, respectively, wherein the first terminal structure includes a first conductive core suspended in a first solder layer, the second terminal structure includes a second conductive core suspended in a second solder layer, and the cross-sectional area of ​​the first conductive core is larger than the cross-sectional area of ​​the second conductive core.

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