Semiconductor device

Abstract

A semiconductor device includes a substrate and a plurality of filler pillars. The substrate has a substrate body and a plurality of detection regions disposed on the top surface of the substrate body, wherein one of the detection regions comprises a fluorescent material. The top surface of the substrate body has a plurality of grooves, and each detection region corresponds to and is disposed in each groove. Each filler pillar is disposed on each detection region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Prior Art

[0002] When a hole (or trench) has a high aspect ratio, there is a problem in that the overlay error of the hole (or trench) cannot be detected by secondary electrons (eg, using a scanning electron microscope (SEM)).

[0003] Based on the aforementioned reasons, in order to solve the above-mentioned problems, it is necessary to provide a semiconductor device that can detect the overlay error of a hole (or trench) regardless of whether the hole (or trench) has a high aspect ratio. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a semiconductor device comprising a substrate and a plurality of filling pillars. The substrate comprises a substrate body and a plurality of detection regions disposed on a top surface of the substrate body, wherein one of the detection regions comprises a fluorescent material. The top surface of the substrate body comprises a plurality of recesses, and each detection region corresponds to and is disposed within each recess. Each filling pillar is disposed above each detection region.

[0005] In the foregoing, the top surface of the detection region is coplanar with the top surface of the substrate body, and the substrate body surrounds the bottom portion of each detection region.

[0006] In the foregoing, the substrate body comprises a first metal material, and one of the detection areas comprises a second metal material, wherein the second metal material is a fluorescent substance.

[0007] In the aforementioned, the fluorescent substance includes monovalent copper ions, monovalent silver ions, monovalent indium ions, divalent vanadium ions, divalent cobalt ions, divalent tin ions, divalent europium ions, divalent manganese ions, divalent nickel ions, divalent lead ions, trivalent bismuth ions, trivalent harzium ions, trivalent neodymium ions, trivalent samarium ions, trivalent europium ions, trivalent gadmium ions, trivalent zirconium ions, trivalent dysprosium ions, trivalent tantalum ions, trivalent rhenium ions, trivalent ytterbium ions, trivalent titanium ions, trivalent cerium ions, or a combination thereof.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the disclosure as claimed. Simple diagram description

[0009] The following diagrams and detailed descriptions clearly illustrate the spirit of the present disclosure. After understanding the preferred embodiments of the present disclosure, anyone with ordinary skill in the art can make changes and modifications based on the techniques taught by the present disclosure without departing from the spirit and scope of the present disclosure. Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments; 2-4, 5A, 6-7, and 8A are cross-sectional views of intermediate stages in the fabrication of a semiconductor device according to some embodiments of the present disclosure; and 5B and 8B are cross-sectional views of two intermediate stages in the fabrication of a semiconductor device according to some other embodiments of the present disclosure. Implementation Method

[0010] Hereinafter, reference will be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0011] The terminology used herein is for the purpose of describing specific example embodiments only and is not intended to limit the present disclosure. As used herein, singular forms such as "a," "an," and "the" include plural forms such as "at least one"; unless expressly stated otherwise, "or" represents "and / or." As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising," "including," and / or "having" specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0012] Embodiments of the present disclosure are described herein with reference to the top drawings, which are schematic illustrations of idealized embodiments of the present disclosure. As such, variations from the shapes of the drawings due to, for example, manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and / or nonlinear features. Furthermore, sharp angles in the drawings may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present disclosure.

[0013] Reference will now be made in detail to embodiments of the present disclosure, examples of which are described herein and illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with the exemplary embodiments, it will be understood that they are not intended to limit the present disclosure to those exemplary embodiments. Accordingly, the scope of the present disclosure is limited solely by the appended claims.

[0014] 1 , a method 100 for manufacturing a semiconductor device is shown. The method 100 includes steps S110 , S120 , S130 , S140 , S150 , and S160 . Steps S110 to S160 of FIG. 1 will be described in conjunction with the following figures.

[0015] Please refer to step S110 of FIG. 1 and FIG. 2 , a substrate body 210 is provided.

[0016] In some embodiments, the substrate body 210 may include a first metal material, such as copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, tungsten (W), a tungsten alloy, titanium (Ti), a titanium alloy, tantalum (Ta), a tantalum alloy, or a combination thereof. Alternatively, other suitable conductive materials may be used.

[0017] Referring to step S120 of FIG. 1 and FIG. 3 , a cover layer 220 is disposed on the substrate body 210 .

[0018] In some embodiments, the capping layer 220 may be, for example, a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a silicon-on-insulator (SOI) substrate, or a multilayer. For example, the capping layer 220 may be an insulating multilayer including an oxide layer and a carbon layer disposed on the oxide layer. In some other embodiments, a conductive material may be used in the capping layer 220.

[0019] In some embodiments, the cover layer 220 may be formed on the substrate body 210 by a suitable method, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0020] Referring to step S130 of FIG. 1 and FIG. 4 , a hole 222 is formed in the cover layer 220 .

[0021] In some embodiments, after forming the hole 222, the exposed portion 212 of the substrate body 210 is exposed. In some embodiments, the hole 222 has a high aspect ratio, such as from 5:1 to 100:1. For example, the hole 222 has an aspect ratio of 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 20:1, 30:1, 40:1, 50:1, 60:1, 70:1, 80:1, 90:1, 100:1, or any value within the aforementioned ranges. In some embodiments, the hole 222 is formed via a patterned capping layer 220. It is worth noting that because the actual position of the hole 222 with a high aspect ratio is difficult to locate using a scanning electron microscope (SEM), the overlay error of the hole 222 cannot be accurately determined. Specifically, due to the high aspect ratio of the hole 222, the secondary electrons reflected by the sidewalls of the cover layer 220 and the exposed portion 212 of the substrate body 210 cannot be received by the SEM.

[0022] 1 and FIG. 5A , a detection region 230 is disposed in the substrate body 210 corresponding to the hole 222. Thus, a semiconductor device 200A is formed.

[0023] In some embodiments, the detection regions 230 and the substrate body 210 form a substrate SUS, and each detection region 230 corresponds to each hole 222 so as to detect the position of each hole 222 in subsequent steps.

[0024] In some embodiments, a fluorescent material LM is doped into the substrate body 210 via ion implantation to form the detection region 230. The fluorescent material LM can emit fluorescence or phosphorescence after absorbing sufficient energy. Specifically, the detection region 230 includes the first metal material of the substrate body 210 and the fluorescent material LM doped into the first metal material. In some embodiments, the fluorescent material LM is a second metal material, such as monovalent copper ion (Cu+), monovalent silver ion (Ag+), monovalent indium ion (In+), divalent vanadium ion (V2+), divalent cobalt ion (Co2+), divalent tin ion (Sn2+), divalent europium ion (Eu2+), divalent manganese ion (Mn2+), divalent nickel ion (Ni2+), divalent lead ion (Pb2+), trivalent bismuth ion (Bi3+), trivalent harzium ion (Pr3+), trivalent neodymium ion (Nd3+), trivalent samarium ion (Sm3+), trivalent europium ion (Eu3+), trivalent gadolinium ion (Gd3+), trivalent zirconium ion (Tb3+), trivalent dysprosium ion (Dy3+), trivalent thorium ion (Ho3+), trivalent thorium ion (Tm3+), or trivalent thorium ion (Tm3+). 3+), trivalent ytterbium ion (Yb 3+), trivalent titanium ion (Ti 3+), trivalent cerium ion (Ce 3+), or a combination thereof, among which Nd 3+ can be used as an excellent candidate because of its concentrated and intense fluorescence.

[0025] It should be emphasized that, compared to selecting an insulating material as the fluorescent material LM, when the fluorescent material LM is selected as the second metal material, the conductive interference of the detection area 230 on the substrate body 210 can be reduced.

[0026] In some embodiments, after performing the ion implantation process, the detection regions 230 are embedded in the substrate body 210, so that the semiconductor device 200A appears as if the top surface 214 of the substrate body 210 has a plurality of recesses 216. Each detection region 230 corresponds to and is disposed within each recess 216. The detection regions 230 are disposed on and in contact with the top surface 214 of the substrate body 210, thereby enabling detection of the positions of the holes 222 in subsequent steps. In some embodiments, the top surface 232 of the detection regions 230 is coplanar with the top surface 214 of the substrate body 210, and the substrate body 210 surrounds the bottom portion 234 of each detection region 230.

[0027] It is worth noting that the configuration of the detection region 230 embedded in the substrate body 210 can reduce the conductive interference of the detection region 230 on the substrate body 210 and can be easily completed through ion implantation.

[0028] In some other embodiments, referring to step S140 of FIG. 1 and FIG. 5B , the detection region 230 is disposed on the substrate body 210 corresponding to the hole 222 .

[0029] FIG5B is substantially similar to FIG5A . The difference between FIG5B and FIG5A is that the semiconductor device 200B in FIG5B includes a detection material including a fluorescent substance LM (not shown in FIG5B ) disposed on the exposed portion 212 of the substrate body 210 to form a detection region 230 . Thus, the semiconductor device 200B is formed.

[0030] In some embodiments, each detection region 230 corresponds to each hole 222 and is disposed in each hole 222, and the bottom surface 236 of each detection region 230 is coplanar with the top surface 214 of the substrate body 210. In other words, the bottom surface 236 of each detection region 230 directly contacts the top surface 214 of the substrate body 210 and the sidewall 224 of the cover layer 220.

[0031] In some embodiments, the detection region 230 can be formed using a suitable method, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some embodiments, the detection material includes a fluorescent material LM (e.g., a second metal material, not shown in FIG5B ) and an additive comprising an inorganic material, a polymer, or a combination thereof. It should be noted that, compared to selecting an insulating material as the fluorescent material LM (not shown in FIG5B ), selecting the second metal material LM (not shown in FIG5B ) can reduce the conductive interference of the detection region 230 with the substrate body 210. In some other embodiments, the detection material is insulating and does not include a conductive material. For example, the fluorescent material LM (not shown in FIG. 5B ) includes fluorescent proteins (e.g., green fluorescent protein (GFP), enhanced green fluorescent protein (EGFP), blue fluorescent protein (BFP), cyan fluorescent protein (CFP), red fluorescent protein (RFP), white fluorescent protein (wtGFP), yellow fluorescent protein (YFP), dsRed, mCherry, mVenus, mCitrine, tdTomato, mTurquoise2, etc.), but does not include the second metal material.

[0032] It should be noted that the detection region 230 is disposed in the hole 222, and the bottom surface 236 of the detection region 230 is coplanar with the top surface 214 of the substrate body 210. This can be easily accomplished through a semiconductor process (such as CVD or PVD) without affecting the structure of the substrate body 210.

[0033] 1 and FIG. 6 , an electron beam E1 is provided to propagate to the detection region 230 so that one of the detection regions 230 emits a fluorescent signal L, wherein the semiconductor device 200A is only provided for illustration and is not limited thereto.

[0034] In some embodiments, when each detection region 230 includes a fluorescent material LM, an electron beam E1 is provided to propagate to the detection region 230 , so that each detection region 230 emits a fluorescent signal L.

[0035] In some embodiments, an electron beam E1 is generated by a charged particle source S1, such as a SEM. The electron beam E1 provides sufficient energy to the detection region 230, causing the fluorescent material LM (not shown in FIG. 6 ) to emit a fluorescent signal L. In some embodiments, as the electron beam E1 propagates along the detection region 230, it also propagates along the cover layer 220. Subsequently, the charged particle source S1 is used to detect secondary electrons E2 reflected from the cover layer 220 to determine the surface image of the cover layer 220. In other words, the electron beam E1 is provided to simultaneously generate an image of the surface of the cover layer 220 and generate the fluorescent signal L from the detection region 230 for further positioning.

[0036] Referring to step S160 of FIG. 1 and FIG. 7 , the overlay error of one of the holes 222 is determined based on the fluorescent signal L. Specifically, the overlay error of one of the holes 222 is determined by comparing the actual position of one of the holes 222 with the theoretical position of one of the holes 222, where the actual position is determined by detecting the fluorescent signal L, and the theoretical position is defined based on alignment marks on the substrate body 210. For example, the overlay error in the x-direction can be calculated using the following formula: Actual position in the x-direction - theoretical position in the x-direction.

[0037] In some embodiments, the overlay error of each hole 222 is determined by comparing the actual position of each hole 222 with the theoretical position of each hole 222. In some embodiments, the fluorescent signal L is detected by capturing a fluorescent image using a fluorescence microscope S2. In some embodiments, the fluorescent image obtained from the fluorescence microscope S2 can be combined with a surface image obtained from a charged particle source S1 (see FIG6 ) to more accurately define the actual position of the hole 222. It should be noted that due to the high aspect ratio of the hole 222, it is difficult to detect the actual position of the hole 222 by detecting secondary electrons E2 (see FIG6 ) using a SEM. In contrast, even if the hole 222 has a high aspect ratio, the actual position of the hole 222 can be detected by using a detection region 230 containing a fluorescent material LM (not shown in FIG7 ).

[0038] In some embodiments, referring to FIG. 8A , when the overlay error of the holes 222 falls within an acceptable range, filling pillars 310 are disposed on the detection region 230 of the semiconductor device 200A to form the semiconductor device 300A. Specifically, before forming the filling pillars 310, the overlay error of the holes 222 is confirmed to avoid unacceptable deviations in the filling pillars 310 due to deviations in the holes 222. In some embodiments, each filling pillar 310 is disposed on each detection region 230. For example, each filling pillar 310 is disposed directly on each detection region 230 and completely fills each hole 222.

[0039] In some embodiments, the filling pillars 310 comprise a third metal material, are disposed directly on the detection region 230, and fill the holes 222. For example, the filling pillars 310 can serve as contacts for a capacitor (not shown in FIG8A ). It is important to note that when the substrate body 210 and the filling pillars 310 are conductive, by selecting a conductive material (e.g., the second metal material) as the material for the detection region 230, the interference of the detection region 230 with the current passing through the substrate body 210 and the filling pillars 310 can be combined.

[0040] In some embodiments, see FIG. 8B . FIG. 8B is substantially similar to FIG. 8A . The difference between FIG. 8B and FIG. 8A is that the semiconductor device 300B in FIG. 8B exhibits a filling pillar 310 disposed on the detection region 230 of the semiconductor device 200B.

[0041] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device. The semiconductor device includes a hole in a detection region corresponding to a cover layer, and the detection region includes a fluorescent material. The use of the fluorescent material in the detection region can successfully confirm the overlay error of a hole with a high aspect ratio.

[0042] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended patent application should not be limited to the description of the embodiments contained herein.

[0043] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to encompass modifications and variations of the present disclosure that fall within the scope of the appended patent applications and their equivalents.

[0044] 100: Method 200A, 200B, 300A, 300B: Semiconductor components 210:Substrate body 212: Exposed part 214: Top surface 216: Groove 220: Covering layer 222: Hole 224: Sidewall 230: Detection area 232: Top surface 234: bottom part 236: bottom surface 310: Filling column E1: Electron Beam E2: Secondary electrons L: Fluorescent signal LM: Fluorescent material SUS:Substrate S1: Charged particle source S2: Fluorescence Microscopy S110, S120, S130, S140, S150, S160: Steps X: x direction Y:y direction Z: z direction

Claims

1. A semiconductor device comprising: a substrate having a substrate body and a plurality of detection regions disposed on a top surface of the substrate body, wherein one of the detection regions comprises a fluorescent material, the top surface of the substrate body having a plurality of grooves, and each detection region corresponding to and disposed in each groove, wherein the detection regions are fitted into the substrate body, a top surface of each detection region is coplanar with the top surface of the substrate body, and the substrate body surrounds a bottom portion of each detection region; a capping layer disposed on the substrate body, wherein the capping layer has a plurality of holes, and each detection region corresponds to each hole; and a plurality of filler pillars, wherein each filler pillar is disposed on each detection region, and a top surface of each filler pillar is completely coplanar with a top surface of the capping layer, wherein each filler pillar comprises a conductive material.

2. The semiconductor device as claimed in claim 1, wherein the substrate body comprises a first metal material, and one of the detection regions comprises a second metal material, wherein the second metal material is the fluorescent material.

3. The semiconductor device as claimed in claim 2, wherein the fluorescent material comprises monovalent copper ions, monovalent silver ions, monovalent indium ions, divalent vanadium ions, divalent cobalt ions, divalent tin ions, divalent europium ions, divalent manganese ions, divalent nickel ions, divalent lead ions, trivalent bismuth ions, trivalent ilium ions, trivalent neodymium ions, trivalent samarium ions, trivalent europium ions, trivalent thiocyanate ions, trivalent tungsten ions, trivalent dysprosium ions, trivalent holmium ions, trivalent thium ions, trivalent ytterbium ions, trivalent titanium ions, trivalent cerium ions, or combinations thereof.

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