Semiconductor stacked package and method of manufacturing the same

Abstract

A semiconductor stacked package includes a semiconductor die. The semiconductor die includes a substrate, a transistor, and a silicon through-hole structure. The transistor is disposed on the substrate. The silicon through-hole structure is perpendicular to the substrate and includes a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is located between the first conductive layer and the second conductive layer. A method for manufacturing a semiconductor stacked package includes the following steps: forming a via on a substrate; forming a first conductive layer in the via; forming a dielectric layer in the via and on the first conductive layer; forming a second conductive layer in the via and on the dielectric layer; and forming a transistor on the substrate. The first conductive layer, the second conductive layer, and the dielectric layer together form the silicon through-hole structure.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor stacked package and a method for manufacturing the same. Specifically, this disclosure relates to a semiconductor stacked package structure. [Previous Technology]

[0002] Semiconductor devices are indispensable for many modern applications. With the advancement of electronic technology, semiconductor devices are becoming smaller and smaller, while possessing stronger functionality and higher-density integrated circuits. Due to the miniaturization of semiconductor devices, wafer stacking technology is now widely used in the manufacture of semiconductor packages.

[0003] In some existing methods, by stacking at least two wafers (or dies) in 3D packaging to form, for example, memory devices, it is possible to produce products with twice the memory capacity achievable by other semiconductor integration processes. In addition to increasing memory capacity, stacked packaging can also improve assembly density and the utilization efficiency of the assembly area. Due to these advantages, research and development of stacked packaging technology has been accelerated. [Summary of the Invention]

[0004] This disclosure provides a through-silicon-via (TSV) structure in a substrate. The TSV structure includes a dielectric layer sandwiched between two conductive layers. With this configuration, the TSV structure can be used as a fuse protection structure, making it a possible option for memory applications in semiconductor stacked packages.

[0005] One aspect of this disclosure provides a semiconductor stacked package including a semiconductor die. The semiconductor die includes a substrate, a transistor, and a silicon through-hole structure. The transistor is disposed on the substrate. The silicon through-hole structure is perpendicular to the substrate and includes a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is located between the first conductive layer and the second conductive layer.

[0006] In some embodiments, the dielectric layer has a rod-shaped cross-sectional profile.

[0007] In some embodiments, the first conductive layer and the second conductive layer have substantially the same width.

[0008] In some embodiments, the dielectric layer comprises an oxide.

[0009] In some embodiments, the dielectric layer is an oxide of the material of the first conductive layer.

[0010] In some embodiments, the first conductive layer and the second conductive layer have different widths.

[0011] In some embodiments, the semiconductor die further includes an insulating layer surrounding the silicon through-hole structure.

[0012] In some embodiments, the first conductive layer, the second conductive layer and the dielectric layer are contact insulating layers.

[0013] In some embodiments, the insulating layer and the dielectric layer are made of the same material.

[0014] In some embodiments, the semiconductor stacked package further includes a package substrate. The semiconductor dies are stacked on the package substrate, and the silicon through-hole structure of the semiconductor dies is electrically connected to the package substrate.

[0015] Another aspect of this disclosure provides a method for manufacturing a semiconductor stacked package, comprising the following steps: forming a through-hole on a substrate; forming a first conductive layer in the through-hole; forming a dielectric layer in the through-hole and on the first conductive layer; forming a second conductive layer in the through-hole and on the dielectric layer; and forming a transistor on the substrate. The first conductive layer, the second conductive layer, and the dielectric layer together form a silicon through-hole structure.

[0016] In some embodiments, forming a dielectric layer involves depositing a dielectric material on the inner surface of the via.

[0017] In some embodiments, forming a dielectric layer involves oxidizing the surface of the first conductive layer exposed in the via.

[0018] In some embodiments, the method of manufacturing a semiconductor stacked package further includes forming an insulating layer on the inner surface of a via before forming a first conductive layer.

[0019] In some embodiments, the method of manufacturing a semiconductor stacked package further includes performing a polishing process on the back side of the substrate until the first conductive layer is exposed.

[0020] In some embodiments, forming the first conductive layer includes: depositing an excess of conductive material in a via; performing a polishing process on the conductive material until the substrate is exposed; and etching back the conductive material to reduce the surface area of ​​the conductive material.

[0021] In some embodiments, the method of manufacturing a semiconductor stacked package further includes forming an interconnect structure electrically connected to the silicon through-hole structure and the transistor.

[0022] In some embodiments, the method of manufacturing a semiconductor stacked package further includes forming a conductive bump on an interconnect structure; and connecting the conductive bump to a package substrate.

[0023] In some embodiments, the method of manufacturing a semiconductor stacked package further includes stacking semiconductor dies on a substrate. The semiconductor dies are electrically connected to a silicon through-hole structure.

[0024] In some embodiments, the method of manufacturing a semiconductor stacked package further includes, after forming a transistor on the substrate, applying a voltage to a first conductive layer or a second conductive layer to destroy the dielectric layer, thereby forming a conductive path between the first conductive layer and the second conductive layer.

[0025] It should be understood that the above general description and the following detailed description are merely examples intended to further explain the content of this disclosure.

Implementation Method

[0027] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0028] The following disclosure provides numerous different embodiments or examples for achieving different functions of the provided subject matter. To simplify this disclosure, specific examples of elements and arrangements are described below. These examples are, of course, merely illustrative and not intended to be limiting. For example, the reference to a first feature formed on or on the surface of a second feature in the following description may include embodiments where the first feature and the second feature are in direct contact, or embodiments where other features are formed between the first feature and the second feature without direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in this disclosure for simplicity and clarity, and are not intended to indicate, in themselves, relationships between the various embodiments and / or configurations discussed.

[0029] Furthermore, for ease of description, this document may use spatially related terms such as "below," "below," "bottom," "above," "top," etc., to describe the relationship of one element or feature relative to another element or feature, as shown in the accompanying drawings. These spatially related terms are intended to cover different orientations of the device in use or operation, and are not limited to the orientation shown in the accompanying drawings. For example, the device may operate in different orientations (such as rotating 90 degrees or other orientations), therefore the spatially related descriptive terms in this document should be interpreted accordingly.

[0030] It should be understood that when referring to a component or layer as "connected to" or "coupled to" another component or layer, it can be a direct connection or coupling, or it can be a case where there are intermediate components or layers.

[0031] Unless the context otherwise requires, terms such as “identical,” “equal,” “plane,” or “coplanar” used in this document, when referring to orientation, layout, location, shape, size, quantity, or other measurements, do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measurements, but are intended to cover orientation, layout, location, shape, size, quantity, or other measurements that are nearly identical within acceptable tolerances, such as variations that may occur due to the manufacturing process. The term “substantially” may be used here to reflect this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially plane” can be exactly the same, equal, or plane, or they can be the same, equal, or plane within acceptable tolerances that may occur during the manufacturing process.

[0032] Please refer to Figure 1, which is a cross-sectional view of a semiconductor stacked package 400 according to some embodiments of the present disclosure. The semiconductor stacked package 400 may include a semiconductor die 500, a semiconductor die 100, and a package substrate 200. The semiconductor die 100 is stacked on the package substrate 200 and electrically connected to the package substrate 200 through corresponding conductive bumps 138. The semiconductor die 500 is stacked on the semiconductor die 100 and electrically connected to the semiconductor die 100 through corresponding conductive bumps 538. In some embodiments, the space between the semiconductor die 100 and the package substrate 200, and the space between the semiconductor die 100 and the semiconductor 500, may be filled with filler materials 141 and 541, respectively. The filler materials 141 and 541 surround the corresponding conductive bumps 138 and 538 and may serve as a protective layer for the conductive bumps 138 and 538.

[0033] Regarding the packaging substrate 200, in some embodiments, the packaging substrate 200 may include, for example, a printed circuit board. For example, the packaging substrate 200 may include a multilayer printed circuit board. The packaging substrate 200 may include a substrate base 201, a lower substrate conductive pad 206 disposed on the lower surface of the substrate base 201, an upper substrate conductive pad 209 disposed on the upper surface of the substrate base 201, and an external connection conductive bump 203 disposed on the lower substrate conductive pad 206.

[0034] In some embodiments, the substrate base 201 may comprise at least one material selected from phenolic resin, epoxy resin, and polyimide. External connection conductive bumps 203 are configured to electrically connect external devices to the semiconductor stack package 400. External connection conductive bumps 203 may comprise, for example, solder balls.

[0035] As shown in Figure 1, two semiconductor dies are stacked vertically on the package substrate 200. However, this disclosure is not limited thereto. For example, three or more semiconductor dies may be stacked vertically on the package substrate 200.

[0036] Please refer to Figure 1 and Figure 2A. Figure 2A is a partially enlarged view of the semiconductor die 100 shown by the dashed line A of the semiconductor stacked package 400 in Figure 1. The semiconductor die 100 may include a substrate 110, a silicon through-hole structure 101, a transistor 122, an interlayer dielectric layer 125, and an intermetallic dielectric layer 128 on the interlayer dielectric layer 125. The silicon through-hole structure 101 may be disposed in the substrate 110 and perpendicular to the substrate 110. The transistor 122 may be disposed on the surface 110a of the substrate 110 and covered by the interlayer dielectric layer 125. The intermetallic dielectric layer 128 may be disposed on the interlayer dielectric layer 125.

[0037] Regarding the silicon through-hole structure 101, each silicon through-hole structure 101 may include a first conductive layer 113, a second conductive layer 119, and a dielectric layer 116 between the first conductive layer 113 and the second conductive layer 119. The dielectric layer 116 may have a rod-shaped cross-sectional profile. The first conductive layer 113 and the second conductive layer 119 have substantially the same width. An insulating layer 105 may surround the respective silicon through-hole structure 101. For example, the insulating layer 105 may extend along the opposite sidewalls of the silicon through-hole structure 101 and separate the silicon through-hole structure 101 from the substrate 110.

[0038] In some embodiments, the first conductive layer 113 and the second conductive layer 119 may comprise a metal, such as copper or other suitable conductive metal. In some embodiments, the insulating layer 105 may comprise a dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the dielectric layer 116 may comprise an oxide. In some embodiments, the dielectric layer 116 may comprise silicon oxide. In some embodiments, the dielectric layer 116 may comprise an oxide of the material of the first conductive layer 113. In some embodiments, the insulating layer 105 and the dielectric layer 116 may have the same material, such as silicon oxide.

[0039] In some embodiments, substrate 110 may comprise a semiconductor substrate. In some embodiments, substrate 110 may comprise, for example, silicon. Alternatively, substrate 110 may comprise a semiconductor element, such as germanium (Ge), or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some embodiments, substrate 110 may comprise a conductive region, such as a doped well or a doped structure. Furthermore, substrate 110 may have various device isolation structures, such as shallow trench isolation (STI) structures.

[0040] In some embodiments, transistor 122 may include, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, transistor 122 may include an n-type metal-oxide-semiconductor (NMOS), a p-type metal-oxide-semiconductor (PMOS), or a similar structure. Other devices, such as system-scale integrated circuits (LSI), image sensors (e.g., complementary metal-oxide-semiconductor (CMOS) image sensors (CIS)), microelectromechanical systems (MEMS), active components, passive components, or similar devices, may also be disposed on substrate 110.

[0041] In some embodiments of Figure 2A, transistor 122 may include a gate structure on substrate 110, and source / drain regions in substrate 110 located on opposite sides of the gate structure. Gate spacers may be disposed on opposite sidewalls of the gate structure.

[0042] In some embodiments, the interlayer dielectric layer 125 may include a dielectric material and a conductive via 1315 (also referred to as a first conductive via). The dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, PSG, BPSG, a low dielectric constant material, and / or other suitable dielectric materials. In some embodiments, the conductive via 1315 may include tungsten (W), copper (Cu), aluminum (Al), or similar materials.

[0043] In some embodiments, the intermetallic dielectric layer 128 may include an interconnect structure 131 therein. For example, the interconnect structure 131 may include conductive lines 1311 and conductive vias 1313 (also referred to as second conductive vias). In some embodiments, the intermetallic dielectric layer 128 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, PSG, BPSG, low dielectric constant materials, and / or other suitable dielectric materials. In some embodiments, the conductive lines 1311 and conductive vias 1313 may include tungsten (W), copper (Cu), aluminum (Al), or similar materials.

[0044] In some embodiments, the semiconductor die 100 may further include a lower conductive pad 134 extending along the surface of the intermetallic dielectric layer 128 and electrically connected to the interconnect structure 131. Connecting conductive bumps 138 may be electrically connected to the lower conductive pad 134. The semiconductor die 100 further includes an upper conductive pad 148 extending along the surface 110b of the substrate 110 and contacting the first conductive layer 113 of the silicon through-hole structure 101. In some embodiments, the lower conductive pad 134 and the upper conductive pad 148 may comprise tungsten (W), copper (Cu), aluminum (Al), or similar materials.

[0045] Regarding semiconductor die 500, its structure is similar to that of semiconductor die 100. For example, semiconductor die 500 may include a substrate 510, a transistor 522 on the substrate 510, an interlayer dielectric layer 525 on the substrate 510 and covering the transistor 522, a conductive via 5315 in the interlayer dielectric layer 525 and electrically connected to the transistor 522, an intermetallic dielectric layer 528 on the interlayer dielectric layer 525, and an interconnect structure 531 in the intermetallic dielectric layer 528 and electrically connected to the intermetallic dielectric layer 528. Semiconductor die 500 further includes a lower conductive pad 534 extending along the surface of the intermetallic dielectric layer 528 and electrically connected to the interconnect structure 531. Connecting conductive bumps 538 contact the lower conductive pad 534.

[0046] Please refer to Figure 2B, which is a partial enlarged view of the semiconductor die 100 in some embodiments according to the present disclosure in other embodiments.

[0047] It should be noted that some components in Figure 2B are similar to those described in Figure 2A and have the same component symbols. For the sake of brevity, relevant details will not be repeated. The difference between Figure 2A and Figure 2B is that the dielectric layer 116 may cover the bottom surface and the opposite sidewall of the second conductive layer 119 in the silicon through-hole structure 101. In other words, the dielectric layer 116 may have a U-shaped cross-sectional profile. In some embodiments, the first conductive layer 113 may be in contact with the insulating layer 105, while the second conductive layer 119 may be spaced apart from the insulating layer 105 through the dielectric layer 116. In some embodiments, the widths of the first conductive layer 113 and the second conductive layer 119 may be different. For example, the width of the first conductive layer 113 may be greater than the width of the second conductive layer 119.

[0048] Referring to Figure 3A, a patterned mask MP may be formed on the surface 110a of the substrate 110. The patterned mask MP may include mask openings MO that expose a portion of the substrate 110. The patterned mask MP may be, for example, a photoresist. The mask openings MO may be formed in the patterned mask MP through a suitable photolithography process.

[0049] Referring to Figure 3B, a photolithography process is performed to remove a portion of the substrate 110 through the mask opening MO of the patterned mask MP, thereby forming a via 102 in the substrate 110. Although the via 102 is described herein as being formed through a photolithography process, this disclosure is not limited thereto. In some embodiments, the via 102 may be formed through a laser drilling process.

[0050] Referring to Figure 3C, after the via 102 is formed, the patterned mask MP is removed. Subsequently, an insulating layer 105 is formed to cover the substrate 110 and the via 102. Specifically, the insulating layer 105 may cover the inner sidewalls and bottom surface of each via 102. In some embodiments, the insulating layer 105 may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or other similar processes.

[0051] Referring to Figure 3D, a conductive material layer 108 is formed on the substrate 110 and the via 102 is filled. The conductive material layer 108 can be formed by a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or similar processes.

[0052] Referring to Figure 3E, a polishing process (e.g., chemical mechanical polishing (CMP)) is performed on the structure of Figure 3D to remove excess material from the conductive material layer 108 and the insulating layer 105 until the substrate 110 is exposed. After the polishing process is completed, the portion of the conductive material layer 108 remaining in the via 102 may be referred to as the first conductive layer 113.

[0053] Referring to Figure 3F, an etch-back process is performed to reduce the top surface of the first conductive layer 113, thereby forming a via 103 within the substrate 110 and above the first conductive layer 113. The etch-back process may include dry etching, wet etching, or a combination of both.

[0054] Referring to Figure 3G, a dielectric layer 116 is formed within the via 103 and over each of the first conductive layers 113. In some embodiments, the dielectric layer 116 can be formed by a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. In some embodiments, the dielectric layer 116 can be formed by oxidizing the exposed surfaces of the first conductive layers 113. In this case, the dielectric layer 116 can be an oxide of the material of the first conductive layers 113. The dielectric layer 116 may have a rod-shaped cross-sectional profile within the via 103.

[0055] Referring to Figure 3H, a second conductive layer 119 is formed within the via 103 and above each dielectric layer 116. The second conductive layer 119 can be formed through a process similar to that used to form the first conductive layer 113, for example, first forming a conductive material layer to fill the via 103, and then removing excess conductive material layer through a polishing process until the substrate 110 is exposed. Subsequently, a silicon through-hole structure 101 is formed in the substrate 110. The silicon through-hole structure 101 may include the first conductive layer 113, the dielectric layer 116, and the second conductive layer 119. The widths of the first conductive layer 113 and the second conductive layer 119 are substantially the same.

[0056] Referring to Figure 3I, a transistor 122 is formed on the substrate 110. The transistor 122 can be formed by appropriate processes known in the art, so relevant details are omitted here for simplicity.

[0057] Referring to Figure 3J, an interlayer dielectric layer 125 is formed on the substrate 110 to cover the transistor 122, and a conductive via 1315 is formed within the interlayer dielectric layer 125. Subsequently, an intermetallic dielectric layer 128 is formed on the interlayer dielectric layer 125, and an interconnect structure 131 is formed within the intermetallic dielectric layer 128. Next, a lower conductive pad 134 is formed on the intermetallic dielectric layer 128 and electrically connected to the interconnect structure 131, while a connecting conductive bump 138 is formed on the lower conductive pad 134.

[0058] Referring to Figure 3K, the substrate 110 is then flipped (e.g., rotated 180 degrees) and attached to the carrier substrate 144 using adhesive tape 142. Specifically, the conductive bumps 138 are attached to the adhesive tape 142. In some embodiments, the adhesive tape 142 may be a UV tape that can be easily separated by ultraviolet (UV) light.

[0059] Referring to Figure 3L, a polishing process is performed to thin the substrate 110 until the silicon through-hole structure 101 is exposed. Specifically, after the polishing process is completed, the surface of the first conductive layer 113 of the silicon through-hole structure 101 can be exposed through the surface 110b of the substrate 110.

[0060] Referring to Figure 3M, an upper conductive pad 148 is formed on the surface 110b of the substrate 110, and a silicon through-hole structure 101 is connected thereto. In some embodiments, the semiconductor die 100 can be formed after the upper conductive pad 148 is formed.

[0061] Referring to Figure 3N, the semiconductor die 100 is separated from the carrier substrate 144. Subsequently, the semiconductor die 100 can be stacked on the package substrate 200. In some embodiments, die stacking is accomplished by attaching the conductive bumps 138 of the semiconductor die 100 to corresponding upper substrate conductive pads 209 on the package substrate 200. Afterward, a filler material 141 fills the gap between the semiconductor die 100 and the package substrate 200.

[0062] Referring to Figure 30, another semiconductor die 500 is stacked on top of semiconductor die 100. In some embodiments, die stacking is accomplished by attaching the conductive bumps 538 of the semiconductor die 500 to the corresponding upper conductive pads 148 on the semiconductor die 100. Subsequently, a filler material 141 fills the gaps between the semiconductor die 500 and the semiconductor die 100.

[0063] Referring to Figure 4A, a dielectric layer 116 is formed within the via 103, on each of the first conductive layers 113, and on the surface 110a of the substrate 110. In some embodiments, the dielectric layer 116 can be formed by a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. The dielectric layer 116 may have a U-shaped cross-sectional profile within the via 103.

[0064] Referring to Figure 4B, a second conductive layer 119 is formed within the via 103 and on the dielectric layer 116. The second conductive layer 119 can be formed by a suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes.

[0065] Referring to Figure 4C, the structure of Figure 4B is subjected to a polishing process, such as chemical mechanical polishing (CMP), to remove excess material from the second conductive layer 119 and dielectric layer 116 until the substrate 110 is exposed. After the polishing process is completed, a silicon through-hole structure 101 is formed in the substrate 110. The silicon through-hole structure 101 may include a first conductive layer 113, a dielectric layer 116, and a second conductive layer 119. In some embodiments, the first conductive layer 113 and the second conductive layer 119 may have different widths.

[0066] Referring to Figure 4D, semiconductor dies 500 are stacked on top of semiconductor dies 100. In some embodiments, die stacking is accomplished by attaching conductive bumps 538 of semiconductor dies 500 to corresponding upper conductive pads 148 on semiconductor dies 100. Subsequently, filler material 141 fills the gaps between semiconductor dies 500 and semiconductor dies 100.

[0067] Figures 5A and 5B illustrate the operation of the silicon through-hole structure 101 of the semiconductor stacked package 400 in Figure 1 under different conditions. In some embodiments, the silicon through-hole structure 101 can be used as a fuse protection structure, and Figures 5A and 5B show different operating procedures for the silicon through-hole structure 101. For simplicity, some components in Figure 1 are omitted here.

[0068] In Figure 5A, under the first condition, voltages V1 and V2 are applied to both ends of the silicon through-hole structure 101. For example, voltage V1 is applied to the first conductive layer 113, and voltage V2 is applied to the second conductive layer 119. In some embodiments, voltage V1 can be applied to the first conductive layer 113 through the semiconductor die 500 in Figure 1, and voltage V2 can be applied to the second conductive layer 119 through the packaging substrate 200 in Figure 1. In some embodiments, voltage V1 can be a high voltage level, while voltage V2 can be a low voltage level (e.g., ground voltage). In some embodiments, voltage V2 can be a high voltage level, while voltage V1 can be a low voltage level (e.g., ground voltage).

[0069] In the embodiment shown in Figure 5A, the voltage difference between voltage V1 and voltage V2 is large enough to damage the dielectric layer 116 (e.g., cause it to break down). When the dielectric layer 116 is damaged, a current path is formed between the first conductive layer 113 and the second conductive layer 119. The circuit thus formed can be considered to have a resistance between the first conductive layer 113 and the second conductive layer 119.

[0070] In Figure 5B, under the second condition, voltages V3 and V4 are applied to both ends of the silicon through-hole structure 101. For example, voltage V3 is applied to the first conductive layer 113, and voltage V4 is applied to the second conductive layer 119. Similarly, voltage V3 can be applied to the first conductive layer 113 through the semiconductor die 500 in Figure 1, and voltage V4 can be applied to the second conductive layer 119 through the packaging substrate 200 in Figure 1. In some embodiments, voltage V3 can be a high voltage level, while voltage V4 can be a low voltage level (e.g., ground voltage).

[0071] Unlike Figure 5A, in the embodiment of Figure 5B, the voltage difference between voltage V3 and voltage V4 may not be sufficient to damage the dielectric layer 116. Therefore, the first conductive layer 113 and the second conductive layer 119 remain electrically isolated from each other through the dielectric layer 116.

[0072] After completing the operation procedure shown in Figure 5A, since the dielectric layer 116 has been damaged, current can flow through the silicon through-hole structure 101, so the data can be determined to be "1". On the other hand, after completing the operation procedure shown in Figure 5B, the dielectric layer 116 remains substantially intact, and current cannot flow through the silicon through-hole structure 101, so the data can be determined to be "0". In other words, if the dielectric layer 116 is broken down, the logic level of the silicon through-hole structure 101 is "1"; if the dielectric layer 116 is not broken down, the logic level of the silicon through-hole structure 101 is "0". Based on the above discussion, it can be seen that the silicon through-hole structure 101 can serve as a fuse protection structure, making it a potential candidate for memory applications in the semiconductor stacked package 400.

[0073] Although this disclosure has been described in detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

[0074] Those skilled in the art will understand that various modifications and changes can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and changes within the scope of the following patent applications. [Simplified Explanation of the Diagram]

[0026] The present disclosure can be more fully understood by referring to the following figures for a detailed description of the embodiments herein: Figure 1 is a cross-sectional view of a semiconductor stacked package according to some embodiments of the present disclosure. Figure 2A is a partially enlarged view of the semiconductor device shown in part A of the semiconductor stacked package in Figure 1. Figure 2B is a partially enlarged view of a semiconductor device according to some embodiments of the present disclosure. Figures 3A to 30 are schematic diagrams of the steps of a method for manufacturing a semiconductor stacked package according to some embodiments of the present disclosure. Figures 4A to 4D are schematic diagrams of the steps of a method for manufacturing a semiconductor stacked package according to some embodiments of the present disclosure. Figures 5A and 5B are schematic diagrams of the silicon through-hole structure of a semiconductor stacked package operating under different conditions according to some embodiments of the present disclosure. [Biomaterial Storage]

[0076] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor stacked package, comprising: A semiconductor die includes: a substrate; A transistor is disposed on the substrate; And a through-silicon-via (TSV) structure perpendicular to the substrate, comprising a first conductive layer, a second conductive layer, and a dielectric layer located between the first conductive layer and the second conductive layer.

2. The semiconductor stacked package as described in claim 1, wherein the dielectric layer has a rectangular cross-sectional profile.

3. The semiconductor stacked package as described in claim 1, wherein the first conductive layer and the second conductive layer have substantially the same width.

4. The semiconductor stacked package as described in claim 1, wherein the dielectric layer comprises an oxide.

5. The semiconductor stacked package as described in claim 1, wherein the dielectric layer is an oxide of one of the materials of the first conductive layer.

6. The semiconductor stacked package as described in claim 1, wherein the first conductive layer and the second conductive layer have different widths.

7. The semiconductor stacked package as claimed in claim 1, wherein the semiconductor die further includes an insulating layer surrounding the silicon through-hole structure.

8. The semiconductor stacked package as described in claim 7, wherein the first conductive layer, the second conductive layer and the dielectric layer are in contact with the insulating layer.

9. The semiconductor stacked package as described in claim 8, wherein the insulating layer and the dielectric layer are made of the same material.

10. The semiconductor stacked package as claimed in claim 1, further comprising: a package substrate, wherein the semiconductor die is stacked on the package substrate, and the silicon through-hole structure of the semiconductor die is electrically connected to the package substrate.

11. A method for manufacturing a semiconductor stacked package, comprising: A through-hole is formed on a substrate; A first conductive layer is formed in the via; a dielectric layer is formed in the via and on the first conductive layer; a second conductive layer is formed in the via and on the dielectric layer, wherein the first conductive layer, the dielectric layer and the second conductive layer together form a silicon through-hole structure; a transistor is formed on the substrate.

12. The method of manufacturing a semiconductor stacked package as described in claim 11, wherein forming the dielectric layer comprises depositing a dielectric material on the inner surface of one of the vias.

13. The method of manufacturing a semiconductor stacked package as described in claim 11, wherein forming the dielectric layer includes oxidizing a surface of the first conductive layer exposed in the via.

14. The method of manufacturing a semiconductor stacked package as described in claim 11, wherein an insulating layer is formed on the inner surface of one of the vias prior to forming the first conductive layer.

15. The method of manufacturing a semiconductor stacked package as described in claim 11, further comprising performing a polishing process on a back side of the substrate until the first conductive layer is exposed.

16. The method of manufacturing a semiconductor stacked package as claimed in claim 11, wherein forming the first conductive layer comprises: depositing an excess of a conductive material in the via; performing a polishing process on the conductive material until the substrate is exposed; and etching back the conductive material to reduce one surface area of ​​the conductive material.

17. The method of manufacturing a semiconductor stacked package as described in claim 11, further comprising forming an interconnect structure electrically connected to one of the silicon through-hole structures and the transistor.

18. The method of manufacturing a semiconductor stacked package as described in claim 17, further comprising: forming a conductive bump on the interconnect structure; and connecting the conductive bump to a package substrate.

19. The method of manufacturing a semiconductor stacked package as described in claim 11, further comprising stacking a semiconductor die on the substrate such that the semiconductor die is electrically connected to the silicon through-hole structure.

20. The method of manufacturing a semiconductor stacked package as described in claim 11, further comprising, after forming the transistor on the substrate, applying a voltage to the first conductive layer or the second conductive layer to destroy the dielectric layer, thereby forming a conductive path between the first conductive layer and the second conductive layer.

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