Semiconductor device and methods of formation

Abstract

The fin-based transistor includes a gate structure arranged perpendicularly to the source / drain regions of the fin-based transistor. The gate structure may cover the top and sides of the fin-based transistor's fin structure, with the source / drain regions of the fin-based transistor located at the bottom of the fin structure. The source / drain contacts of the fin-based transistor are located on the source / drain regions above the bottom of the fin structure. This allows the gate structure and the source / drain contacts to be located on opposite vertical sides of the fin structure, thus eliminating the need for a gate spacer in the fin-based transistor.

Description

Technical Field

[0001] Patent application related documents

[0002] This patent application claims priority to Greek Patent Application No. 20240100924, filed on December 27, 2024, entitled "Semiconductor Device and Method of Forming Thereof". The disclosures of the prior application are considered part of this patent application and are incorporated herein by reference. Prior Technology

[0003] Fin transistors, such as fin field-effect transistors (finFETs) and nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, and nanoribbon transistors), are three-dimensional structures comprising channel regions within a fin (or a portion thereof), the channel regions extending as a three-dimensional structure above a semiconductor substrate. A gate structure is configured to control the flow of charge carriers within the channel regions, and it surrounds the fins of the semiconductor material. For example, in a fin field-effect transistor, the gate structure surrounds three sides of the fin (and therefore the channel regions), thus increasing control over the channel regions (and thus switching the fin field-effect transistor). As another example, in a nanostructure transistor, the gate structure surrounds multiple channel regions within the fin structure, thus the gate structure surrounds each of the multiple channel regions. The source / drain regions (e.g., epitaxial regions) are located on opposite sides of the gate structure. Simple Explanation of the Diagram

[0004] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various feature components are not drawn to scale. In fact, for clarity, the dimensions of the various feature components may be arbitrarily increased or decreased. Figures 1, 2A, 2B, 3, 4A, 4B, 5, 6A to 6C and 7A to 7I illustrate example embodiments of the finned transistor structure described herein. Figures 8A to 8E are illustrations of example embodiments of the source / drain region arrangement of the semiconductor device described herein. Figures 9A to 9E are illustrations of example embodiments of forming a semiconductor device as described herein. Figures 10A to 10E are illustrations of example embodiments of forming a semiconductor device as described herein. Figures 11A to 11D are illustrations of example embodiments of forming a semiconductor device as described herein. Figures 12A to 12C are illustrations of example embodiments of forming a semiconductor device as described herein. Figure 13 is a flowchart of an example process related to the formation of a semiconductor device as described herein. Figure 14 is a flowchart of an example process related to the formation of a semiconductor device as described herein. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify the content of this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "below," "below," "lower," "above," and "upper" may be used herein to facilitate the description of the relationship between one element or feature shown in the figures and another (other) element or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0007] In some cases, finned transistors may include a gate spacer between the gate structure and the source / drain contacts. The gate spacer is included to provide electrical isolation and / or facilitate the patterning of various layers and / or structures of the finned transistor. However, the gate spacer can become a source of parasitic capacitance between the gate structure and the source / drain contacts, leading to a decrease in the switching speed of the finned transistor (e.g., due to an increase in the resistance-capacitance (RC) time constant). Furthermore, the gate spacer can account for approximately 25% or more of the overall size of the finned transistor. Therefore, with advancements in semiconductor process nodes, the gate spacer presents a challenge in reducing the overall side dimension of the finned transistor.

[0008] In some embodiments described herein, the fin transistor includes a gate structure perpendicularly aligned to the source / drain regions of the fin transistor. The gate structure may cover the top and sides of the fin structure of the fin transistor, and the source / drain regions of the fin transistor may be located at the bottom of the fin structure. Source / drain contacts of the fin transistor are located on the source / drain regions above the bottom of the fin structure. This allows the gate structure and source / drain contacts to be located on perpendicularly opposite sides of the fin structure, thereby allowing the gate spacer to be omitted from the fin transistor. Thus, parasitic capacitance in the fin transistor is reduced, and further size reduction of the fin transistor is possible. Furthermore and / or alternatively, the vertical stacking of the gate structure and source / drain regions of the fin transistor allows for front and back connections to be formed for the fin transistor. This enables multilayer fin transistors to be vertically stacked and interconnected to realize complementary metal-oxide-semiconductor (CMOS) logic circuits and / or to achieve higher fin transistor density in semiconductor devices.

[0009] Figures 1, 2A, 2B, 3, 4A, 4B, 5, 6A to 6C, and 7A to 7I illustrate exemplary embodiments of the formation of the finned transistor structure described herein. Figures 1, 2A, and 2B are alternative embodiments of forming a semiconductor layer of a semiconductor device, wherein a finned transistor will be formed. The alternative embodiments are illustrated from a top view in the xy plane and a cross-sectional view along line segment AA in the y-direction of Figures 1, 2A, and 2B.

[0010] As shown in Example Embodiment 100 of FIG1, the semiconductor layer forming the semiconductor device 102 may include providing a semiconductor substrate 104, forming an etch stop layer (e.g., a semiconductor etch stop layer) 106 above and / or on the semiconductor substrate 104, and forming a semiconductor layer 108 above and / or on the etch stop layer 106.

[0011] The semiconductor substrate 104 may be provided in the form of a semiconductor die, a semiconductor wafer, and / or other types of semiconductor workpieces. The semiconductor substrate 104, etch stop layer 106, and semiconductor layer 108 may each comprise a semiconductor material, such as silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), and / or other types of semiconductor materials. In some embodiments, the semiconductor substrate 104 and semiconductor layer 108 comprise a first semiconductor material, such as silicon, while the etch stop layer 106 comprises a second semiconductor material, such as silicon-germanium. This allows the etch stop layer 106 to function as an etch stop layer during the etching of the semiconductor layer 108 or the removal of the semiconductor substrate 104.

[0012] The etch stop layer 106 and / or semiconductor layer 108 can be deposited using epitaxial methods with deposition tools. The etch stop layer 106 and / or semiconductor layer 108 can be deposited using deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and / or atomic layer deposition (ALD).

[0013] In some embodiments, the epitaxial operation may be performed at low temperatures, such as below about 350 degrees Celsius, to minimize and / or avoid mixing between germanium in the etch stop layer 106 and silicon in the semiconductor substrate 104 and semiconductor layer 108. Silicon precursors such as disilane (Si2H6), trisilane (Si3H8), and / or tetrasilane (Si4H10) may be used to deposit the etch stop layer 106 and / or semiconductor layer 108. A germanium precursor such as digermanane (Ge2H6) may be used to deposit the etch stop layer 106.

[0014] In some embodiments, the thickness of the etch stop layer is in the range of about 20 nanometers to about 200 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the germanium concentration contained in the etch stop layer 106 during formation is in the range of about 10% to about 40% by atomic volume percentage. However, other values ​​and ranges are also within the scope of this disclosure.

[0015] In some embodiments, the thickness of the semiconductor layer 108 is in the range of about 30 nanometers to about 60 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, ions are implanted into the semiconductor layer 108 using an ion implantation tool to dope the semiconductor layer 108 with one or more types of dopants such as p-type dopants (e.g., boron (B)) and / or n-type dopants (e.g., phosphorus (P) and / or arsenic (As)). In some embodiments, the dopant concentration of the semiconductor layer 108 may be in the range of about 1 × 10¹⁵ atoms / cm³ to about 1 × 10¹⁹ atoms / cm³. However, other values ​​and ranges are also within the scope of this disclosure.

[0016] Alternatively, as shown in Example Embodiment 200 of FIG2A, the etch stop layer 106 may be formed as a composite etch stop layer, which includes a first type semiconductor etch stop layer 202 and a second type semiconductor etch stop layer 204. The first type semiconductor layer 206 may be formed on the etch stop layer 106. The first type semiconductor layer 206 may be a semiconductor material of the same type as the first type semiconductor etch stop layer 202.

[0017] As shown in Figure 2B, a shallow trench isolation (STI) region 208 may be formed above the first type etch stop layer 202, such that the STI region 208 defines a first type transistor region 210 and a second type transistor region 212. The first type transistor region 210 may be the region in the semiconductor device 102 where an n-type transistor is to be formed, while the second type transistor region 212 may be the region in the semiconductor device 102 where a p-type transistor is to be formed. In the first type transistor region 210, the second type etch stop layer 204 and the first type semiconductor layer 206 may be removed (e.g., by etching using an etching tool and / or by another type of material removal process) and replaced by a semiconductor layer 108 (e.g., a second type semiconductor layer containing the same semiconductor material as the second type etch stop layer 204). The semiconductor layer 108 may be epitaxially grown on the first type etch stop layer 202.

[0018] The first type etch stop layer 202 may have a different germanium concentration than the first type semiconductor layer 206 to allow selective etching of the first type semiconductor layer 206 while minimizing etching of the first type etch stop layer 202. In some embodiments, the thickness of the second type etch stop layer 204 is in the range of about 2 nanometers to about 8 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0019] Figure 3 illustrates an example embodiment 300 of the fin structure formation process described herein, including a perspective view, a top view in the xy plane, and a cross-sectional view along line segment AA in the y direction. As shown in Figure 3, one or more fin structures 302 may be formed from semiconductor layer 108. Additionally and / or alternatively, one or more fin structures 302 may be formed from a first-type semiconductor layer 206.

[0020] Fin structure 302 is a semiconductor protrusion extending beyond semiconductor substrate 104 in the z-direction and may extend (and be extended in the x-direction) within semiconductor device 102. If multiple fin structures 302 are formed, the fin structures 302 may be arranged in the y-direction. Alternatively, semiconductor device 102 may include other types of semiconductor protrusion structures, such as stacks of protrusion layers of nanostructured semiconductor layers (e.g., silicon and silicon-germanium layers). These stacks may be processed to form nanostructured transistors, such as all-ring gate (GAA) transistors, sheet transistors, wire transistors, and / or other types of nanostructured transistors.

[0021] In some embodiments, a pattern in the photoresist layer is used to etch the semiconductor layer 108 to form the fin structure 302. In these embodiments, the photoresist layer can be formed on the semiconductor layer 108 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The semiconductor layer 108 can be etched based on the pattern using an etching tool to form the fin structure 302. In some embodiments, the remaining portions of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0022] In some embodiments, the etching operation includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or other types of etching. The etching operation may be stopped at the etching stop layer 106. Alternatively, a portion of the etching stop layer 106 may be removed during the etching operation.

[0023] In some embodiments, a rigid mask layer is used as an alternative to pattern-etched semiconductor layer 108. In some embodiments, patterning techniques such as double patterning, triple patterning, quadruple patterning, self-aligned double patterning, and / or self-aligned quadruple patterning may be used to form the fin structure 302.

[0024] In some embodiments, the width of the fin structure 302 (denoted as dimension D1 in FIG. 3) ranges from approximately 4 nanometers to approximately 10 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the spacing of the fin structure 302 (denoted as dimension D2 in FIG. 3) ranges from approximately 20 nanometers to approximately 50 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0025] Figures 4A and 4B illustrate an example embodiment 400 of the dummy gate formation process described herein, including perspective views, a top view in the xy plane, and a cross-sectional view along line segment AA in the y-direction. As shown in Figure 4A, a dummy gate stack 402 is formed above the fin structure 302. The dummy gate stack 402 may include a dummy dielectric layer 404 formed above and / or on the front side of the semiconductor device 102, such that the dummy dielectric layer 404 is formed on the sidewalls and top surface of the fin structure 302. The front side of the semiconductor device 102 is one side of the semiconductor substrate 104 on which the fin structure 302 is formed. The top of the fin structure 302 is the portion of the fin structure 302 away from the semiconductor substrate 104 in the z-direction. The bottom of the fin structure 302 is the portion of the fin structure 302 close to the semiconductor substrate 104 in the z-direction.

[0026] The dummy dielectric layer 404 may include one or more dielectric materials, such as silicon oxide (SiOx, e.g., SiO2) and / or silicon nitride (SixNy, e.g., Si3N4). The dummy dielectric layer 404 can be deposited using deposition tools via PVD, ALD, CVD, epitaxial growth, oxidation, and / or other suitable deposition techniques. In some embodiments, the thickness of the dummy dielectric layer 404 is in the range of approximately 1 nanometer to approximately 4 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0027] As further shown in FIG4A, the dummy gate stack 402 may include a dummy electrode layer 406 formed on the front side of the semiconductor device 102, such that the dummy electrode layer 406 is formed above and / or on the dummy dielectric layer 404. The dummy electrode layer 406 may include polysilicon and / or other suitable materials.

[0028] A dummy electrode layer 406 may be deposited as a blanket, thereby covering the fin structure 302. The dummy electrode layer 406 may be deposited using deposition tools via PVD, ALD, CVD, epitaxial growth, oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization operation (e.g., chemical mechanical planarization (CMP)) may be performed using planarization tools to planarize the dummy electrode layer 406. In some embodiments, the thickness of the formed dummy electrode layer 406 includes a range of approximately 40 nm to approximately 200 nm. However, other values ​​and ranges are also within the scope of this disclosure.

[0029] As shown in Figure 4B, the dummy dielectric layer 404 and dummy electrode layer 406 can be etched to define one or more dummy gate structures 408 of the semiconductor device 102. The dummy gate structure 408 is a temporary gate structure formed as a temporary occupant structure for the transistor gate structure (e.g., a metal gate structure) of the semiconductor device 102. The dummy gate structure 408 temporarily occupies the space of the gate structure and acts as a sacrificial structure during the formation of other layers and / or structures of the semiconductor device 102. Thus, the final damage caused by these processes is absorbed by the dummy gate structure 408, rather than the transistor gate structure, thereby minimizing damage to the gate structure.

[0030] A dummy gate structure 408 extends along the y-direction in the semiconductor device and covers the top and sides of the fin structure 302. In some embodiments, the dummy gate structure 408 completely covers all four sides of the fin structure 302. In embodiments in which multiple dummy gate structures 408 are formed, the dummy gate structures 408 may be arranged along the x-direction. Thus, the dummy gate structures 408 extend to the fin structure 302 in an approximately orthogonal direction, such that the dummy gate structures 408 span one or more fin structures 302.

[0031] In some embodiments, a pattern in the photoresist layer is used to etch the dummy dielectric layer 404 and the dummy electrode layer 406 to form a dummy gate structure 408. In these embodiments, a photoresist layer can be formed on the dummy electrode layer 406 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dummy dielectric layer 404 and the dummy electrode layer 406 based on the pattern to form the dummy gate structure 408. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for forming the dummy gate structure 408 based on the pattern.

[0032] As shown in Figure 4B, the dummy gate structure 408 may have a gate length (denoted as dimension D3 in Figure 4B) ranging from about 10 nanometers to about 40 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. The spacing between adjacent dummy gate structures 408 (denoted as dimension D4 in Figure 4B) may range from about 28 nanometers to about 56 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. In some embodiments, the opposite ends of the dummy gate structure 408 may extend outward from the fin structure 302 by approximately the same distance. In some embodiments, the opposite ends of the dummy gate structure 408 may extend outward from the fin structure 302 asymmetrically, such that a first distance at the first end (denoted as dimension D5 in Figure 4B) and a second distance at the second end (denoted as dimension D6 in Figure 4B) are different distances.

[0033] Figure 5 illustrates an example embodiment 500 of the fin doping process described herein, and includes a top view in the xy plane and a cross-sectional view along the y direction of line segment AA. As shown in Figure 5, an ion implantation operation can be performed to dope one or more fin structures 302 with one or more types of dopants. In some embodiments, the fin structure 302 for an n-type transistor can be doped with an n-type dopant, such as arsenic (As) and / or phosphorus (P). In some embodiments, the fin structure 302 for a p-type transistor can be doped with a p-type dopant, such as boron (B), indium (In), and / or gallium (Ga). In some embodiments, the fin structure 302 can be doped to have a dopant concentration ranging from about 1 × 10¹⁹ atoms / cm³ to about 1 × 10²¹ atoms / cm³. However, other values ​​and ranges are also within the scope of this disclosure.

[0034] Figures 6A to 6C illustrate an example embodiment 600 of the replacement gate process described herein, and include perspective views, a top view in the xy plane, and a cross-sectional view along the y-direction of line segment BB. Line segment BB passes through dummy gate structure 408 along the y-direction. As shown in Figures 6A to 6C, the replacement gate process includes replacing dummy gate structure 408 with the gate structure (e.g., a metal gate structure) of the transistor of semiconductor device 102.

[0035] As shown in Figure 6A, an interlayer dielectric (ILD) layer 602 may be deposited around the dummy gate structure 408. In some embodiments, the deposition of the ILD layer 602 covers the dummy gate structure 408, and a planarization operation (e.g., CMP operation) is performed using a planarization tool to expose the top of the dummy gate structure 408, with the top of the ILD layer 602 being substantially coplanar with the top of the dummy gate structure 408.

[0036] The ILD layer 602 may include one or more dielectric materials, such as silicon oxide (SiOx, such as SiO2) and / or silicon nitride (SixNy, such as Si3N4). The ILD layer 602 may be deposited using deposition tools via PVD, ALD, CVD, epitaxial growth, oxidation, and / or other suitable deposition techniques.

[0037] As shown in Figure 6B, one or more etching operations can be performed to remove the dummy gate structure 408. This leaves an opening 604 in which a portion of the fin structure 302 is exposed.

[0038] As shown in Figure 6C, a gate structure 606 is formed in the opening 604 left after the dummy gate structure 408 is removed. Therefore, the gate structure 606 is formed on the front side of the semiconductor device 102, such that the gate structure 606 covers the top and sidewalls of the fin structure 302. The gate structure 606 may extend in the y-direction and be arranged in the x-direction. In some embodiments, the gate structure 606 may extend across multiple fin structures 302.

[0039] The gate structure 606 may include a conformal stack 608 that conforms to the profile of the fin structure 302. The conformal stack 608 may include an interface layer 610, a gate dielectric layer 612, and / or a work function metal layer 614, etc. The gate structure may also include a gate electrode layer 616 that fills the remaining area of ​​the opening 604.

[0040] Interface layer 610 may include an oxide layer formed by a chemical reaction with the surface of fin structure 302. For example, a chemical oxidation process using ozone (O3) combined with hydrofluoric acid (HF) and / or hydrochloric acid (HCl) may be used to oxidize the exposed portion of fin structure 302 in opening 604 to form interface layer 610.

[0041] Additionally and / or alternatively, the interface layer 610 may be formed via a thermal oxidation process, such as rapid thermal annealing (RTA). The semiconductor device 102 may be placed in a processing chamber, and oxygen-containing gas may be supplied to the processing chamber for the RTA process. In some embodiments, the thermal oxidation process is performed using in-situ steam generation (ISSG) technology.

[0042] In some embodiments, the interface layer 610 is formed by deposition, which can be performed using deposition tools via ALD, CVD, and / or other suitable deposition techniques.

[0043] In some embodiments, the thickness of the interface layer 610 is in the range of about 0.2 nanometers to about 2 nanometers. However, other values ​​and ranges are also within the scope of this disclosure. After the interface layer 610 is formed, it may be annealed in a hydrogen-containing environment and / or using a hydrogen-based plasma to passivate the dangling bonds at the interface between the interface layer 610 and the fin structure 302.

[0044] The gate dielectric layer 612 may include a high-k dielectric material having a dielectric constant greater than about 3.9. These high-k dielectric materials may include hafnium oxide (HfOx, e.g., HfO2), aluminum oxide (AlxOy, e.g., Al2O3), zirconium oxide (ZrOx, e.g., ZrO2), hafnium zirconium oxide (HfZrOx), hafnium silicon oxide (HfSiOx), lanthanum oxide (LaxOy, e.g., La2O3), and / or titanium oxide (TiOx, e.g., TiO2), etc. Furthermore and / or alternatively, the gate dielectric layer 612 may include one or more low-k dielectric materials, such as silicon oxide (SiOx, e.g., SiO2).

[0045] In some embodiments, the gate dielectric layer 612 is formed by deposition, which can be performed using deposition tools via ALD, CVD, and / or other suitable deposition techniques. In some embodiments, the thickness of the gate dielectric layer 612 formed ranges from about 1 nanometer to about 4 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0046] After the gate dielectric layer 612 is deposited, it can be annealed to repair bulk defects in the gate dielectric layer 612. Annealing can be carried out in an environment containing hydrogen, oxygen and / or nitrogen.

[0047] The work function metal layer 614 may include one or more metals and / or one or more metal alloys for adjusting the work function of the gate structure 606. In some embodiments, the work function metal layer 614 of the n-type transistor may include an n-type metal that adjusts the work function of the gate structure 606 of the n-type transistor to be close to the conduction band of the fin structure 302 material. Examples of such n-type metals include titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), and / or other aluminum-containing metals. In some embodiments, the work function metal layer 614 of the p-type transistor may include one or more p-type metals, such as titanium nitride (TiN), tungsten nitride (WN), and / or other metals having a work function greater than about 4.7 eV. The p-type metal can be used to adjust the work function of the p-type transistor to be close to the valence band of the fin structure 302 material.

[0048] In some embodiments, the work function metal layer 614 is formed by deposition, which can be performed using deposition tools via ALD, CVD, and / or other suitable deposition techniques. In some embodiments, the thickness of the work function metal layer 614 is in the range of about 2 nanometers to about 8 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0049] The gate electrode layer 616 may include one or more metals, such as tungsten (W), titanium (Ti), and / or copper (Cu). In some embodiments, the gate electrode layer 616 is formed by deposition, which can be performed using deposition tools via ALD, CVD, and / or other suitable deposition techniques. In some embodiments, after the gate electrode layer 616 is deposited, the gate structure 606 is planarized using a planarization tool.

[0050] Figures 7A to 7I illustrate an example embodiment 700 of the back-side process of the semiconductor device 102 described herein. Figures 1, 2A, 2B, 3, 4A, 4B, 5, and 6A to 6C illustrate the front-side process operation of the semiconductor device 102, wherein the fin structure 302 and the gate structure 606 are formed on the front side of the semiconductor device 102. Figures 7A to 7I illustrate the back-side process operation of the semiconductor device 102, wherein the source / drain regions and source / drain contacts of the transistors of the semiconductor device 102 are formed on the back side of the semiconductor device 102. Thus, the source / drain contacts and the gate structure 606 are located on opposite sides of the fin structure 302 (e.g., the gate structure 606 is located on the front or top of the fin structure 302, while the source / drain contacts are located on the back or bottom of the fin structure 302), thus the gate spacer can be omitted.

[0051] Figures 7A to 7E include perspective views, top views in the xy plane, and cross-sectional views along line BB in the y-direction. Line BB represents the gate structure 606 along the y-direction. Figures 7F to 7H include perspective views, top views in the xy plane, and cross-sectional views along line segment CC in the y-direction. Line segment CC runs along a fin structure 302 and spans multiple gate structures in the x-direction. Figure 7I is a composite view of superimposed cross-sections in the y-direction, including cross-sections spanning multiple source / drain regions and cross-sections spanning multiple gate structures 606.

[0052] As shown in Figures 7A and 7B, a bonding layer 702 can be formed on the front side of the semiconductor device 102 so that the front side of the semiconductor device 102 can be bonded to the carrier substrate 704 using the bonding layer 702. In order to bond the semiconductor device 102 to the carrier substrate 704, a bonding operation can be performed using a bonding tool to bond the bonding layer 702 on the front side of the semiconductor device 102 to the bonding layer 706 on the carrier substrate 704.

[0053] Figure 7B depicts the semiconductor device 102 after the bonding operation, flipped over with the semiconductor substrate now facing upwards. As shown in Figure 7B, bonding layers 702 and 706 can be merged to form bonding layer 708. In some embodiments, a bonding interface 710 between bonding layers 702 and 706 is visible in the semiconductor device 102. In some embodiments, there is no visible bonding interface, and bonding layers 702 and 706 are merged into a single layer.

[0054] Bonding layers 702 and 706 may each comprise one or more dielectric materials, such as silicon oxide (SiOx, e.g., SiO2), silicon nitride (SixNy, e.g., Si3N4), and / or silicon carbonitride (SiCN). Bonding layers 702 and 706 can be deposited using deposition tools via ALD, CVD, and / or other suitable deposition techniques. In some embodiments, bonding layers 702 and / or 706 are planarized using a planarization tool after deposition. In some embodiments, the thickness of bonding layer 702 and / or bonding layer 706 may range from about 10 nanometers to about 100 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0055] As further shown in FIG7B, the semiconductor device 102 is bonded to the carrier substrate 704 such that the front side of the semiconductor device 102 faces the carrier substrate 704 and the back side of the semiconductor device 102 faces away from the carrier substrate 704. This allows back-side processing to be performed on the semiconductor device 102.

[0056] As shown in FIG7C, the back-side fabrication of semiconductor device 102 may include removing semiconductor substrate 104 and etch stop layer 106 from the back side of semiconductor device 102. In some embodiments, an etching operation is performed using an etching tool to etch semiconductor substrate 104 and / or etch stop layer 106 to remove semiconductor substrate 104 and / or etch stop layer 106. In some embodiments, a planarization operation is performed using a planarization tool (e.g., a CMP tool) to remove semiconductor substrate 104 and / or etch stop layer 106. In some embodiments, a polishing operation is performed using a planarization tool (e.g., a wafer polishing tool) to remove semiconductor substrate 104 and / or etch stop layer 106. In some embodiments, the etching operation, planarization operation, and / or polishing operation are stopped once the bottom of fin structure 302 is exposed on the back side of semiconductor device 102.

[0057] Figure 7D illustrates an alternative to Figure 7C, wherein an STI region 712 is included around the fin structure 302. The STI region 712 may correspond to the STI region 208 in Figure 2B, and / or may correspond to a different STI region. The STI region 712 may be formed after the fin structure 302 is formed and before the dummy gate structure 408 is formed. In these embodiments, once the STI region 712 is reached, the etching, planarization, and / or polishing operations are stopped to prevent material removal from the gate structure 606.

[0058] As shown in FIG7E, an ILD layer 714 may be formed above and / or on the back side of the semiconductor device 102. The ILD layer 714 may contain one or more dielectric materials, such as silicon oxide (SiOx, e.g., SiO2) and / or silicon nitride (SixNy, e.g., Si3N4). In some embodiments, ILD layer 602 and ILD layer 714 contain the same dielectric material. In some embodiments, ILD layer 602 and ILD layer 714 contain different dielectric materials.

[0059] The ILD layer 714 can be deposited using deposition tools employing PVD, ALD, CVD, epitaxial, oxidation, and / or other suitable deposition techniques. A planarization operation (e.g., CMP) is performed using a planarization tool to planarize the ILD layer 714. In some embodiments, the thickness of the ILD layer 714 formed ranges from about 40 nanometers to about 200 nanometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0060] In some embodiments, the ILD layer 714 is formed as a multilayer stack. For example, a first dielectric layer of the multilayer stack may be formed on the back side of the semiconductor device 102, and a second dielectric layer of the multilayer stack may be formed on the first dielectric layer. The first dielectric layer may include a thin film (e.g., with a thickness ranging from about 2 nanometers to about 8 nanometers) containing a high-k dielectric material, and the second dielectric layer may include a thick film containing a low-k dielectric material.

[0061] As shown in Figure 7F, the ILD layer 714 can be patterned and etched to expose portions of the fin structure 302 not located below the gate structure 606. For example, the ILD layer 714 can be patterned and etched to expose portions of the fin structure 302 located adjacent to the gate structure 606. Another example is that the ILD layer 714 can be patterned and etched to expose portions of the fin structure 302 located between adjacent gate structures 606.

[0062] In some embodiments, the pattern in the photoresist layer is used to etch the ILD layer 714 to expose portions of the fin structure 302. In these embodiments, the photoresist layer can be formed on the ILD layer 714 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the ILD layer 714 based on the pattern to expose portions of the fin structure 302. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the ILD layer 714.

[0063] As described above, the ILD layer 714 may comprise a multi-layer stack. This multi-layer stack allows for highly controlled etching of the ILD layer 714, which helps minimize etching of the underlying fin structure 302. A first etch operation can be performed to etch a second dielectric layer through the multi-layer stack, and a second etch operation can be performed to etch a first dielectric layer through the multi-layer stack.

[0064] As shown in Figure 7G, source / drain regions 716 of one or more transistors are formed on the back side of the semiconductor device 102. In particular, the source / drain regions 716 are formed on the exposed portion of the fin structure 302. Therefore, the source / drain regions 716 are formed at the bottom of the fin structure 302. "Source / drain region" may refer to the source or drain, individually or collectively, depending on the context.

[0065] Forming the source / drain region 716 may include epitaxially growing a semiconductor material on the exposed portion of the fin structure 302. In some embodiments, the source / drain region 716 may be doped with one or more types of dopants. For example, the source / drain region 716 for an n-type transistor may be silicon, doped with n-type dopants such as arsenic (As) and / or phosphorus (P). Another example is that the source / drain region 716 for a p-type transistor may be silicon or silicon-germanium, doped with p-type dopants such as boron (B), indium (In), and / or gallium (Ga).

[0066] As shown in Figure 7H, source / drain contacts 718 may be formed on and / or around source / drain regions 716. Source / drain contacts 718 may include vias, plugs, and / or other types of conductive structures. Source / drain contacts 718 may include conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), aluminum (Al), and / or gold (Au). Source / drain contacts 718 may be deposited using deposition tools via PVD, ALD, CVD, and / or other suitable deposition techniques. Source / drain contacts 718 may be deposited in one or more deposition operations. Source / drain contacts 718 may be deposited on the top and / or sides around source / drain regions 716.

[0067] In some embodiments, one or more pads may be formed on the sidewalls of the ILD layer 714, and source / drain contacts 718 may be formed on the sidewalls. The pads may include barrier pads, adhesive pads, and / or other types of pads, and may include materials such as tantalum, tantalum nitride (TaN), titanium nitride (TiN), and / or ruthenium oxide (RuOx).

[0068] In some embodiments, a metal silicate layer is formed at the interface between the source / drain region 716 and the source / drain contact 718, and the source / drain contact 718 is formed on the metal silicate layer. The metal silicate layer can be formed by depositing a metal layer, such as a layer of titanium and / or a layer of ruthenium, at the bottom of the fin structure 302, and then performing an annealing operation to diffuse the metal layer to the surface of the bottom of the fin structure 302.

[0069] As further shown in Figure 7H, source / drain interconnects 720 may be formed on source / drain contacts 718. Source / drain interconnects 720 may include vias, conductive pillars, conductive columns, and / or other types of conductive structures. Source / drain interconnects may include conductive materials such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au). Source / drain interconnects 720 may be deposited using deposition tools via PVD, ALD, CVD, and / or other suitable deposition techniques.

[0070] As further shown in Figure 7H, gate interconnect 722 may be formed on and / or around gate structure 606. Gate interconnect 722 may include vias, conductive pillars, conductive columns, and / or other types of conductive structures. Gate interconnect may include conductive materials such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au). Gate interconnect 722 may be deposited using deposition tools via PVD, ALD, CVD, and / or other suitable deposition techniques.

[0071] As shown in FIG7I, in Example Embodiment 700, source / drain contacts 718, source / drain interconnects 720, and gate interconnects 722 are formed on the back side of semiconductor device 102. The source / drain interconnects 720 and gate interconnects 722 can be part of an interconnect layer 724 formed on the back side of semiconductor device 102. Therefore, the interconnect layer 724 can be referred to as the back-side interconnect layer 724 (or the back-side back-end (BEOL) region).

[0072] The source / drain interconnect 720 may be formed in the ILD layer 726 of the interconnect layer 724. The gate interconnect 722 may be formed in the ILD layer 726 of the interconnect layer 724 and may extend through the ILD layer 714 to the lower gate structure 606 on the front side of the semiconductor device 102. Therefore, the gate interconnect 722 may extend between the front and back sides of the semiconductor device.

[0073] Source / drain interconnects 720 and gate interconnects 722 are electrically connected to conductive structures 728 in interconnect layer 724. Conductive structures 728 provide electrical wiring, enabling signal and / or power distribution throughout the semiconductor device 102. Conductive structures 728 may include trenches, metallization layers, conductive traces, vias, interconnects, and / or combinations of other types of conductive structures. Each conductive structure 728 may comprise one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof.

[0074] Thus, the semiconductor device 102 may include a fin structure 302, a gate structure 606 located on a first side of the fin structure 302, a source / drain region 716 located on a second side of the fin structure 302 perpendicular to the first side, a source / drain contact 718 located on the source / drain region 716 above the second side of the fin structure 302, a source / drain interconnect 720 located on the source / drain contact 718 above the second side of the fin structure 302, and a gate interconnect 722 extending from the second side of the fin structure 302 to the gate structure 606. The ILD layer 602 may be laterally adjacent to and in contact with the gate structure 606, while the ILD layer 714 laterally adjacent to the source / drain region 716 may be in contact with the source / drain region 716.

[0075] As described above, Figures 1, 2A, 2B, 3, 4A, 4B, 5, 6A to 6C, and 7A to 7I are provided as examples. Other examples may differ from those described in Figures 1, 2A, 2B, 3, 4A, 4B, 5, 6A to 6C, and / or 7A to 7I.

[0076] Figures 8A to 8E are example embodiments of the source / drain region arrangement of the semiconductor device 102 described herein.

[0077] As shown in Example Embodiment 800 in Figure 8A, non-merged source / drain regions 716 can be formed on adjacent fin structures 302, such that the non-merged source / drain regions 716 are spaced apart from each other and do not physically contact each other.

[0078] As shown in Example Embodiment 802 of Figure 8B, the merged source / drain region 716 can be formed on multiple fin structures 302, such that the merged source / drain region 716 spans multiple fin structures 302. The merged source / drain region 716 can be formed by epitaxially growing the source / drain region 716 on multiple fin structures 302 until the source / drain regions 716 merge to form the merged source / drain region 716.

[0079] As shown in Example Embodiment 804 of FIG8C, by etching the ILD layer 602 from the back side of the semiconductor device 102 (e.g., during the operation described in relation to FIG7F), the bottom of the ILD layer 602 around one or more fin structures 302 can be recessed. This allows the source / drain region 716 to cover a portion of the sidewall of the fin structure 302 in the y-direction. Furthermore, the source / drain contact 718 formed on the source / drain region 716 can extend below the bottom of the ILD layer 714.

[0080] As shown in Example Embodiment 806 of FIG8D, the bottom of one or more fin structures 302 can be recessed by etching the bottom of one or more fin structures 302 from the back side of the semiconductor device 102 (e.g., during operation described in relation to FIG7F). This allows the source / drain region 716 to be recessed into the bottom of the fin structure 302. The source / drain region 716 may extend along a portion laterally adjacent to the gate structure 606.

[0081] As shown in Example Embodiment 808 of Figure 8E, one or more fin structures 302 can be completely etched through along the side of one or more gate structures 606. This allows the source / drain region 716 to be recessed into the ILD layer 602 and extend fully along the height of the fin structure 302. The source / drain region 716 may extend along a portion laterally adjacent to the gate structure 606.

[0082] The fin structure 302 can be completely etched through along the sidewall of one or more gate structures 606 by forming a sidewall spacer 810 on the sidewall of the ILD layer 714 and etching through the fin structure 302 while protecting the ILD layer 714 from etching with the sidewall spacer 810. The source / drain region 716 can be formed in the groove formed by completely etching through the fin structure 302, and a portion of the source / drain region 716 laterally adjacent to the ILD layer 714 can contact the sidewall spacer 810.

[0083] As described above, Figures 8A to 8E are provided as examples. Other examples may differ from those described with respect to Figures 8A to 8E.

[0084] Figures 9A to 9E are diagrams illustrating an exemplary embodiment 900 of the semiconductor device 102 described herein. The exemplary embodiment 900 may include similar processes described in relation to Figures 1, 2A, 2B, 3, 4A, 4B, 5, 6A to 6C, and / or 7A to 7I. However, in the exemplary embodiment 900, interconnect layers (e.g., BEOL regions) are formed on both the front and back sides of the semiconductor device 102. These interconnect layers on the front and back sides of the semiconductor device 102 allow signals and / or power to be distributed across both sides of the semiconductor device 102, thereby providing increased interconnect layout flexibility.

[0085] As shown in Figure 9A, the fin structure 302, the gate structure 606, and the ILD layer 602 can be formed on the front side of the semiconductor device 102.

[0086] As shown in FIG9B, an interconnect layer 724a (e.g., a front-side interconnect layer) may be formed on the front side of the semiconductor device 102, such that the interconnect layer 724a is located on top of the fin structure 302 and above the gate structure 606. The interconnect layer 724a may be formed in a manner similar to that described in FIG7I, and may include an ILD layer 726a and a conductive structure 728a. Furthermore, a gate interconnect 722 may be formed in the interconnect layer 724a, such that the gate interconnect 722 electrically connects one or more gate structures 606 to the conductive structure 728a of the interconnect layer 724a.

[0087] As shown in Figure 9C, the semiconductor device 102 is flipped and bonded to the carrier substrate 704 using the bonding layer 708.

[0088] As shown in FIG9D, after the interconnect layer 724a is formed on the front side of the semiconductor device 102, a back side process is performed on the semiconductor device 102. The back side process includes forming an ILD layer 714, forming a source / drain region 716, and forming a source / drain contact 718 on the back side of the semiconductor device 102.

[0089] As shown in FIG9E, the back-side process may include forming an interconnect layer 724b (e.g., a back-side interconnect layer) on the back side of the semiconductor device 102, such that the interconnect layer 724b is located above the source / drain regions 716 and the source / drain contacts 718. The interconnect layer 724b may be formed in a manner similar to that described in FIG7I, and may include an ILD layer 726b and a conductive structure 728b. Furthermore, source / drain interconnects 720 may be formed in the interconnect layer 724b, such that the source / drain interconnects 720 electrically connect one or more source / drain contacts 718 to the conductive structure 728b of the interconnect layer 724b.

[0090] As further shown in FIG9E, the through-insulator internal interconnect structure 902 may be formed from the back side of the semiconductor device 102, such that the through-insulator internal interconnect structure 902 extends through the ILD layer 714, through the ILD layer 602, and into the conductive structure 728a in the ILD layer 726a to the inner interconnect layer 724a. The conductive structure 728b of the inner interconnect layer 724b may be formed on the through-insulator internal interconnect structure 902, such that the through-insulator internal interconnect structure 902 electrically connects the inner interconnect layers 724a and 724b. In some embodiments, the through-insulator internal interconnect structure 902 may extend in the z-direction next to the source / drain region 716 in the semiconductor device. In some embodiments, the through-insulator internal interconnect structure 902 may extend in the z-direction next to the fin structure 302 in the semiconductor device. In some embodiments, the through-insulator internal interconnect structure 902 may extend in the z-direction next to the gate structure 606 in the semiconductor device.

[0091] Thus, the semiconductor device 102 may include a fin structure 302, a gate structure 606 located on a first side of the fin structure 302, a source / drain region 716 located on a second side of the fin structure 302 perpendicular to the first side, a source / drain contact 718 located on the second side of the fin structure 302 above the source / drain region 716, a source / drain interconnect 720 located on the second side of the fin structure 302 above the source / drain contact 718, and a gate interconnect 722 located above the gate structure 606. An interconnect layer 724a is located above the first side of the fin structure 302, and a conductive structure 728a in the interconnect layer 724a is electrically connected to the gate interconnect 722. The interconnect layer 724b is located above the second side of the fin structure 302. The conductive structure 728b in the interconnect layer 724b is electrically connected to the source / drain contact 718 through the source / drain interconnect 720 in the interconnect layer 724b. The through-insulator interconnect structure 902 extends vertically between the interconnect layers 724a and 724b.

[0092] As indicated above, Figures 9A to 9E are provided as examples. Other examples may differ from those described with respect to Figures 9A to 9E.

[0093] Figures 10A to 10E are diagrams of an exemplary embodiment 1000 of forming the semiconductor device 102 described herein. The exemplary embodiment 1000 may include similar processes described in relation to Figures 1, 2A, 2B, 3, 4A, 4B, 5, 6A to 6C, and / or 7A to 7I. However, in the exemplary embodiment 1000, interconnect layers (e.g., BEOL regions) are formed on both the front and back sides of the semiconductor device 102. These interconnect layers on the front and back sides of the semiconductor device 102 allow signals and / or power to be distributed across both sides of the semiconductor device 102, thereby providing increased interconnect layout flexibility.

[0094] As shown in Figure 10A, the fin structure 302, the gate structure 606, and the ILD layer 602 can be formed on the front side of the semiconductor device 102. The semiconductor device 102 is flipped and bonded to the carrier substrate 704 using a bonding layer 708.

[0095] After forming the fin structure 302 and the gate structure 606 on the front side of the semiconductor device 102, the back side process is performed on the semiconductor device 102.

[0096] The back-side process includes forming an ILD layer 714, a source / drain region 716, and source / drain contacts 718 on the back side of the semiconductor device 102. Furthermore, the back-side process may include forming an interconnect layer 724b (e.g., a back-side interconnect layer) on the back side of the semiconductor device 102. Therefore, in example embodiment 1000, the interconnect layer 724b (e.g., a back-side interconnect layer) is formed prior to the formation of the interconnect layer 724a (e.g., a front-side interconnect layer). Source / drain interconnects 720 may be formed in the interconnect layer 724b, electrically connecting one or more source / drain contacts 718 to one or more conductive structures 728b in the interconnect layer 724b.

[0097] As shown in FIG10B, the bonding layer 1002 may be formed on the interconnect layer 724b on the back side of the semiconductor device 102.

[0098] As shown in FIG10C, bonding layer 1002 is used to bond the back side of semiconductor device 102 to carrier substrate 1004. Bonding layer 1002 may be bonded to bonding layer 1008 on carrier substrate 1004 to form bonding layer 1006. Bonding layer 1006 may be a merged layer including bonding layers 1002 and 1008, or a visible interface 1010 between bonding layers 1002 and 1008.

[0099] As shown in Figure 10D, an additional front-side process can be performed after the back-side process. The additional front-side process may include removing the carrier substrate 704 and the bonding layer 708 (e.g., in a manner similar to that described in Figure 7C).

[0100] As shown in FIG10E, the additional front-side process includes forming an interconnect layer 724a on the front side of the semiconductor device 102. A gate interconnect 722 may be formed from the front side of the semiconductor device 102, such that the gate interconnect 722 electrically connects one or more gate structures 606 to one or more conductive structures 728a in the interconnect layer 724a.

[0101] As further shown in FIG10E, the through-insulator internal interconnect structure 1012 may be formed from the front side of the semiconductor device 102, such that the through-insulator internal interconnect structure 1012 extends through the ILD layer 602, through the ILD layer 714, and into the conductive structure 728b in the ILD layer 726b to the inner interconnect layer 724b. The conductive structure 728a of the inner interconnect layer 724a may be formed on the through-insulator internal interconnect structure 1012, such that the through-insulator internal interconnect structure 1012 electrically connects the inner interconnect layers 724a and 724b. In some embodiments, the through-insulator internal interconnect structure 1012 may extend in the z-direction beside the source / drain region 716 in the semiconductor device. In some embodiments, the through-insulator internal interconnect structure 1012 may extend in the z-direction beside the fin structure 302 in the semiconductor device. In some embodiments, the through-insulator internal interconnect structure 1012 may extend in the z-direction beside the gate structure 606 in the semiconductor device.

[0102] In this manner, the semiconductor device 102 may include a fin structure 302, a gate structure 606 on a first side of the fin structure 302, a source / drain region 716 on a second side of the fin structure 302 perpendicular to the first side, a source / drain contact 718 on the source / drain region 716 above the second side of the fin structure 302, a source / drain interconnect 720 on the source / drain contact 718 above the second side of the fin structure 302, and a gate interconnect 722 above the gate structure 606. An interconnect layer 724a is included above the first side of the fin structure 302, and a conductive structure 728a in the interconnect layer 724a is electrically connected to the gate interconnect 722. The interconnect layer 724b is included above the second side of the fin structure 302, and the conductive structure 728b in the interconnect layer 724b is electrically connected to the source / drain contact 718 through the source / drain interconnect 720 in the interconnect layer 724b. The through-insulator interconnect structure 1012 extends vertically between the interconnect layers 724a and 724b.

[0103] As shown above, Figures 10A to 10E are provided as examples. Other examples may differ from those illustrated with respect to Figures 10A to 10E.

[0104] Figures 11A to 11D are illustrations of an exemplary embodiment 1100 forming the semiconductor device 102 described herein. The exemplary embodiment 1100 may include similar processes associated with Figures 1, 2A, 2B, 3, 4A, 4B, 5, 6A to 6C, and / or 7A to 7I. However, in the exemplary embodiment 1100, the semiconductor device 102 includes a plurality of vertically arranged (or stacked) transistor layers that are electrically interconnected. Arranging the transistor layers along the z-direction in the semiconductor device 102 allows for an increase in the number of transistors in the semiconductor device 102, while the lateral footprint of the semiconductor device 102 is hardly increased or not increased at all.

[0105] As shown in Figure 11A, the fin structure 302, the gate structure 606, and the ILD layer 602 can be formed on the front side of the semiconductor device 102. The bonding layer 1102 can be formed on the ILD layer 602 above the front side of the semiconductor device 102.

[0106] As shown in Figure 11B, semiconductor device 102 is flipped and bonded to another semiconductor device 1104 using bonding layer 1102. Bonding layer 1102 may be bonded to bonding layer 1106 on semiconductor device 1104 to form bonding layer 1108. Bonding layer 1108 may be a combined layer including bonding layers 1102 and 1106, or an interface 1110 may be visible between bonding layers 1102 and 1106.

[0107] As shown in Figure 11B, the semiconductor device 1104 includes a semiconductor substrate 1112, a transistor layer 1114 above the semiconductor substrate 1112, and an interconnect layer 724a (e.g., a front interconnect layer) above the transistor layer 1114. The transistors in the transistor layer 1114 may include fin structures 302, gate structures 606, source / drain regions 716 (not shown), and / or source / drain contacts 718 (not shown), as well as other examples.

[0108] As shown in Figure 11C, a back-side process can be performed on the back side of the semiconductor device 102 to form an ILD layer 714, a source / drain region 716, and a source / drain contact 718. The semiconductor device 102 includes another transistor layer 1116 above the transistor layer 1114. The transistors in the transistor layer 1116 may include fin structures 302, gate structures 606, source / drain regions 716, and / or source / drain contacts 718, among other examples. The transistor layers 1114 and 1116 in the semiconductor device 102 are stacked and vertically aligned along the z-direction in the semiconductor device 102.

[0109] As shown in FIG11D, an interconnect layer 724b (e.g., a back-side interconnect layer) may be formed above the back side of the semiconductor device 102, such that the interconnect layer 724b is located above the source / drain regions 716 and source / drain contacts 718 of the transistor layer 1116. Furthermore, source / drain interconnects 720 may be formed in the interconnect layer 724b, such that the source / drain interconnects 720 electrically connect one or more source / drain contacts 718 to the conductive structure 728b of the interconnect layer 724b.

[0110] As further shown in Figure 11D, the through-insulator internal interconnect structure 1118 can be formed from the back side of the semiconductor device 102, such that the through-insulator internal interconnect structure 1118 extends through the transistor layer 1116, through the bonding layer 1108, and enters the ILD layer 726a to reach the conductive structure 728a in the inner interconnect layer 724a. The conductive structure 728b of the inner interconnect layer 724b can be formed on the through-insulator internal interconnect structure 1118, such that the through-insulator internal interconnect structure 1118 electrically connects the inner interconnect layers 724a and 724b. Thus, the through-insulator internal interconnect structure 1118 can electrically connect the transistor layer 1114 and the transistor layer 1116.

[0111] As described above, Figures 11A to 11D are provided as examples. Other examples may differ from those described with respect to Figures 11A to 11D.

[0112] Figures 12A to 12C are illustrations of an exemplary embodiment 1200 forming the semiconductor device 102 described herein. Exemplary embodiment 1200 may include similar processes described in relation to Figures 11A to 11D. However, in exemplary embodiment 1200, a bonding structure 1202 is formed and included in a bonding layer 1102, while a bonding structure 1204 is formed and included in a bonding layer 1106. Bonding structures 1204 and 1205 may include bonding vias, bonding pads, and / or other types of bonding structures. Bonding structures 1202 and 1204 comprise a metal, such as Cu.

[0113] As shown in Figure 12B, bonding structures 1204 and 1204 can be bonded together at interface 1110 between bonding layers 1102 and 1106. This forms a "hybrid bonding," which includes a dielectric bond between bonding layers 1102 and 1106 and a metallic bond between bonding structures 1202 and 1204. A gate interconnect 722 in the semiconductor device 102 can electrically connect the gate structure 606 to the bonding structure 1202. Additionally and / or alternatively, a source / drain interconnect 720 in the semiconductor device 102 can electrically connect the source / drain contact 718 to the bonding structure 1202. As further shown in Figure 12B, a conductive structure 728a in the interconnect layer 724a can be electrically connected to the bonding pad 1204 via the bonding interconnect 1206 (e.g., a bonding via).

[0114] As shown in Figure 12C, an interconnect layer 724b (e.g., a back-side interconnect layer) may be formed above the back side of the semiconductor device 102, such that the interconnect layer 724b is located above the source / drain region 716 and the source / drain contact 718 of the transistor layer 1116. Furthermore, source / drain interconnects 720 may be formed in the interconnect layer 724b, such that the source / drain interconnects 720 electrically connect one or more source / drain contacts 718 to the conductive structure 728b of the interconnect layer 724b.

[0115] As further shown in Figure 12C, a through-insulator interconnect structure 1118 can be formed from the back side of the semiconductor device 102, such that the through-insulator interconnect structure 1118 extends through the transistor layer 1116, through the bonding layer 1108, and into the conductive structure 728a in the ILD layer 726a to the inner interconnect layer 724a. The conductive structure 728b of the inner interconnect layer 724b can be formed on the through-insulator interconnect structure 1118, such that the through-insulator interconnect structure 1118 electrically connects the inner interconnect layers 724a and 724b. Thus, the transistor layers 1114 and 1116 can be electrically interconnected through the connection between one or more through-insulator interconnect structures 1118 and the bonding structures 1202 and 1204.

[0116] As described above, Figures 12A to 12C are provided as examples. Other examples may differ from those illustrated with respect to Figures 12A to 12C.

[0117] Figure 13 is a flowchart of an example process 1300 associated with forming the semiconductor device described herein. In some embodiments, one or more process blocks of Figure 13 are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor processing tools.

[0118] As shown in Figure 13, process 1300 may include forming a semiconductor fin structure (block 1310) on a first side of the semiconductor device. For example, one or more semiconductor processing tools may be used to form a semiconductor fin structure (e.g., fin structure 302) on a first side of the semiconductor device (e.g., semiconductor device 102), as described herein.

[0119] As further shown in Figure 13, process 1300 may include forming a gate structure on a first side of the semiconductor device such that the gate structure is located on top of the semiconductor fin structure (block 1320). For example, one or more semiconductor processing tools may be used to form a gate structure (e.g., gate structure 606) on the first side of the semiconductor device such that the gate structure is located on top of the semiconductor fin structure, as described herein.

[0120] As further shown in Figure 13, process 1300 may include forming a source / drain region on a second side of the semiconductor device perpendicular to the first side, such that the source / drain region is located at the bottom of the semiconductor fin structure (block 1330). For example, one or more semiconductor processing tools may be used to form the source / drain region (e.g., source / drain region 716) on the second side of the semiconductor device perpendicular to the first side, such that the source / drain region is located at the bottom of the semiconductor fin structure, as described herein.

[0121] Process 1300 may include additional implementations, such as any single implementation or any combination of implementations set forth below and / or in conjunction with one or more other processes set forth elsewhere herein.

[0122] In a first embodiment, process 1300 includes forming an adhesive layer (e.g., adhesive layer 702) on top of a semiconductor device and using the adhesive layer to bond the semiconductor device to a carrier substrate (e.g., carrier substrate 704), wherein the tops of the gate structure and the semiconductor fin structure face the carrier substrate.

[0123] In the second embodiment, forming a source / drain region on the second side of the semiconductor device, alone or in combination with the first embodiment, includes forming a source / drain region at the bottom of the semiconductor fin structure after bonding the semiconductor device to the carrier substrate.

[0124] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 1300 includes forming an interconnect layer (e.g., interconnect layer 724) on a second side of the semiconductor device, such that the interconnect layer is located above the source / drain region.

[0125] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 1300 includes forming source / drain contacts (e.g., source / drain contacts 718) on the source / drain regions, wherein forming an interconnect layer includes forming an interconnect layer such that the interconnect layer is located above the source / drain contacts.

[0126] In the fifth embodiment, forming an interconnect layer, alone or in combination with one or more of the first to fourth embodiments, includes forming a source / drain interconnect (e.g., source / drain interconnect 720) on the source / drain contact and forming a conductive structure (e.g., conductive structure 728) on the source / drain interconnect.

[0127] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 1300 includes forming a gate interconnect (e.g., gate interconnect 722) from a second side of the semiconductor device to the gate structure, wherein the gate interconnect extends along the source / drain region.

[0128] In the seventh embodiment, forming the source / drain region, alone or in combination with one or more of the first to sixth embodiments, includes forming the source / drain region such that the source / drain region covers the side portion of the semiconductor fin structure below the gate structure.

[0129] In the eighth embodiment, forming the source / drain region, alone or in combination with one or more of the first to seventh embodiments, includes forming a dielectric layer on a second side of the semiconductor device, forming sidewall spacers on the dielectric layer, etching a portion of the semiconductor fin structure through one side of the gate structure to form a groove on the side of the gate structure, and forming the source / drain region in the groove.

[0130] Although Figure 13 shows an example of the steps of process 1300, some embodiments of process 1300 may include additional steps, fewer steps, different steps, and steps in a different order than those shown in Figure 13. Multiple steps of process 1300 may be performed simultaneously, either additionally or alternatively.

[0131] Figure 14 is a flowchart of an example process 1400 associated with forming the semiconductor device described herein. In some embodiments, one or more process blocks of Figure 14 are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor processing tools.

[0132] As shown in Figure 14, process 1400 may include forming a semiconductor fin structure (block 1410) on a first side of the semiconductor device. For example, one or more semiconductor processing tools may be used to form a semiconductor fin structure (e.g., fin structure 302) on a first side of the semiconductor device (e.g., semiconductor device 102), as described herein.

[0133] As further shown in Figure 14, process 1400 may include forming a gate structure on a first side of the semiconductor device, such that the gate structure is located on top of the semiconductor fin structure (block 1420). For example, one or more semiconductor processing tools may be used to form a gate structure (e.g., gate structure 606) on the first side of the semiconductor device, such that the gate structure is located on top of the semiconductor fin structure, as described herein.

[0134] As further shown in Figure 14, process 1400 may include forming a source / drain region on a second side of the semiconductor device, the second side being perpendicular to the first side, such that the source / drain region is located at the bottom of the semiconductor fin structure (block 1430). For example, one or more semiconductor processing tools may be used to form the source / drain region (e.g., source / drain region 716) on a second side of the semiconductor device, the second side being perpendicular to the first side, such that the source / drain region is located at the bottom of the semiconductor fin structure, as described herein.

[0135] As further shown in Figure 14, process 1400 may include forming an interconnect layer on a second side of the semiconductor device, such that the interconnect layer is located above the source / drain regions (block 1440). For example, one or more semiconductor processing tools may be used to form an interconnect layer (e.g., interconnect layer 724, interconnect layer 724b) on the second side of the semiconductor device, such that the interconnect layer is located above the source / drain regions, as described herein.

[0136] Process 1400 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere in this document.

[0137] In the first embodiment, process 1400 includes forming another interconnect layer (e.g., interconnect layer 724a) on a first side of the semiconductor device, such that the other interconnect layer is located above the gate structure and the semiconductor fin structure.

[0138] In the second embodiment, forming an interconnect layer, alone or in combination with the first embodiment, includes forming the interconnect layer prior to forming the other interconnect layer.

[0139] In the third embodiment, forming the other interconnect layer, either alone or in combination with one or more of the first and second embodiments, includes bonding the interconnect layer to a carrier substrate (e.g., carrier substrate 704) and forming the other interconnect layer on a second side of the semiconductor device after bonding the interconnect layer to the carrier substrate.

[0140] In the fourth embodiment, forming an interconnect layer, either alone or in combination with one or more of the first to third embodiments, includes forming the interconnect layer after forming the other interconnect layer.

[0141] In the fifth embodiment, forming an interconnect layer, either alone or in combination with one or more of the first to fourth embodiments, includes bonding the other interconnect layer to a carrier substrate (e.g., carrier substrate 704) and forming an interconnect layer on a first side of the semiconductor device after bonding the other interconnect layer to the carrier substrate.

[0142] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 1400 includes bonding a semiconductor device to another semiconductor device (e.g., semiconductor device 1104), the other semiconductor device including a first transistor structure (e.g., transistor layer 1114) with a gate structure and a semiconductor fin structure facing the first transistor structure, wherein the gate structure, semiconductor fin structure and source / drain regions are contained in a second transistor structure (e.g., transistor layer 1116) arranged perpendicularly to the first transistor structure.

[0143] Although Figure 14 shows an example block of process 1400, in some embodiments, process 1400 may include additional blocks, fewer blocks, different blocks, or blocks with different configurations compared to those described in Figure 14. Additionally or alternatively, two or more blocks of process 1400 may be executed in parallel.

[0144] Thus, the fin transistor includes a gate structure arranged perpendicularly to the source / drain regions of the fin transistor. The gate structure may cover the top and sides of the fin structure, with the source / drain regions of the fin transistor located at the bottom of the fin structure. The source / drain contacts of the fin transistor are located on the source / drain regions above the bottom of the fin structure. This allows the gate structure and source / drain contacts to be located on opposite vertical sides of the fin structure, thereby eliminating the need for gate spacers. This reduces parasitic capacitance in the fin transistor and allows for further size reduction. Additionally and / or alternatively, the vertical stacking of the gate structure and source / drain regions of the fin transistor enables the fin transistor to form front and back connections. This allows multilayer fin transistors to be vertically stacked and interconnected to implement CMOS logic circuits and / or achieve higher fin transistor density in semiconductor devices.

[0145] As detailed above, some embodiments described herein provide a method. The method includes forming a semiconductor fin structure on a first side of a semiconductor device. The method includes forming a gate structure on the first side of the semiconductor device, such that the gate structure is located on top of the semiconductor fin structure. The method includes forming a source / drain region on a second side of the semiconductor device, the second side being perpendicular to the first side, such that the source / drain region is located at the bottom of the semiconductor fin structure.

[0146] As detailed above, some embodiments described herein provide a method. The method includes forming a semiconductor fin structure on a first side of a semiconductor device. The method includes forming a gate structure on the first side of the semiconductor device, such that the gate structure is located on top of the semiconductor fin structure. The method includes forming a source / drain region on a second side of the semiconductor device, the second side being perpendicular to the first side, such that the source / drain region is located at the bottom of the semiconductor fin structure. The method includes forming an interconnect layer on the second side of the semiconductor device, such that the interconnect layer is located above the source / drain region.

[0147] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor protrusion structure. The semiconductor device includes a gate structure located on a first side of the semiconductor protrusion structure. The semiconductor device includes a source / drain region located on a second side of the semiconductor protrusion structure, the second side being perpendicular to the first side. The semiconductor device includes a first dielectric layer adjacent to the gate structure, wherein the first dielectric layer is in contact with the gate structure. The semiconductor device includes a second dielectric layer adjacent to the source / drain region, wherein the second dielectric layer is in contact with the source / drain region.

[0148] As detailed above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a semiconductor protrusion structure located above a first side of the semiconductor device. The semiconductor device includes a gate structure located above the first side of the semiconductor device. The gate structure is located above the top of the semiconductor protrusion structure. The semiconductor device includes a source / drain region located on a second side of the semiconductor device, the second side being perpendicular to the first side. The source / drain region is located above the bottom of the semiconductor protrusion structure.

[0149] The terms "approximately" and "substantially" can indicate that the value of a given quantity varies within a range of 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and not limiting. The terms "approximately" and "substantially" can also refer to a percentage of the given quantity as interpreted by someone skilled in the art to which this disclosure pertains.

[0150] The features of the above embodiments are beneficial for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and changes, substitutions, or modifications can be made without departing from the spirit and scope of the present invention.

[0151] 100, 1000, 1100, 1200, 200, 300, 400, 500, 600, 700, 800, 802, 804, 806, 808, 900: Example Implementations 102, 1104: Semiconductor devices 104, 1112: Semiconductor substrate 106: Etching Stop Layer 108: Semiconductor layer 202: Type I Semiconductor Etching Stop Layer 204: Type II Semiconductor Etching Stop Layer 206: Type I semiconductor layer 208, 712: STI area 210: Type I transistor region 212: Type II transistor region 302: Fin Structure 402: Dummy gate stack 404: Dummy Dielectric Layer 406: Dummy Electrode Layer 408: Dummy gate structure 602, 714, 726, 726a, 726b: ILD layers 604: Opening 606: Gate structure 608: Conformal Stacking 610: Interface Layer 612: Gate dielectric layer 614: Work function metal layer 616: Gate electrode layer 704, 1004: Carrier substrate 710: Interface 716: Source / Drain Region 718: Source / Drain Contact 720: Source / Drain Interconnect 722: Gate Interconnection 724, 724a, 724b: Interconnection layer 728, 728a, 728b: Conductive structure 810: Sidewall spacer 1002, 1006, 1008, 1102, 1106, 1108, 702, 706, 708: Bonding layer 1010, 1110: Interface 1012, 1118, 902: Through-insulator interconnect structure 1114, 1116: Transistor layers 1202, 1204: Joint structure 1206: Interconnection 1300, 1400: Process 1310, 1320, 1330, 1410, 1420, 1430, 1440: Square AA, BB, CC: line segments D1, D2, D3, D4, D5, D6: Dimensions

Claims

1. A semiconductor device, comprising: A semiconductor protrusion structure is located above the first side of the semiconductor device; A gate structure is located above the first side of the semiconductor device, wherein the gate structure is located above the top of the semiconductor protrusion; and a source / drain region on a second side of the semiconductor device perpendicular to the first side, wherein the source / drain region is located above the bottom of the semiconductor protrusion, and wherein the source / drain region covers the side portion of the semiconductor protrusion below the gate structure.

2. The semiconductor device as claimed in claim 1, further comprising: An interconnect layer is located on the second side of the semiconductor device, wherein the interconnect layer is situated above the source / drain region.

3. The semiconductor device as claimed in claim 2, further comprising: Source / drain contacts are located on the source / drain regions.

4. The semiconductor device as claimed in claim 1, further comprising: The gate interconnect extends from the second side of the semiconductor device to the gate structure.

5. The semiconductor device as claimed in claim 3, wherein the interconnect layer is located above the source / drain contacts.

6. A method of forming a semiconductor device, comprising: A semiconductor fin structure is formed on the first side of the semiconductor device; A gate structure is formed on the first side of the semiconductor device, such that the gate structure is located on top of the semiconductor fin structure; a source / drain region is formed on the second side of the semiconductor device perpendicular to the first side, such that the source / drain region is located at the bottom of the semiconductor fin structure; and an interconnect layer is formed on the second side of the semiconductor device, such that the interconnect layer is located above the source / drain region, wherein the source / drain region covers the side portion of the semiconductor fin structure below the gate structure.

7. The method as described in claim 6, wherein forming the source / drain region comprises: A dielectric layer is formed on the second side of the semiconductor device; Sidewall spacers are formed on the dielectric layer; Etching through a portion of the semiconductor fin structure on one side of the gate structure to form a groove on the side of the gate structure; and forming the source / drain region in the groove.

8. The method as described in claim 7, further comprising: Another interconnect layer is formed on the first side of the semiconductor device, such that the other interconnect layer is located above the gate structure and the semiconductor fin structure.

9. A semiconductor device, comprising: Semiconductor prominent structure; A gate structure is located on the first side of the semiconductor protrusion structure; A source / drain region is located on a second side of the semiconductor protrusion perpendicular to the first side; a first dielectric layer is located adjacent to the gate structure, wherein the first dielectric layer is in contact with the gate structure; and a second dielectric layer adjacent to the source / drain region, wherein the second dielectric layer contacts the source / drain region, wherein the source / drain region covers the side portion of the semiconductor protrusion structure below the gate structure.

10. The semiconductor device as claimed in claim 9, further comprising: Another semiconductor protrusion structure; And another source / drain region, laterally adjacent to the source / drain region, wherein the other source / drain region is located on the other semiconductor protrusion structure.

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