Semiconductor device and methods of forming the same

Abstract

A channel isolation structure and a method of forming the same are provided. An element comprises a multilayer stack, including a first complex nanostructure; a second complex nanostructure located above the first complex nanostructure; and a first channel isolation structure. The element further includes a first source / drain region located at opposite endpoints of the first complex nanostructure; a second source / drain region located above the first source / drain region and at opposite endpoints of the second complex nanostructure; a first gate structure surrounding the first complex nanostructure; and a second gate structure surrounding the second complex nanostructure. The first gate structure contacts a first lateral surface of the first channel isolation structure.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. As the semiconductor industry further moves towards increasing component density, improving performance, and reducing costs, challenges from manufacturing and design have led to the emergence of stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). However, with the reduction of the minimum feature size, additional features are introduced. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] When read with reference to the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 shows a perspective view of an exemplary stacked transistor according to some embodiments. Figures 2-8 are views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Figures 9-15 are views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Figures 16-18 are views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Figures 19-21 are views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Figures 22-24 are views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Figures 25, 26, 27A, 27B, 27C, 28, 29A, 29B, and 29C are views of intermediate stages in the fabrication of stacked transistors according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0008] A stacked transistor structure comprising a vertically stacked upper transistor and a lower transistor, and a method thereof, are provided. A channel isolation structure is formed between and isolates the upper channel region of the upper transistor and the lower channel region of the lower transistor. The channel isolation structure can be formed separately from other isolation structures in the device, such as internal spacers separating the upper and lower gate stacks from the upper and lower source / drain regions that directly contact the upper and lower source / drain regions. The exemplary channel isolation structure provides improved electrical performance (e.g., improved alternating current (AC) current), improved leakage current, etc., resulting from a simplified process that is easy to implement.

[0009] Figure 1 illustrates an example of a stacked transistor 10 (including FETs 10U and FETs 10L) according to some embodiments. Figure 1 is a three-dimensional view, and some features of the stacked transistors are omitted for clarity.

[0010] Stacked transistors include multiple vertically stacked FETs. For example, a stacked transistor may include a lower nanostructure-FET 10L of a first element type (e.g., n-type / p-type) and an upper nanostructure-FET 10U of a second element type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second element type of the upper nanostructure-FET 10U is the opposite of the first element type of the lower nanostructure-FET 10L. Both nanostructure-FET 10U and nanostructure-FET 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as the channel region of the nanostructure-FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure-FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure-FET 10U. In other embodiments, the stacked transistor may also be applied to other types of transistors (e.g., finFETs, etc.).

[0011] A gate dielectric 78 surrounds a corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and on the corresponding gate electrodes 80. Each source / drain region 62 may individually or collectively refer to a source or drain depending on the context. Isolation features (not shown) may be formed to separate desired regions in the source / drain regions 62 and / or desired regions in the gate electrodes 80.

[0012] Figure 1 further illustrates the reference cross-section used in subsequent figures. Cross-section A-A' is a vertical cross-section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistors and in the direction of current flow, for example, between the source / drain regions 62 of the stacked transistors. Subsequent figures show details along cross-section A-A'.

[0013] Figures 2-8 illustrate perspective and cross-sectional views of intermediate stages in the formation of stacked transistors (schematically shown in Figure 1) according to some embodiments. In Figure 2, a wafer including substrate 20 is provided. Substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., p-type or n-type doped) or undoped. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or similar materials, or combinations thereof.

[0014] Semiconductor bundles 28 extend upward from semiconductor substrate 20 to form a semiconductor bundle 28. Each semiconductor bundle 28 includes a semiconductor bundle 20 (a patterned portion of semiconductor substrate 20, also referred to as semiconductor fin 20') and a multilayer stack 22. The stacking composition of the multilayer stack 22 is referred to hereinafter as a nanostructure. Specifically, the multilayer stack 22 includes a dummy nanostructure 24A, a dummy nanostructure 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Dummy nanostructures 24A and dummy nanostructures 24B can also be collectively referred to as dummy nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0015] The dummy nanostructure 24A is formed of a first semiconductor material, and the dummy nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the dummy nanostructure 24B can be removed at a faster rate than the dummy nanostructure 24A.

[0016] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor materials can be selected from candidate semiconductor materials of substrate 20. Lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of dummy nanostructure 24 have high etch selectivity relative to the third semiconductor material of semiconductor nanostructure 26. Therefore, dummy nanostructure 24 can be selectively removed in subsequent process steps without significantly removing semiconductor nanostructure 26. In some embodiments, dummy nanostructure 24A is formed of or includes silicon germanium, semiconductor nanostructure 26 is formed of silicon, and dummy nanostructure 24B can be formed of germanium or silicon germanium having a higher percentage of germanium atoms than dummy nanostructure 24A. For example, dummy nanostructure 24A can be made of silicon-germanium with a germanium concentration of about 5% to 30% or about 15% to 30%, and dummy nanostructure 24B can be made of silicon-germanium with a germanium concentration of about 30% to 60% or about 35% to about 60%. It has been observed that by adjusting the germanium concentrations of dummy nanostructures 24A and 24B within the aforementioned ranges, sufficient selective etching can be achieved, allowing for the selective removal of dummy nanostructure 24B in subsequent processes while substantially removing dummy nanostructure 24A. For example, it has been observed that when the germanium concentration of dummy nanostructure 24A is less than 15%, dummy nanostructure 24A may not be completely removed during the gate replacement process. Furthermore, it has been observed that when the germanium concentration of dummy nanostructure 24A is greater than 30% and the germanium concentration of dummy nanostructure 24B is less than 35%, the etching selectivity between dummy nanostructure 24A and dummy nanostructure 24B may not be sufficient. As a result, during subsequent processing, dummy nanostructure 24B cannot be completely removed while at least a portion of dummy nanostructure 24A remains intact.

[0017] The lower semiconductor nanostructure 26L provides a channel region for the lower nanostructure-FETs of the CFETs. The upper semiconductor nanostructure 26U provides a channel region for the upper nanostructure-FETs of the CFETs. The dummy nanostructure 24B can be formed to directly contact the two dummy nanostructures 24A and may not contact any semiconductor nanostructure 26. Compared to the embodiments described later (e.g., see Figures 9-29C), the semiconductor nanostructures 26 immediately above / below (e.g., in contact) the dummy nanostructure 24B are excluded, and all semiconductor nanostructures 26 can provide channel regions in the resulting element. The dummy nanostructure 24B will then be replaced by an isolation structure defining the boundary between the lower and upper nanostructure-FETs.

[0018] To form the semiconductor bundle 28, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer (as shown and described above) can be deposited over the semiconductor substrate 20. The first, second, and third semiconductor material layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic deposition (ALD), or similar processes. Next, a patterning process can be applied to the first, second, and third semiconductor material layers and the semiconductor substrate 20 to define the semiconductor bundle 28, which includes the semiconductor bundle 20', the dummy nanostructure 24, and the semiconductor nanostructure 26.

[0019] Semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process can include one or more photolithography processes, including dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography and self-aligned processes, thereby enabling the creation of patterns, for example, with a pitch smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used as an etch mask for the patterning process to etch the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer, as well as the semiconductor substrate 20. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar etching processes, or combinations thereof. Etching can be anisotropic.

[0020] As shown in Figure 2, an STI region 32 is formed over the substrate 20 and between adjacent semiconductor bundles 28. The STI region 32 may include a dielectric pad and a dielectric material above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof. Forming the STI region 32 may include depositing a dielectric layer and performing a planarization process (e.g., chemical mechanical polishing (CMP), mechanical polishing, etc.) to remove excess dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flow CVD (FCVD), or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process followed by an annealing process. The dielectric layer is then recessed to define the STI region 32. The dielectric layer may be recessed such that the upper portion of the semiconductor bundles 28 (including the multilayer stack 22) protrudes above the remaining STI region 32.

[0021] After forming the STI region 32, a dummy gate stack 42 can be formed above and along the sidewall of the upper portion of the semiconductor bundle 28 (the portion protruding above the STI region 32). Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor bundle 28. The dummy dielectric layer 36 may include or be formed from, for example, silicon oxide, silicon nitride, combinations thereof, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed above the dummy dielectric layer 36. The dummy gate layer 38 may be deposited by, for example, physical vapor deposition (PVD), CVD, or other techniques, and then planarized by, for example, a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, or the like. A mask layer 40 is formed over a planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, or similar materials. The mask layer 40 is then patterned using photolithography and etching processes to form a mask, and the mask is used to etch and pattern the dummy gate layer 38 and, possibly, the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form a dummy gate stack 42.

[0022] In Figure 3, a gate spacer 44 and a source / drain groove 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed through deposition processes such as CVD and ALD.

[0023] Subsequently, source / drain recesses 46 are formed in the semiconductor bundle 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into the semiconductor bundle 20'. The bottom surface of the source / drain recesses 46 can be above, below, or flush with the top surface of the isolation region 32. During the etching process, the gate spacers 44 and the dummy gate stack 42 may obscure portions of the semiconductor bundle 28. Etching may include a single etching process or multiple etching processes. A timed etching process can be used to stop etching the source / drain recesses 46 when they reach the desired depth.

[0024] In Figures 4-6, the inner spacer 54 and the channel isolation structure 56 are formed in separate steps, which enhances control during their formation. For example, the materials, thicknesses, etc., of the inner spacer 54 and the channel isolation structure 56 can be independently selected and controlled, thereby improving electrical performance (e.g., improving AC current, reducing leakage current, etc.) while still providing a feasible process that is easily implemented. Furthermore, by independently forming the channel isolation structure 56, the dummy nanostructure 24A can be directly formed between and in contact with the dummy nanostructures 24B without any intermediate semiconductor nanostructure 26. Therefore, the dummy semiconductor nanostructure (e.g., dummy semiconductor nanostructure 26M, see Figures 9-29C) can be advantageously omitted from the manufacturing process and the resulting structure, which reduces leakage current in the resulting device. By omitting this dummy semiconductor nanostructure (e.g., dummy semiconductor nanostructure 26M, see Figures 9-29C), leakage current through the dummy semiconductor nanostructure can also be avoided.

[0025] In Figure 4, forming the channel isolation structure 56 may include an etching process for removing the dummy nanostructure 24B. The etching process may be isotropic and selective in its material selection for the dummy nanostructure 24B, such that the etching rate of the dummy nanostructure 24B is faster than that of the semiconductor nanostructure 26 and the dummy nanostructure 24A. In this way, the dummy nanostructure 24B can be completely removed between the lower semiconductor nanostructure 26L (collectively) and the upper semiconductor nanostructure 26U (collectively) without removing the semiconductor nanostructure 26 or the dummy nanostructure 24A. In some embodiments, the dummy nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the dummy nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, the semiconductor nanostructure 26 is formed of germanium-free silicon, and the etching process may include a dry etching process using chlorine gas (with or without plasma). Alternatively, the etching process can be a wet etching process, wherein the etchant exhibits an etch selectivity greater than 40 (e.g., in the range of 40 to 100) between dummy nanostructures 24A and 24B. The wet etching process may include dispensing a liquid etchant onto the device or immersing the device in a liquid etchant. The liquid etchant may include one or more elements / compounds (e.g., H₂O₂, O₃, etc.), germanium oxide (e.g., germanium in dummy nanostructures 24A and 24B), and one or more elements / compounds that etch away the germanium oxide. Etching selectivity can be achieved because dummy nanostructure 24B has a sufficiently high germanium concentration (e.g., within the range described above) compared to dummy nanostructure 24A. Furthermore, because the dummy gate stack 42 bends around the sidewalls of semiconductor nanostructure 26 (see Figure 2), the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, preventing it from collapsing during the removal of dummy nanostructure 24B.

[0026] In Figure 5, a channel isolation structure 56 is formed between an upper semiconductor nanostructure 26U (collectively referred to as such) and a lower semiconductor nanostructure 26L (collectively referred to as such). As will be described in more detail later, a source / drain region is subsequently formed in a source / drain recess 46. The channel isolation structure 56 can be used to isolate the upper semiconductor nanostructure 26U (collectively referred to as such) from the lower semiconductor nanostructure 26L (collectively referred to as such). The channel isolation structure 56 can be formed by conformally depositing an insulating material in the source / drain recess 46, on the sidewalls of the dummy nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, followed by etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value less than about 3.9 can be used. Insulating materials can be formed through deposition processes such as ALD and CVD. The etching of insulating materials can be anisotropic or isotropic. During etching, some insulating material remains between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, thereby forming a channel isolation structure 56.

[0027] Subsequently, in Figure 6, an inner spacer 54 is formed on the sidewall of the dummy nanostructure 24A. Forming the inner spacer 54 may include an etching process that recesses the sidewall of the dummy nanostructure 24A away from the sidewalls of the semiconductor nanostructure 26 and the channel isolation structure 56. The etching process may be isotropic and selective for the material of the dummy nanostructure 24A, such that the etching rate of the dummy nanostructure 24A is faster than the etching rate of the semiconductor nanostructure 26 and the channel isolation structure 56. In this way, the dummy nanostructure 24A can be recessed without removing the semiconductor nanostructure 26 or the channel isolation structure 56. In some embodiments, recessing the dummy nanostructure 24A may partially etch the exposed surfaces of the semiconductor nanostructure 26, including the top and / or bottom surfaces of the semiconductor nanostructure 26 and the outer regions of the semiconductor nanostructure 26. The etching process may include a dry etching process using chlorine gas (with or without plasma). Although the sidewalls of the dummy nanostructure 24A shown in the figure are straight after etching, the sidewalls can be concave or convex.

[0028] The inner spacer 54 is then formed on the recessed sidewalls of the dummy nanostructure 24A. As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 46, and the dummy nanostructure 24A will be replaced by a corresponding gate structure. The inner spacer 54 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the inner spacer 54 can be used to prevent subsequent etching processes (e.g., etching processes for forming the gate structure) from damaging the subsequently formed source / drain regions. The inner spacer 54 can be formed by conformally depositing an insulating material in the source / drain recess 46, on the sidewalls of the dummy nanostructure 24A, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, followed by etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. Other low-k materials with a k value less than approximately 3.9 can be used. The insulating material can be formed through deposition processes such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. During etching, a portion of the insulating material remains on the sidewalls of the dummy nanostructure 26A, forming inner spacers 54. The material composition of the channel isolation structure 56 can be the same as or different from the material composition of the inner spacers 54.

[0029] As shown in Figure 6, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain groove 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L but not with the upper semiconductor nanostructure 26U. An inner spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy nanostructure 24A, which will be replaced by a replacement gate in a subsequent process.

[0030] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure-FETs. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon, doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, its respective material may include silicon or silicon-germanium, doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain region 62L can be in-situ doped, and may or may not be doped with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U can be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can be removed.

[0031] Due to the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has facets that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0032] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed of a dielectric material with high etch selectivity for etching the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed of a dielectric material that can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phospholipid glass (PSG), borosilicate glass (BSG), boron-doped phospholipid glass (BPSG), undoped silicate glass (USG), silicon oxide, or similar materials.

[0033] The fabrication process may include depositing a conformal CESL layer, depositing material for the first ILD 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 68 is etched first, while the first CESL 66 is not etched. An anisotropic etch process is then performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0034] The upper epitaxial source / drain region 62U is then formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials as those forming the lower epitaxial source / drain region 62L, depending on the required conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in the opposite direction to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can also have the same conductivity type. The upper epitaxial source / drain region 62U can be doped in situ and / or implanted with n-type or p-type dopants. Adjacent upper epitaxial source / drain regions 62U can remain separate or merged after the epitaxial process.

[0035] After forming the upper epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods are similar to those for the first CESL 66 and the first ILD 68, respectively, and therefore will not be discussed in detail here. The formation process may include depositing layers of CESL 70 and ILD 72, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within the process variation range). Therefore, the top surface of the mask 40 (if present) or dummy gate 38 is exposed through the second ILD 72. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, such that the top surface of the dummy gate 38 is exposed through the second ILD 72.

[0036] Figure 7 illustrates an alternative gate process, replacing the dummy gate stack 42 and dummy nanostructure 24A with a gate stack 90. ​​The alternative gate process includes first removing the remaining portions of the dummy gate stack 42 and dummy nanostructure 24A. The dummy gate stack 42 is removed through one or more etching processes, thereby defining a groove between the gate spacers 44 and exposing the upper portion of the semiconductor bundle 28. The remaining portions of the dummy nanostructure 24A are then removed through etching, such that the groove extends between the semiconductor nanostructures 26. During etching, the dummy nanostructure 24A is etched at a faster rate than the semiconductor nanostructures 26, the channel isolation structure 56, and the inner spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0037] Next, gate dielectric 78 is deposited in the grooves between the gate spacers 44 and on the exposed semiconductor nanostructure 26. Gate dielectric 78 is conformally formed on the exposed surface of the grooves (removed gate stack 42 and dummy nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, gate dielectric 78 surrounds all sides (e.g., four sides) of the semiconductor nanostructure 26. Specifically, gate dielectric 78 may be formed on the top surface of fin 20'; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 26; and on the sidewalls of the gate spacers 44. Gate dielectric 78 may include oxides (e.g., silicon oxide or metal oxide), silicates (e.g., metal silicates), combinations thereof, multilayers thereof, etc. The gate dielectric 78 may comprise a high-k material having a k-value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove a portion of the gate dielectric 78 above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 may comprise multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0038] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L surrounds the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multiples thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0039] The lower gate electrode 80L is formed of a material suitable for the device type of lower nanostructure FETs. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of a material suitable for the device type of lower nanostructure FETs. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or alternatively, the lower gate electrode 80L may include a dipole induction element suitable for the device type of lower nanostructure FETs. Acceptable dipole induction elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0040] The lower gate electrode 80L can be formed by conformally depositing one or more gate electrode layers and recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0041] In some embodiments, an isolation layer (not explicitly shown) may be selectively formed on the lower gate electrode 80L. The isolation layer serves as an isolation feature between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0042] Next, an upper gate electrode 80U is formed on the aforementioned isolation layer (if present) or the lower gate electrode 80L. The upper gate electrode 80U is located between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U surrounds the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed using the same candidate materials and candidate processes as the lower gate electrode 80L. The upper gate electrode 80U is formed from materials suitable for the device type of the upper nanostructure-FETs. For example, the upper gate electrode 80U may include one or more work function adjustment layers (e.g., n-type work function adjustment layers and / or p-type work function adjustment layers) formed from materials suitable for the device type of the upper nanostructure-FETs. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0043] In addition, a removal process is performed to planarize the top surfaces of the upper gate electrode 80U and the second ILD 72. The removal process used to form the gate dielectric 78 can be the same as the removal process used to form the upper gate electrode 80U. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof, can be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within the range of process variations). Each pair of gate dielectrics 78 and gate electrodes 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a "gate structure" 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1). The lower gate structure 90L may also extend along the sidewall and / or top of the semiconductor fin 20'. Furthermore, since any intermediate dummy semiconductor nanostructures on the channel isolation structure 56 are omitted, the lower gate structure 90L and the upper gate structure 90U may each be in direct physical contact with the channel isolation structure 56.

[0044] As shown in Figure 7, a gate shield 92 is formed above the gate stack 42. The forming process may include recessing the gate stack 90, filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, or silicon oxycarbonitride, and performing a planarization process to remove excess dielectric material above the second ILD 72.

[0045] In Figure 8, a metal-semiconductor alloy region 94 and a source / drain contact 96 are formed through the second ILD 72 to electrically couple to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. As an embodiment of forming the source / drain contact 96, an opening is formed through the second ILD 72 and the second CESL 70 using acceptable photolithography and etching techniques. A pad (not shown separately), such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process may be performed to remove excess material from the gate spacer 44 and the top surface of the second ILD 72. The remaining pad and conductive material form the source / drain contact 96 in the opening. In some embodiments, a planarization process, such as CMP, etch-back process, or a combination thereof, is utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contact 96 are substantially coplanar (within the range of process variations).

[0046] Selectively, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 may be a silicate region formed from metal silicates (e.g., titanium silicates, cobalt silicates, nickel silicates, etc.), a germanium silicate region formed from metal germanides (e.g., titanium germanides, cobalt germanides, nickel germanides), and the metal silicate region includes: a silica-germanium silicate region formed by both metal silicates and metal germanides; and a silica-germanium silicate region formed by both metal silicates and metal germanides. The metal-semiconductor alloy region 94 can be formed before the material of the source / drain contact 96 by depositing metal in the opening of the source / drain contact 96 followed by a thermal annealing process. This metal can be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited using deposition processes such as ALD, CVD, or PVD. After a thermal annealing process, a cleaning process (e.g., wet cleaning) can be performed to remove any residual metal from the openings in the source / drain contact 96 (e.g., from the surface of the metal-semiconductor alloy region 94). The material for the source / drain contact 96 can then be formed on the metal-semiconductor alloy region 94.

[0047] Next, ESL 104 and third ILD 106 are formed. In some embodiments, ESL 104 may include a dielectric material with high etch selectivity for etching the third ILD 106, such as alumina, aluminum nitride, silicon carbide, etc. The third ILD 106 may be formed using methods such as flow CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc.

[0048] Subsequently, gate contact 108 and source / drain via 110 are formed to contact the upper gate electrode 80U and source / drain contact 96, respectively. As an embodiment of forming gate contact 108 and source / drain via 110, openings for gate contact 108 and source / drain via 110 are formed through the third ILD 106 and ESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers, adhesive layers, etc., and conductive material are formed in the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process (e.g., CMP) can be performed to remove excess material from the top surface of the third ILD 106. The remaining pads and conductive material form gate contact 108 and source / drain via 110 in the openings. The gate contact 108 and the source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed in a different cross-section, which can prevent short circuits in the contacts.

[0049] A front-side interconnect structure 114 is formed on device layer 112. The front-side interconnect structure 114 includes a dielectric layer 116 and conductive features 118 within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a protective layer formed on the low-k dielectric layer 116 of a non-low-k and dense dielectric material (e.g., undoped silicate glass (USG), silicon oxide, silicon nitride, etc.) or a combination thereof. The dielectric layer 116 may also include a polymer layer.

[0050] Conductive feature 118 may include conductive lines and vias, and may be formed using an inlay fabrication method. Conductive feature 118 may include metal lines and metal vias, including a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. An aluminum pad may also be present above the metal lines and vias and electrically connected to the metal lines and vias. In some embodiments, contacts with the lower gate stack 90L and the lower gate electrode 80L may be formed through the rear side of device layer 112 (e.g., the side opposite to the front interconnect structure 114).

[0051] Figures 9-14 show cross-sectional views of intermediate process steps for forming stacked transistors according to some other embodiments, wherein the channel isolation structure 56 has a multilayer structure. In Figures 9-14, unless otherwise stated, the same reference numerals denote the same elements formed through the same process discussed above with respect to Figures 2-8. Figure 9 shows a structure of a process stage similar to that in Figure 3 above, wherein the source / drain recess 46 is patterned through a multilayer stack 22. However, in Figure 9, the dummy nanostructure 26B is not formed directly between the dummy nanostructures 26A. Instead, the dummy semiconductor nanostructure 26M is disposed on the top and bottom surfaces of the dummy nanostructure 24B. The dummy semiconductor nanostructure 26M can be formed using the same material and the same process as the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L. For example, in some embodiments, the upper semiconductor nanostructure 26U, the lower semiconductor nanostructure 26L, and the dummy semiconductor nanostructure 26M can be formed of silicon, while the dummy nanostructures 24A and 24B are formed of silicon with different germanium concentrations. The dummy semiconductor nanostructure 26M, also referred to as the intermediate semiconductor nanostructure, helps define the boundary between the upper and lower transistors in a stacked transistor configuration. The dummy semiconductor nanostructure 26M can be used to widen the process window for forming the channel isolation structure, allowing for a wider etch selectivity window between the dummy nanostructures 24A and 24B, since the etch selectivity between the dummy nanostructure 24B (e.g., high germanium concentration silicon-germanium) and the dummy semiconductor nanostructure 26M (e.g., silicon) is generally greater than that between the dummy nanostructure 24A (e.g., low germanium concentration silicon-germanium) and the dummy semiconductor nanostructure 26M (e.g., silicon).

[0052] In Figure 10, the dummy nanostructure 24B is removed. Removing the dummy nanostructure 24B can include an etching process similar to that described above with respect to Figure 4. For example, the etching process can be isotropic and selective in its material selection for the dummy nanostructure 24B, such that the etching rate of the dummy nanostructure 24B is faster than that of the upper semiconductor nanostructure 26U, the dummy semiconductor nanostructure 26M, and the lower semiconductor nanostructure 26B. In this way, the dummy nanostructure 24B can be completely removed between the lower semiconductor nanostructure 26L (collectively referred to as the dummy nanostructure) and the upper semiconductor nanostructure 26U (collectively referred to as the dummy nanostructure), without removing semiconductor nanostructure 26, the dummy semiconductor nanostructure 26M, or the dummy nanostructure 24A. In some embodiments, dummy nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, dummy nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructure 26 and dummy semiconductor nanostructure 26M are formed of silicon-germanium with a low percentage of germanium atoms. Alternatively, the etching process can be a wet etching process, wherein the etchant exhibits an etch selectivity greater than 40 (e.g., in the range of 40 to 100) between dummy nanostructures 24A and 24B. The wet etching process can include dispensing a liquid etchant onto the device or immersing the device in a liquid etchant. The liquid etchant can include one or more elements / compounds (e.g., H₂O₂, O₃, etc.) that oxidize germanium (e.g., germanium in dummy nanostructures 24A and 24B) and includes one or more elements / compounds that etch away the oxidized germanium. Since dummy nanostructure 24B has a sufficiently high germanium concentration (e.g., within the range described above) compared to dummy nanostructure 24A, etch selectivity can be achieved. Furthermore, since the dummy gate stack 42 is bent around the sidewall of the semiconductor nanostructure 26 (see Figure 2), the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, so that the upper semiconductor nanostructure 26U will not collapse when the dummy nanostructure 24B is removed.

[0053] In Figure 11, dielectric material layers 50A and 50B are sequentially deposited within the source / drain groove 46, on the sidewalls of the dummy nanostructure 24A, on the sidewalls of the semiconductor nanostructure 26, on the sidewalls of the dummy semiconductor nanostructure 26M, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, using suitable conformal deposition processes such as CVD and ALD. Specifically, dielectric material layer 50A can be formed to contact the lateral surface of the dummy semiconductor nanostructure 26M, while dielectric material layer 50B can fill the remaining space between the vertically stacked dummy semiconductor nanostructures 26M. Dielectric material layers 50A and 50B can have different material compositions. For example, dielectric material layer 50A can be a relatively hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonitrides, silicon oxycarbides, silicon oxynitrides, or similar materials with relatively high k values. In some embodiments, dielectric layer 50A may be a high-k material with a k value in the range of about 3.9 to about 10. Conversely, dielectric layer 50B may be made of a relatively low-k dielectric material with a k value less than about 3.9. In some embodiments, dielectric layer 50B has a lower k value than dielectric layer 50A, while dielectric layer 50A is harder than dielectric layer 50B (e.g., having higher etch resistance relative to the same etch process). By using a combination of materials, the resulting channel isolation structure can be relatively strong and less susceptible to damage in subsequent process steps (e.g., due to the inclusion of a harder material in dielectric layer 50A), while still having a low k value to improve isolation (e.g., due to the inclusion of a low-k dielectric layer 50B). Therefore, the resulting stacked transistor can have improved electrical properties (e.g., improved alternating current) and can be easily formed through feasible manufacturing processes.

[0054] In Figure 12, an etching process is performed to remove dielectric material layers 50A and 50B from the sidewalls of the source / drain recess 46, the sidewalls of the gate spacer 44, and above the dummy gate stack 42. The remaining portions of dielectric material layers 50A and 50B form channel isolation materials 56A and 56B, respectively. Channel isolation material 56B may be disposed between the upper and lower portions of channel isolation material 56A. As described in more detail later, source / drain regions are subsequently formed in the source / drain recess 46. Channel isolation materials 56A and 56B can be used to isolate the upper semiconductor nanostructure 26U (collectively referred to as such) from the lower semiconductor nanostructure 26L (collectively referred to as such). The etching of dielectric material layers 50A and 50B can be anisotropic or isotropic.

[0055] In Figure 13, an etching process is performed to recess the sidewalls of the dummy nanostructure 24A away from the sidewalls of the semiconductor nanostructure 26 and the channel isolation materials 56A and 56B. The etching process can be isotropic and selective for the material of the dummy nanostructure 24A, such that the etching rate of the dummy nanostructure 24A is faster than the etching rate of the semiconductor nanostructure 26 and the channel isolation materials 56A and 56B. In this way, the dummy nanostructure 24A can be recessed without removing the semiconductor nanostructure 26 or the channel isolation structure 56. In some embodiments, recessing the dummy nanostructure 24A can partially etch the exposed surfaces of the semiconductor nanostructure 26, including the top and / or bottom surfaces of the semiconductor nanostructure 26 and the outer regions of the semiconductor nanostructure 26. The etching process can also partially recess the sidewalls of the channel isolation material 56B (and selectively, to a lesser extent, partially recess the sidewalls of the channel isolation material 56A). However, due to the relative hardness of the channel isolation material 56A, even if the channel isolation material 56B is recessed, the channel isolation material 56A remains relatively unetched, and the overall channel isolation structure remains intact. The etching process can include a dry etching process using chlorine gas (with or without plasma). Although the sidewalls of the dummy nanostructure 24A shown in the figure are straight after etching, the sidewalls can also be concave or convex.

[0056] Subsequently, in Figure 14, an inner spacer 54 is formed on the recessed sidewall of the dummy nanostructure 24A. The inner spacer 54 can be formed using a similar material and a similar process as described above with respect to Figure 6. For example, the inner spacer 54 can be formed by conformally depositing an insulating material in the source / drain recess 46, on the sidewall of the dummy nanostructure 24A, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, followed by etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value less than about 3.9 can be used. A portion of the insulating material on the recessed sidewall of the channel isolation material 56B can be patterned to form the channel isolation material 56C. The channel isolation material 56C has the same material composition as the inner spacer 54 and is formed using the same process. The resulting multi-layer channel isolation structure 56 includes a relatively rigid channel isolation material 56A, a low-k channel isolation material 56B sandwiched between the channel isolation materials 56A, and a channel isolation material 56C located on the sidewall of the channel isolation material 56B. The material composition of the channel isolation materials 56A and 56B may be the same as or different from the material composition of the inner spacer 54.

[0057] As further shown in Figure 14, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L, CESLs 66 and CESLs 70, and ILDs 68 and ILDs 72 are formed in the source / drain recess 46. Additional process steps can be performed, including alternative gate processes, formation of gate and source / drain contacts, and formation of front-side interconnects, as described above, to achieve the structure of Figure 15. Figure 15 shows a structure similar to that of Figure 8, wherein the same reference numerals denote the same elements. However, the channel isolation structure 56 of Figure 15 is a multilayer structure, having a relatively rigid channel isolation material 56A, a low-k channel isolation material 56B sandwiched between the channel isolation materials 56A, and a channel isolation material 56C located on the sidewall of the channel isolation material 56A. Furthermore, the dummy semiconductor nanostructure 26M can be retained in the resulting device, separating the channel isolation structure 56 from the upper gate structure 90U and the lower gate structure 90L. The dummy semiconductor nanostructure 26M cannot serve as a channel region because it is not adjacent to any epitaxial source / drain region.

[0058] Figures 16-18 show cross-sectional views of intermediate process steps in forming stacked transistors according to some other embodiments, wherein the channel isolation structure 56 is made of a single material and includes a dummy semiconductor nanostructure 26M. In Figures 16-18, unless otherwise stated, the same reference numerals denote the same elements formed through the same process discussed above with respect to Figures 2-15. Figure 16 shows a structure of a process stage similar to Figure 12 above, wherein the source / drain recess 46 is patterned through a multilayer stack 22, and the channel isolation structure 56 is formed between an upper semiconductor nanostructure 26U (collectively referred to as such) and a lower semiconductor nanostructure 26L (collectively referred to as such). However, in Figure 16, the channel isolation structure 56 does not have a multilayer structure but is made of a single material. In some embodiments, the channel isolation structure 56 is made of a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. The channel isolation structure 56 can be formed by direct contact with the dummy semiconductor nanostructure 26M.

[0059] In Figure 17, an inner spacer 54 is formed on the sidewall of the dummy nanostructure 24A. The inner spacer 54 can be formed from similar materials and using a similar process as described above. Similar to the embodiments described above, the inner spacer 54 and the channel isolation structure 56 can be formed in different processes to increase the flexibility and control when forming different isolation structures in the stacked transistors. The inner spacer 54 can be formed from the same or different materials as the channel isolation structure 56. In addition, an upper epitaxial source / drain region 62U and a lower epitaxial source / drain region 62L, CESLs 66 and CESLs 70, and ILDs 68 and ILDs 72 can also be formed in the source / drain groove 46.

[0060] Additional process steps can be performed, including alternative gate processes, formation of gate and source / drain contacts, and formation of front-side interconnects, as described above, to achieve the structure of Figure 18. Figure 18 shows a structure similar to that of Figure 15, wherein the same reference numerals denote the same elements. However, the channel isolation structure 56 of Figure 18 is not a multilayer structure but is made of a single material.

[0061] Although in the above embodiments, the channel isolation structure 56 is only disposed between the upper semiconductor nanostructure 26U (general term) and the lower semiconductor nanostructure 26L (general term), separating the upper semiconductor nanostructure 26U (general term) and the lower semiconductor nanostructure 26L (general term), the channel isolation structure 56 may also be formed at other locations relative to the semiconductor nanostructure 26. For example, Figures 19-21 illustrate an intermediate stage of the manufacturing embodiment, wherein the channel isolation structure 56 is also formed below the lower semiconductor nanostructure 26L, for example, below the lower gate stack 90L. The channel isolation structure 56 may be formed between the lower gate stack 90L and the lower semiconductor fin 20' / substrate 20 to improve isolation in the bottom region of the stacked transistor and further reduce leakage current in the resulting device. For example, the channel isolation structure 56 below the lower gate stack 90L can reduce leakage current from the lower epitaxial source / drain region 62L through the semiconductor fin 20' and the semiconductor substrate 20. The channel isolation structure 56 can be formed to directly contact the lower gate stack 90L and the semiconductor fin 20'. The channel isolation structure 56 can be formed using similar processes and materials as described above, wherein the lower channel isolation structure 56 (e.g., below the lower semiconductor nanostructure 26L) is formed by first forming a dummy nanostructure 24B below the lower semiconductor nanostructure 26L, as shown in Figure 19. For example, the dummy nanostructure 24B can be formed to directly contact the top surface of the semiconductor fin 20'. The dummy nanostructure 24B can then be replaced with the channel isolation structure 56 as described above (as shown in Figure 20).

[0062] Additional process steps include forming an inner spacer 54, forming an upper epitaxial source / drain region 62L and a lower epitaxial source / drain region 62U, forming CESLs 66 and CESLs 70, forming ILDs 68 and ILDs 72, an alternative gate process, forming gate and source / drain contacts, and forming a front-side interconnect, which can be performed as described above to obtain the structure shown in Figure 21. As further shown in Figure 21, a bottom ILD 120 and a bottom CESL 122 can be formed below the lower epitaxial source / drain region 62L, for example, between the lower epitaxial source / drain region 62L and the semiconductor fin 20'. The bottom ILD 120 and bottom CESL 122 can be formed in the source / drain recess 46 using similar materials and similar processes to the first ILD 68 and the first CESL 66, respectively, prior to the formation of the lower epitaxial source / drain region 62L. The bottom ILD 120 and bottom CESL 122 can further reduce leakage current from the lower epitaxial source / drain region 62L through the semiconductor fin 20'.

[0063] As another example, Figures 22-24 illustrate an intermediate stage of a manufacturing embodiment, wherein a channel isolation structure 56 is formed below the lower semiconductor nanostructure 26L, for example below the lower gate stack 90L, and above the upper semiconductor nanostructure 26U. The channel isolation structure 56 may be formed between the lower gate stack 90L and the lower semiconductor fin 20' / substrate 20 to improve isolation in the bottom region of the stacked transistors and further reduce leakage current in the resulting device. For example, the channel isolation structure 56 below the lower gate stack 90L can reduce leakage current from the lower epitaxial source / drain region 62L through the semiconductor fin 20' and the semiconductor substrate 20. The channel isolation structure above the upper semiconductor nanostructure 26U can be used to protect the upper semiconductor nanostructure 26U during the manufacturing process to improve nanostructure profile and controllability. The channel isolation structure 56 can be formed using similar processes and similar materials as described above. As shown in Figure 22, the lower channel isolation structure 56 (e.g., below the lower semiconductor nanostructure 26L) is formed by first forming a dummy nanostructure 24B below the lower semiconductor nanostructure 26L, while the upper channel isolation structure 56 (e.g., above the upper semiconductor nanostructure 26U) can be formed by first forming a dummy nanostructure 24B above the upper semiconductor nanostructure 26U. For example, the dummy nanostructure 24B can be formed to directly contact the top surface of the semiconductor fin 20', or it can be formed to directly contact the very top of the upper semiconductor nanostructure 26U. The dummy nanostructure 24B can then be replaced by the channel isolation structure 56 as described above (as shown in Figure 23).

[0064] Additional process steps include forming inner spacers 54, forming upper epitaxial source / drain regions 62L and lower epitaxial source / drain regions 62U, forming CESLs 66 and CESLs 70, forming ILDs 68 and ILDs 72, alternative gate processes, formation of gate and source / drain contacts, and formation of front-side interconnects, which can be performed as described above to obtain the structure shown in Figure 21. As further shown in Figure 24, bottom ILD 120 and bottom CESL 122 can be formed below the lower epitaxial source / drain region 62L, for example, between the lower epitaxial source / drain region 62L and the semiconductor fin 20'. The bottom ILD 120 and bottom CESL 122 can be formed in the source / drain recess 46 using similar materials and similar processes to the first ILD 68 and the first CESL 66, respectively, prior to the formation of the lower epitaxial source / drain region 62L. The bottom ILD 120 and bottom CESL 122 can further reduce leakage current from the lower epitaxial source / drain region 62L through the semiconductor fin 20'.

[0065] In the various embodiments described above, after the epitaxial source / drain regions are formed, the dummy nanostructure 24A is removed as part of the alternative gate process. In other embodiments, the dummy nanostructure 24A may be replaced with sacrificial material before the epitaxial source / drain regions are formed. For example, Figures 26-29C show cross-sectional views of forming a stacked transistor according to some other embodiments, wherein the dummy nanostructure 24A is replaced with sacrificial material before the lower source / drain region 62L and the upper epitaxial source / drain region 62U are formed. In Figures 26-29C, unless otherwise stated, the same reference numerals denote the same elements formed through the same process discussed above with respect to Figures 2-25. Specifically, Figure 25 shows a structure at the same manufacturing stage as Figure 16 above, wherein the source / drain recesses are patterned through a multilayer stack 22, and the dummy nanostructure 24B is replaced by a channel isolation structure 56. The channel isolation structure can be set between and separate the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L).

[0066] In Figures 26-27C, the dummy nanostructure 24A is replaced by a sacrificial material 58 (also referred to as a one-time oxide interposer (DOI) 58). Replacing the dummy nanostructure 24A may include etching it away using a suitable etching process (e.g., an isotropic etching process) through the source / drain recess 46, as shown in Figure 26. The etching process may selectively select the material of the dummy nanostructure 24A and remove it without significantly removing the semiconductor nanostructure 26, the dummy semiconductor nanostructure 26M, or the channel isolation structure 56. In embodiments where the dummy nanostructure 24A comprises, for example, SiGe, and the semiconductor nanostructure 26 / dummy semiconductor nanostructure 26M comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or a similar process may be used to remove the dummy nanostructure 24A.

[0067] In Figures 27A-27C, sacrificial material 58 can be formed in the gaps between semiconductor nanostructures 26. Forming sacrificial material 58 can include depositing a sacrificial material layer in the source / drain recess 46 and the space after removing the dummy semiconductor nanostructure 24A. The sacrificial material layer can be deposited using a conformal deposition process (e.g., CVD, ALD, etc.). The sacrificial material layer can include an insulating material, such as silicon oxide (e.g., SiO2), which can be selectively etched from the channel isolation structure 56, the semiconductor nanostructure 26, and the dummy semiconductor nanostructure 26M. The sacrificial material layer can then be etched to form sacrificial material 58. The etching can be isotropic or anisotropic. For example, diluted HF or the like can be used as an etchant to etch the sacrificial material layer using a wet etching process. In some embodiments, etching continues until the sidewalls of the sacrificial material 58 are recessed into the sidewalls of the semiconductor nanostructure 26. Although the sidewalls of the sacrificial material 58 are shown as straight in Figures 27A-27C, the sidewalls may be concave or convex. Furthermore, although the sidewalls of the sacrificial material 58 are shown aligned with the sidewalls of the semiconductor nanostructure 26, in some embodiments, the sidewalls of the sacrificial material 58 may be recessed from the sidewalls of the semiconductor nanostructure 26.

[0068] Figure 27A shows an embodiment consistent with Figures 16-18, wherein the channel isolation structure 56 is formed only between the upper semiconductor nanostructure 26U (collectively referred to as) and the lower semiconductor nanostructure 26L (collectively referred to as) . Figure 27B shows an embodiment consistent with Figures 19-21, wherein the channel isolation structure 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as) and the lower semiconductor nanostructure 26L (collectively referred to as) , and between the lower semiconductor nanostructure 26L (collectively referred to as) and the semiconductor fin 20' . Figure 27C shows an embodiment consistent with Figures 22-24, wherein the channel isolation structure 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as) and the lower semiconductor nanostructure 26L (collectively referred to as) ; between the lower semiconductor nanostructure 26L (collectively referred to as) and above the upper semiconductor nanostructure 26U (collectively referred to as) .

[0069] Replacing the dummy nanostructure 24A with sacrificial material 58 may offer advantages. For example, one or more high-temperature processes can be performed in subsequent source / drain formation steps, such as activating dopants in the source / drain regions. When the material of the dummy nanostructure 24A (e.g., silicon-germanium) is exposed to high temperatures, germanium mixing and increased roughness at the interface between the semiconductor nanostructure 26 and the dummy nanostructure 24A may occur. Such manufacturing defects can degrade the performance of the final transistor device. For example, when germanium diffuses into the semiconductor nanostructure 26, germanium residue may remain in the channel regions of the resulting stacked transistor device, negatively impacting the performance of the channel regions. By replacing the dummy nanostructure 24A with an insulating material prior to high-temperature processes (e.g., source / drain annealing), manufacturing defects can be reduced and device performance improved (e.g., increased current drive, reduced capacitance, and improved short-channel effects).

[0070] In Figure 28, an inner spacer 54 is formed on the sidewall of the sacrificial material 58. The inner spacer 54 can be formed from a similar material using a similar process as described above. For example, forming the inner spacer 54 may include recessing the sidewall of the sacrificial material 58 from the sidewall of the semiconductor nanostructure 26 and the dummy semiconductor nanostructure 26M (if not previously recessed). Next, an insulating material layer is deposited and etched to form the inner spacer 54. Similar to the embodiments described above, the inner spacer 54 and the channel isolation structure 56 can be formed using different processes to increase flexibility and control when forming different isolation structures in the stacked transistors. The inner spacer 54 can be formed from the same material as the channel isolation structure 56 or a different material. Furthermore, an upper epitaxial source / drain region 62L and a lower epitaxial source / drain region 62U, CESLs 66 and CESLs 70, and ILDs 68 and ILDs 72 can also be formed in the source / drain recess 46.

[0071] Additional process steps, including alternative gate processes, formation of gate and source / drain contacts, and formation of front-side interconnects, can be performed as described above to obtain the structure shown in Figures 29A-29C. Figure 29A illustrates an embodiment consistent with Figures 16-18 and 27A, wherein the channel isolation structure 56 is formed only between the upper semiconductor nanostructure 26U (collectively referred to as) and the lower semiconductor nanostructure 26L (collectively referred to as) . Figure 29B illustrates an embodiment consistent with Figures 19-21 and 27B, wherein the channel isolation structure 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as) and the lower semiconductor nanostructure 26L (collectively referred to as) , and between the lower semiconductor nanostructure 26L (collectively referred to as) and the semiconductor fin 20'. Figure 29C shows an embodiment consistent with Figures 22-24 and Figure 27C, wherein a channel isolation structure 56 is formed between an upper semiconductor nanostructure 26U (collectively referred to as such) and a lower semiconductor nanostructure 26L (collectively referred to as such); between the lower semiconductor nanostructure 26L (collectively referred to as such) and a semiconductor fin 20'; and above the upper semiconductor nanostructure 26U (collectively referred to as such).

[0072] Various embodiments provide a stacked transistor structure including a vertically stacked upper transistor and a lower transistor, and a method of forming this stacked transistor. A channel isolation structure is formed between an upper channel region of the upper transistor and a lower channel region of the lower transistor, isolating the upper channel region of the upper transistor from the lower channel region of the lower transistor. The channel isolation structure can be formed separately from other isolation structures in the device, such as internal spacers separating the upper and lower gate stacks from directly contacting upper and lower source / drain regions. The channel isolation structure of these embodiments provides improved electrical performance (e.g., improved alternating current (AC) current, improved leakage current, etc.) through a simplified process that is easy to implement.

[0073] In some embodiments, an element includes a multilayer stack comprising: a first complex nanostructure; a second complex nanostructure located above the first complex nanostructure; and a first channel isolation structure. The element further includes a first source / drain region located at opposite endpoints of the first complex nanostructure; a second source / drain region located above the first source / drain region and at opposite endpoints of the second complex nanostructure; a first gate structure surrounding the first complex nanostructure, wherein the first gate structure contacts a first lateral surface of the first channel isolation structure; and a second gate structure surrounding the second complex nanostructure. Optionally, in some embodiments, the first channel isolation structure is disposed between the first complex nanostructure and the second complex nanostructure. Optionally, in some embodiments, the second gate structure contacts a second lateral surface of the first channel isolation structure. Optionally, in some embodiments, the first channel isolation structure is disposed below the first complex nanostructure. Optionally, in some embodiments, the element further includes an interlayer dielectric (ILD) located below the first source / drain region, wherein the interlayer dielectric extends along the sidewall of the first channel isolation structure. Optionally, in some embodiments, the multilayer stack further includes a second channel isolation structure located above the second complex nanostructure. Optionally, in some embodiments, the element further includes a first inner spacer located between the sidewall of the first gate structure and the first source / drain region; and a second inner spacer located between the sidewall of the second gate structure and the second source / drain region, wherein the first inner spacer and the second inner spacer have the same compositional material. Optionally, in some embodiments, the first inner spacer and the second inner spacer have different compositional materials compared to the first channel isolation structure.

[0074] In some embodiments, an element includes a first complex nanostructure; a second complex nanostructure located above the first complex nanostructure; and a channel isolation structure located between the first and second complex nanostructures. The channel isolation structure has a multilayer structure and includes: a first channel isolation material; and a second channel isolation material located between an upper and lower portion of the first channel isolation material. The element further includes a first source / drain region located at opposite endpoints of the first complex nanostructure; a second source / drain region located above the first source / drain region and at opposite endpoints of the second complex nanostructure; a first gate structure surrounding the first complex nanostructure; and a second gate structure surrounding the second complex nanostructure. Optionally, in some embodiments, the multilayer structure further includes a third channel isolation material located on the sidewall of the second channel isolation material, wherein the element further includes: a first inner spacer located between the sidewall of the first gate structure and the first source / drain region; and a second inner spacer located between the sidewall of the second gate structure and the second source / drain region, wherein the first inner spacer, the second inner spacer, and the third channel isolation material have the same constituent material. Optionally, in some embodiments, the second inner spacer overlaps with the first channel isolation material, the second channel isolation material, and the third channel isolation material. Optionally, in some embodiments, the second channel isolation material has a lower dielectric constant than the first channel isolation material. Optionally, in some embodiments, the first channel isolation material is harder than the second channel isolation material.

[0075] In some embodiments, a method includes forming a multilayer stack comprising: a lower semiconductor nanostructure stacked alternately with a first dummy nanostructure; an upper semiconductor nanostructure stacked alternately with a second dummy nanostructure; and a third dummy nanostructure located between the lower semiconductor nanostructure and the upper semiconductor nanostructure. The method further includes patterning source / drain grooves through multiple stacked layers; replacing the third dummy nanostructure with one or more channel isolation materials; after replacing the third dummy nanostructure with one or more channel isolation materials, recessing the sidewalls of the first and second dummy nanostructures; forming inner spacers on the recessed sidewalls of the first and second dummy nanostructures; forming a first source / drain region and a second source / drain region in the source / drain grooves, the first source / drain region being adjacent to the lower semiconductor nanostructure and the second source / drain region being adjacent to the upper semiconductor nanostructure; replacing the first dummy nanostructure with a first gate structure; and replacing the second dummy nanostructure with a second gate structure. Optionally, in some embodiments, the third dummy nanostructure directly contacts the first and second dummy nanostructures. Optionally, in some embodiments, the third dummy nanostructure directly contacts the first dummy semiconductor nanostructure and the second dummy semiconductor nanostructure, wherein the first and second dummy semiconductor nanostructures have the same constituent materials as the lower and upper semiconductor nanostructures. Optionally, in some embodiments, replacing the third dummy nanostructure with one or more channel isolation materials includes: removing the third dummy nanostructure to define a gap between the lower and upper semiconductor nanostructures; depositing a first channel isolation material layer on the top and bottom surfaces of the gap; filling the remaining portion of the gap with a second channel isolation material layer; and removing excess portions of the first and second channel isolation material layers disposed outside the gap to define the first and second channel isolation materials. Optionally, in some embodiments, the second channel isolation material layer has a lower k-value than the first channel isolation material layer. Optionally, in some embodiments, the method further includes: simultaneously recessing the sidewalls of the first dummy nanostructure and the second dummy nanostructure; and simultaneously forming the inner spacer, forming the third channel spacer on the recessed sidewalls of the second channel spacer. Optionally, in some embodiments, each of the first dummy nanostructure, the second dummy nanostructure, and the third dummy nanostructure comprises silicon germanium, wherein the third dummy nanostructure has a higher germanium concentration than the first dummy nanostructure and the second dummy nanostructure.

[0076] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0077] 10: Transistor 10L, 10U: FETs (Transistors) 20:Substrate 20': Semiconductor beam (semiconductor fin) 22: Stacking 24, 24A, 24B: Feigned nanostructures 26, 26A, 26B, 26L, 26M, 26U: Nanostructures 28: Semiconductor beam 32: STI Area (Isolation Area) 36: Dummy dielectric layer 38: Dummy gate (Dummy gate layer) 40: Mask (mask layer) 42: Gate Stacking 44: Gate spacer 46: Source / Drain Groove 50A, 50B: Dielectric material layers 54: Internal spacers 56, 56A, 56B, 56C: Channel isolation structure (channel isolation material) 58: Sacrificial Material (DOI) 62, 62L, 62U: Source / Drain Region 66: Contact Etching Stop Layer (First CESL) 68: First ILD 70:CESL 72:ILD 78: Gate Dielectric 80, 80L, 80U: Gate electrode 84: Dummy gate 86: Mask 90, 90U, 90L: Gate stacking (gate structure) 92, 92L: Gate shield 94: Metal-Semiconductor Alloy Region 96, 96U: Source / Drain Contacts 104:ESL 106: Third ILD 108: Gate Contact 110: Source / Drain Through-hole 112: Device Layer 114: Front-side interconnect structure 116: Dielectric layer 118: Electrical conductivity characteristics 120:ILD 122:CESL A-A': Cross-section B-B': Cross section

[0078] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device comprising: a multilayer stack including: a first complex nanostructure; a second complex nanostructure above the first complex nanostructure; a first channel isolation structure; and a second channel isolation structure above the second complex nanostructure; a plurality of first source / drain regions on a plurality of opposite endpoints of the first complex nanostructure; a plurality of second source / drain regions above the first source / drain regions on a plurality of opposite endpoints of the second complex nanostructure; a first gate structure surrounding the first complex nanostructure, wherein the first gate structure contacts a first lateral surface of the first channel isolation structure; and a second gate structure surrounding the second complex nanostructure.

2. The semiconductor device as claimed in claim 1, wherein the first channel isolation structure is disposed below the first complex nanostructure.

3. The semiconductor device as claimed in claim 2, further comprising: an interlayer dielectric (ILD) located below the first source / drain regions, wherein the interlayer dielectric extends along a plurality of sidewalls of the first channel isolation structure.

4. The semiconductor device as claimed in claim 1, wherein the first channel isolation structure is disposed between the first complex nanostructure and the second complex nanostructure.

5. A semiconductor device comprising: a first complex nanostructure; a second complex nanostructure located above the first complex nanostructure; a channel isolation structure located between the first complex nanostructure and the second complex nanostructure, wherein the channel isolation structure has a multilayer structure comprising: a first channel isolation material; a second channel isolation material located between an upper portion and a lower portion of the first channel isolation material; and a third channel isolation material located on a plurality of sidewalls of the second channel isolation material; a plurality of first source / drain regions located on a plurality of opposite endpoints of the first complex nanostructure; a plurality of second source / drain regions located above the first source / drain regions, the second source / drain regions located on a plurality of opposite endpoints of the second complex nanostructure; a first gate structure surrounding the first complex nanostructure; and a second gate structure surrounding the second complex nanostructure.

6. The semiconductor device of claim 5, further comprising: a plurality of first inner spacers located between a plurality of sidewalls of the first gate structure and the first source / drain regions; and a plurality of second inner spacers located between a plurality of sidewalls of the second gate structure and the second source / drain regions, wherein the first inner spacers, the second inner spacers, and the third channel isolation material have the same constituent material.

7. The semiconductor element as claimed in claim 6, wherein the second inner spacers overlap with the first channel isolation material, the second channel isolation material and the third channel isolation material.

8. A method of forming a semiconductor device, comprising: forming a multilayer stack comprising: a plurality of lower semiconductor nanostructures stacked alternately with a plurality of first dummy nanostructures; a plurality of upper semiconductor nanostructures stacked alternately with a plurality of second dummy nanostructures; and a third dummy nanostructure located between the lower semiconductor nanostructures and the upper semiconductor nanostructures; patterning a source / drain groove through the multilayer stack; replacing the third dummy nanostructure with one or more channel isolation materials; after replacing the third dummy nanostructure with one or more channel isolation materials, forming a plurality of recessed sidewalls of the first dummy nanostructures and the second dummy nanostructures; and forming a plurality of inner spacers located on the plurality of recessed sidewalls of the first dummy nanostructures and the second dummy nanostructures. A first source / drain region and a second source / drain region are formed in the source / drain groove, the first source / drain region being adjacent to the lower semiconductor nanostructures and the second source / drain region being adjacent to the upper semiconductor nanostructures; the first dummy nanostructures are replaced with a first gate structure; and the second dummy nanostructures are replaced with a second gate structure.

9. The method of claim 8, wherein replacing the third dummy nanostructure with one or more channel isolation materials comprises: removing the third dummy nanostructure to define a gap between the lower semiconductor nanostructures and the upper semiconductor nanostructures; depositing a first channel isolation material layer on a top surface and a bottom surface of the gap; filling a plurality of remaining portions of the gap with a second channel isolation material layer; and removing a plurality of excess portions of the first channel isolation material layer and the second channel isolation material layer disposed outside the gap to define a first channel isolation material and a second channel isolation material.

10. The method of claim 9, further comprising: recessing one sidewall of the second channel isolation material while recessing a plurality of sidewalls of the first dummy nanostructures and the second dummy nanostructures; and forming a third channel isolation material on a recessed sidewall of the second channel isolation material while forming the inner spacers.

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