Semiconductor devices and methods for manufacturing semiconductor devices

Abstract

The present invention readily forms patterns with a high aspect ratio. A semiconductor device 1 according to an embodiment includes: a first structure; a first columnar body extending in the first structure along a first direction; a second structure; a second columnar body extending in the second structure along the first direction; and a bonding surface disposed between the first structure and the second structure; wherein the first columnar body and the second columnar body are connected in the first direction within the bonding surface.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Prior Technology

[0002] As the aspect ratio increases, there is a tendency for patterns to be difficult to form. As a result, the yield of semiconductor devices may decrease. Summary of the Invention

[0003] One embodiment aims to provide a semiconductor device capable of easily forming patterns with high aspect ratios and a method for manufacturing the semiconductor device.

[0004] The semiconductor device of the embodiment includes: a first structure; a first column extending in the first structure along a first direction; a second structure; a second column extending in the second structure along the first direction; and a bonding surface disposed between the first structure and the second structure; and the first column and the second column are connected in the bonding surface in the first direction. Simple Explanation of the Diagram

[0005] Figures 1A and 1B are schematic diagrams illustrating examples of the configuration of a semiconductor device according to an embodiment. Figures 2A and 2B are cross-sectional views showing a detailed example of the configuration of the memory area in the implementation method. Figures 3A and 3B are diagrams illustrating a detailed configuration example of the stepped area in the implementation method. Figures 4A and 4B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 5A and 5B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 6A and 6B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 7A and 7B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figure 8 is a diagram illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figure 9 is a diagram illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 10A to 10D are diagrams illustrating a portion of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 11A and 11B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 12A and 12B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 13A and 13B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figures 14A and 14B are diagrams illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figure 15 is a diagram illustrating part of the sequence of a semiconductor device manufacturing method according to an embodiment. Figure 16 is a diagram illustrating part of the manufacturing process of the semiconductor device in Example 1. Figures 17A and 17B are diagrams illustrating part of the manufacturing process of the semiconductor device in Variation 1. Figure 18 is a diagram showing the detailed composition of the stepped area in Variation Example 2. Implementation

[0006] Hereinafter, with reference to the drawings, the semiconductor device and the method for manufacturing the semiconductor device according to the embodiments will be described in detail. Furthermore, the present invention is not limited to these embodiments.

[0007] (Example of a semiconductor device) Figures 1A and 1B are schematic diagrams illustrating a schematic configuration example of the semiconductor device 1 according to the embodiment. Figure 1A shows a cross-section of the semiconductor device 1 along the X direction. In Figure 1A, the shaded lines are omitted for ease of observation.

[0008] Furthermore, in this specification, the direction along the orientation of the faces of the plurality of character lines WL is defined as the X direction and the Y direction, which are orthogonal to each other. Also, sometimes the electrical lead-out direction of the character lines WL is referred to as the second direction, which is the direction along the X direction. Also, the direction intersecting the X and Y directions, i.e., the direction intersecting the orientation of the faces of the plurality of character lines WL, is defined as the Z direction. The Z direction is an example of the first direction. Furthermore, in the extension direction of the contact CC, the connection end of the contact CC to the character line WL is defined as the lower side of the semiconductor device 1, and the opposite side is defined as the upper side.

[0009] As shown in Figure 1A, the semiconductor device 1 sequentially comprises an electrode film EL, a source line SL, and a stacked body LM formed by stacking a plurality of character lines WL, starting from the bottom side of the paper. Furthermore, the semiconductor device 1 has a peripheral circuit CBA disposed on the semiconductor substrate SB above the stacked body LM.

[0010] On the electrode film EL, a source electrode line SL is disposed with an insulating layer 60 in between. The source electrode line SL is, for example, a polycrystalline silicon layer.

[0011] A plurality of plugs PG are disposed in the insulating layer 60, and the source line SL and the electrode film EL are electrically connected through the plugs PG. In this way, a source potential can be applied to the source line SL from outside the semiconductor device 1 through the electrode film EL and the plugs PG.

[0012] As shown in Figures 1A and 1B, a stacked body LM, composed of multiple word lines WL, is disposed on the source line SL. A memory region MR is disposed in the center of the stacked body LM, and stepped regions ER are disposed at both ends of the stacked body LM. The memory region MR and the stepped regions ER are divided into multiple regions by multiple plate-shaped contacts LI, which extend through the stacked body LM in the X direction.

[0013] A plurality of pillars PL are disposed in the memory region MR, and the plurality of pillars PL extend through the word line WL in the stacking direction. The lower ends of the pillars PL reach the source line SL. A plurality of memory cells are formed at the intersection of the pillars PL and the word line WL. In this way, the semiconductor device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells are disposed in three dimensions in the memory region MR.

[0014] The stepped area ER is equipped with a plurality of contacts CC that are connected to a plurality of character lines WL respectively.

[0015] Write and read voltages are applied to the memory cells contained in the memory region MR in the central part of the multilayer stack LM via contact CC and word lines WL at the same height as the memory cells. In this way, the word lines WL of the multilayer stack are brought out separately through these contacts CC.

[0016] Multiple character lines WL, posts PL, and contacts CC are covered by an insulating layer 50. The insulating layer 50 also extends around the multiple character lines WL.

[0017] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuitry CBA, including transistors TR and wiring, is disposed on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuitry CBA, which is electrically connected to the contacts CC. Thus, the peripheral circuitry CBA controls the electrical operation of the memory cell.

[0018] The peripheral circuit CBA is covered by an insulating layer 40. The semiconductor device 1 is formed by bonding the insulating layer 40 with the insulating layer 50 covering the stacked body LM. The semiconductor device 1 is composed of a plurality of character lines WL, pillars PL and contacts CC, as well as the peripheral circuit CBA.

[0019] Next, a detailed configuration example of the semiconductor device 1 will be described using Figures 2A to 3B. Figures 2A and 2B are cross-sectional views showing a detailed configuration example of the memory region MR in the embodiment.

[0020] Figure 2A is a cross-sectional view of the memory region MR of semiconductor device 1 along the Y direction. In Figure 2A, the structures above insulating layer 52 and below insulating layer 60 are omitted. Figure 2B is an enlarged cross-sectional view of the pillar PL at the height of the bonding surface SP1.

[0021] As shown in Figure 2A, the laminate LM is constructed by sequentially bonding laminates LM1, LM2, and LM3 from bottom to top. Therefore, the laminate LM has a bonding surface SP1 between laminates LM1 and LM2, and a bonding surface SP2 between laminates LM2 and LM3. The laminate LM3 is sequentially covered by insulating layers 51 and 52. Insulating layers 51 and 52 constitute a portion of the insulating layer 50 in Figure 1.

[0022] The stacked body LM1 is constructed by alternating layers of a plurality of character lines WL1 and a plurality of insulating layers OL1. The topmost layer of the stacked body LM1 is, for example, the insulating layer OL1. Furthermore, the stacked body LM1 is an example of a first structure and a first stacked body. Also, the character lines WL1 are an example of a first conductive layer, and the insulating layer OL1 is an example of a first insulating layer.

[0023] A plurality of pillars PL1 and plate-like portions LI1 are formed in the laminate LM1.

[0024] A plurality of pillars PL1 have a generally cylindrical shape extending along the Z direction within the laminate LM1. These pillars PL1 may, for example, have a tapered shape with a diameter decreasing from the upper end to the lower end. The lower end of the plurality of pillars PL1 reaches the source line SL, and the upper end reaches the bonding surface SP1. The plurality of pillars PL1 sequentially have a core layer CR1, a channel layer CN1 serving as the first semiconductor layer, and a memory film ME1 from the center outwards. The pillars PL1 are an example of a first pillar-shaped body and a first pillar.

[0025] The plate-shaped portion LI1 is formed as a plate extending along the XZ direction within the laminate LM1. The lower end of the plate-shaped portion LI1 reaches the source line SL, and the upper end reaches the bonding surface SP1. A conductive portion EC1 and a pad layer LL1 are sequentially disposed in the plate-shaped portion LI1, starting from the inside. The plate-shaped portion LI1 is an example of the first plate-shaped portion.

[0026] The laminate LM2 is bonded to the laminate LM1 via the bonding surface SP1. The laminate LM2 is constructed by alternating layers of multiple character lines WL2 and multiple insulating layers OL2. The bottom layer of the laminate LM2 is the insulating layer OL2. Therefore, the bottom insulating layer OL2 of the laminate LM2 and the top insulating layer OL1 of the laminate LM1 are directly bonded via the bonding surface SP1. Furthermore, the top layer of the laminate LM2 is the insulating layer OL2. Moreover, the laminate LM2 is an example of a second structure and a second laminate. Also, the character lines WL2 are an example of a second conductive layer, and the insulating layer OL2 is an example of a second insulating layer.

[0027] A plurality of pillars PL2 and plate-like portions LI2 are formed in the laminate LM2.

[0028] A plurality of pillars PL2 extend along the Z direction within the laminate LM2. The lower ends of the plurality of pillars PL2 are connected in the Z direction to the upper ends of the plurality of pillars PL1 in the mating surface SP1, and the upper ends of the plurality of pillars PL2 reach the mating surface SP2.

[0029] More specifically, as shown in Figure 2B, each column PL2 has: an extension PE1 that extends in the Z direction from the mating surface SP2 to a predetermined depth of the laminate LM2; and a joint PJ1 that extends from the predetermined depth to the mating surface SP1. The joint PJ1 is connected to the lower end of the extension PE1 by a surface SE1, which serves as a first surface, and to the upper end of the column PL1 by a surface SE2, which serves as a second surface.

[0030] The joint PJ1 is formed into a generally cylindrical shape with a diameter D2. The extension PE1 is also formed into a generally cylindrical, tapered shape with its diameter decreasing from the upper end to the lower end. That is, the diameter D1 of the lower end of the extension PE1 is smaller than the diameter D3 of the upper end of the extension PE1. Furthermore, the diameter D2 of the joint PJ1 is greater than or equal to the diameter D1 of the lower end of the extension PE2, and less than or equal to the diameter D3 of the upper end of the extension PE2. The upper end of the extension PE2 is one example of the other end.

[0031] Each pillar PL2 has a core layer CR2, a channel layer CN2 serving as the second semiconductor layer, and a memory film ME2, starting from its center. The core layer CR2, the channel layer CN2, and the memory film ME2 are respectively connected to the core layer CR1, the channel layer CN1, and the memory film ME1 of pillar PL1 in the bonding surface SP1. Pillar PL2 is an example of a second pillar and a second column.

[0032] The plate-shaped portion LI2 is formed as a plate extending along the XZ direction within the laminate LM2. The lower end of the plate-shaped portion LI2 is connected to the plate-shaped portion LI1 in the Z direction at the bonding surface SP1, and the upper end reaches the bonding surface SP2. A conductive portion EC2 and a padding layer LL2 are disposed on the plate-shaped portion LI2 from the inside. The lower end of the conductive portion EC2 is connected to the conductive portion EC1 of the plate-shaped portion LI1 in the bonding surface SP1. The plate-shaped portion LI2 is an example of a second plate-shaped portion.

[0033] A multilayer assembly LM3 is bonded to the upper surface of the multilayer assembly LM2 via a bonding surface SP2. The multilayer assembly LM3 is constructed by alternating layers of multiple character lines WL3 and multiple insulating layers OL3. The bottom layer of the multilayer assembly LM3 is the insulating layer OL3. Therefore, the top insulating layer OL2 of the multilayer assembly LM2 and the bottom insulating layer OL3 of the multilayer assembly LM3 are directly bonded via the bonding surface SP2.

[0034] Furthermore, the aforementioned character lines WL1~WL3 are, for example, tungsten or molybdenum layers, and the insulating layers OL1~OL3 are, for example, silicon oxide layers.

[0035] A plurality of pillars PL3 and plate-like portions LI3 are formed in the laminate LM3.

[0036] A plurality of pillars PL3 extend along the Z direction within the laminate LM3. The lower ends of each of the plurality of pillars PL3 are connected to the plurality of pillars PL2 in the bonding surface SP2 in the Z direction, and the upper ends of each of the plurality of pillars PL3 penetrate the uppermost insulating layer OL3 of the laminate LM3, reaching the insulating layer 51.

[0037] Furthermore, each of the plurality of pillars PL3 also has: an extension PE2 that extends from the insulating layer 52 to a predetermined depth of the laminate LM3 in the Z direction; and a bonding portion PJ2 that extends from the predetermined depth of the laminate LM3 to the mating surface SP2. Since the bonding portion PJ2 and the extension PE2 have configurations corresponding to those of the bonding portion PJ1 and the extension PE2, their description is omitted here.

[0038] Each of the plurality of pillars PL3 has a core layer CR3, a channel layer CN3, a memory membrane ME3 starting from the center, and a capping layer CP above the core layer CR3. The core layer CR3, the channel layer CN3, and the memory membrane ME3 are respectively connected to the core layer CR2, the channel layer CN2, and the memory membrane ME2 of the pillar PL2 in the bonding surface SP2.

[0039] The capping layer CP is connected to the bit line BL disposed in the insulating layer 52 via the plug CH disposed in the insulating layers 51 and 52. The bit line BL is connected to the transistor TR (Fig. 1A) via the upper wiring and via (not shown).

[0040] Furthermore, the aforementioned core layers CR1-CR3 are, for example, silicon oxide, and the channel layers CN1-CN3 and capping layer CP are, for example, polycrystalline silicon layers or amorphous silicon layers, or other semiconductor layers. Also, the memory films ME1-ME3 have, in a direction extending outward from the center of each pillar PL1-PL3, a tunnel insulating layer (not shown), a charge storage layer, and a barrier insulating layer, arranged sequentially (not shown). The tunnel insulating layer and the barrier insulating layer are, for example, silicon oxide layers, and the charge storage layer is, for example, a silicon nitride layer.

[0041] The plate-shaped portion LI3 is formed as a plate extending along the XZ direction within the laminate LM3. The lower end of the plate-shaped portion LI3 is connected to the plate-shaped portion LI2 in the Z direction at the bonding surface SP2, and the upper end reaches the insulating layer 52. Furthermore, a conductive portion EC3 and a padding layer LL3 are also disposed on the plate-shaped portion LI3 from the inside. The lower end of the conductive portion EC3 is connected to the conductive portion EC2 of the plate-shaped portion LI2 in the bonding surface SP2.

[0042] Furthermore, the aforementioned pad layers LL1 to LL3 are, for example, silicon oxide layers. Also, the conductive parts EC1 to EC3, which are conductive materials, are, for example, tungsten layers, tungsten nitride layers, titanium layers, titanium nitride layers, molybdenum layers, or molybdenum nitride layers.

[0043] The column PL is formed by connecting the columns PL1 to PL3 described above to each other, and the plate-shaped contact LI is formed by connecting the plate-shaped parts LI1 to LI3 to each other.

[0044] Figures 3A and 3B are detailed examples of the structure of the stepped region ER in the implementation method.

[0045] Figure 3A is a cross-sectional view of the stepped region ER of semiconductor device 1 along the X direction. In Figure 3A, the structures above insulating layer 52 and below insulating layer 60 are omitted. Figure 3B is an enlarged cross-sectional view of the contact CC at the height position of the bonding surface SP1.

[0046] As shown in Figure 3A, a stepped portion SR1 and a contact point CC1 are formed at the end of the laminate LM1 in the X direction.

[0047] A stepped portion SR1 is formed by machining a plurality of character lines WL1 of the laminate LM1 into a stepped shape extending in the X direction. The stepped portion SR1 is covered by an insulating layer 53 up to the height of the uppermost insulating layer OL1, i.e., the height of the bonding surface SP1. The insulating layer 53 is, for example, a silicon oxide layer, and together with insulating layers 51 and 52, constitutes a part of the insulating layer 50 in FIG. 1. Insulating layer 53 is an example of a third insulating layer. The stepped portion SR1 is an example of a first stepped portion.

[0048] Contact CC1 extends along the Z direction within insulating layer 53. The lower end of contact CC1 is connected to the character lines WL1 of each step constituting stepped portion SR1, and the upper end reaches the mating surface SP1. Contact CC1 has a conductive layer EL1 and an insulating layer LE1 from the inside to the outside. Contact CC1 is an example of the first columnar body and the first contact.

[0049] More specifically, as shown in Figure 3B, contact CC1 has: a bonding portion CJ1 extending in the Z direction from the mating surface SP1 to a predetermined depth of the insulating layer 53; and an extension portion CE1 extending from the predetermined depth to each character line WL1. The bonding portion CJ1 is connected to the upper end of the extension portion CE1 via a surface SJ1, which serves as a third surface, and is connected to the lower end of contact CC2 via a surface SJ2, which serves as a fourth surface. The diameter D4 of the conductive layer EL1 formed in the bonding portion CJ1 is greater than or equal to the diameter D5 of the lower end of the conductive layer EL2 of contact CC2.

[0050] A stepped portion SR2 and a contact point CC2 are formed at the end of the laminate LM2 in the X direction.

[0051] Stepped section SR2 is formed by machining multiple character lines WL2 of the laminate LM2 into a stepped shape extending in the X direction. The lowest step surface TRb of each step in stepped section SR2 is located further towards the rising step than the uppermost step surface TRa of stepped section SR1. That is, stepped sections SR1 and SR2 form a continuous stepped shape in the X direction. Stepped section SR2 is an example of a second stepped section.

[0052] The stepped portion SR2 and the bonding surface SP1 are covered by the insulating layer 54 up to the height of the uppermost insulating layer OL2, which is also the height of the bonding surface SP2. The insulating layer 54 is, for example, a silicon oxide layer, and together with the aforementioned insulating layer 53, constitutes a part of the insulating layer 50 in Figure 1. The insulating layer 54 is an example of the fourth insulating layer.

[0053] Contact CC2 extends along the Z direction within the insulating layer 54. A portion of contact CC2 has its lower end connected to the character lines WL2 constituting each step of the stepped portion SR2, and its upper end reaches the mating surface SP2. Furthermore, the lower end of the remaining portion of contact CC2 is connected to contact CC1 in the mating surface SP1 along the Z direction, and its upper end reaches the mating surface SP2. Contact CC2 is an example of the second columnar body and the second contact.

[0054] Contact CC2 has a conductive layer EL2 and an insulating layer LE2 starting from the inside. The conductive layer EL2 is connected to the conductive layer EL1 in the bonding surface SP1.

[0055] Furthermore, contact CC2 also has: a bonding portion CJ2, which extends in the Z direction from the mating surface SP2 to a predetermined depth of the insulating layer 54; and an extension portion CE2, which extends from the predetermined depth of the insulating layer 54 to the mating surface SP1. Since the bonding portion CJ2 and the extension portion CE2 have configurations corresponding to the bonding portion CJ1 and the extension portion CE1, their description is omitted here.

[0056] A stepped portion SR3 and a contact point CC3 are formed at the end of the laminate LM3 in the X direction.

[0057] The stepped section SR3 is formed by machining multiple character lines WL3 of the laminate LM3 into a stepped shape extending in the X direction. The lowermost stepped surface TRd of the stepped section SR3 is located further to the rising step side than the uppermost stepped surface TRc of the stepped section SR2. That is, the stepped sections SR2 and SR3 form a continuous stepped shape in the X direction.

[0058] The stepped portion SR3 and the bonding surface SP2 are covered by an insulating layer 55 up to the height of the uppermost insulating layer OL3. The insulating layer 55 is, for example, a silicon oxide layer, and together with the aforementioned insulating layers 53 and 54, constitutes a part of the insulating layer 50 in FIG1. ​​Thus, insulating layers 53-55 are made of the same material, for example, and therefore these insulating layers 53-55 are essentially a single unit.

[0059] Contact CC3 extends along the Z direction within insulating layer 55. The lower end of a portion of contact CC3 is connected to the character lines WL3 constituting each step of the stepped portion SR3, and the upper end penetrates insulating layer 51 to reach insulating layer 52. Furthermore, the lower end of the remaining portion of contact CC3 is connected to contact CC2 in the mating surface SP2, and the upper end penetrates insulating layer 51 to reach insulating layer 52.

[0060] Contact CC3 has a conductive layer EL3 and an insulating layer LE3 starting from the inside. The conductive layer EL3 is connected to the conductive layer EL2 of contact CC2 in the bonding surface SP2.

[0061] The conductive layer EL3 is connected to the upper layer wiring MX via the plug CH disposed in the insulating layer 52. In this way, the character lines WL1 to WL3 of each layer are electrically led out via contacts CC1 to CC3.

[0062] Contact CC is formed by connecting the contacts CC1 to CC3 described above to each other.

[0063] Furthermore, Figures 2 and 3 illustrate suitable number of layers for illustration as stacks LM1 to LM3, but the number of layers in stacks LM1 to LM3 is not limited to the examples shown. In each stack LM1 to LM3, a plurality of character lines and a plurality of insulating layers may be stacked, for example, more than 100 layers.

[0064] Furthermore, when the aspect ratio is obtained by dividing the height of the column PL and the contact CC in the Z direction by the diameter of the portion with the largest diameter, such as the upper end of each, the aspect ratio of the column PL and the contact CC in this embodiment is, for example, 25 or more and 100 or less, and more preferably 50 or more and 100 or less.

[0065] (Manufacturing method of semiconductor devices) Figures 4A to 15 are diagrams illustrating part of the manufacturing process of the semiconductor device 1 according to an embodiment.

[0066] The manufacturing steps of the semiconductor device 1 include at least: a first step, in which a multilayer LM1 is formed on a substrate SB1; a second step, in which a multilayer LM2 is formed on a substrate SB2; a third step, in which a multilayer LM3 is formed on a substrate SB3; and a bonding step, in which substrates SB1 to SB3 are bonded together respectively.

[0067] Furthermore, step 1 includes at least the steps of forming the aforementioned pillar PL1, contact CC1, and plate-shaped portion LI1; step 2 includes at least the steps of forming the pillar PL2, contact CC2, and plate-shaped portion LI2; and step 3 includes at least the steps of forming the pillar PL3, contact CC3, and plate-shaped portion LI3. Moreover, steps 1 to 3 each include an inspection step to check the shape of the formed pattern.

[0068] The process of step 1 is explained using Figures 4A to 9.

[0069] First, Figures 4A and 4B show the formation of the portion on substrate SB1 that will subsequently become the stepped portion SR1 and the pillar PL1. Figure 4A shows a cross-section along the X direction of the portion of substrate SB1 that will subsequently become the stepped region ER, and Figure 4B shows a cross-section along the Y direction of the portion of substrate SB1 that will subsequently become the memory region MR.

[0070] As shown in Figure 4A, an insulating layer 60 and a source line SL are formed on a substrate SB1, such as a silicon substrate. A multilayer structure LMs1 is formed by alternately depositing a plurality of insulating layers OL1 and a plurality of sacrificial layers NL1 on the source line SL. The substrate SB1 is an example of a first substrate.

[0071] The sacrificial layer NL1 is, for example, a silicon nitride layer. The sacrificial layer NL1 functions as a sacrificial layer that will subsequently be replaced by the character line WL1. The sacrificial layer NL1 is an example of a second insulating layer.

[0072] Subsequently, a stepped portion SR1 is fabricated in a portion of the laminate LMs1 through a series of steps: forming a mask using photoresist, etching using the mask, refining the mask, and etching using the refined mask. At this point, the stepped portion SR1 is formed such that each step of the stepped portion SR1 is positioned between positions P1 and P2. Position P1 is located in the X direction at a distance L1 from a predetermined reference point P0 of the laminate LMs1, and position P2 is located in the X direction at a distance L2 from the predetermined reference point P0 of the laminate LMs1. Position P2 is closer to the reference point P0 than position P1. Therefore, each step of the stepped portion SR1 continuously ascends from position P1 to position P2.

[0073] Subsequently, an insulating layer 53 is formed, covering the stepped section SR1 and reaching the height of the uppermost insulating layer OL1.

[0074] As shown in Figure 4B, an insulating layer 60, a source line SL, and a stacked body LMs1 are also formed on the substrate SB1 in the region that will subsequently become the memory region MR. A plurality of memory vias MHA1 are formed, which penetrate the stacked body LMs1 in the Z direction and reach the source line SL. The memory vias MHA1 are configured to form pillars PL1.

[0075] Here, the plurality of exposure areas (shots) SH on the substrate SB1 will be described. Figure 5A is a top view showing the state of the exposure areas formed on the substrate SB1. Figure 5B is an example of the inspection results of the memory vias MHA1 formed in each exposure area.

[0076] As shown in Figure 5A, the area of ​​substrate SB1 excluding the outermost periphery is the component area DA where the semiconductor device 1 will be disposed. The component area DA is divided into a plurality of exposure areas SH1 to SHn (n is an integer greater than or equal to 1) by a plurality of intersecting dividing lines DL. Each of these exposure areas SH becomes an element of a processing unit in the manufacturing process of the semiconductor device 1.

[0077] In the steps of Figures 4A and 4B above, at least one stacked layer LMs1 is formed in each of the exposure areas SH1 to SHn. That is, at least n stacked layers LMs1 are formed on the substrate SB1, and a plurality of memory vias MHA1 are formed in each of the n stacked layers LMs1. In the final stage of the manufacturing process of the semiconductor device 1, these n stacked layers LMs1 are monolithized along a plurality of dividing lines DL and are cut into wafers, each of which carries the semiconductor device 1. Therefore, the example in Figure 5 shows a case where the exposure area SH and the wafer to be monolithized have approximately the same area. A wafer of one semiconductor device 1 may also contain a plurality of stacked layers LM1, etc.

[0078] In the inspection step of memory hole MHA1, the substrate SB1 is first moved into the inspection device. As an inspection device, for example, a length measuring SEM (CD-SEM: Critical Dimension Scanning Electron Microscope) is used.

[0079] Length measurement SEM acquires image data of multiple memory holes (MHA1) formed on substrate SB1, analyzes the acquired image data, and measures the size of each memory hole (MHA1). For example, based on the size deviation of the multiple memory holes (MHA1), length measurement SEM determines whether the memory hole (MHA1) is formed normally for each exposed area.

[0080] For example, if the dimensional deviation of multiple memory apertures MHA1 exceeds a specified threshold, it is determined that the memory apertures MHA1 have not formed properly in their exposed areas (unqualified), such as not penetrating the stacked body LMs1. If the memory apertures MHA1 are not formed properly, the pillars PL1 may not be formed properly in subsequent steps. As a result, the memory cells may not function properly. On the other hand, if the dimensional deviation of multiple memory apertures MHA1 is below the specified threshold, it is determined that the memory apertures MHA1 have formed properly in their exposed areas (qualified).

[0081] As shown in Figure 5B, the length measurement SEM output establishes a correspondence between the judgment result and the exposure area number. The substrate SB1 is then removed from the inspection device, and the inspection process ends.

[0082] Furthermore, the aforementioned determination process based on the measurement results of the memory hole MHA1 can also be performed in an information processing device different from the length measurement SEM. Moreover, such devices can also be operated by an operator.

[0083] Subsequently, Figures 6A and 6B show the formation of a plurality of pillars PL1 and plate-shaped portions LI1 on the substrate SB1 after the inspection process. Figures 6A and 6B show cross-sections along the Y direction of the portion of the substrate SB1 that will subsequently become the memory region MR.

[0084] As shown in Figure 6A, a memory film ME1 and a channel layer CN1 are sequentially formed inside the memory hole MHA1. Furthermore, before forming the channel layer CN1, the memory film ME1 on the bottom surface of the memory hole MHA1 is removed. This allows the channel layer CN1 to connect to the source line SL on its bottom surface. The core layer CR1 is then filled into the voids remaining inside the channel layer CN1. Through these operations, a plurality of pillars PL1 are formed.

[0085] Subsequently, a slit STA1 is formed that penetrates the stacked body LMs1 and reaches the source line SL. Slit STA1 also extends in the stacked body LMs1 along the X-direction. Slit STA1 is the part that will become the plate-like portion LI1.

[0086] Subsequently, in Figure 6B, character lines WL1 are formed in the portion where the sacrificial layer NL1 of the stacked volume LMs1 is located, thus forming the stacked volume LM1.

[0087] Specifically, firstly, the sacrificial layer NL1 is removed via wet etching through slit STA1. This removes the sacrificial layer NL1 exposed on the side of slit STA1 in both the X and Y directions, creating a space (not shown) between insulating layers OL1. This space extends in the XY plane and is arranged in layers in the Z direction. Next, a conductive gas such as tungsten or molybdenum is injected into the space between the insulating layers OL1 through slit STA1. This replaces the sacrificial layer NL1 with word lines WL1, forming a stacked product LM1. The subsequent process of forming word lines at the locations where the sacrificial layer was previously present is sometimes referred to as a replacement process.

[0088] Subsequently, a padding layer LL1 is formed on the sidewall of the slit STA1, and a conductive part EC1 is filled in the padding layer LL1 to form a plate-shaped part LI1.

[0089] Next, the formation of contact CC is shown in Figures 7A-8. Figures 7A-7B and 8 show a cross-section along the X direction of the portion of substrate SB1 that will subsequently become the stepped region ER.

[0090] As shown in Figure 7A, by means of the replacement process described in Figure 6B, a plurality of character lines WL1 are also formed in the stepped section SR1.

[0091] A plurality of contact holes HLc are formed, penetrating the insulating layer 53 and reaching each character line WL1. The contact holes HLc will subsequently become part of the contact CC1.

[0092] Next, a photoresist film RF is coated on the laminate LM1 and the insulating layer 53. Through exposure and development, the photoresist film RF is opened so that it is exposed above the contact hole HLc. Furthermore, the opening OP is made larger than the diameter of the contact hole HLc. Then, using the photoresist film RF as a mask, dry etching is performed to a depth that does not penetrate the insulating layer 53. This forms the opening OP at the upper end of the contact CC1. The opening OP will subsequently become the junction CJ1.

[0093] Therefore, in the subsequent bonding step, when the joint SJ1 of contact CC1 is connected to the lower end of contact CC2, it can be ensured that the allowable range of positional offset of contact CC2 relative to the upper end of contact CC1 is larger. As a result, contact CC1 and contact CC2 can be connected more reliably.

[0094] After removing the photoresist film RF, as shown in Figure 8, the conductive layer EL1 is filled into the insulating layer LE1 covering the sidewalls of the plurality of contact holes HLC, and into the gaps of the contact holes HLC retained inside the insulating layer LE1. Through the above operations, the contact CC1 is formed.

[0095] Then, Figure 9 shows the process of monolithizing the substrate SB1 into multiple wafers for each stacked layer LM1 and selecting qualified wafers from the multiple wafers.

[0096] As shown in Figure 9, the substrate SB1 is cut along the dividing line DL in the Z direction. This forms wafers CPL1 to CPLn. As described above, in this embodiment, wafers CPL1 to CPLn each correspond to exposure areas SH1 to SHn.

[0097] Based on the inspection results of the memory hole MHA1 output during the inspection steps described in Figures 5A and 5B, wafers containing "qualified" exposure areas are selected from wafers CPL1 to CPLn. For example, in the case of Figure 9, wafers other than wafer CPL3 are qualified wafers. The selected qualified wafers are then bonded to other wafers in the bonding step described later. With the above operations, step 1 is completed.

[0098] Next, the process of step 2 will be explained using Figures 10A to 12B.

[0099] First, Figures 10 and 11 show the formation of the portion on substrate SB2 that will subsequently become pillar PL2. Figures 10A-10D, 11A, and 11B show cross-sections along the X direction of the portion of substrate SB2 that will subsequently become the stepped region ER.

[0100] As shown in Figure 10A, a laminate LMs21 is formed by alternately depositing a predetermined number of insulating layers OL2 and sacrificial layers NL2 on a substrate SB2, such as a silicon substrate. The sacrificial layer NL2 is, for example, a silicon nitride layer. The sacrificial layer NL2 functions as a sacrificial layer that will subsequently be replaced by a character line WL2. The sacrificial layer NL2 is an example of a third insulating layer. The substrate SB2 is an example of a second substrate.

[0101] As shown in Figure 10B, a plurality of holes MHA21 are formed, which penetrate the laminate LMs21 in the Z direction and reach the substrate SB2. Holes MHA21 will subsequently become part of the bonding portion PJ1. The plurality of holes MHA21 have a diameter D2.

[0102] As shown in Figure 10C, for example, a CVD carbon layer is embedded in a hole MHA21, and an insulating layer OL2 and a sacrificial layer NL2 are further deposited on top of the laminate LMs21 and the CVD carbon layer. In this way, the laminate LMs2 is formed.

[0103] Subsequently, as shown in Figure 10D, a hole MHA22 is formed above hole MHA21. Hole MHA22 penetrates the insulating layer OL2 and the sacrificial layer NL2 in the Z direction, reaching the CVD carbon layer embedded in hole MHA21. Hole MHA22 will subsequently become part of the extension PE2. The upper end of hole MHA22 has a diameter D3, and the lower end has a diameter D1 smaller than D3. That is, hole MHA22 is a tapered shape with a diameter decreasing from the upper end to the lower end.

[0104] Here, the diameter D2 of hole MHA21 is larger than the diameter D1 of the lower end of hole MHA22. Therefore, in the subsequent bonding step, when the joint PJ1 of post PL2 is connected to the upper end of post PL1, a larger allowable range of positional offset of post PL2 relative to the upper end of post PL1 can be ensured. As a result, post PL1 and post PL2 can be connected more reliably.

[0105] Furthermore, the diameter D2 of hole MHA21 is less than or equal to the diameter D3 of the upper end of hole MHA22. That is, when viewed from the Z direction, the cross-sectional area of ​​joint PJ1 does not exceed the cross-sectional area of ​​the upper end of column PL2. Therefore, it is possible to avoid a decrease in the arrangement density of columns PL2 due to the formation of joint PJ1. In addition, it is possible to suppress interference between adjacent columns PL2 in joint PJ1.

[0106] As shown in Figure 11A, the CVD carbon layer embedded in the pore MHA21 is removed by ashing and other methods. This forms the memory pore MHA2.

[0107] Next, the substrate SB2 is moved into the inspection device to inspect the shape of the plurality of memory holes MHA2 formed on the substrate SB2.

[0108] Although the illustrations are omitted, the unshown component area of ​​substrate SB2 is also divided into n exposure areas corresponding to exposure areas SH1~SHn. Through the processing described in Figures 10A~11A, a multilayer LMs2 and a plurality of memory vias MHA2 are formed in each of the plurality of exposure areas.

[0109] Using the methods illustrated in Figures 5A and 5B, it is determined whether the memory via MHA2 is formed correctly for each exposed area. An inspection result is output, establishing a correspondence between the determination result and the exposed area number. After removing the substrate SB2 from the inspection device, the inspection process ends.

[0110] Subsequently, as shown in Figure 11B, a memory film ME2, a channel layer CN2, and a core layer CR2 are sequentially formed inside the memory hole MHA2 of the substrate SB2, which has undergone the inspection step. At this time, before forming the channel layer CN2, the memory film ME2 on the bottom surface of the memory hole MHA2 is removed, so that the channel layer CN2 is in contact with the substrate SB2. This allows the channel layer CN2 to be connected to the channel layer CN1 of the pillar PL1 when subsequently connected to the stacked body LM1. Through the above operations, a plurality of pillars PL2, each containing a junction portion PJ1 and an extension portion PE1, are formed.

[0111] Subsequently, a slit (not shown) is formed that extends through the laminate LMs2 and reaches the substrate SB2. Through a replacement process, a character line WL2 is formed at the location of the sacrificial layer NL2 of the laminate LMs2, thus forming the laminate LM2. A pad layer LL2 and a conductive portion EC2 are formed within the slit. Through these operations, a plate-like portion LI2 is formed.

[0112] Next, Figure 12 shows the formation of contact CC2. Figures 12A and 12B show cross-sections along the X direction of the portion of substrate SB2 that will subsequently become the stepped region ER.

[0113] In the area of ​​substrate SB2 that will subsequently become the stepped region ER, a multilayer LMs2 is formed by the process shown in Figures 10A-10C. Furthermore, although detailed descriptions are omitted, a stepped portion SR2 is formed by the process corresponding to the stepped portion SR1. Next, an insulating layer 54 is formed on substrate SB2 and the stepped portion SR2, reaching the height of the uppermost insulating layer OL2. Then, by the replacement process shown in Figure 11B, a plurality of character lines WL2 as shown in Figure 12A are formed.

[0114] When forming the stepped portion SR2, the stepped surfaces of the stepped portion SR2 are arranged between positions P2 and P3. Position P2 is located in the X direction at a distance L2 from a predetermined reference point P0 of the laminate LMs2, and position P3 is located in the X direction at a distance L3 from the predetermined reference point P0 of the laminate LMs2. Reference point P0 is defined such that the positions on each substrate SB1 and SB2 coincide with the reference point P0 set for the laminate LMs1 in the processing shown in Figure 4A. The distance L2 from position P2 to reference point P0 coincides with the position P2 set for the laminate LMs1. Position P3 is closer to reference point P0 than position P2. Therefore, each step of the stepped portion SR2 continuously rises from position P2 to position P3. Therefore, when laminates LM1 and LM2 are subsequently bonded together with their respective reference points P0 overlapping vertically, the stepped portion SR1 and the stepped portion SR2 become a continuous stepped shape in the X direction.

[0115] Subsequently, after processing corresponding to the processing shown in Figures 7A, 7B and 8, the contact CC2 shown in Figure 12B is formed.

[0116] Next, after grinding the substrate SB2 until the bottom insulating layer OL2 is exposed from below, it is cut along the dividing line in the Z direction. In this way, n wafers are formed.

[0117] Next, based on the inspection results of the memory hole MHA2 output in the inspection step of Figure 11A, wafers containing "qualified" exposure areas are selected from n wafers. The selected qualified wafers are then bonded to other wafers in the bonding step, which will be described later. With the above operations, step 2 is completed.

[0118] Next, the process of step 3 will be explained using Figures 13A to 14B.

[0119] First, Figure 13A shows the portion formed on substrate SB3 that will subsequently become pillar PL3. Figure 13A shows a cross-section along the X direction of the portion of substrate SB3 that will subsequently become memory region MR.

[0120] Specifically, an insulating layer OL3 and a sacrificial layer NL3 are alternately deposited on a substrate SB3, such as a silicon substrate, to form a multilayer LMs3. The sacrificial layer NL3 is, for example, a silicon nitride layer. The sacrificial layer NL3 functions as a sacrificial layer that will subsequently be replaced by a character line WL3.

[0121] Through the processing corresponding to Figures 10A to 11A, a plurality of memory holes MHA3 are formed. The plurality of memory holes MHA3 penetrate the laminate LMs3 in the Z direction and reach the substrate SB3.

[0122] Furthermore, the plurality of memory holes MHA3 includes hole MHA31, which will subsequently become the junction PJ2, and hole MHA32, which will subsequently become the extension PE2. The method of forming holes MHA31 and MHA32 has been described using Figures 10A to 10D, therefore, its description is omitted here.

[0123] Next, the substrate SB3 is moved into the inspection device to inspect the shape of the plurality of memory holes MHA3 formed on the substrate SB3.

[0124] Although the diagram is omitted, the unshown component area of ​​substrate SB3 is also divided into n exposure areas corresponding to the exposure areas SH1~SHn of substrate SB1. A multilayer LMs3 and a plurality of memory vias MHA3 are formed in the plurality of exposure areas respectively.

[0125] Using the methods illustrated in Figures 5A and 5B, it is determined whether the memory via MHA3 is formed correctly for each exposed area. An inspection result is output, establishing a correspondence between the determination result and the exposed area number. After removing the substrate SB3 from the inspection device, the inspection process ends.

[0126] Subsequently, as shown in Figure 13B, a memory film ME3, a channel layer CN3, and a core layer CR3 are sequentially formed inside the memory via MHA3 of the substrate SB3, which has undergone inspection. A capping layer CP is formed above the core layer CR3. Through the above operations, a plurality of pillars PL3 are formed.

[0127] Subsequently, an insulating layer 51 is formed on the laminate LMs3. A slit (not shown) is formed in the Z direction, penetrating the laminate LMs3 and the insulating layer 51 and reaching the substrate SB3. The laminate LM3 is formed by replacement processing. A pad layer LL3 and a conductive portion EC3 are formed in the slit. Through the above operations, a plate-shaped portion LI3 is formed.

[0128] An insulating layer 52 is formed on the insulating layer 51, and a plug CH is formed in the insulating layer 52 extending in the Z direction and connecting to the capping layer CP and the conductive part EC3. A bit line BL connected to the post PL3 ​​via the plug CH and an upper layer wiring MX connected to the conductive part EC3 via the plug CH are formed.

[0129] Next, Figure 14 shows the formation of contact CC3. Figures 14A and 14B show cross-sections along the X direction of the portion of substrate SB3 that will subsequently become the stepped region ER.

[0130] A multilayer LMs3 is formed in the area of ​​substrate SB3 that will subsequently become the stepped region ER, and a stepped portion SR3 is formed by processing corresponding to stepped portions SR1 and SR2. Subsequently, an insulating layer 55 is formed on substrate SB3 and stepped portion SR3 at a height position reaching the uppermost insulating layer OL3, and by replacement processing, a plurality of character lines WL3 as shown in FIG14A are formed.

[0131] Furthermore, Figure 14A shows the state before the insulating layer 52, plug CH, bit line BL and upper wiring MX are formed using the process described in Figure 13B above.

[0132] When forming the stepped portion SR3, the stepped surface of the stepped portion SR3 is positioned between position P3 and reference point P0. Position P3 is a distance L3 from the designated reference point P0 of the laminate LMs3 in the X direction. Reference point P0 is set at the same position as the reference point P0 set for the laminates LMs1 and LMs2, and position P3 is set at the same position P3 set for the laminate LMs2. Furthermore, each step of the stepped portion SR3 continuously rises from position P3 towards reference point P0. Therefore, when the laminates LM2 and LM3 are subsequently bonded together with their respective reference points P0 overlapping vertically, the stepped portions SR2 and SR3 become a continuous stepped shape in the X direction.

[0133] Subsequently, a plurality of contact holes are formed, penetrating the insulating layer 55 and reaching each character line WL1 and substrate SB3. An insulating layer LE3 and a conductive layer EL3 are formed in the plurality of contact holes. Through the above operations, as shown in FIG14B, contact CC3 is formed.

[0134] Furthermore, in parallel with the processing in Figure 13B above, an insulating layer 52 is also formed on the insulating layer 51 in the stepped portion SR3, and a plug CH is formed in the insulating layer 52 extending in the Z direction and connected to the contact CC3 in the conductive layer EL3. An upper wiring MX is formed that is connected to the contact CC3 via the plug CH.

[0135] Next, the substrate SB3 is polished until the bottom insulating layer OL3 is exposed from below, and then cut along the dividing line in the Z direction. In this way, n wafers are formed.

[0136] Next, based on the inspection results of the memory hole MHA3 output in the inspection step of Figure 13A, the chips containing the "qualified" exposure area are selected from the n chips. Through the above operations, step 3 ends.

[0137] Next, Figure 15 shows the bonding of the wafers selected in steps 1 through 3. Figure 15 shows a cross-section along the X direction of the portion that will subsequently become the memory region MR. The bonding step shown in Figure 15 is performed as part of the manufacturing process of the semiconductor device 1.

[0138] Although the illustration is omitted here, the upper surface F15 of the monolithized multilayer LM3 is respectively attached to the semiconductor substrate SB containing multiple peripheral circuits CBA, corresponding to the multiple exposure areas disposed on the semiconductor substrate SB.

[0139] For example, the upper surface F15 of the multilayer LM3 and the insulating layer 40 covering the peripheral circuit CBA (see Figure 1A) can be activated by pre-treatment with plasma, thereby bonding the multilayer LM3 and the peripheral circuit CBA. In this way, the multilayer LM3 and the peripheral circuit CBA are electrically connected.

[0140] Then, as shown in Figure 15, the lower surface F14 of the laminate LM3 is bonded to the upper surface F13 of the laminate LM2 cut from the substrate SB2 and selected.

[0141] The laminates LM2 and LM3 can be joined, for example, by activating the upper surface F14 and lower surface F13 beforehand using plasma treatment. Furthermore, when joining the laminates LM2 and LM3, they are aligned such that the pillars PL2, plate-like portions LI2, and contacts CC2 (not shown) formed on the laminate LM2 coincide with the pillars PL3, plate-like portions LI3, and contacts CC3 (not shown) formed on the laminate LM3 in the Z direction.

[0142] After the laminates LM2 and LM3 are joined together, an annealing process is performed. This electrically connects the pillars PL2~PL3, the plate portions LI2~LI3, and the contacts CC2~CC3.

[0143] Then, the lower surface F12 of the laminate LM2 and the lower surface F11 of the laminate LM1 are bonded together in the same way.

[0144] Subsequently, using CMP (Chemical Mechanical Polishing) or similar methods, the substrate SB1 and the insulating layer 60 are polished from below to the specified position of the insulating layer 60, thereby forming a plug PG that penetrates the insulating layer 60 and reaches the source line SL. At this time, the insulating layer 60 can also be thickened as needed. Then, the electrode film EL is formed below the plug PG.

[0145] Through the above operations, the manufacturing of semiconductor device 1 is completed.

[0146] (Summary) Previously, with the miniaturization of semiconductor devices, it was desirable to increase the number of word lines and arrange more pillar patterns in order to form more memory cells in a specified area of ​​the semiconductor device. Due to the high stacking of word lines and the high density of pillar patterns, sometimes reducing the diameter of each pillar pattern can also cause the pillar patterns to be too close together. If the diameter of the pillar patterns decreases while the word lines are highly stacked, poor pattern bottom detachment may occur during etching. The more stacked the word lines, that is, the higher the aspect ratio of the pillar patterns, the more significant this problem of poor pattern bottom detachment becomes. Furthermore, if the pillar patterns are arranged too close together, short circuits may sometimes occur between the pillar patterns.

[0147] The semiconductor device 1 of the embodiment includes a stacked body LM1, a pillar PL1 extending in the Z direction within the stacked body LM1, a stacked body LM2, a pillar PL2 extending in the Z direction within the stacked body LM2, and a bonding surface SP1 disposed between the pillar PL1 and the pillar PL2. The pillar PL1 and the pillar PL2 are connected in the Z direction in the bonding surface SP1.

[0148] Thus, by connecting columns PL1 and PL2, which are formed in different layers, in the Z direction, it is easy to form a column PL with a high aspect ratio.

[0149] Furthermore, in the semiconductor device 1 of the embodiment, the pillar PL2 has: an extension PE2 that extends in the Z direction within the stacked body LM2; and a bonding portion PJ1 that is connected to the lower end of the extension PE2 by a surface SE1 and to the upper end of the pillar PL1 by a surface SE2. The diameter of the bonding portion PJ1 is greater than or equal to the diameter of the lower end of the extension PE2 and less than or equal to the diameter of the upper end of the extension PE2.

[0150] Thus, by setting the diameter D2 of the joint PJ1 to be greater than or equal to the diameter D1 of the lower end of the extension PE2, a larger permissible range of positional offset can be ensured when the upper ends of the column PL2 and column PL1 are connected. Furthermore, by setting the diameter D2 of the joint PJ1 to be less than or equal to the diameter D3 of the upper end of the extension PE2, the columns PL2 can be formed more closely together, and contact between adjacent columns PL2 in the joint PJ1 can be suppressed.

[0151] Furthermore, in the manufacturing method of the semiconductor device 1 according to the embodiment, when the substrate SB1 is monolithically formed, a plurality of stacked layers LM1 are inspected, and stacked layers LM1 that pass the inspection are selected. When the substrate SB2 is monolithically formed, a plurality of stacked layers LM2 are inspected, and stacked layers LM2 that pass the inspection are selected. The selected stacked layers LM1 and the selected stacked layers LM2 are then bonded together.

[0152] By bonding the inspected and qualified laminates LM1 and LM2 together, the formation defects of pillar PL can be reduced. This is because, for example, if pillar PL is formed together without bonding LM1 and LM2, a defect in either the portion corresponding to pillar PL1 or the portion corresponding to pillar PL2 will be judged as an overall defect in pillar PL. By bonding the selected laminates together, the yield of semiconductor device 1 can be improved.

[0153] (Variation Example 1) Figures 16 and 17 are diagrams illustrating a portion of the manufacturing process of the semiconductor device according to Variation 1. In the manufacturing process of the semiconductor device in Variation 1, the timing of bonding the multilayers together differs from the embodiment described above. Furthermore, in the following Variation 1, for the sake of simplicity, the description will focus on the manufacturing process of the portion that will subsequently become the memory region MR. Also, hereafter, components identical to those in the embodiment described above will sometimes be labeled with the same symbols, and their descriptions will be omitted.

[0154] Figures 16, 17A, and 17B show cross-sections along the X direction of the portion that will subsequently become the memory region MR.

[0155] First, an insulating layer 60, a source line SL, and a stacked body LMs1 are formed on the substrate SB1 to form a memory via MHA1. Then, a slit STA1 is formed. After the inspection step of the memory via MHA1, a CVD carbon layer and the like are embedded in the memory via MHA1 and the slit STA1.

[0156] Next, a multilayer LMs2 and a memory via MHA2 are formed on substrate SB2. Following an inspection of the memory via MHA2, a slit STA2 is formed, and a CVD carbon layer is embedded within the memory via MHA2 and the slit STA2. Each multilayer LMs2 is then monolithically assembled.

[0157] Next, a multilayer assembly LMs3 and a memory via MHA3 are formed on substrate SB3. Following an inspection of the memory via MHA3, a slit STA3 is formed, embedding a CVD carbon layer or similar material into the memory via MHA3 and the slit STA3. Furthermore, an insulating layer 52 is formed on insulating layer 51, forming plugs CH, bit lines BL, and upper layer wiring MX. Each multilayer assembly LMs3 is monolithically fabricated.

[0158] Next, as shown in Figure 16, the upper surface F31 of the stacked layer LMs1 is bonded to the lower surface F32 of the stacked layer LMs2, and the upper surface F33 of the stacked layer LMs2 is bonded to the lower surface F34 of the stacked layer LMs3. That is, in Variation 1, the monolithized substrates SB2 to SB3 are bonded to the unmonolithified substrate SB1. Furthermore, whenever the stacked layers LM2 and LM3 are bonded to the stacked layers LM1 and LM2 respectively, the substrates SB2 and SB3 of the stacked layers LM2 and LM3 are removed by CMP or the like. Also, when the stacked layers LM2 and LM3 are bonded to the stacked layer LM1, in addition to using only stacked layers LM2 and LM3 with qualified wafers, the stacked layers LM2 and LM3 are bonded only to the inspected and qualified stacked layers LM1.

[0159] Subsequently, as shown in Figure 17A, after removing the CVD carbon layer, a memory film ME, a channel layer CN, a core layer CR, and a capping layer CP are formed in the memory holes MHA1~MHA3 to form pillars PL. Then, through a replacement process, laminates LM1~LM3 are formed. A padding layer LL and a conductive portion EC are filled into the sidewalls of slits STA1~3 to form plate-shaped contacts LI.

[0160] Subsequently, although the illustration is omitted, the semiconductor substrate SB containing the peripheral circuit CBA is attached to the upper surface F35 of the stacked body LM3. After the substrate SB1 of the stacked body LM1 is removed by CMP or the like, as shown in Figure 17B, the plug PG through the insulating layer 60 and the electrode film EL are formed below the source line SL. Then, the substrate SB is monolithized for each stacked body LM1~LM3 and the peripheral circuit CBA.

[0161] Through the above operations, the semiconductor device of Variation 1 is manufactured.

[0162] The semiconductor device and its manufacturing method according to Variation 1 achieve the same effects as the above-described embodiments.

[0163] [Variation Example 2] Next, using Figure 18, Variation Example 2 will be described. The configuration of the stepped region ER of the semiconductor device in Variation Example 2 is different from that in Embodiment 1 described above.

[0164] Figure 18 is a diagram showing a detailed configuration example of the stepped region ER in Variation Example 2. More specifically, Figure 18 is a cross-sectional view of the stepped region ER along the X direction, and corresponds to Figure 3A. Furthermore, in Figure 18, the structures above the insulating layer 52 and below the insulating layer 60 are omitted. Also, hereafter, the same symbols will sometimes be used to refer to the same configurations as in Embodiment 1 and Variation Example 1, and their descriptions will be omitted.

[0165] As shown in Figure 18, a plurality of contacts CC1 are formed at the X-direction end of the laminate LM1. The plurality of contacts CC1 extend along the Z-direction within the laminate LM1. That is, no stepped portion SR1 is formed in the laminate LM1 (Figure 3A). The lower ends of each contact CC1 reach the character lines WL1 constituting the laminate LM1, and the upper ends reach the mating surface SP1. The depth reached by the lower ends of the contacts CC1 gradually decreases when viewed from the X-direction end side of the laminate LM1.

[0166] A plurality of contacts CC2 are formed at the X-direction end of the laminate LM2. The contacts CC2 extend along the Z-direction within the laminate LM2. That is, no stepped portion SR2 is formed in the laminate LM2 (Fig. 3A). The lower end of a portion of the contacts CC2 reaches the character lines WL2 constituting the laminate LM2, and the upper end reaches the mating surface SP2. The depth reached by the lower end of the contacts CC2 gradually decreases when viewed from the X-direction end side of the laminate LM2. Furthermore, the lower end of the remaining portion of the contacts CC2 connects to the contacts CC1 in the mating surface SP1 along the Z-direction, and the upper end reaches the mating surface SP2.

[0167] A plurality of contacts CC3 are formed at the X-direction end of the laminate LM3. The contacts CC3 extend along the Z-direction within the laminate LM3. That is, no stepped portion SR3 is formed in the laminate LM3 (Fig. 3A). The lower end of a portion of the contacts CC3 reaches the character line WL3 constituting the laminate LM3, and the upper end penetrates the insulating layer 51 and reaches the insulating layer 52. The depth reached by the lower end of the contacts CC3 gradually decreases when viewed from the X-direction end side of the laminate LM3. Furthermore, the lower end of the remaining portion of the contacts CC3 is connected to the contacts CC2 in the mating surface SP2, and the upper end penetrates the insulating layer 51 and reaches the insulating layer 52.

[0168] By connecting the contacts CC1 to CC3 as described above, a contact CC with a depth that gradually decreases from the end side in the X direction is formed. Furthermore, although the illustration is omitted, the semiconductor device of Variation 2 may also have a configuration corresponding to the junction CJ1 and extension CE1 of Embodiment 1.

[0169] Furthermore, although the illustrations are omitted, the semiconductor device in Variation Example 2 is manufactured in the same manner as in Embodiment 1 by steps 1 to 3 and the bonding step.

[0170] In the first step of forming contact CC1, after forming the multilayer LMs1, a mask pattern with multiple openings is formed on the upper surface of the multilayer LMs1. The mask pattern is, for example, a silicon oxide layer. Next, a resist pattern covering a portion of the mask pattern is formed, and the multilayer LMs1 is etched through the mask pattern exposed from the resist pattern. Then, the resist pattern is refined so that the openings of the mask pattern gradually expose from the end side in the X direction, while etching is repeated. This forms a contact hole whose depth gradually decreases from the end side in the X direction. Next, a replacement process is performed, and then the insulating layer LE1 and the conductive layer EL1 are filled into the contact hole. Through the above operations, contact CC1 is formed. Afterwards, after screening qualified wafers, the first step is completed.

[0171] In each of steps 2 and 3, contacts CC2 and CC3 are formed by steps corresponding to those in step 1. Subsequently, after bonding steps, the manufacturing of the semiconductor device of variation 2 is completed.

[0172] According to the semiconductor device and the method for manufacturing the semiconductor device in Variation 2, the same effects as in Embodiment 1 and Variation 1 are achieved.

[0173] (Other examples of variations) In the above embodiments and variations, the shape of the memory holes MHA1 to MHA3 was inspected during the inspection step. However, the inspection target is not limited to the memory holes MHA1 to MHA3. For example, contact holes HLc, slits STA1 to STA3, or pillars PL1 to PL3 on which the memory film ME, channel layer CN, and core layer CR are formed may also be inspected.

[0174] In the above embodiments and variations, joints PJ1 and PJ2 are formed at the lower ends of pillars PL2 and PL3 respectively, while joints CJ1 and CJ2 are formed at the upper ends of contacts CC1 and CC2 respectively. However, the formation positions of the joints are not limited to the above. For example, joints PJ1 and PJ2 may be formed at the upper ends of pillars PL1 and PL2, and joints CJ1 and CJ2 may be formed at the lower ends of contacts CC2 and CC3. Furthermore, when the alignment accuracy is sufficient when joining the various laminates LM1 to LM3, joints PJ1 and PJ2 of pillars PL2 and PL3, and joints CJ1 and CJ2 of contacts CC2 and CC3 may not be formed.

[0175] In the above embodiments and variations, multilayers LM1 to LM3 are formed on substrates SB1 to SB3 respectively, but the multilayers LM1 to LM3 may not be distinguished. For example, multilayers with the same structure may be formed on multiple substrates. Alternatively, multilayers with the same structure may be formed on a single substrate. Subsequently, these are monolithically processed, qualified wafers are selected from them, and they are sequentially bonded to substrate SB on which peripheral circuits CBA are formed, in the order of any of embodiments or variations 1 and 2. In this case, bit lines BL, upper layer wiring MX, plugs CH, etc., can be pre-formed on the peripheral circuit CBA side. Furthermore, by forming source lines SL, insulating layer 60, plugs PG, and electrode films EL on the side of the multilayer LM opposite to the peripheral circuit CBA after bonding with the peripheral circuit CBA, a semiconductor device 1 identical to that in the above embodiments can be obtained.

[0176] In the above embodiments and variations, the semiconductor device 1 includes three stacked layers LM1 to LM3. However, the number of stacked layers included in the semiconductor device 1 may also be two or more.

[0177] Furthermore, in the above embodiments and variations, pillars or the like are formed on at least one of the substrates SB1 to SB3 without being monolithized. However, for example, substrates SB1 to SB3 may be monolithized before forming pillars or the like, and pillars or the like may be formed on substrates SB1 to SB3 while they are fixed on a non-monolithized substrate different from substrates SB1 to SB3.

[0178] In the above embodiments and variations, the case of forming a three-dimensional non-volatile memory as a semiconductor device 1 has been described, but the application of the present invention is not limited to three-dimensional non-volatile memory. The present invention can also be applied to other semiconductor devices with structures having a high aspect ratio. For example, the present invention can also be applied to volatile memory such as DRAM (Dynamic Random Access Memory).

[0179] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention described in the claims and their equivalents.

[0180] 1: Semiconductor devices 40, 50, 51, 52, 53, 54, 55, 60, LE1, LE2, LE3, OL1, OL2, OL3: Insulation layer 100, SB1, SB2, SB3:Substrate BL: Bitline CBA: Peripheral Circuits CC, CC1, CC2, CC3: Contacts CE1, CE2, PE1, PE2: Extension sections CH: plug CJ1, CJ2, PJ1, PJ2: Joint CN, CN1, CN2, CN3: Channel Layer CP: cap layer CPL1: Chip CPL2: Chip CPL3: Chip CPLn: Chip CR, CR1, CR2, CR3: Core layer D1, D2, D3, D4, D5: Diameter DA: Component Area DL: Divider EC: Conductive part EC1: Conductive part EC2: Conductive part EC3: Conductive part EL: Electrode film EL1, EL2, EL3: Conductive parts ER: Stepped area F11: Lower surface F12: Lower surface F13: Upper surface F14: Lower surface F15: Top surface F31: Upper surface F32: Lower surface F33: Upper surface F34: Lower surface F35: Upper surface HLc: Contact Hole L1: Distance L2: Distance L3: Distance LI: Plate-shaped contact LI1, LI2, LI3: plate-shaped part LL: Padding layer LL1: Padding layer LL2: Padding layer LL3: Padding layer LM, LM1, LM2, LM3, LMs1, LMs2, LMs3, LMs21: laminated body ME, ME1, ME2, ME3: Memory membrane MHA1: Memory Hole MHA2: Memory Hole MHA3: Memory Hole MHA21: Hole MHA22: Hole MHA31: Hole MHA32: Hole MR: Memory Region MX: Upper layer wiring NL1, NL2, NL3: Sacrificial Layers OP: Opening P0: Reference point P1: Location P2: Location P3: Location PG: Plug PL, PL1, PL2, PL3: Columns RF: Photoresist film SB: Semiconductor substrate SB1:Substrate SB2:Substrate SB3:Substrate SE1: Face SE2: Face SH1: Exposure Area SH2: Exposure Area SH3: Exposure Area SHn: Exposure area SJ1: noodles SJ2: Face SL: Source Line SP1, SP2: Adhesive Surface SR1, SR2, SR3: Stepped section STA1: Slit STA2: Slit STA3: Slit TR: Transistor TRa: Stepped surface TRb: Stepped surface TRc: Stepped surface TRd: Stepped surface WL, WL1, WL2, WL3: Character lines X: Direction Y: direction Z: Direction

Claims

1. A semiconductor device comprising: a first structure; a first columnar body extending in the first structure along a first direction; a second structure; a second columnar body extending in the second structure along the first direction; and a bonding surface disposed between the first structure and the second structure; wherein the first columnar body and the second columnar body are connected in the bonding surface in the first direction, the first structure being configured as a first laminate, the first laminate being formed by alternately stacking a plurality of first conductive layers and a plurality of first insulating layers, the first columnar body being configured as a first pillar, the first pillar having a first semiconductor layer extending in the first laminate within the first laminate along the first direction, the second structure being configured as a second laminate, the second laminate being formed by alternately stacking a plurality of second conductive layers and a plurality of second insulating layers, the second columnar body being configured as a second pillar. The second pillar has a second semiconductor layer extending in the second stacked body along the first direction. The second pillar has: an extension extending in the second stacked body along the first direction; and a bonding portion connected to the end of the extension on the mating surface side with a first surface and connected to the end of the first pillar on the mating surface side with a second surface; and the diameter of the bonding portion is greater than or equal to the diameter of the end of the extension on the mating surface side and less than or equal to the diameter of the other end of the extension.

2. The semiconductor device of claim 1, wherein the first structure is configured as the first laminate, the first laminate further includes a first step portion formed by processing the plurality of first conductive layers into a step shape extending in a second direction intersecting the first direction, the first step portion being covered by a third insulating layer, the semiconductor device further comprising: a third pillar and a fourth pillar, the third pillar being configured as a first contact, the first contact extending in the third insulating layer along the first direction and connected to any one of the plurality of first conductive layers processed into a step shape, the second structure being configured as the second laminate, the second laminate further including a second step portion formed by processing the plurality of second conductive layers into a step shape continuous with the first step portion in the second direction. The second step portion is covered by the fourth insulating layer, and the fourth columnar body constitutes the second contact. The second contact extends in the fourth insulating layer along the first direction and is connected to any one of the plurality of second conductive layers that are processed into a step shape.

3. The semiconductor device of claim 2, wherein the first and second contacts have conductive portions comprising a conductive material, and the diameter of the conductive portion in the mating surface of the first contact is greater than the diameter of the conductive portion in the mating surface of the second contact.

4. The semiconductor device of claim 1, further comprising: a first plate-shaped portion extending in the first structure along the first direction and a second direction intersecting the first direction; and a second plate-shaped portion extending in the second structure along the first direction and the second direction; and the first plate-shaped portion and the second plate-shaped portion being connected in the first direction in the mating surface.

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