memory devices

Abstract

This invention suppresses interface speed degradation and reduces chip size. The memory device of the embodiment includes a substrate W1, a first circuit layer 100, a second circuit layer 200, and a wiring layer 300. The substrate has a first region AA and a second region DA. The first circuit layer includes CMOS circuitry. The wiring layer is disposed above the second circuit layer and includes pads electrically connected to the CMOS circuitry via the second circuit layer. The second circuit layer includes a stacked body and a plurality of first pillars MP. The stacked body includes alternating layers of a first insulating layer 32 and a first conductive layer 22 in the first region, and alternating layers of a first insulating layer and a first component SM in the second region. The plurality of first pillars penetrate the stacked body in the first region and are electrically connected to a source line 21 above the stacked body. The pads have portions overlapping the stacked body but not portions overlapping the source line.

Description

Technical Field

[0001] The implementation method relates to a memory device. Prior Technology

[0002] NAND flash memory is known to be able to store data in a non-volatile manner. Summary of the Invention

[0003] This invention suppresses interface speed degradation and reduces chip size. The memory device of the embodiment has a bonding surface. The memory device includes a substrate, a first circuit layer, a second circuit layer, and a wiring layer. The substrate has a first region and a second region arranged in a first direction. The first circuit layer is disposed between the substrate and the bonding surface and includes CMOS circuitry. The second circuit layer is disposed above the bonding surface. The wiring layer is disposed above the second circuit layer and includes pads electrically connected to the CMOS circuitry via the second circuit layer. The second circuit layer includes a stack body, a plurality of first pillars, and source lines. Within the first region, the stack body includes alternating layers of a first insulating layer and a first conductive layer in a second direction intersecting the first direction; and within the second region, it includes alternating layers of a first insulating layer and a first conductive layer in the second direction, or alternating layers of a first insulating layer and a first member in the second direction, wherein the material of the first member is different from that of the first insulating layer and the first conductive layer. A plurality of first pillars penetrate the laminate in a second direction within a first region and are electrically connected to the source line above the laminate. The pads have portions overlapping the laminate in the second direction but not portions overlapping the source line in the second direction. Simple Explanation of the Diagram

[0004] Figure 1 is a block diagram showing an example of the overall configuration of a memory system equipped with the memory device of the first embodiment. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array provided in the memory device of the first embodiment. Figure 3 is a perspective view showing an example of the appearance of the memory device according to the first embodiment. Figure 4 is a top view showing an example of the plan layout of the memory device according to the first embodiment. Figure 5 is a top view showing an example of the planar layout of the core area of ​​the memory cell array in the memory device of the first embodiment. Figure 6 is a cross-sectional view along line VI-VI of Figure 5, showing an example of the cross-sectional structure of the storage area of ​​the memory cell array provided by the memory device of the first embodiment. Figure 7 is a cross-sectional view along line VII-VII of Figure 6, showing an example of the cross-sectional structure of the memory column of the memory device of the first embodiment. Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment. Figure 9 is a top view showing an example of the plan layout of the wiring layer in the memory device according to the first embodiment. Figure 10 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the first embodiment. Figure 11 is a cross-sectional view along line XI-XI of Figure 10, showing an example of the cross-sectional structure near the solder pad in the memory device of the first embodiment. Figure 12 is a flowchart illustrating an example of a method for manufacturing a memory device according to the first embodiment. Figure 13 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the first embodiment. Figure 14 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the first embodiment. Figure 15 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the first embodiment. Figure 16 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the first embodiment. Figure 17 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the first embodiment. Figure 18 is a top view showing an example of the planar layout near the solder pads in the memory device of the first comparative example. Figure 19 is a cross-sectional view along line XIX-XIX of Figure 18, showing an example of the cross-sectional structure near the solder pad in the memory device of the first comparative example. Figure 20 is a top view showing one example of the planar layout near the solder pads in the memory device of the second comparative example. Figure 21 is a cross-sectional view along line XXI-XXI of Figure 20, showing an example of the cross-sectional structure near the solder pad in the memory device of the second comparative example. Figure 22 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the second embodiment. Figure 23 is a cross-sectional view along line XXIII-XXIII of Figure 22, showing an example of the cross-sectional structure near the solder pad in the memory device of the second embodiment. Figure 24 is a flowchart illustrating an example of a method for manufacturing a memory device according to the second embodiment. Figure 25 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the second embodiment. Figure 26 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the second embodiment. Figure 27 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the second embodiment. Figure 28 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the third embodiment. Figure 29 is a cross-sectional view along line XXIX-XXIX of Figure 28, showing an example of the cross-sectional structure near the solder pad in the memory device of the third embodiment. Figure 30 is a flowchart illustrating an example of a method for manufacturing a memory device according to the third embodiment. Figure 31 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the third embodiment. Figure 32 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the third embodiment. Figure 33 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the third embodiment. Figure 34 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the third embodiment. Figure 35 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the fourth embodiment. Figure 36 is a cross-sectional view along line XXXVI-XXXVI of Figure 35, showing an example of the cross-sectional structure near the solder pad in the memory device of the fourth embodiment. Figure 37 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the fifth embodiment. Figure 38 is a cross-sectional view along line XXXVIII-XXXVIII of Figure 37, showing an example of the cross-sectional structure near the solder pad in the memory device of the fifth embodiment. Figure 39 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided in the memory device of the sixth embodiment. Figure 40 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the sixth embodiment. Figure 41 is a cross-sectional view along line XLI-XLI of Figure 40, showing an example of the cross-sectional structure near the solder pad in the memory device of the sixth embodiment. Figure 42 is a flowchart illustrating an example of a method for manufacturing a memory device according to the sixth embodiment. Figure 43 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the sixth embodiment. Figure 44 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the manufacturing process of the sixth embodiment. Figure 45 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the seventh embodiment. Figure 46 is a cross-sectional view along line XLVI-XLVI of Figure 45, showing an example of the cross-sectional structure near the solder pad in the memory device of the seventh embodiment. Figure 47 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the eighth embodiment. Figure 48 is a cross-sectional view along line XLVIII-XLVIII of Figure 47, showing an example of the cross-sectional structure near the solder pad in the memory device of the eighth embodiment. Figure 49 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the ninth embodiment. Figure 50 is a cross-sectional view along line LL of Figure 49, showing an example of the cross-sectional structure near the solder pad in the memory device of the 9th embodiment. Figure 51 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the tenth embodiment. Figure 52 is a cross-sectional view along line LII-LII of Figure 51, showing an example of the cross-sectional structure near the solder pad in the memory device of the 10th embodiment. Figure 53 is a top view showing an example of the planar layout near the solder pad portion in the memory device of the 11th embodiment. Figure 54 is a cross-sectional view along the LIV-LIV line in Figure 53, showing an example of the cross-sectional structure near the solder pad in the memory device of the 11th embodiment. Figure 55 is a cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bonding pads in a memory device according to the first embodiment. Implementation

[0005] The following description describes each embodiment with reference to the drawings. Each embodiment illustrates an apparatus and method for realizing the technical concept of the invention. The drawings are schematic diagrams or conceptual diagrams. The dimensions, scales, etc., of each drawing may not be the same as the actual situation. The structural illustrations have been appropriately omitted. The shading lines added to the top view may not be related to the raw materials and characteristics of the constituent elements. In this specification, constituent elements having substantially the same function and structure are labeled with the same symbols. The numbers, characters, etc., added to the reference symbols are used to distinguish similar elements represented by the same reference symbols from each other.

[0006] <1> Implementation Method 1 The first embodiment relates to a memory device having a structure in which the source lines in the region where the ends of the memory cell array overlap with the solder pads exposed on the surface of the memory device are removed, and an insulating film is embedded in that region. Hereinafter, the memory device 1 of the first embodiment will be described.

[0007] <1-1> Composition First, the configuration of the memory device 1 in the first embodiment will be described.

[0008] [] <1-1-1> Overall Structure of Memory Device 1 Figure 1 is a block diagram showing an example of the overall configuration of a memory system equipped with the memory device 1 of the first embodiment. As shown in Figure 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 is, for example, a NAND flash memory capable of non-volatile data storage. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a temporary register circuit 13, a sequencer 14, a driver circuit 15, a column decoder module 16, and a sense amplifier module 17.

[0009] The memory cell array 10 contains a plurality of blocks BLK0 to BLKn (where "n" is an integer greater than or equal to 1). A block BLK is a collection of a plurality of memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK contains a plurality of pages. A page corresponds to a unit of data read and write. The memory cell array 10 is provided with a plurality of bit lines BL0 to BLm (where "m" is an integer greater than or equal to 1) and a plurality of word lines WL, but the relevant illustrations are omitted. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0010] Input / output circuit 11 is an interface circuit responsible for sending and receiving input / output signals with memory controller 2. Input / output signals include, for example, data (DAT), status information, address information, and instructions. Input / output circuit 11 can input and output data (DAT) with both the sense amplifier module 17 and the memory controller 2. Input / output circuit 11 can output status information transmitted from register circuit 13 to memory controller 2. Input / output circuit 11 can output address information and instructions transmitted from memory controller 2 to register circuit 13 respectively.

[0011] The logic controller 12 controls the input / output circuit 11 and the sequencer 14 based on the control signals input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to activate the memory device 1. The logic controller 12 notifies the input / output circuit 11 of the input / output signals received from the input / output circuit 11, such as instructions or address information. The logic controller 12 commands the input / output circuit 11 to input or output the input / output signals.

[0012] The temporary register circuit 13 temporarily stores state information, address information, and instructions. The state information is updated based on the control of the sequencer 14 and transmitted to the input / output circuit 11. The address information includes block addresses, page addresses, row addresses, etc. The instructions include commands related to various operations of the memory device 1.

[0013] The sequencer 14 controls the overall operation of the memory device 1. Based on the instructions and address information stored in the temporary register circuit 13, the sequencer 14 performs read operations, write operations, erase operations, etc.

[0014] The driver circuit 15 generates the voltage used in read, write, and erase operations. Furthermore, the driver circuit 15 supplies the generated voltage to the column decoder module 16, the sense amplifier module 17, and the like.

[0015] The column decoder module 16 is a circuit used to select the block BLK as the target of action or to transmit voltage to wiring such as word lines WL. The column decoder module 16 includes a plurality of column decoders RD0~RDn. Column decoders RD0~RDn are associated with blocks BLK0~BLKn respectively and are used to select blocks BLK. Each column decoder RD transmits the voltage generated by the driver circuit 15 to various wirings disposed in the memory cell array 10.

[0016] The sense amplifier module 17 is a circuit used to transmit voltage to each bit line BL or to read data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm. Each sense amplifier unit SAU includes a sense amplifier that can determine data based on the voltage of the bit line BL with which it is associated, and a latching circuit for temporarily storing data.

[0017] Furthermore, the combination of memory device 1 and memory controller 2 can also constitute a semiconductor device. Examples of such semiconductor devices include memory cards such as SDTM cards or SSDs (solid state drives).

[0018] <1-1-2> Circuit Structure of Memory Cell Array 10 Figure 2 is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 10 included in the memory device 1 of the first embodiment. Figure 2 shows two blocks BLK0 and BLK1 within a plurality of blocks BLK included in the memory cell array 10. As shown in Figure 2, in the memory cell array 10, each block BLK is provided with select gate lines SGD and SGS, and word lines WL0 to WL(N-1) (N is an integer of 2 or more). The bit lines BL0 to BLm and the source line SL are shared by the plurality of blocks BLK, for example.

[0019] Each BLK block contains a plurality of NAND strings NS. Each NAND string NS is associated with bit lines BL0 to BLm. In other words, each bit line BL is shared by the NAND strings NS that are allocated the same row address among the plurality of BLK blocks. Each NAND string NS is connected between the associated bit line BL and the source line SL. Each NAND string NS, for example, contains N memory cell transistors MT0 to MT(N-1), and select transistors ST1 and ST2. Each memory cell transistor MT is a memory cell with a control gate and a charge storage layer, non-volatilely storing (memorizing) data. Select transistors ST1 and ST2 are used to select the BLK block.

[0020] In each NAND string NS, select transistor ST1, memory cell transistors MT(N-1)~MT0, and select transistor ST2 are connected in series sequentially. Specifically, the drain and source terminals of select transistor ST1 are connected to the associated bit line BL and the drain terminal of memory cell transistor MT(N-1), respectively. The drain and source terminals of select transistor ST2 are connected to the source terminal of memory cell transistor MT0 and the source line SL, respectively. Memory cell transistors MT0~MT(N-1) are connected in series between select transistors ST1 and ST2.

[0021] Each select gate line SGD is connected to the gate terminals of the plurality of select transistors ST1 contained in the associated block BLK. The select gate line SGS is connected to the gate terminals of the plurality of select transistors ST2 contained in the associated block BLK. Word lines WL0~WL(N-1) are respectively connected to the control gate terminals of the plurality of memory cell transistors MT0~MT(N-1) contained in the associated block BLK. A "page" corresponds to the set of plurality of memory cell transistors MT connected to the common word line WL within the same BLK. The set of plurality of memory cell transistors MT connected to the common word line WL within the same BLK may have a memory capacity of more than two pages of data, depending on the number of bits stored by the memory cell transistor MT.

[0022] Furthermore, the circuit configuration of the memory cell array 10 can also be other circuit configurations. For example, multiple select gate lines (SGDs) that can be independently controlled can be provided on each BLK. In this case, each BLK is configured to be able to select in units of multiple cells corresponding to the multiple select gate lines (SGDs).

[0023] Hereinafter, the memory device 1 of the first embodiment will be described as follows, taking the case where each NAND string NS has 8 memory cell transistors MT0 to MT7 connected to word lines WL0 to WL7 respectively (i.e., the case where N=8).

[0024] <1-1-3> Structure of Memory Device 1 The structure of the memory device 1 according to the first embodiment will be described below.

[0025] Furthermore, a three-dimensional orthogonal coordinate system is used in the following referenced diagrams. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the front surface of the reference semiconductor substrate. "Up and down" is defined based on the direction along the Z direction. The positive direction (above) corresponds to the direction away from the reference semiconductor substrate. The XY plane (section) corresponds to the plane (section) parallel to the X and Y directions, respectively. The YZ section corresponds to the section parallel to the Y and Z directions, respectively. The XZ section corresponds to the section parallel to the X and Z directions, respectively.

[0026] (1: Appearance of memory device 1) First, the appearance of the memory device 1 according to the first embodiment will be described. The memory device 1 of the first embodiment is formed by bonding two semiconductor circuit substrates on which semiconductor circuits are respectively formed, and then separating the bonded semiconductor circuit substrates one wafer at a time. That is, the memory device 1 of the first embodiment has a bonding surface formed by bonding semiconductor substrates W1 and W2. Semiconductor substrates W1 and W2 are silicon substrates. Hereinafter, the situation where semiconductor substrate W2 is removed during the manufacturing process of memory device 1 will be described. According to the structure of memory cell array 10, a portion of semiconductor substrate W2 can also be retained after semiconductor substrates W1 and W2 are bonded together.

[0027] Figure 3 is a perspective view showing an example of the appearance of the memory device 1 according to the first embodiment. As shown in Figure 3, the memory device 1 includes, for example, a semiconductor substrate W1, a CMOS layer 100, a bonding layer B1, a bonding layer B2, a memory layer 200, and a wiring layer 300.

[0028] A CMOS layer 100 is disposed on a semiconductor substrate W1. The CMOS layer 100 includes CMOS circuitry (control circuitry) formed using the semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., consistent with the design of the CMOS circuitry. The CMOS layer 100 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a column decoder module 16, and a sense amplifier module 17. The CMOS layer 100 may also be referred to as a circuit layer.

[0029] A bonding layer B1 is disposed on the CMOS layer 100. The bonding layer B1 is formed using a semiconductor substrate W1. The bonding layer B1 includes a plurality of bonding pads that are electrically connected to the CMOS circuit disposed on the CMOS layer 100 to form a part of the semiconductor circuit.

[0030] Bonding layer B2 is disposed on bonding layer B1. Bonding layer B2 is formed using semiconductor substrate W2 (not shown). Bonding layer B2 includes a plurality of bonding pads that are electrically connected to the memory cell array 10 disposed on memory layer 200 to form a part of a semiconductor circuit. The plurality of bonding pads in bonding layer B2 are respectively connected to the plurality of bonding pads in bonding layer B1. The interface between bonding layers B1 and B2 corresponding to the layer formed using semiconductor substrate W1 and the layer formed using semiconductor substrate W2 is called the bonding surface.

[0031] The memory layer 200 is disposed on the bonding layer B2. The memory layer 200 includes a memory cell array 10 formed using the semiconductor substrate W2. The memory layer 200 may also be referred to as a circuit layer.

[0032] A wiring layer 300 is disposed on the memory layer 200. The wiring layer 300 is formed after bonding semiconductor substrates W1 and W2. The wiring layer 300 includes wiring that connects to semiconductor circuits disposed on the memory layer 200, and a plurality of solder pads PD. The plurality of solder pads PD includes conductive portions (solder pads) exposed on the surface of the memory device 1. The plurality of solder pads PD are used to connect the memory device 1 to the memory controller 2, etc., or to supply power, etc.

[0033] (2: Planar layout of memory device 1) Figure 4 is a top view showing an example of the planar layout of the memory device 1 according to the first embodiment. As shown in Figure 4, the memory device 1 includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a slot region KR.

[0034] The core region CR is, for example, a rectangular area located near the center of the semiconductor substrate W1. Within the core region CR, for example, a memory cell array 10, a temporary register circuit 13, a sequencer 14, a driver circuit 15, a column decoder module 16, and a sense amplifier module 17 are configured.

[0035] The peripheral region PR is a square ring-shaped area surrounding the core region CR. Within the peripheral region PR, for example, input / output circuits 11 and a logic controller 12 are configured. Furthermore, within the peripheral region PR, for example, contacts are configured to connect wiring on the wiring layer 300 to circuits on the CMOS layer 100 or the memory layer 200.

[0036] The wall region WR is a square annular region that surrounds the outer perimeter of the surrounding region PR. Within the wall region WR, at least one sealing part ES (not shown) is disposed, which surrounds the outer perimeter of the surrounding region PR. Details of the sealing part ES will be described below.

[0037] The trench region KR is a square annular region that surrounds the outer periphery of the wall region WR. The trench region KR is connected to the outermost periphery of the memory device 1. Within the trench region KR, for example, alignment marks used during the manufacture of the memory device 1 are disposed. The structure of the trench region KR can also be removed during the cutting step of cutting the semiconductor circuit board into individual wafers (memory devices 1).

[0038] (3: Planar layout of memory cell array 10) Figure 5 is a top view showing an example of the planar layout within the core region CR of the memory cell array 10 of the memory device 1 according to the first embodiment. As shown in Figure 5, the memory cell array 10 includes a plurality of slits SLT, a plurality of memory pillars MP, and a plurality of contacts CV and CC. Furthermore, the memory cell array 10 includes, for example, a storage region SA and a contact region CA arranged in the X direction.

[0039] Each slot SLT is a plate-shaped member extending along the X direction. Each slot SLT has a portion extending along the X direction, transversely cutting the storage area SA and the contact area CA along the X direction. A plurality of slot SLTs are arranged in the Y direction. Each slot SLT separates adjacent wirings (e.g., character lines WL0~WL7, and select gate lines SGD and SGS) separated by that slot SLT. In each slot SLT, a conductor with insulating spacers on its sidewalls can be configured to insulate it from the wiring, or an insulator can be embedded. In the memory cell array 10, the area divided by the slot SLTs along the Y direction corresponds to one block BLK.

[0040] Storage area SA contains a plurality of memory columns MP. Each memory column MP is, for example, a columnar member that functions as a NAND string NS. The plurality of memory columns MP are arranged in a grid pattern within each block BLK. At least one bit line BL is arranged overlapping each memory column MP. The plurality of bit lines BL each have a portion extending in the Y direction and are arranged in the X direction. In this example, two bit lines BL are arranged overlapping one memory column MP. The associated memory columns MP and bit lines BL are electrically connected via contacts CV.

[0041] The contact area CA is used to connect the stacked wiring (e.g., word lines WL, select gate lines SGD and SGS) of the memory cell array 10 to the column decoder module 16. Within the contact area CA, each block BLK is configured with a plurality of contacts CC. In each block BLK, the plurality of contacts CC are electrically connected to a corresponding wiring in the stacked wiring. In each block BLK, at least one contact CC is electrically connected to the select gate line SGS, word lines WL0~WL7, and select gate line SGD.

[0042] Furthermore, within the contact area CA, the multiple contacts CC in each BLK are not limited to a row arrangement in the X direction as shown in Figure 5; they can also be arranged in a grid pattern within each BLK. Alternatively, two contact areas CA can be configured within the core area CR, sandwiching the storage area SA in the X direction. Furthermore, the contact areas CA can also be configured by dividing the storage area SA in the X direction.

[0043] Furthermore, the core region CR includes an active region AA and a dummy region DA arranged in the Y direction. The active region AA and the dummy region DA each overlap with the storage region SA and the contact region CA, respectively. Within the overlapping area of ​​the storage region SA and the active region AA, a plurality of memory columns MP for storing data are configured. Within the overlapping area of ​​the contact region CA and the active region AA, a plurality of contacts CC for controlling the active block BLK are configured.

[0044] A dummy region DA is positioned at the Y-direction end of the core region CR. Within the core region CR, two dummy regions DA, sandwiching the effective region AA in the Y-direction, can be configured. A dummy block DBLK corresponds to the region within the dummy region DA divided along the Y-direction by the slit SLT. The dummy region DA contains at least one dummy block DBLK. Figure 5 shows two dummy blocks DBLK0 and DBLK1 arranged in the Y-direction. Within the region where the dummy block DBLK overlaps with the storage region SA, a plurality of dummy pillars DMP can be configured. The dummy pillars DMP are patterns used to compensate for the shape of the memory pillars MP and have the same structure as the memory pillars MP. The dummy pillars DMP are not connected to the contact CV and are not connected to the bit line BL. Therefore, the dummy pillars DMP are not used to store data.

[0045] The dummy region DA, corresponding to the outer edge of the core region CR, further includes a dummy step portion DS. The dummy step portion DS includes the ends of stacked wiring arranged in a stepped manner. A sacrificial member SM remains in the portion of the dummy step portion DS corresponding to the stacked wiring. The sacrificial member SM is a member used in the replacement process of forming the stacked wiring. In the replacement process, the sacrificial members SM of alternating stacks and the sacrificial members SM in the insulating layer are replaced with conductors, thereby forming the stacked wiring. More specifically, in the replacement process, the sacrificial member SM is removed via a slit SLT, and then a conductor is embedded in the space where the sacrificial member SM has been removed. Therefore, sacrificial members SM located in portions far from the slit SLT may not be replaced with conductors and remain in the replacement process. Thus, the ends of the stacked sacrificial members SM are arranged in a stepped manner. An example of the structure of the dummy step portion DS is shown in Figure 11 described below.

[0046] (4: Cross-sectional structure of the storage area SA of memory cell array 10) Figure 6 is a cross-sectional view along line VI-VI of Figure 5, showing an example of the cross-sectional structure within the storage region SA of the memory cell array 10 of the memory device 1 of the first embodiment. Figure 6 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before bonding with the semiconductor substrate W1, and the bonding layer B2 above it, and the coordinate axis with the semiconductor substrate W2 as the reference is marked. As shown in Figure 6, the memory cell array 10 includes, for example, conductive layers 21-24, insulating layers 31-34, insulating member 36, and contacts CV, V1, and V2 within the storage region SA.

[0047] A conductive layer 21 is disposed on the semiconductor substrate W2. An insulating layer 31 is disposed on the conductive layer 21. Conductive layers 22 and insulating layers 32 are alternately disposed on the insulating layer 31 in the Z direction. That is, a plurality of conductive layers 22 are arranged in the Z direction. Thus, the stacked layer corresponding to the memory cell array 10 includes conductive layers 22 and insulating layers 32 alternately disposed in the Z direction. The number of conductive layers 22 corresponds, for example, to the number of stacked wiring layers (select gate line SGS, word line WL, and select gate line SGD).

[0048] An insulating layer 33, a conductive layer 23, and an insulating layer 34 are sequentially disposed on the uppermost conductive layer 22. Conductive layers 21 and 22 are, for example, formed as plates extending along the XY plane. Conductive layer 23, for example, has a portion formed as a line extending in the Y direction. Conductive layer 21 is used as a source line SL. In this example, the 10 conductive layers 22 arranged in the Z direction are used sequentially from the source line SL side as select gate line SGS, word lines WL0~WL7, and select gate line SGD. Conductive layer 23 is used as a bit line BL. Conductive layer 21, for example, contains polycrystalline silicon (Si). Conductive layer 22, for example, contains tungsten (W). Conductive layer 23, for example, contains copper (Cu).

[0049] A conductive layer 24 is disposed above the conductive layer 23. The conductive layer 24 is the wiring connecting the relay bit line BL and the sense amplifier module 17. The conductive layer 23 and the conductive layer 24 are connected via a contact V1. A conductive layer 25 is disposed above the conductive layer 24. The conductive layer 25 corresponds to a bonding pad. The conductive layer 24 and the conductive layer 25 are connected via a contact V2. The sides of the conductive layer 24, and the contacts V1 and V2 are covered by an insulating layer 34. The insulating layer 34 may be composed of multiple insulating films. The sides of the conductive layer 25 are covered by an insulating layer 35. The insulating layer 35 and the conductive layer 25 are contained in the bonding layer B2. The memory cell array 10 may contain a plurality of conductive layers 24. The bonding layer B2 may contain a plurality of conductive layers 25. The conductive layer 25 may contain, for example, copper.

[0050] The insulating member 36 has a plate-like portion that extends along the XZ plane. The insulating member 36 separates the insulating layer 31 from the alternately arranged conductive layers 22 and insulating layers 32. In this example, the insulating member 36 is embedded in the slit SLT. Alternatively, a conductor with insulating spacers on its sidewalls can be arranged in the slit SLT and insulated from the conductive layers 21 and 22 respectively.

[0051] Each memory column (MP) extends along the Z-direction, connecting the insulating layer 31 with alternating conductive layers 22 and insulator layers 32, and is connected to the conductive layer 21. Each memory column (MP) includes, for example, a core component 40, a semiconductor layer 41, and a multilayer film 42. The core component 40 is an insulator extending along the Z-direction. The semiconductor layer 41 covers the core component 40. A portion of the side surface of the semiconductor layer 41 is in contact with the conductive layer 21. That is, the semiconductor layer 41 and the conductive layer 21 (source line SL) within the memory column (MP) are electrically connected via the side surface of the memory column (MP). The multilayer film 42 covers the side surface and bottom surface of the semiconductor layer 41, except for the contact portion between the semiconductor layer 41 and the conductive layer 21. A connection is established between the corresponding semiconductor layer 41 (memory column (MP)) and the conductive layer 23 (bit line BL) via a contact CV.

[0052] The portion of the conductive layer 22 used as the select gate line SGS that intersects with the memory pillar MP functions as the select transistor ST2. The portion of the conductive layer 22 used as the word line WL that intersects with the memory pillar MP functions as the memory cell transistor MT. The portion of the conductive layer 22 used as the select gate line SGD that intersects with the memory pillar MP functions as the select transistor ST1. In each memory pillar MP, the semiconductor layer 41 serves as the channel (current path) for the memory cell transistors MT0~MT7 contained in the NAND string NS, as well as the select transistors ST1 and ST2.

[0053] (5: Cross-sectional structure of memory column MP) Figure 7 is a cross-sectional view along line VII-VII of Figure 6, showing an example of the cross-sectional structure of the memory column MP of the memory device 1 according to the first embodiment. Figure 7 shows a cross-section including the memory column MP and the conductive layer 22, parallel to the front side of the semiconductor substrate W2. As shown in Figure 7, the laminated film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a barrier insulating film 45. The tunnel insulating film 43 surrounds the side of the semiconductor layer 41. The insulating film 44 surrounds the side of the tunnel insulating film 43. The barrier insulating film 45 surrounds the side of the insulating film 44. The conductive layer 22 surrounds the side of the barrier insulating film 45. The tunnel insulating film 43 and the barrier insulating film 45 each contain, for example, silicon oxide (SiO2). The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The insulating film 44 contains, for example, silicon nitride (SiN).

[0054] (6: Cross-sectional structure of memory device 1) Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment. Figure 8 shows a portion of the core region CR, peripheral region PR, and wall region WR after the semiconductor substrate W1 and semiconductor substrate W2 are bonded, and the coordinate axis with semiconductor substrate W1 as the reference is marked. Furthermore, in this example, semiconductor substrate W2 is removed after the bonding process of semiconductor substrates W1 and W2. The memory layer 200 and the bonding layer B2 have a structure in which the structure related to the memory cell array 10 shown in Figure 6 is reversed vertically within the core region CR. As shown in Figure 8, the CMOS layer 100 includes an insulating layer 110. The bonding layer B1 includes an insulating layer 111. The memory layer 200 includes an insulating layer 210, a conductive layer 211, a sacrificial member 212, and a conductive layer 213. The wiring layer 300 includes an insulating layer 301, an insulating member 302, a conductive layer 303, an insulating layer 304, an insulating layer 305, and an insulating layer 306.

[0055] An insulating layer 110 is disposed on a semiconductor substrate W1. The insulating layer 110 covers at least a portion of the wiring, contacts, components, etc., disposed on the CMOS layer 100. The insulating layer 110 may be composed of a plurality of insulating films. An insulating layer 111 is disposed on the insulating layer 110. The insulating layer 111 covers the side surface of the bonding pads of the bonding layer B1. An insulating layer 35 of the bonding layer B2 is disposed on the insulating layer 111.

[0056] An insulating layer 210 is disposed on an insulating layer 35. The insulating layer 210 covers at least a portion of the wiring, contacts, components, etc., disposed on the memory layer 200. The insulating layer 210 may be composed of a plurality of insulating films and may include insulating layers 33 and 34. A conductive layer 211, a sacrificial member 212, and a conductive layer 213 are sequentially deposited on the insulating layer 210. The conductive layer 211, the sacrificial member 212, and the conductive layer 213 are disposed at the height of the conductive layer 21. Specifically, the height of the lower surface of the conductive layer 211 is aligned with the height of the lower surface of the conductive layer 21 (source line SL). The height of the upper surface of the conductive layer 213 is aligned with the height of the upper surface of the conductive layer 21 (source line SL). The conductive layer 21 within the core region CR corresponds to the structure obtained by replacing the sacrificial member 212 with a conductor after stacking conductive layers 211, sacrificial member 212, and conductive layers 213. That is, the height of the sacrificial member 212 is the same as the height after connecting the conductive layer 21 and the semiconductor layer 41 within each memory pillar MP. Conductor layers 211 and 213, for example, each contain polycrystalline silicon (Si). The sacrificial member 212, for example, contains silicon nitride (SiN).

[0057] An insulating layer 301 is disposed on conductive layers 213 and 21. An insulating member 302 is disposed in a portion of the peripheral region PR and a portion of the wall region WR, respectively, penetrating the insulating layer 301, conductive layer 213, sacrificial member 212, and conductive layer 211. The upper surface of the insulating member 302 can be aligned with the upper surface of the insulating layer 301, or a step difference can be formed between the insulating member 302 and the insulating layer 301. The lower surface of the insulating member 302 can be aligned with the lower surface of the conductive layer 211, or it can be located at the height between the lower surface of the conductive layer 211 and the conductive layer 26 described below.

[0058] A conductive layer 303 is disposed on an insulating layer 301. Furthermore, the conductive layer 303 may have portions disposed on an insulating member 302 within the peripheral region PR and the wall region WR. The conductive layer 303 is interrupted (insulated) at least between the peripheral region PR and the wall region WR. The conductive layer 303 may also have portions continuously disposed between the core region CR and the peripheral region PR.

[0059] The wiring layer 300 includes a through-hole VA in the core region CR, a through-hole VB in the peripheral region PR, and a through-hole VC in the wall region WR. Through-hole VA penetrates the insulating layer 301. The conductive layer 303 in the core region CR is disposed along the through-hole VA and may have a portion connected to the conductive layer 21 via the through-hole VA. Through-hole VB penetrates the insulating member 302. The conductive layer 303 in the peripheral region PR is disposed along the through-hole VB and may have a portion connected to the contact C3 described below via the through-hole VB. The portion of the conductive layer 303 disposed in the through-hole VB is insulated from the conductive layers 211 and 213 by the insulating member 302. Through-hole VC penetrates the insulating member 302. The conductive layer 303 in the wall region WR is disposed along the through-hole VC and may have a portion connected to the sealing portions ES1 and ES2 described below via the through-hole VC. The portion of conductive layer 303 disposed in the through hole VC is insulated from conductive layers 211 and 213 by insulating member 302.

[0060] Insulating layers 304, 305, and 306 are sequentially disposed on insulating layer 301 or conductive layer 303. Each of insulating layers 304, 305, and 306 has portions disposed along vias VA, VB, and VC, respectively. Insulating layer 301, insulating member 302, and insulating layer 304, for example, each comprise a silicon oxide film (SiO2). Insulating layer 305, for example, comprises silicon nitride (SiN). Insulating layer 306, for example, comprises polyimide.

[0061] Within the core region CR, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0-C2. The bonding layer B1 includes a conductive layer 105. The gate insulating film 101 is disposed on the semiconductor substrate W1. The gate electrode 102 of the core region CR is disposed on the gate insulating film 101 and is used as the gate electrode of the transistor TR1. The transistor TR1 is included, for example, in the sense amplifier module 17. The conductive layer 103 is a wiring layer above the gate electrode 102. Contact C0 connects the gate electrode 102 and the conductive layer 103. Contact C1 connects the impurity diffusion region of the transistor TR1 disposed on the semiconductor substrate W1 to the conductive layer 103. The conductive layer 104 is a wiring layer disposed at the height between the conductive layer 103 and the bonding layer B1. Contact C2 is located at the height between conductive layer 103 and bonding layer B1. At least one conductive layer 103 is connected to conductive layer 105 via at least one contact C2 and at least one conductive layer 104. Conductive layer 105 corresponds to the bonding pad disposed on bonding layer B1. Conductive layer 105 is connected to conductive layer 25 disposed opposite to conductive layer 105 in bonding layer B2. Thereby, semiconductor layer 41 in core region CR is electrically connected to transistor TR1 via conductive layers 23-25 ​​and 103-105, and contacts CV, V1, V2, C1 and C2.

[0062] Similar to the core region CR, in the peripheral region PR, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductor layers 103 and 104, and contacts C0 to C2, and the bonding layer B1 includes a conductor layer 105. The gate electrode 102 of the peripheral region PR is used as the gate electrode of the transistor TR2. The transistor TR2 can be, for example, a transistor connected to a power line, or a transistor included in the input / output circuit 11. In the peripheral region PR, the bonding layer B2 includes a conductor layer 25, and the memory layer 200 includes conductor layers 24 and 26, and contacts V1, V2, and C3. The conductor layer 26 is a wiring disposed on the same layer as the conductor layer 23. At least one contact C3 is disposed on the conductor layer 26. The upper part of each contact C3 reaches at least the height of the conductor layer 211. Furthermore, the upper part of each contact C3 is covered by a conductive layer 303 and electrically connected to the conductive layer 303. In this way, the conductive layer 303 in the peripheral region PR is electrically connected to the transistor TR2 via at least one contact C3, conductive layers 24-26 and 103-105, and contacts V1, V2, C1 and C2.

[0063] Within the wall region WR, the memory device 1 includes contacts C1W, C2W, C3W, V1W, and V2W, and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W in each of the sealing portions ES1 and ES2. Contacts C1W, C2W, C3W, V1W, and V2W are disposed on the same layer as contacts C1, C2, C3, V1, and V2, respectively. Conductive layers 103W, 104W, 105W, 24W, 25W, and 26W are disposed on the same layer as conductive layers 103, 104, 105, 24, 25, and 26, respectively. The contacts C1W, C2W, C3W, V1W, and V2W, along with the conductive layers 103W, 104W, 105W, 24W, 25W, and 26W, are arranged in a ring shape when viewed from above, but the relevant illustrations are omitted. Specifically, the sealing portions ES1 and ES2 are each arranged in a square ring shape within the wall region WR, surrounding the outer perimeter of the core region CR, and also surrounding the peripheral region PR. Compared to sealing portion ES1, sealing portion ES2 is positioned further outward.

[0064] Within the wall region WR, the semiconductor substrate W1 includes a P-type well region PW and an N-type well region NW. The P-type well region PW is a diffusion region (p+) of P-type impurities disposed near the upper surface of the semiconductor substrate W1. The N-type well region NW is a diffusion region (n+) of N-type impurities disposed near the upper surface of the semiconductor substrate W1. The P-type well region PW and the N-type well region NW correspond to the sealing portions ES1 and ES2, respectively. Furthermore, the conductive layer 303 within the wall region WR is connected to the P-type well region PW via contacts C1W, C2W, C3W, V1W, and V2W corresponding to the sealing portion ES1, and conductive layers 103W, 104W, 105W, 24W, 25W, and 26W. Furthermore, the conductive layer 303 within the wall region WR is connected to the N-type well region NW via contacts C1W, C2W, C3W, V1W and V2W corresponding to the sealing part ES2, and conductive layers 103W, 104W, 105W, 24W, 25W and 26W.

[0065] The sealing portions ES1 and ES2 described above are structures that allow positive and negative charges generated inside and outside the wall region WR to dissipate to the semiconductor substrate W1. Furthermore, both sealing portions ES1 and ES2 can suppress the penetration of moisture and other substances from the outside of the wall region WR into the core region CR. Both sealing portions ES1 and ES2 can suppress stress generated on the interlayer insulating film (e.g., tetraethoxysilane (TEOS)) of the memory device 1. Additionally, both sealing portions ES1 and ES2 can be used as crack arresters.

[0066] (7: Wiring layer 300 planar layout) Figure 9 is a top view showing an example of the planar layout of the wiring layer 300 in the memory device 1 according to the first embodiment. Figure 9 illustrates the core region CR, the peripheral region PR, the wall region WR, and a portion of the wiring and pad portion PD. As shown in Figure 9, within the wall region WR, the sealing portion ES1 is provided in a manner that surrounds the outer periphery of the core region CR and the peripheral region PR. The sealing portion ES2 is provided in a manner that surrounds the outer periphery of the sealing portion ES1.

[0067] Inside the wall region WR, a plurality of conductive layers 303 are disposed. Each of the plurality of conductive layers 303 has a portion extending in the Y direction. The plurality of conductive layers 303 are arranged in the X direction. For example, the plurality of conductive layers 303 includes conductive layer 303A, which is used as part of the source line SL, and conductive layer 303B, which is used as part of the power line PL. Conductor layers 303A and 303B are, for example, alternately disposed. Conductor layer 303A, for example, corresponds to a conductive layer 303 having a portion connected to conductive layer 21 via via VA within the core region CR shown in FIG8. On the other hand, conductive layer 303B does not have a portion connected to conductive layer 21 via via VA.

[0068] A plurality of pad portions PD are disposed inside the wall region WR. One pad portion PD is connected to each conductive layer 303B. Power supply voltage, ground voltage, etc. are applied to the pad portions PD connected to the conductive layers 303B. On the other hand, the pad portions PD that do not overlap with conductive layers 303A and 303B are connected to interface circuits such as input / output circuit 11 and logic controller 12. The pad portions PD that do not overlap with conductive layers 303A and 303B are respectively overlapped with the core region CR and the peripheral region PR.

[0069] (8: Planar layout of solder pad section PD) Figure 10 is a top view showing an example of the planar layout near the solder pad PD in the memory device 1 of the first embodiment. Figure 10 shows a portion of the solder pad PD for connection to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1.

[0070] As shown in Figure 10, the pad portion PD overlaps with the core region CR and the surrounding region PR, respectively. Furthermore, the pad portion PD overlaps with the dummy region DA within the core region CR, but does not overlap with the active region AA. The pad portion PD includes a conductive portion MA, an insulating portion BA, a through-hole TV, and a through-hole VB.

[0071] The conductive portion MA, for example, includes a conductive layer 303. The conductive portion MA is rectangular in shape, for example, when viewed from above. The outer edge of the conductive portion MA corresponds to the outer edge of the solder pad portion PA. The insulating portion BA, for example, includes an insulating member 302. The insulating portion BA is rectangular in shape, for example, when viewed from above, and overlaps with the conductive portion MA. Compared to the outer edge of the conductive portion MA, the outer edge of the insulating portion BA is located further inward.

[0072] Through-holes TV and VB are rectangular in shape when viewed from above and overlap with conductive portion MA. Through-holes TV and VB are arranged in the Y direction. Compared to the outer edge of insulating portion BA, the outer edges of each through-hole TV and VB are located further inward. Through-hole TV is contained within the dummy region DA and the peripheral region PR. Therefore, the boundary between the dummy region DA and the peripheral region PR overlaps with the through-hole TV when viewed from above. A portion of conductive portion MA is exposed through through-hole TV. The portion of conductive portion MA exposed through through-hole TV corresponds to the solder pads used to connect memory device 1 and memory controller 2. Through-hole VB is contained within the peripheral region PR and is disposed through a portion of insulating portion BA. Conductive portion MA is electrically connected via through-hole VB to a plurality of contacts C3 arranged in a manner overlapping with through-hole VB.

[0073] (9: Cross-sectional structure of the solder pad portion PD) Figure 11 is a cross-sectional view along line XI-XI of Figure 10, showing an example of the cross-sectional structure near the solder pad portion PD in the memory device 1 of the first embodiment. As shown in Figure 11, in the memory device 1, the laminate corresponding to the memory cell array 10, within the dummy region DA, includes an insulating layer 32 and a conductive layer 22 alternately laminated in the Z direction, or an insulating layer 32 and a sacrificial member SM alternately laminated in the Z direction. The material of the sacrificial member SM is different from that of the insulating layer 32 and the conductive layer 22. The dummy step portion DS, for example, includes an insulating layer 32 and a sacrificial member SM alternately laminated in the Z direction. In other words, the laminate corresponding to the memory cell array 10, within the dummy region DA, has a laminate portion formed by the alternating laminated insulating layer 32 and sacrificial member SM in the Z direction. Moreover, in this laminate portion, the ends of the laminated sacrificial members SM are provided in a stepped shape. Multiple dummy pillars DMP are located within the dummy region DA, and penetrate the stacked volume corresponding to the memory cell array 10 in the Z direction.

[0074] The through-hole TV penetrates the insulating layers 304, 305, and 306. At the bottom of the through-hole TV, a portion of the conductive layer 303 corresponding to the conductive portion MA is exposed. Furthermore, the insulating member 302 corresponding to the insulating portion BA is provided at the same height as the source line SL and is provided in the region overlapping with the through-hole TV in the Z direction. Therefore, conductive layers 21, 211, and 213 are not provided in the region overlapping with the through-hole TV in the Z direction. In other words, the portion of the conductive layer 303 corresponding to the conductive portion MA that is exposed through the through-hole TV does not have a portion overlapping with conductive layers 21, 211, and 213 in the Z direction. In the memory device 1 of the first embodiment, at least the source line SL between the dummy step portion DS and the conductive layer 303 is removed.

[0075] The conductive layer 303 corresponding to the conductive portion MA has a portion disposed along the via VB and connected to a plurality of contacts C3 via the via VB. Furthermore, the conductive layer 303 corresponding to the conductive portion MA is electrically connected to the transistor TR2 on the semiconductor substrate W1 via the plurality of contacts C3. In other words, the pad corresponding to the conductive portion MA is electrically connected via the memory layer 200 to the interface circuitry (e.g., input / output circuitry 11 and logic controller 12) included in the CMOS circuitry disposed on the CMOS layer 100.

[0076] Furthermore, when a step difference is formed between the insulating layer 301 and the insulating member 302, the conductive layer 303 may have a portion disposed along the step difference formed between the insulating layer 301 and the insulating member 302. The through-hole TV may have a portion facing at least the dummy step portion DS in the Z direction, and a portion facing the dummy pillar DMP in the Z direction. The insulating portion BA may be disposed in such a way that a portion of the dummy pillar DMP is removed, or it may be disposed in such a way that a portion of the dummy step portion DS is removed.

[0077] In the memory device 1 described above, the memory layer 200 is disposed in the same layer as the source line SL within the peripheral region PR, and has a first sublayer (e.g., conductor layer 211) containing a material as the main component that is at least a portion of the source line SL, and a second sublayer (e.g., conductor layer 213) disposed above the first sublayer with a spacer member (e.g., sacrificial member 212). Furthermore, the via TV does not have any portion overlapping the first sublayer and the second sublayer in the Z direction.

[0078] Furthermore, a conductive layer 303 is disposed above the source line SL in the Z direction, including a portion corresponding to the pad (via TV), and is electrically connected to the CMOS circuit on the semiconductor substrate W1. The conductive layer 303 has a portion overlapping the dummy pillar DMP in the Z direction. This portion of the conductive layer 303 is not separated from the source line SL, but is separated from the insulating member 302 disposed at the same height as the source line SL, and faces the dummy pillar DMP in the Z direction. The pad (via TV) has a portion overlapping the dummy pillar DMP in the Z direction, but does not have a portion overlapping the source line SL in the Z direction. An insulating layer 304 is disposed to cover the upper part of the conductive layer 303. A via TV is disposed in the insulating layer 304 such that the surface of the portion of the conductive layer 303 corresponding to the pad is exposed. The memory layer 200 further includes: an insulating layer 210 disposed around the stacked layer corresponding to the memory cell array 10 in top view; and at least one contact C3, wherein a portion disposed at the same height as the stacked layer extends in the Z direction within the insulating layer 210 and is electrically connected to the CMOS circuit. The conductive layer 303 further has a portion electrically connected to the at least one contact C3.

[0079] <1-2> Manufacturing Method Next, regarding the manufacturing method of the memory device 1 according to the first embodiment, the method for forming the solder pad portion PD after bonding the semiconductor substrate W1 and the semiconductor substrate W2 will be described with reference to FIG12. FIG12 is a flowchart showing an example of the manufacturing method of the memory device 1 according to the first embodiment. FIG13 to FIG17 are cross-sectional views showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment during the manufacturing process, showing a cross-section including the area near the solder pad portion PD.

[0080] First, semiconductor substrate W2 is removed from the bonded semiconductor substrates W1 and W2 (step ST11). For example, CMP (Chemical Mechanical Polishing) is used to remove semiconductor substrate W2. After removing semiconductor substrate W2, an insulating layer 301 is formed as shown in FIG13. Alternatively, insulating layer 301 can be pre-formed between semiconductor substrate W2 and conductive layer 21. In this case, the surface of insulating layer 301 will be exposed by the process of step ST11.

[0081] Next, as shown in Figure 14, the opening BAH is formed (step ST12). Specifically, first, a mask is formed to partially open the insulating portion BA as viewed from above. Then, by anisotropic etching, the insulating layer 301, conductive layers 21, 211, and 213, and the sacrificial member 202 are removed from the opening of the mask to form the opening BAH. At the opening BAH, the upper parts of a plurality of dummy pillars DMP and the upper parts of a plurality of contacts C3 are exposed. The upper parts of each of the plurality of dummy pillars DMP and the plurality of contacts C3 may remain in the opening BAH in a protruding shape.

[0082] Next, as shown in Figure 15, an insulating member 302 is formed in the opening BAH (step ST13). Specifically, firstly, the insulating member 302 is formed by filling the opening BAH. Then, for example, by CMP treatment, the insulating member 302 formed outside the opening BAH is removed. In this way, the insulating member 302 remaining in the opening BAH corresponds to the insulating portion BA. Furthermore, the CMP treatment in step ST13 can also be used to maintain a step difference between the insulating layer 301 and the insulating member 302.

[0083] Next, as shown in Figure 16, a through-hole VB is formed (step ST14). Specifically, firstly, a mask is formed to partially open the through-hole VB in top view. Then, by anisotropic etching, the insulating member 302 is removed from the opening of the mask to form the through-hole VB. At the through-hole VB, the upper parts of several contacts C3 are exposed.

[0084] Next, as shown in FIG17, a conductive layer 303 is formed (step ST15). Specifically, for example, firstly, a conductive layer 303 is formed by CVD (Chemical Vapor Deposition) and a mask covering the conductive portion MA is formed. Then, an anisotropic etching process is performed to process the conductive layer 303 into the shape of the conductive portion MA.

[0085] Next, insulating layers 304, 305, and 306 are formed (step ST16), and through-holes TV are formed (step ST17). At this point, the structure corresponding to the solder pad portion PD shown in Figure 11 is completed.

[0086] <1-3> Effects of the first implementation method The memory device 1 according to the first embodiment described above can suppress interface speed degradation and reduce chip size. Hereinafter, the effects of the memory device 1 according to the first embodiment will be explained using a first comparative example and a second comparative example.

[0087] Figure 18 is a top view showing an example of the planar layout near the solder pad portion PDy in the memory device 1Y of the first comparative example. As shown in Figure 18, the solder pad portion PDy in the memory device 1Y of the first comparative example is contained in the peripheral region PR and is far from the core region CR. Moreover, unlike the solder pad portion PD, the solder pad portion PDy does not have an insulating portion BA.

[0088] Figure 19 is a cross-sectional view along line XIX-XIX of Figure 18, showing an example of the cross-sectional structure near the solder pad PDy in the memory device 1Y of the first comparative example. As shown in Figure 19, in the memory device 1Y, the insulating member 302 is replaced by an insulating layer 307. The insulating layer 307 is disposed on the insulating layer 301 and has a portion disposed along the opening BAH and the via VB. The conductive layer 303 corresponding to the conductive part MA is disposed along the insulating layer 307 and is connected to a plurality of contacts C3 via the via VB. In the memory device 1Y, the structure corresponding to the source line SL below the via TV is removed. This suppresses the parasitic capacitance between the conductive part MA and the source line SL. On the other hand, depending on the layout of the solder pad PDy, the chip size of the memory device 1Y may increase.

[0089] Figure 20 is a top view showing an example of the planar layout near the solder pad portion PDz in the memory device 1Z of the second comparative example. As shown in Figure 20, the solder pad portion PDz in the memory device 1Z of the second comparative example, like in the first embodiment, has a portion that overlaps with the dummy area DA. On the other hand, the insulating portion BA in the solder pad portion PDz is arranged in a manner that does not overlap with the through-hole TV when viewed from above.

[0090] Figure 21 is a cross-sectional view along line XXI-XXI of Figure 20, showing an example of the cross-sectional structure near the pad portion PDz in the memory device 1Z of the second comparative example. As shown in Figure 21, in the memory device 1Z, the via TV is arranged to overlap with the dummy region DA (e.g., the dummy step portion DS). On the other hand, unlike the first embodiment, the memory device 1Z has a conductive layer 21, or conductive layers 211 and 213 disposed in the portion facing the via TV in the Z direction. Therefore, in the memory device 1Z, the chip size can be reduced compared to the first comparative example, but the parasitic capacitance between the conductive portion MA and the source line SL may increase. Therefore, in the second comparative example, there is a risk of interface speed degradation compared to the first comparative example.

[0091] In contrast, the memory device 1 of the first embodiment has a structure in which the source line SL is removed in the region where the end of the memory cell array 10 (dummy region DA) overlaps with the pad portion PD, and an insulating member 302 is embedded in this region. Specifically, in the memory device 1 of the first embodiment, the memory layer 200 includes: a laminate containing an insulating layer 32 and a conductive layer 22 alternately laminated in the Z direction in the effective region AA, and a sacrificial member SM disposed in the same layer as the conductive layer 22 in the dummy region DA; a plurality of memory pillars MP and a plurality of dummy pillars DMP, which penetrate the laminate; and a source line SL (conductive layer 21) connected above the laminate to the plurality of memory pillars MP. Moreover, the pad (via TV) corresponding to a portion of the conductive portion MA exposed at the via TV has a portion overlapping the sacrificial member SM in the Z direction, but does not have a portion overlapping the source line SL in the Z direction.

[0092] Therefore, in the memory device 1 of the first embodiment, the parasitic capacitance between the conductive portion MA and the source line SL, i.e., the parasitic capacitance of the solder pad, can be reduced. Furthermore, regarding the chip size of the memory device 1 of the first embodiment, since the solder pad portion PD and the dummy region DA overlap in the Z direction, it can be reduced in size, similar to the second comparative example. Thus, the memory device 1 of the first embodiment can suppress interface speed degradation and reduce chip size.

[0093] <2> Implementation Method 2 The memory device 1A of the second embodiment has a structure in which, instead of forming a through-hole VB as described in the first embodiment, a contact VBP is formed through the insulating member 302, and the conductive layer 303 and the contact C3 are electrically connected via the contact VBP. The details of the memory device 1A of the second embodiment will be described below.

[0094] <2-1> Composition The memory device 1A of the second embodiment has the same structure as the memory device 1 of the first embodiment, except for the structure of the solder pad portion PD. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDa in the memory device 1A of the second embodiment will be described.

[0095] [] <2-1-1> Planar Layout of PDA for Solder Pads Figure 22 is a top view showing an example of the planar layout near the solder pad PDa in the memory device 1A of the second embodiment. Figure 22 shows a portion of the solder pad PDa, which is used to connect to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1A.

[0096] As shown in Figure 22, the pad portion PDa overlaps with both the core region CR and the surrounding region PR. Furthermore, the pad portion PDa overlaps with the dummy region DA within the core region CR, but not with the effective region AA. The pad portion PDa includes a conductive portion MA, an insulating portion BA, a through-hole TV, and multiple contacts VBP.

[0097] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDA are each configured the same as in the pad portion PD of the first embodiment. A plurality of contacts VBP are each included in the peripheral region PR, and are disposed through a portion of the insulating portion BA. The region where the plurality of contacts VBP are formed is adjacent to the through-hole TV in the Y direction, and is arranged in a manner that does not overlap with the through-hole TV. The plurality of contacts VBP are arranged, for example, in a grid pattern. The plurality of contacts VBP overlap with a plurality of contacts C3. One set of overlapping contacts VBP and contacts C3 are electrically connected.

[0098] [] <2-1-2> Cross-sectional structure of the pad PDA Figure 23 is a cross-sectional view along line XXIII-XXIII of Figure 22, showing an example of the cross-sectional structure near the solder pad portion PDa in the memory device 1A of the second embodiment. As shown in Figure 23, the solder pad portion PDa has the same structure as the solder pad portion PD described in Figure 11 of the first embodiment, except that the through hole VB is omitted and a plurality of contacts VBP are added. The plurality of contacts VBP are respectively provided through the insulating member 302 corresponding to the insulating portion BA. The bottom of each of the plurality of contacts VBP is connected to the upper part of the contacts C3 which are arranged overlapping in the Z direction. In the solder pad portion PDa, the upper surface of the insulating member 302, the upper surface of the contacts VBP, and the upper surface of the insulating layer 301 are aligned.

[0099] A conductive layer 303 corresponding to the conductive portion MA is disposed on the upper surface of the planarized insulating member 302 and the contact VBP. In the second embodiment, the conductive portion MA does not have a step difference at the interface between the insulating layer 301 and the insulating member 302. The other configurations of the pad portion PDa are the same as those of the pad portion PD in the first embodiment.

[0100] <2-2> Manufacturing Method Next, regarding the manufacturing method of the memory device 1A according to the second embodiment, the method for forming the solder pad PDa after bonding the semiconductor substrate W1 and the semiconductor substrate W2 will be described with reference to FIG24. FIG24 is a flowchart showing an example of the manufacturing method of the memory device 1A according to the second embodiment. FIG25 to FIG27 are cross-sectional views showing an example of the cross-sectional structure of the memory device 1A according to the second embodiment during the manufacturing process, showing the cross-section including the vicinity of the solder pad PDa.

[0101] First, similar to the first embodiment, the semiconductor substrate W2 is removed (step ST11), an opening BAH is formed (step ST12), and an insulating member 302 is formed in the opening BAH (step ST13).

[0102] Next, as shown in Figure 25, a plurality of holes VBH are formed (step ST21). Specifically, first, a mask is formed that partially overlaps with the openings of each contact C3 in a top view. Then, an anisotropic etching process is performed to remove the insulating member 302 at the openings of the mask, forming a plurality of holes VBH. At the bottom of each hole VBH, the upper part of the corresponding contact C3 is exposed.

[0103] Subsequently, as shown in Figure 26, conductive members 310 are formed in each hole VBH (step ST22). Specifically, firstly, conductive members 310 are formed by filling each hole VBH using methods such as CVD. Then, for example, by CMP processing, the conductive members 310 formed on the outside of each hole VBH are removed to form a plurality of contacts VBP. Through this CMP processing, the upper surface of the conductive members 310 (contacts VBP) in each hole VBH, the upper surface of the insulating member 302, and the upper surface of the insulating layer 301 are aligned.

[0104] Next, as shown in FIG27, a conductive layer 303 is formed (step ST23). Specifically, for example, firstly, a conductive layer 303 is formed, and a mask covering the portion of the conductive part MA is formed. Then, an anisotropic etching process is performed to process the conductive layer 303 into the shape of the conductive part MA.

[0105] Subsequently, similar to the first embodiment, insulating layers 304, 305, and 306 are formed (step ST16), and through-hole TV is formed (step ST17). At this point, the structure corresponding to the solder pad portion PDa shown in FIG23 is completed.

[0106] <2-3> Effects of the second implementation method The memory device 1A of the second embodiment, like the one of the first embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DA is removed, and the dummy region DA and the pad portion PDa overlap in the Z direction. Therefore, the memory device 1A of the second embodiment, like the one of the first embodiment, can reduce the parasitic capacitance of the pads, suppress interface speed degradation, and reduce the chip size.

[0107] Furthermore, in the memory device 1A of the second embodiment, the connection between the conductive portion MA and the contact C3 is not achieved using a through-hole VB as in the first embodiment, but rather using a contact VBP. Moreover, in the memory device 1A, when the contact VBP is formed, the upper surfaces of both the insulating portion BA and the contact VBP are planarized. As a result, the memory device 1A of the second embodiment can suppress defects caused by the step difference of the conductive portion MA formed along the through-hole VB as in the first embodiment. Therefore, compared to the first embodiment, the memory device 1A of the second embodiment can improve yield.

[0108] <3> Third implementation method The memory device 1B according to the third embodiment has a structure in which a conductive member 320 is formed to cover the upper part of the plurality of contacts C3 described in the first embodiment, and the conductive layer 303 is electrically connected to each contact C3 via the conductive member 320. The details of the memory device 1B according to the third embodiment will be described below.

[0109] <3-1> Composition The memory device 1B of the third embodiment has the same structure as the memory device 1 of the first embodiment, except for the structure of the solder pad portion PD. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDb in the memory device 1B of the third embodiment will be described.

[0110] [] <3-1-1> Planar Layout of the Pad Section PDb Figure 28 is a top view showing an example of the planar layout near the solder pad PDb in the memory device 1B according to the third embodiment. Figure 28 shows a portion of the solder pad PDb for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1B.

[0111] As shown in Figure 28, the pad portion PDb overlaps with the core region CR and the surrounding region PR, respectively. Furthermore, the pad portion PDb overlaps with the dummy region DA within the core region CR, but not with the effective region AA. The pad portion PDb includes a conductive portion MA, an insulating portion BA, a through-hole TV, a conductive portion ZB, and multiple through-holes VBa.

[0112] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDb are each configured the same as in the pad portion PD of the first embodiment. The conductive portion ZB is contained in the peripheral region PR and is arranged overlapping the conductive portion MA and insulating portion BA, respectively. Furthermore, the conductive portion ZB is adjacent to the through-hole TV in the Y direction, but is arranged in a manner that does not overlap with the through-hole TV. The conductive portion ZB is connected to a plurality of contacts C3 electrically connected to the conductive portion MA. The plurality of through-holes VBa are arranged overlapping the conductive portion ZB in top view and are provided to penetrate a portion of the insulating portion BA. The plurality of through-holes VBa are, for example, arranged in a grid pattern. The conductive portion MA is electrically connected to the conductive portion ZB via the plurality of through-holes VBa. That is, the conductive portion MA is electrically connected to the plurality of contacts C3 via the conductive portion ZB.

[0113] [] <3-1-2> Cross-sectional structure of the solder pad PDb Figure 29 is a cross-sectional view along line XXIX-XXIX of Figure 28, showing an example of the cross-sectional structure near the solder pad portion PDb in the memory device 1B of the third embodiment. As shown in Figure 29, the solder pad portion PDb has the configuration where the through-hole VB is replaced by a plurality of through-holes VBa, and a conductive portion ZB is added, as described in Figure 11 of the first embodiment. The conductive member 320 corresponding to the conductive portion ZB is provided to cover the upper part of the plurality of contacts C3. Furthermore, the upper part of the conductive member 320 has a portion covered by an insulating member 302 corresponding to the insulating portion BA. The plurality of through-holes VBa penetrate the insulating member 302. Moreover, the bottom of each of the plurality of through-holes VBa reaches the conductive member 320.

[0114] A conductive layer 303 corresponding to the conductive portion MA is disposed on the insulating member 302, and has a portion disposed along a plurality of through holes VBa. Furthermore, the conductive layer 303 is embedded in the plurality of through holes VBa and is connected to the conductive member 320 at the bottom of the through holes VBa. Additionally, the conductive layer 303 is electrically connected to a plurality of contacts C3 via the conductive member 320, and is electrically connected to the transistor TR2 via the plurality of contacts C3. The conductive layer 303 may also have a concave portion above the through holes VBa. The other configurations of the pad portion PDb are the same as those of the pad portion PD in the first embodiment.

[0115] <3-2> Manufacturing Method Next, regarding the manufacturing method of the memory device 1B according to the third embodiment, the method for forming the solder pad portion PDb after bonding the semiconductor substrate W1 and the semiconductor substrate W2 will be described with reference to FIG30. FIG30 is a flowchart showing an example of the manufacturing method of the memory device 1B according to the third embodiment. FIG31 to FIG34 are cross-sectional views showing an example of the cross-sectional structure of the memory device 1B during the manufacturing process of the third embodiment, showing a cross-section including the area near the solder pad portion PDb.

[0116] First, similar to the first embodiment, the semiconductor substrate W2 is removed (step ST11) to form the opening BAH (step ST12).

[0117] Subsequently, as shown in FIG31, a conductive member 320 is formed in a portion of the opening BAH (step ST31). Specifically, for example, firstly, the conductive member 320 is formed by CVD or the like, and a mask is formed covering the portion of the conductive part ZB. Then, an anisotropic etching process is performed to process the conductive member 320 into the shape of the conductive part ZB.

[0118] Subsequently, as shown in Figure 32, an insulating member 302 is formed in the opening BAH (step ST32). Specifically, firstly, the insulating member 302 is formed by filling the opening BAH. Then, for example, by CMP treatment, the insulating member 302 formed outside the opening BAH is removed. The insulating member 302 remaining in the opening BAH corresponds to the insulating portion BA. Furthermore, the CMP treatment in step ST32 can also be used to maintain a step difference between the insulating layer 301 and the insulating member 302.

[0119] Next, as shown in Figure 33, the via VBa is formed (step ST33). Specifically, first, a mask is formed to partially open the via VBa in top view. Then, by anisotropic etching, the insulating member 302 is removed from the opening of the mask to form the via VBa. At the via VBa, the upper part of the conductive portion ZB is exposed.

[0120] Next, as shown in FIG34, a conductive layer 303 is formed (step ST34). Specifically, for example, firstly, the conductive layer 303 is formed by embedding it into a via VBa using CVD or the like, and a mask covering the portion of the conductive part MA is formed. Afterward, an anisotropic etching process is performed to process the conductive layer 303 into the shape of the conductive part MA.

[0121] Subsequently, similar to the first embodiment, insulating layers 304, 305, and 306 are formed (step ST16), and through-holes TV are formed (step ST17). At this point, the structure corresponding to the solder pad portion PDb shown in FIG29 is completed.

[0122] <3-3> Effects of the Third Implementation Method The memory device 1B of the third embodiment, like that of the first embodiment, has a structure in which the structure corresponding to the source line SL in the dummy region DA is removed, and the dummy region DA and the pad portion PDb overlap in the Z direction. Therefore, the memory device 1B of the third embodiment, like that of the first embodiment, can reduce the parasitic capacitance of the pad, suppress interface speed degradation, and reduce the chip size.

[0123] Furthermore, in the memory device 1B of the third embodiment, the conductive part MA and the contact C3 are connected via the conductive part ZB. This provides a more reliable electrical connection between the conductive layer 303 and the contact C3 compared to the case where the conductive layer 303 is directly connected to the protrusion of the contact C3. Therefore, the memory device 1B of the third embodiment also improves yield compared to the first embodiment.

[0124] <4> Implementation Method 4 The memory device 1C of the fourth embodiment, compared with the memory device 1A of the second embodiment, has a structure in which the region forming the contacts VBP and C3 and the region forming the via TV overlap in the Z direction. The details of the memory device 1C of the fourth embodiment will be described below.

[0125] <4-1> Composition The memory device 1C of the fourth embodiment has the same structure as the memory device 1A of the second embodiment, except for the structure of the solder pad portion PDa. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDc in the memory device 1C of the fourth embodiment will be described.

[0126] [] <4-1-1> Planar Layout of PDC for Solder Pads Figure 35 is a top view showing an example of the planar layout near the solder pad PDc in the memory device 1C of the fourth embodiment. Figure 35 shows a portion of the solder pad PDc for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1C.

[0127] As shown in Figure 35, the pad portion PDc overlaps with both the core region CR and the surrounding region PR. Furthermore, the pad portion PDc overlaps with the dummy region DA within the core region CR, but not with the active region AA. The pad portion PDc includes a conductive portion MA, an insulating portion BA, a through-hole TV, and multiple contacts VBP.

[0128] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDc are each configured the same as those in the pad portion PDA of the second embodiment. A plurality of contacts VBP are each included in the peripheral region PR, and are disposed through a portion of the insulating portion BA. Furthermore, the region where the plurality of contacts VBP are formed overlaps with the through-hole TV when viewed from above. The plurality of contacts VBP overlaps with a plurality of contacts C3. A set of overlapping contacts VBP and contacts C3 are electrically connected.

[0129] [] <4-1-2> Cross-sectional structure of the solder pad PDC Figure 36 is a cross-sectional view along line XXXVI-XXXVI of Figure 35, showing an example of the cross-sectional structure near the solder pad portion PDc in the memory device 1C of the fourth embodiment. As shown in Figure 36, the solder pad portion PDc has the configuration in which a plurality of contacts VBP and vias TV are arranged overlapping in the Z direction within the solder pad portion PDa described in Figure 23 of the second embodiment. Therefore, compared with the solder pad portion PDa of the second embodiment, the solder pad portion PDc of the fourth embodiment can be designed to be smaller. The other configurations of the solder pad portion PDc are the same as those of the solder pad portion PDa of the second embodiment.

[0130] <4-2> Manufacturing Method The manufacturing method of the memory device 1C in the fourth embodiment is the same as that of the manufacturing method of the memory device 1A in the second embodiment described using Figures 24 to 27, except that the regions forming the contacts VBP and C3 and the regions forming the through-hole TV are arranged to overlap in the Z direction.

[0131] <4-3> Effects of the fourth implementation method The memory device 1C of the fourth embodiment, like that of the first embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DA is removed, and the dummy region DA and the pad portion PDc overlap in the Z direction. Therefore, the memory device 1C of the fourth embodiment, like that of the first embodiment, can reduce the parasitic capacitance of the pad, suppress interface speed degradation, and reduce the chip size.

[0132] Furthermore, in the memory device 1C of the fourth embodiment, the through-hole TV and the plurality of contacts VBP are arranged overlapping in the Z direction. Therefore, compared to the memory device 1A of the second embodiment, the memory device 1C of the fourth embodiment can reduce the chip area. As a result, compared to the memory device 1A of the second embodiment, the memory device 1C of the fourth embodiment can reduce manufacturing costs.

[0133] <5> Fifth Implementation The memory device 1D of the fifth embodiment has a structure in which the area where a plurality of contacts C3 and conductive members 320 are formed overlaps with the area where a through hole TV is formed in the third embodiment of the memory device 1B in the Z direction. The details of the memory device 1D of the fifth embodiment will be described below.

[0134] <5-1> Composition The memory device 1D of the fifth embodiment has the same structure as the memory device 1B of the third embodiment, except for the structure of the solder pad portion PDb. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDd in the memory device 1D of the fifth embodiment will be described.

[0135] [] <5-1-1> Planar Layout of the Pad Section PDd Figure 37 is a top view showing an example of the planar layout near the solder pad PDd in the memory device 1D of the fifth embodiment. Figure 37 shows a portion of the solder pad PDd for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1D.

[0136] As shown in Figure 37, the pad portion PDd overlaps with the core region CR and the surrounding region PR, respectively. Furthermore, the pad portion PDd overlaps with the dummy region DA within the core region CR, but not with the effective region AA. The pad portion PDd includes a conductive portion MA, an insulating portion BA, a through-hole TV, a conductive portion ZB, and multiple through-holes VBa.

[0137] The conductive portion MA, insulating portion BA, and through-hole TV in the pad portion PDd are configured the same as those in the pad portion PDb of the third embodiment. The conductive portion ZB is contained in the peripheral region PR and is disposed overlapping the conductive portion MA and the insulating portion BA. Furthermore, the conductive portion ZB overlaps with the through-hole TV when viewed from above. The conductive portion ZB is connected to a plurality of contacts C3 electrically connected to the conductive portion MA. A plurality of through-holes VBa are disposed overlapping the conductive portion ZB when viewed from above and are provided to penetrate a portion of the insulating portion BA. The conductive portion MA is electrically connected to the conductive portion ZB via the plurality of through-holes VBa. That is, the conductive portion MA is electrically connected to the plurality of contacts C3 via the conductive portion ZB.

[0138] [] <5-1-2> Cross-sectional structure of the solder pad PDd Figure 38 is a cross-sectional view along line XXXVIII-XXXVIII of Figure 37, showing an example of the cross-sectional structure near the solder pad PDd in the memory device 1D of the fifth embodiment. As shown in Figure 38, the solder pad PDd has the configuration in the solder pad PDb described in Figure 29 of the third embodiment, where the conductive portion ZB and the via TV are arranged overlapping in the Z direction. Therefore, compared with the solder pad PDb of the third embodiment, the solder pad PDd of the fifth embodiment can be designed to be smaller. The other configurations of the solder pad PDd are the same as those of the solder pad PDb of the third embodiment.

[0139] <5-2> Manufacturing Method The manufacturing method of the memory device 1D in the fifth embodiment is the same as that in the manufacturing method of the memory device 1B in the third embodiment described using Figures 30 to 34, except that the areas where the conductive part ZB and the contact C3 are formed overlap with the area where the through hole TV is formed in the Z direction.

[0140] <5-3> Effects of the 5th Implementation Method The memory device 1D of the fifth embodiment, like that of the first embodiment, has a structure in which the structure corresponding to the source line SL in the dummy region DA is removed, and the dummy region DA and the pad portion PDd overlap in the Z direction. Therefore, the memory device 1D of the fifth embodiment, like that of the first embodiment, can reduce the parasitic capacitance of the pad, suppress interface speed degradation, and reduce the chip size.

[0141] Furthermore, in the memory device 1D of the fifth embodiment, the through-hole TV and the conductive portion ZB are arranged overlapping in the Z direction. Therefore, compared to the memory device 1B of the third embodiment, the memory device 1D of the fifth embodiment can reduce the chip area. As a result, compared to the memory device 1B of the third embodiment, the memory device 1D of the fifth embodiment can reduce manufacturing costs.

[0142] <6> Implementation Method 6 The sixth embodiment relates to a memory device that uses a source line SL with a structure different from that of the memory device 1E in the first embodiment. Details of the memory device 1E in the sixth embodiment will be described below.

[0143] <6-1> Composition The memory device 1E of the sixth embodiment has the same configuration as the memory device 1 of the first embodiment, except for the source line SL. Hereinafter, the cross-sectional structure of the memory cell array 10 and the planar layout and cross-sectional structure of the pad portion PD in the memory device 1E of the sixth embodiment will be described.

[0144] <6-1-1> Cross-sectional structure of memory cell array 10 Figure 39 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 10 provided in the memory device 1E according to the sixth embodiment. Figure 39 shows an example of the structure of the memory cell array 10 formed on the semiconductor substrate W2 before bonding with the semiconductor substrate W1, and the coordinate axis with the semiconductor substrate W2 as the reference is marked. The area shown in Figure 39 corresponds to the same area as in Figure 6 described in the first embodiment. As shown in Figure 39, in the memory device 1E, the memory cell array 10 formed on the semiconductor substrate W2 before bonding with the semiconductor substrate W1 has, for example, the structure in the memory cell array 10 of the first embodiment, in which the conductor layer 21 is replaced by a semiconductor layer 214, a member 215, and a semiconductor layer 216.

[0145] Semiconductor layer 216 is disposed on semiconductor substrate W2, for example, with insulating layer 301 in between. Member 215 is disposed on semiconductor layer 216. Semiconductor layer 214 is disposed on member 215. Insulator layer 31 is disposed on semiconductor layer 214. Semiconductor layers 214 and 216 are, for example, amorphous silicon. Semiconductor layer 216 is used, for example, as an etch stop layer when forming memory pillars MP and slits SLT. For example, memory pillars MP and slits SLT penetrate semiconductor layer 214. Furthermore, the bottom of each memory pillar MP and slit SLT reaches semiconductor layer 216. The other structures of the memory cell array 10 of the sixth embodiment are the same as those of the memory cell array 10 of the first embodiment.

[0146] [] <6-1-2> Planar Layout of the Solder Pad Part PD Figure 40 is a top view showing an example of the planar layout near the solder pad PD in the memory device 1E according to the sixth embodiment. Figure 40 shows a portion of the solder pad PD for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1E.

[0147] As shown in Figure 40, the memory device 1E has a configuration in which the effective region AA and the dummy region DA of the core region CR are replaced with effective region AAa and dummy region DAa, respectively, in the memory device 1 of the first embodiment. Within the effective region AAa and the dummy region DAa, the structures of the portions corresponding to the source line SL are different from those of the effective region AA and the dummy region DA, respectively. The detailed structure of the source line SL in the memory device 1E will be described below. The pad portion PD of the sixth embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PD of the sixth embodiment has a portion that overlaps with the dummy region DAa in the core region CR, but does not have a portion that overlaps with the effective region AAa. The pad portion PD of the sixth embodiment, like the pad portion PD of the first embodiment, includes a conductive portion MA, an insulating portion BA, a through-hole TV, and a through-hole VB.

[0148] [] <6-1-3> Cross-sectional structure near the pad PD Figure 41 is a cross-sectional view along line XLI-XLI of Figure 40, showing an example of the cross-sectional structure near the solder pad PD in the memory device 1E of the sixth embodiment. Figure 41 shows a portion of the effective region AAa, the dummy region DAa, and the peripheral region PR after the semiconductor substrates W1 and W2 are bonded and a wiring layer 300 is formed, and the coordinate axes with the semiconductor substrate W1 as the reference are marked. Furthermore, in the memory device 1E, the structure within the wall region WR is similar to that of the peripheral region PR, therefore the description of the structure within the wall region WR is omitted.

[0149] As shown in Figure 41, in the memory device 1E, the laminated film 42 on the upper part of the memory column MP is removed. Also, the laminated film 42 on the upper part of the dummy column DMP is removed. In the active region AAa, the dummy region DAa, and the peripheral region PR, a semiconductor layer 214 is provided on the laminated body or insulating layer 210 corresponding to the memory cell array 10. On the semiconductor layer 214, in the portion of the peripheral region PR and the portion of the peripheral region PR of the dummy region DAa, a member 215, a semiconductor layer 216, and an insulating layer 301 are sequentially provided. Furthermore, on the semiconductor layer 214, in the portion of the active region AAa and the portion of the dummy region DAa on the active region AAa side, a semiconductor layer 217, a conductive layer 218, and an insulating layer 330 are sequentially provided.

[0150] Semiconductor layers 214, 216, and 217 are, for example, polycrystalline silicon. Semiconductor layer 217 is doped with impurities. Therefore, semiconductor layer 217 functions as a conductor. When impurities are doped into semiconductor layer 217, the impurities may diffuse into semiconductor layer 214 within the effective region AAa. Therefore, semiconductor layer 214 within the effective region AAa may contain impurities and function as a conductor. On the other hand, when impurities are doped into semiconductor layer 217, the peripheral region PR is excluded from the region where impurities are doped. Therefore, semiconductor layer 214 within the peripheral region PR does not contain such impurities.

[0151] Semiconductor layer 217 is disposed such that it covers the semiconductor layer 41 above each memory pillar MP, the semiconductor layer 41 above each dummy pillar DMP (not shown), and the upper part of the slit SLT. Therefore, conductor layer 217 and conductor layer 218 each have portions disposed along the upper parts of the memory pillar MP, dummy pillar DMP, and slit SLT. Furthermore, semiconductor layer 217 is electrically connected to the semiconductor layer 41 of each memory pillar MP. In memory device 1E, the group of semiconductor layers 214 and 217 and conductor layer 218 functions as part of the source line SL. The upper surface of insulating layer 330 is aligned, for example, with the upper surface of insulating layer 301 within the peripheral region PR.

[0152] The insulating member 302 of the memory device 1E is disposed within a portion of the peripheral region PR, penetrating the insulating layer 301, the semiconductor layer 216, the component 215, and the semiconductor layer 214. Furthermore, the insulating member 302 is disposed within a portion of the dummy region DAa, penetrating the insulating layer 330, the conductive layer 218, the semiconductor layer 217, and the semiconductor layer 214. The upper surface of the insulating member 302 can be aligned with the upper surfaces of the insulating layers 301 and 330, or a step difference can be formed between the insulating member 302 and the insulating layers 301 and 330. The lower surface of the insulating member 302 can be aligned with the lower surface of the semiconductor layer 214, or it can be located at the height between the lower surface of the semiconductor layer 214 and the conductive layer 26.

[0153] The conductive layer 303 of the memory device 1E is disposed on the insulating layers 301 and 330. Furthermore, the conductive layer 303 may have a portion disposed on the insulating member 302 within the dummy region DAa and the surrounding region PR. Insulating layers 304, 305, and 306 are sequentially disposed on the insulating layers 301 and 330 and the conductive layer 303.

[0154] The pad portion PD of the sixth embodiment has the same configuration as the pad portion PD described using FIG11 in the first embodiment. In the pad portion PD of the sixth embodiment, semiconductor layers 214, 216, and 217, and conductor layer 218 are not provided in the region overlapping with the via TV in the Z direction. That is, in the memory device 1E, the portion of the conductor layer 303 corresponding to the conductive portion MA that is exposed through the via TV does not have a portion overlapping with semiconductor layers 214, 216, and 217, and conductor layer 218 in the Z direction. The other configurations of the memory device 1E of the sixth embodiment are the same as those of the memory device 1 of the first embodiment.

[0155] <6-2> Manufacturing Method Next, regarding the manufacturing method of the memory device 1E according to the sixth embodiment, the method for forming the source line SL and the pad portion PD after the semiconductor substrate W1 and the semiconductor substrate W2 are bonded will be described with reference to FIG42. FIG42 is a flowchart showing an example of the manufacturing method of the memory device 1E according to the sixth embodiment. FIG43 and FIG44 are cross-sectional views showing an example of the cross-sectional structure of the memory device 1E according to the sixth embodiment during the manufacturing process, showing a cross-section including the area near the pad portion PD.

[0156] First, similar to the first embodiment, the semiconductor substrate W2 is removed (step ST11).

[0157] Next, as shown in Figure 43, a portion of the insulating layer 301, semiconductor layer 216, component 215, and laminated film 42 within the effective region AAa are removed (step ST61). Specifically, first, a mask is formed that partially opens the effective region AAa. Then, by anisotropic etching, the insulating layer 301, semiconductor layer 216, and component 215 are removed from the opening of the mask. At this time, component 215 and semiconductor layer 214 can be used as etching stop layers. Afterward, for example, by wet etching, the laminated film 42 disposed above the semiconductor layer 214 within the effective region AAa is selectively removed. Furthermore, in step ST61, depending on the shape of the mask used, a portion of the insulating layer 301, semiconductor layer 216, component 215, and laminated film 42 within the dummy region DAa can also be removed.

[0158] Next, a semiconductor layer 217 and a conductive layer 218 are formed (step ST62). Specifically, firstly, amorphous silicon corresponding to semiconductor layer 217 is formed on the exposed surface of semiconductor layer 214. Then, through impurity introduction toward the formed amorphous silicon and subsequent heat treatment, impurities diffuse into semiconductor layers 214 and 217, and the formed amorphous silicon is modified into polycrystalline silicon. Next, a conductive layer 218 is formed on semiconductor layer 217. Conductive layer 218 includes, for example, at least one of tungsten, aluminum, titanium, and titanium nitride. Furthermore, in step ST62, semiconductor layers 214 and 216 are modified from amorphous silicon to polycrystalline silicon during the heat treatment that modifies semiconductor layer 217 into polycrystalline silicon.

[0159] Next, as shown in Figure 44, an insulating layer 330 is formed (step ST63). In step ST63, for example, firstly, an insulating layer 330 is formed on the conductive layer 218 and the insulating layer 301. Then, the upper surfaces of the insulating layers 330 and 301 are planarized by CMP processing or the like. In this example, the insulating layer 330 formed on the insulating layer 301 is removed. Furthermore, the insulating layer 330 may also remain on the upper surface of the insulating layer 301.

[0160] Then, similarly to the first embodiment, steps ST12 to ST17 are executed sequentially. At this point, the structures corresponding to the source line SL shown in FIG. 41 and the structures corresponding to the solder pad portion PD are completed. Thus, the manufacturing method of the memory device 1E of the sixth embodiment has a configuration that inserts steps ST61, ST62, and ST63 between steps ST11 and ST12 in the manufacturing method of the memory device 1 of the first embodiment shown in FIG. 12.

[0161] <6-3> Effects of the 6th Implementation Method The memory device 1E of the sixth embodiment has a structure in which the structure corresponding to the source line SL in the dummy region DAa is removed, and the dummy region DAa overlaps with the pad portion PD in the Z direction. Therefore, the memory device 1E of the sixth embodiment, like the first embodiment, can reduce the parasitic capacitance of the pad, suppress interface speed degradation, and reduce the chip size.

[0162] <7> Implementation Method 7 The memory device 1F of the seventh embodiment has a structure in which the solder pad portion PDa described in the second embodiment and the source line SL described in the sixth embodiment are combined. Hereinafter, details of the memory device 1F of the seventh embodiment will be described.

[0163] <7-1> Composition The memory device 1F of the seventh embodiment has the same structure as the memory device 1A of the second embodiment, except for the source line SL. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDa in the memory device 1F of the seventh embodiment will be described.

[0164] [] <7-1-1> Planar Layout of PDA for Solder Pads Figure 45 is a top view showing an example of the planar layout near the pad portion PDA in the memory device 1F of the seventh embodiment. Figure 45 shows a portion of the pad portion PDA for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1F.

[0165] As shown in Figure 45, the memory device 1F has the configuration of the memory device 1A of the second embodiment, in which the effective area AA and the dummy area DA of the core region CR are replaced with the effective area AAa and the dummy area DAa of the sixth embodiment, respectively. The pad portion PDa of the seventh embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDa of the seventh embodiment has a portion that overlaps with the dummy area DAa in the core region CR, but does not have a portion that overlaps with the effective area AAa. Like the pad portion PDa of the second embodiment, the pad portion PDa of the seventh embodiment includes a conductive portion MA, an insulating portion BA, a through-hole TV, and a plurality of contacts VBP.

[0166] [] <7-1-2> Cross-sectional structure of the pad PDA Figure 46 is a cross-sectional view along line XLVI-XLVI of Figure 45, showing an example of the cross-sectional structure near the solder pad PDa in the memory device 1F of the seventh embodiment. As shown in Figure 46, the memory device 1F has a structure in which the source line SL in the effective region AAa and the dummy region DAa described in Figure 41 of the sixth embodiment is combined with the solder pad PDa described in Figure 23 of the second embodiment. The other configurations of the memory device 1F of the seventh embodiment are the same as those of the memory device 1A of the second embodiment.

[0167] <7-2> Manufacturing Method The manufacturing method of the memory device 1F in the seventh embodiment is equivalent to the manufacturing method of the memory device 1A in the second embodiment shown in FIG24, by inserting the processes of steps ST61, ST62 and ST63 shown in FIG42 between steps ST11 and ST12. That is, in the manufacturing method of the memory device 1F in the seventh embodiment, similarly to the sixth embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similarly to the second embodiment, a structure corresponding to the pad portion PDa is formed.

[0168] <7-3> Effects of the 7th Implementation Method The memory device 1F of the seventh embodiment has the structure corresponding to the source line SL in the dummy region DAa removed, and similarly to the sixth embodiment, the dummy region DAa and the pad portion PDa overlap in the Z direction. Therefore, the memory device 1F of the seventh embodiment, like the sixth embodiment, can reduce the parasitic capacitance of the pad, suppress interface speed degradation, and reduce the chip size. Furthermore, the memory device 1F of the seventh embodiment can suppress defects caused by the step difference in the conductive portion MA, and similarly to the second embodiment, can improve yield.

[0169] <8> Implementation Method 8 The memory device 1G of the eighth embodiment has a structure in which the solder pad portion PDb described in the third embodiment and the source line SL described in the sixth embodiment are combined. Hereinafter, details of the memory device 1G of the eighth embodiment will be described.

[0170] <8-1> Composition The memory device 1G of the eighth embodiment has the same structure as the memory device 1B of the third embodiment, except for the source line SL. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDb in the memory device 1G of the eighth embodiment will be described.

[0171] [] <8-1-1> Planar Layout of the Pad Section PDb Figure 47 is a top view showing an example of the planar layout near the solder pad PDb in the memory device 1G of the eighth embodiment. Figure 47 shows a portion of the solder pad PDb for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1G.

[0172] As shown in Figure 47, the memory device 1G has the configuration of the memory device 1B of the third embodiment, in which the effective region AA and the dummy region DA of the core region CR are replaced with the effective region AAa and the dummy region DAa of the sixth embodiment, respectively. The pad portion PDb of the eighth embodiment overlaps with the core region CR and the peripheral region PR, respectively. Moreover, the pad portion PDb of the eighth embodiment has a portion that overlaps with the dummy region DAa in the core region CR, but does not have a portion that overlaps with the effective region AAa. The pad portion PDb of the eighth embodiment, like the pad portion PDb of the third embodiment, includes a conductive portion MA, an insulating portion BA, a through hole TV, a conductive portion ZB, and a plurality of through holes VBa.

[0173] [] <8-1-2> Cross-sectional structure of the solder pad PDb Figure 48 is a cross-sectional view along line XLVIII-XLVIII of Figure 47, showing an example of the cross-sectional structure near the solder pad PDb in the memory device 1G of the eighth embodiment. As shown in Figure 48, the memory device 1G has a structure in which the source line SL in the effective region AAa and the dummy region DAa described in Figure 41 of the sixth embodiment is combined with the solder pad PDb described in Figure 29 of the third embodiment. The other configurations of the memory device 1G of the eighth embodiment are the same as those of the memory device 1B of the third embodiment.

[0174] <8-2> Manufacturing Method The manufacturing method of the memory device 1G in the eighth embodiment is equivalent to the manufacturing method of the memory device 1B in the third embodiment shown in FIG30, by inserting the processes of steps ST61, ST62 and ST63 shown in FIG42 between steps ST11 and ST12. That is, in the manufacturing method of the memory device 1G in the eighth embodiment, similarly to the sixth embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similarly to the third embodiment, a structure corresponding to the solder pad portion PDb is formed.

[0175] <8-3> Effects of the 8th Implementation Method The memory device 1G of the eighth embodiment, like that of the sixth embodiment, has a structure in the dummy region DAa corresponding to the source line SL that is removed, and the dummy region DAa and the pad portion PDb overlap in the Z direction. Therefore, the memory device 1G of the eighth embodiment, like that of the sixth embodiment, can reduce the parasitic capacitance of the pad, suppress interface speed degradation, and reduce the chip size. Furthermore, since the conductive portion MA and the contact C3 are connected via the conductive portion ZB, the memory device 1G of the eighth embodiment, like that of the third embodiment, can improve yield.

[0176] <9> Implementation Method 9 The memory device 1H of the ninth embodiment has a structure in which the solder pad portion PDc described in the fourth embodiment and the source line SL described in the sixth embodiment are combined. Hereinafter, details of the memory device 1H of the ninth embodiment will be described.

[0177] <9-1> Composition The memory device 1H of the ninth embodiment has the same structure as the memory device 1C of the fourth embodiment, except for the source line SL. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDc in the memory device 1H of the ninth embodiment will be described.

[0178] [] <9-1-1> Planar Layout of PDC for Solder Pads Figure 49 is a top view showing an example of the planar layout near the solder pad PDc in the memory device 1H of the ninth embodiment. Figure 49 shows a portion of the solder pad PDc for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1H.

[0179] As shown in Figure 49, the memory device 1H has a configuration in the memory device 1C of the fourth embodiment, where the effective region AA and the dummy region DA of the core region CR are replaced with the effective region AAa and the dummy region DAa of the sixth embodiment, respectively. The pad portion PDc of the ninth embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDc of the ninth embodiment has a portion that overlaps with the dummy region DAa in the core region CR, but does not have a portion that overlaps with the effective region AAa. Like the pad portion PDc of the fourth embodiment, the pad portion PDc of the ninth embodiment includes a conductive portion MA, an insulating portion BA, a through-hole TV, and a plurality of contacts VBP.

[0180] [] <9-1-2> Cross-sectional structure of the solder pad PDC Figure 50 is a cross-sectional view along line LL of Figure 49, showing an example of the cross-sectional structure near the solder pad PDc in the memory device 1H of the ninth embodiment. As shown in Figure 50, the memory device 1H has a structure in which the source line SL in the effective region AAa and the dummy region DAa described in Figure 41 of the sixth embodiment is combined with the solder pad PDc described in Figure 36 of the fourth embodiment. The other configurations of the memory device 1H of the ninth embodiment are the same as those of the memory device 1C of the fourth embodiment.

[0181] <9-2> Manufacturing Method The manufacturing method of the memory device 1H in the ninth embodiment is equivalent to the manufacturing method of the memory device 1C in the fourth embodiment, which is based on the manufacturing method of the memory device 1A in the second embodiment shown in FIG. 24, by inserting the processes of steps ST61, ST62, and ST63 shown in FIG. 42 between steps ST11 and ST12. That is, in the manufacturing method of the memory device 1H in the ninth embodiment, similar to the sixth embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similar to the fourth embodiment, a structure corresponding to the solder pad portion PDc is formed.

[0182] <9-3> Effects of the 9th Implementation Method The memory device 1H of the ninth embodiment, like the sixth embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DAa is removed, and the dummy region DAa and the pad portion PDc overlap in the Z direction. Therefore, the memory device 1H of the ninth embodiment, like the sixth embodiment, can reduce the parasitic capacitance of the pads, suppress interface speed degradation, and reduce the chip size. Furthermore, because the through-hole TV and the plurality of contacts VBP are arranged to overlap in the Z direction, the memory device 1H of the ninth embodiment, like the fourth embodiment, can suppress the chip area.

[0183] <10> 10th Implementation The memory device 1I of the tenth embodiment has a structure in which the solder pad portion PDd described in the fifth embodiment and the source line SL described in the sixth embodiment are combined. Hereinafter, details of the memory device 1I of the tenth embodiment will be described.

[0184] <10-1> Composition The memory device 1I of the tenth embodiment has the same structure as the memory device 1D of the fifth embodiment, except for the structure of the source line SL. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDd in the memory device 1I of the tenth embodiment will be described.

[0185] [] <10-1-1> Planar Layout of the Pad Section PDd Figure 51 is a top view showing an example of the planar layout near the solder pad PDd in the memory device 1I of the tenth embodiment. Figure 51 shows a portion of the solder pad PDd for connection with the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1I.

[0186] As shown in Figure 51, the memory device 1I has a configuration in the memory device 1D of the fifth embodiment, where the effective region AA and the dummy region DA of the core region CR are replaced with the effective region AAa and the dummy region DAa of the sixth embodiment, respectively. The pad portion PDd of the tenth embodiment overlaps with both the core region CR and the peripheral region PR. Furthermore, the pad portion PDd of the tenth embodiment has a portion overlapping with the dummy region DAa in the core region CR, but not a portion overlapping with the effective region AAa. Similar to the pad portion PDd of the fifth embodiment, the pad portion PDd of the tenth embodiment includes a conductive portion MA, an insulating portion BA, a through-hole TV, a conductive portion ZB, and a plurality of through-holes VBa.

[0187] [] <10-1-2> Cross-sectional structure of the solder pad PDd Figure 52 is a cross-sectional view along line LII-LII of Figure 51, showing an example of the cross-sectional structure near the solder pad PDd in the memory device 1I of the tenth embodiment. As shown in Figure 52, the memory device 1I has a structure in which the source line SL in the effective region AAa and the dummy region DAa described in Figure 41 of the sixth embodiment is combined with the solder pad PDd described in Figure 38 of the fifth embodiment. The other configurations of the memory device 1I of the tenth embodiment are the same as those of the memory device 1D of the fifth embodiment.

[0188] <10-2> Manufacturing Method The manufacturing method of the memory device 1I in the tenth embodiment is equivalent to the manufacturing method of the memory device 1D in the fifth embodiment, which is based on the manufacturing method of the memory device 1B in the third embodiment shown in FIG30, by inserting the processes of steps ST61, ST62, and ST63 shown in FIG42 between steps ST11 and ST12. That is, in the manufacturing method of the memory device 1I in the tenth embodiment, similar to the sixth embodiment, after removing the semiconductor substrate W2, the source line SL is formed, and then, similar to the fifth embodiment, a structure corresponding to the solder pad portion PDd is formed.

[0189] [] <10-3> Effects of the 10th Implementation Method The memory device 1I of the tenth embodiment, like the sixth embodiment, has a structure in which the structure corresponding to the source line SL within the dummy region DAa is removed, and the dummy region DAa and the pad portion PDd overlap in the Z direction. Therefore, the memory device 1I of the tenth embodiment, like the sixth embodiment, can reduce the parasitic capacitance of the pads, suppress interface speed degradation, and reduce the chip size. Furthermore, because the through-hole TV and the conductive portion ZB are arranged to overlap in the Z direction, the memory device 1I of the tenth embodiment, like the fifth embodiment, can suppress the chip area.

[0190] <11> Implementation Method 11 The memory device 1J of the 11th embodiment has a structure in which the top view dimension of the conductive part MA of the solder pad PD is designed to be smaller than the top view dimension of the insulating part BA, as in the memory device 1 of the 11th embodiment. The details of the memory device 1J of the 11th embodiment will be described below.

[0191] [] <11-1> Composition The memory device 1J of the 11th embodiment has the same structure as the memory device 1 of the 1st embodiment, except for the structure of the solder pad portion PD. Hereinafter, the planar layout and cross-sectional structure of the solder pad portion PDe in the memory device 1J of the 11th embodiment will be described.

[0192] [] <11-1-1> Planar Layout of PDE Pad Section Figure 53 is a top view showing an example of the planar layout near the pad portion PDe in the memory device 1J according to the 11th embodiment. Figure 53 shows a portion of the pad portion PDe, which is used to connect to the input / output circuit 11 and the logic controller 12, as well as a portion of the core region CR and the peripheral region PR in the memory device 1J.

[0193] As shown in Figure 53, the pad portion PDe overlaps with the core region CR and the surrounding region PR, respectively. Furthermore, the pad portion PDe overlaps with the dummy region DA in the core region CR, but does not overlap with the active region AA. The pad portion PDe includes a conductive portion MA, an insulating portion BA, a via TV, and a via VB. The insulating portion BA is rectangular in shape, for example, when viewed from above. The outer edge of the insulating portion BA corresponds to the outer edge of the pad portion PDe. The conductive portion MA is rectangular in shape, for example, when viewed from above, and overlaps with the conductive portion MA. Compared to the outer edge of the insulating portion BA, the outer edge of the conductive portion MA is located further inward. The vias TV and VB in the pad portion PDe are configured the same as those described in the first embodiment.

[0194] [] <11-1-2> Cross-sectional structure of the PDE pad Figure 54 is a cross-sectional view along line LIV-LIV of Figure 53, showing an example of the cross-sectional structure near the pad portion PDe in the memory device 1J of the 11th embodiment. As shown in Figure 54, the pad portion PDe has a configuration in the pad portion PD described in Figure 11 of the first embodiment, in which the outer edge of the conductive portion MA is located further inward than the outer edge of the insulating portion BA. Therefore, the conductive layer 303 corresponding to the conductive portion MA does not have a portion that overlaps with the conductive layers 21, 211, and 213 in the Z direction. The other configurations of the memory device 1J of the 11th embodiment are the same as those of the memory device 1 of the first embodiment.

[0195] <11-2> Manufacturing Method The manufacturing method of the memory device 1J in the 11th embodiment is the same as that in the manufacturing method of the memory device 1 in the first embodiment described using Figures 12 to 17, except that the conductive part MA is positioned further inside when viewed from above compared to the insulating part BA.

[0196] [] <11-3> Effects of the 11th Implementation Method In the memory device 1J of the 11th embodiment, compared with the first embodiment, the area of ​​the portion of the conductive part MA and the source line SL facing each other in the Z direction can be reduced. As a result, compared with the first embodiment, the memory device 1J of the 11th embodiment can reduce the parasitic capacitance of the solder pads and suppress the degradation of the interface speed.

[0197] Furthermore, the ideas described in Embodiment 11 can also be combined with Embodiments 2 through 10. That is, in Embodiments 2 through 10, the outer edge of the conductive portion MA can be configured such that it is located further inward than the outer edge of the insulating portion BA. As a result, Embodiments 2 through 10 can achieve the same effects as Embodiment 11.

[0198] <12> Examples of changes, etc. The memory device 1 described above can be modified in various ways.

[0199] Figure 55 is a cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bonding pads in the memory device 1 of the first embodiment. Figure 55 shows a conductive layer 105 (bonding pad) formed using a semiconductor substrate W1 (not shown), a conductive layer 25 (bonding pad) formed using a semiconductor substrate W2 (not shown), some contacts C2 and V2 connected thereto, and conductive layers 104 and 24. As shown in Figure 55, the two opposing bonding pads may have different conical shapes depending on the etching direction during formation. Specifically, the conductive layer 105 formed using the semiconductor substrate W1 has, for example, an inverted conical shape. The conductive layer 25 formed using the semiconductor substrate W2 has, for example, a conical shape. Therefore, the sidewalls of the cross-section along the Z direction of the portion where the conductive layers 105 and 25 are bonded may not be straight, but may be non-rectangular. Furthermore, the two opposing bonding pads may be staggered during bonding depending on their alignment during the bonding process. Therefore, a step difference may form between the side surface of conductor layer 105 and the side surface of conductor layer 25. The two opposing bonding pads may have an interface or be integrated. The bonding pads and the contacts C2 and V2 connected to them may also be integrally formed. A plurality of corresponding contacts C2 and V2 may also be connected to the bonding pads. For example, conductor layer 105 may be connected to conductor layer 104 via a plurality of contacts C2. Similarly, conductor layer 25 may be connected to conductor layer 24 via a plurality of contacts V2.

[0200] In the above embodiments, the memory device 1 may also include a plurality of memory cell arrays 10. When the memory device 1 includes a plurality of memory cell arrays 10, the memory device 1 may have a sense amplifier module 17 and a column decoder module 16 in each memory device 10. In this case, each memory cell array 10 is provided with a multilayer wiring including a plurality of word lines WL. Moreover, the groups of conductive layers 21, 211, and 213 corresponding to the source line SL, or the groups of semiconductor layers 214 and 217 and conductive layer 218 corresponding to the source line SL, are all interrupted in each memory cell array 10.

[0201] In the above embodiments, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 can be appropriately modified. Other contacts can also be inserted between the memory pillar MP and the conductive layer 23. Other contacts can also be inserted between contact C3 and the conductive layer 26. Conductive layers can also be inserted into the connection portions of multiple contacts. The number of wiring layers and contacts in the memory device 1 can be appropriately changed according to the circuit design. The memory pillar MP and each contact can also have a conical shape, an inverted conical shape, or a curved shape. The XY cross-sectional structure of the memory pillar MP can be circular or elliptical. Each wiring in the multilayer wiring can also be wiring with a metal oxide film surrounding a conductor such as tungsten. The conductive layers that are alternately multiplied with insulating layers in the multilayer wiring can also be considered to contain such a metal oxide film.

[0202] In this specification, "connection" refers to an electrical connection, excluding situations where other components are in between. An "electrical connection" simply means a connection that functions in the same way as an electrical connection, and can be separated by an insulator. "Semiconductor substrate" can also be simply referred to as "substrate." "Semiconductor layer" can also be called "conductive layer." "Region" can also be considered as a component contained within the substrate. For example, when the semiconductor substrate W1 is defined to include a storage region SA and a contact region CA, the storage region SA and the contact region CA are associated with different regions above the semiconductor substrate W1. "Height" corresponds, for example, to the distance in the Z direction between the component being measured and the semiconductor substrate W1. A component other than the semiconductor substrate W1 can also be used as a reference for "height." "View from top surface (top view)" corresponds, for example, to viewing the front side of the semiconductor substrate W1 from a vertical direction. "Through-hole" can also be called an opening.

[0203] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention described in the claims and its equivalents.

[0204] 1,1A,1B,1C,1D,1E,1F,1G,1H,1I,1J,1Y,1Z: Memory devices 2: Memory controller 10: Memory Cell Array 11: Input / output circuit 12: Logic Controller 13: Temporary Register Circuit 14: Sequencer 15: Driver circuit 16: Column Decoder Module 17: Sensing Amplifier Module 21~26, 24W, 25W, 26W, 103~105, 103W, 104W, 105W, 211, 213, 218, 303, 303A, 303B: Conductor layer 31~35, 110, 111, 210, 301, 304~307, 330: Insulating layer 36,302: Insulating components 40: Core Components 41,214,216,217: Semiconductor layer 42: Stacked membrane 43: Tunnel insulation film 44: Insulating film 45: Barrier insulating film 100: CMOS layer 101: Gate insulating film 102: Gate electrode 200: Memory Layer 212,SM: Sacrificial Component 215: Components 300: Wiring layer 310, 320: Conductive components AA, AAa: Valid region B1, B2: Bonding layers BA: Insulation section BL, BL0~BLm: Bit lines BLK, BLK0~BLKn: blocks C0~C3,C1W,C2W,C3W,CC,CV,V1,V2,V1W,V2W,VBP: Contacts CA: Contact Area CR: Core Area DA, DAa: Virtual regions DAT: Data DBLK, DBLK0, DBLK1: Dummy blocks DMP: Dummy Column DS: Virtual staircase section ES1, ES2: Sealing section KR: Slot area MA, ZB: Conductive parts MP: Memory Column MT, MT0~MT(N-1): Memory cell transistors NS: NAND string NW: N-type well area PD, PDa, PDb, PDc, PDd, PDe, PDy, PDz: Solder pad portion PL: Power cord PR: Surrounding Area PW: P-type well area RD, RD0~RDn: Column decoder SA: Storage Area SAU, SAU0~SAUm: Sensing amplifier unit SGD, SGS: Selecting the gate wire SL: Source Line SLT: Slit ST1, ST2: Select Transistor ST11~ST17, ST21~ST23, ST31~ST34, ST61~ST63: Steps TR1, TR2: Transistors TV, VA, VB, VBa, VC: Through-hole VBH: Hole W1, W2: Semiconductor substrates WL, WL0~WL(N-1): Character lines WR: wall area

Claims

1. A memory device having a bonding surface and comprising: a substrate having a first region and a second region arranged in a first direction; a first circuit layer disposed between the substrate and the bonding surface, comprising CMOS circuitry; a second circuit layer disposed above the bonding surface; and a wiring layer disposed above the second circuit layer, comprising pads electrically connected to the CMOS circuitry via the second circuit layer. The second circuit layer comprises: a stack body comprising, within the first region, alternatingly stacked first insulating layers and first conductive layers in a second direction intersecting the first direction, and within the second region, alternatingly stacked first insulating layers and first conductive layers in the second direction, or alternatingly stacked first insulating layers and first members in the second direction, wherein the material of the first member is different from that of the first insulating layers and the first conductive layers; and a plurality of first pillars, equal to those within the first region, penetrating the stack body in the second direction, and electrically connected to the source line above the stack body; the solder pads have portions overlapping the stack body in the second direction, but not portions overlapping the source line in the second direction.

2. The memory device of claim 1, wherein the stacked body has a stacked body portion in the second region in which the first insulating layer and the first member are alternately stacked in the second direction, and the end of the first member of the stacked body is provided in a stepped shape.

3. The memory device of claim 1, wherein the second circuit layer further includes a plurality of second pillars, the plurality of second pillars penetrating the laminate in the second region and in the second direction; and the plurality of first pillars are configured to store data to the portion intersecting with the first conductive layer, the plurality of second pillars are not used for storing data, the pads have portions overlapping the plurality of second pillars in the second direction, and the plurality of second pillars are electrically insulated from the source line.

4. The memory device of claim 1, wherein the aforementioned pads are electrically connected to the interface circuitry included in the aforementioned CMOS circuitry.

5. The memory device of claim 1, wherein the wiring layer includes a second conductor layer having a portion corresponding to the solder pad, and a second insulating layer disposed such that it covers the upper part of the second conductor layer, and the second insulating layer is provided with a first opening such that the surface of the second conductor layer corresponding to the solder pad is exposed.

6. The memory device of claim 5, wherein the wiring layer further includes an insulating member that insulates the source line from the second conductor layer, and the insulating member has a portion disposed at the same height as the source line and between the first opening and the laminate in the second region.

7. The memory device of claim 6, wherein the substrate further has a third region disposed in a manner that surrounds the first region and the second region in plan view, and the second circuit layer further includes at least one first contact, wherein the at least one first contact has a portion disposed at the same height as the stack in the third region and is electrically connected to the CMOS circuit; the second conductive layer has a portion overlapping the stack in the second direction in the second region, and has a portion electrically connected to the at least one first contact in the third region.

8. The memory device of claim 7, wherein the insulating member has a second opening in the portion overlapping with the at least one first contact in the second direction, and the second conductive layer is disposed along the second opening in the third region, and is connected to the at least one first contact at the bottom of the second opening.

9. The memory device of claim 7, wherein the wiring layer further includes at least one second contact, the at least one second contact passing through the insulating member and respectively connected to the at least one first contact; and the second conductive layer is electrically connected to the at least one first contact via the at least one second contact.

10. The memory device of claim 9, wherein the first opening has a portion that overlaps with the at least one second contact in the second direction.

11. The memory device of claim 7, wherein the wiring layer further includes a conductive member, the upper portion of which is covered by the insulating member, and the conductive member is connected to the at least one first contact; and the insulating member has a third opening at the portion overlapping the conductive member in the second direction, the second conductive layer is embedded in the third opening, and the bottom of the third opening is connected to the conductive member.

12. The memory device of claim 11, wherein the first opening has a portion that overlaps with the conductive member in the second direction.

13. The memory device of claim 5, wherein the substrate further has a third region disposed in a manner that surrounds the first region and the second region in plan view, and the second circuit layer further includes a first sublayer and a second sublayer, the first sublayer being disposed on the same layer as the source line in the third region and comprising a material as the main component being at least a portion of the source line, and the second sublayer being disposed above the first sublayer via a second member; the first opening does not have a portion overlapping the first sublayer and the second sublayer in the second direction.

14. The memory device of claim 1, wherein the second circuit layer further includes a third conductor layer used as part of the source line in the first region, and each of the plurality of first pillars includes a semiconductor layer extending in the second direction, and the semiconductor layer and the third conductor layer are electrically connected via the side of each of the plurality of first pillars.

15. The memory device of claim 1, wherein the wiring layer further includes a third conductor layer used as part of the source line in the first region, and the plurality of first pillars are each included in a semiconductor layer extending in the second direction, the third conductor layer having a portion disposed along the upper part of the semiconductor layer and electrically connected to the semiconductor layer.

16. The memory device of claim 1 further comprises: a first pad disposed adjacent to the aforementioned bonding surface and electrically connected to the aforementioned CMOS circuit; and a second pad disposed adjacent to the aforementioned bonding surface and electrically connected between one of the plurality of first pillars and the aforementioned first pad; wherein the direction of the cone shape of the aforementioned first pad is different from the direction of the cone shape of the aforementioned second pad.

17. A memory device having a bonding surface and comprising: a first circuit layer disposed between a substrate and the bonding surface, comprising CMOS circuitry; a second circuit layer comprising: a stack body disposed above the first circuit layer via the bonding surface, comprising a first insulating layer and a first conductive layer alternately stacked in a stacking direction; and a plurality of pillars, each comprising a first pillar and a second pillar extending in the stack body along the stacking direction, the first pillar being electrically connected to a source line above the stack body and configured to store data to a portion intersecting with the first conductive layer, the second pillar not used for storing data; and a second conductive layer disposed above the source line in the stacking direction, comprising a portion corresponding to a pad and electrically connected to the CMOS circuit. The second conductor layer has a portion that overlaps with the second post in the stacking direction. The portion of the second conductor layer is not separated from the source line, but is separated from the insulating member disposed at the same height as the source line, and faces the second post in the stacking direction.

18. The memory device of claim 17, wherein the solder pads have portions that overlap with the second post in the stacking direction and do not have portions that overlap with the source line in the stacking direction.

19. The memory device of claim 18 further includes a second insulating layer disposed in such a way as to cover the upper part of the second conductive layer, and the second insulating layer is provided with a first opening such that the surface of the second conductive layer corresponding to the solder pad is exposed.

20. The memory device of claim 17, wherein the second circuit layer further comprises: a third insulating layer disposed around the stack in plan view; and at least one first contact, a portion of which is disposed at the same height as the stack and extends in the stacking direction within the third insulating layer and is electrically connected to the CMOS circuit; and the second conductive layer further comprises a portion electrically connected to the at least one first contact.

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