memory devices

Abstract

This invention improves the integral density. One embodiment of a memory device includes: a substrate, a first semiconductor layer, and a second semiconductor layer, which are spaced apart from each other and arranged sequentially in a first direction; a plurality of first wiring layers, which are spaced apart from each other in a first direction between the substrate and the first semiconductor layers, and include the first layer; a plurality of second wiring layers, which are spaced apart from each other in a first direction between the first semiconductor layer and the second semiconductor layer, and include the second layer; and a first memory pillar extending in the first direction. The portion intersecting with each of the plurality of first wiring layers functions as a memory cell; the second memory pillar extends in the first direction and the portion intersecting with each of the plurality of second wiring layers functions as a memory cell; and the first contact extends in the first direction in a manner intersecting with the plurality of first wiring layers to reach the first semiconductor layer, is in contact with the first layer, and is electrically insulated from the plurality of first wiring layers and the first semiconductor layer other than the first layer, electrically connecting the substrate and the second layer.

Description

[Technical Field]

[0001] The implementation relates to a memory device. [Previous Technology]

[0002] As a memory device that can store non-volatile data, NAND (Not And) flash memory is known. In memory devices like NAND flash memory, a 3D memory structure is used in order to achieve high integration and large capacity. [Summary of the Invention]

[0003] It can improve the compactness of memory devices.

[0004] An embodiment of the memory device includes: a substrate, a first semiconductor layer, and a second semiconductor layer, which are spaced apart from each other and arranged sequentially in a first direction; a plurality of first wiring layers, which are spaced apart from each other between the substrate and the first semiconductor layer in the first direction and include the first layer; a plurality of second wiring layers, which are spaced apart from each other between the first semiconductor layer and the second semiconductor layer in the first direction and include the second layer; and a first memory pillar extending in the first direction and connected to the substrate. The portion where each of the plurality of first wiring layers intersects functions as a memory cell; the portion of the second memory pillar extending in the first direction intersecting with each of the plurality of second wiring layers functions as a memory cell; and the first contact extending in the first direction in a manner intersecting with the plurality of first wiring layers to reach the first semiconductor layer, being in contact with the first layer, and electrically insulated from the plurality of first wiring layers and the first semiconductor layer other than the first layer, electrically connecting the substrate and the second layer.

Implementation Method

[0006] The embodiments will be described below with reference to the drawings. The dimensions and proportions of the drawings may not be the same as those of the actual objects.

[0007] Furthermore, in the following description, the same symbol is used to mark constituent elements that have roughly the same function and structure. When distinguishing between constituent elements that have the same structure, different words or numbers are sometimes marked at the end of the same symbol.

[0008] 1. First Embodiment 1.1 Configuration 1.1.1 Configuration of the Memory System Figure 1 is a block diagram showing an example of the configuration of a memory system including the memory device of the first embodiment. The memory system 1 is a memory device configured to be connected to an external host (not shown). The memory system 1 is, for example, a memory card such as an SDTM card, UFS (universal flash storage), or SSD (solid state drive). The memory system 1 includes a memory controller 2 and a memory device 3.

[0009] The memory controller 2 is configured as an integrated circuit, such as a SoC (system-on-a-chip). Based on requests from the host, the memory controller 2 controls the memory device 3. Specifically, for example, the memory controller 2 writes data requested by the host to the memory device 3. Furthermore, the memory controller 2 reads data requested by the host from the memory device 3 and sends it to the host.

[0010] The memory device 3 is a non-volatile memory. The memory device 3 is, for example, a NAND flash memory. The memory device 3 stores data non-volatilely.

[0011] The communication between the memory controller 2 and the memory device 3 is, for example, based on the SDR (single data rate) interface, switching the DDR (double data rate) interface, or ONFI (open NAND flash memory interface).

[0012] 1.1.2 Configuration of Memory Device Next, referring to the block diagram shown in FIG1, the internal configuration of the memory device in the first embodiment will be described. The memory device 3 includes, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a column decoder module 15, and a sense amplifier module 16.

[0013] The memory cell array 10 contains a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The number of blocks BLK contained in the memory cell array 10 may also be one. A block BLK is a collection of a plurality of memory cells. A block BLK is used, for example, as a unit for data erasure. Furthermore, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed structure of the memory cell array 10 is described below.

[0014] The instruction register 11 stores the instruction CMD received by the memory device 3 from the memory controller 2. The instruction CMD contains commands, such as causing the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0015] The address register 12 stores the address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, the block address BAD, the page address PAd, and the row address CAd. For example, the block address BAD, the page address PAd, and the row address CAd are used for the selection of the block BLK, word line, and bit line, respectively.

[0016] The sequencer 13 controls the operation of the entire memory device 3. For example, based on the instruction CMD stored in the instruction register 11, the sequencer 13 controls the driver module 14, the column decoder module 15, and the sense amplifier module 16 to perform read operations, write operations, erase operations, etc.

[0017] The driver module 14 generates voltages for read operations, write operations, erase operations, etc. Furthermore, the driver module 14 applies the generated voltages to signal lines corresponding to the selected word lines, for example, based on the page address PAd stored in the address register 12.

[0018] The column decoder module 15 selects one block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Furthermore, the column decoder module 15 transmits, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0019] During the write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. Furthermore, during the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transmits the determination result as read data DAT to the memory controller 2.

[0020] Figure 2 is a perspective view showing the outline of the bonding structure of the memory device in the first embodiment.

[0021] As shown in FIG2, the memory device 3 includes memory chips 100 and 200, and a circuit chip 300. The memory chips 100 and 200 each include a configuration corresponding to the memory cell array 10. The circuit chip 300 includes, for example, a configuration corresponding to the instruction register 11, the address register 12, the sequencer 13, the driver module 14, the column decoder module 15, and the sense amplifier module 16.

[0022] Furthermore, memory chips 100 and 200, and circuit chip 300 each include a plurality of bonding pads BP. The memory device 3 is formed by bonding memory chips 100 and 200, and memory chips 200 and circuit chip 300, through a plurality of bonding pads BP. That is, memory chip 200 is disposed between memory chip 100 and circuit chip 300, and has a surface for bonding with memory chip 100 and a surface for bonding with circuit chip 300.

[0023] Hereinafter, the surface (attachment surface) on which the memory chips 100 and 200 and the circuit chip 300 are bonded is designated as the XY plane. The mutually orthogonal directions in the XY plane are designated as the X direction and the Y direction. Furthermore, the direction approximately perpendicular to the XY plane and extending from the memory chip 100 toward the circuit chip 300 is designated as the Z1 direction. The direction approximately perpendicular to the XY plane and extending from the circuit chip 300 toward the memory chip 100 is designated as the Z2 direction. When neither the Z1 nor Z2 direction is limited, it is referred to as the Z direction.

[0024] 1.1.3 Memory Cell Array Next, the configuration of the memory cell array provided in the memory device of the embodiment will be explained.

[0025] <Circuit Configuration> Figure 3 is a circuit diagram showing an example of the circuit configuration of the memory cell array provided in the memory device of the first embodiment. In Figure 3, one block BLK of the plurality of blocks BLK contained in the memory cell array 10 is shown. As shown in Figure 3, the block BLK contains, for example, four serial units SU0 to SU3.

[0026] Each string cell SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1). The number of bit lines BL can also be 1. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge accumulation section, which non-volatilely stores data. Select transistors ST1 and ST2 are used to select the string cell SU during various operations.

[0027] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selector transistor ST1 is connected to the bit line BL for establishing association. The source of selector transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selector transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selector transistor ST2 is connected to the source line SL.

[0028] Within the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 within serial units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gates of multiple select transistors ST2 are connected to select gate line SGS.

[0029] Different row addresses are assigned to bit lines BL0 to BLm. Each bit line BL is shared by NAND strings NS that are assigned the same row address among multiple blocks BLK. Word lines WL0 to WL7 are each set according to each block BLK. Source lines SL are shared among multiple blocks BLK, for example.

[0030] A collection of multiple memory cell transistors (MTs) connected to a common word line (WL) within a single string unit (SU) is called a cell (CU). For example, the memory capacity of a cell (CU) containing memory cell transistors (MTs) that each stores 1 bit of data is defined as "1 page of data". Depending on the number of bits of data stored in the memory cell transistors (MTs), a cell (CU) may have a memory capacity of more than 2 pages of data.

[0031] Furthermore, the circuit configuration of the memory cell array 10 provided in the memory device 3 of the first embodiment is not limited to the configuration described above. For example, the number of string cells SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT, and select transistors ST1 and ST2 included in each NAND string NS can each be designed to be any number.

[0032] <Planar Layout> Figure 4 is a top view showing an example of the planar layout of the memory cell array provided by the memory device of the first embodiment. In Figure 4, four blocks BLK0 to BLK3 of the plurality of blocks BLK provided by the memory cell array 10 are shown.

[0033] As shown in Figure 4, the memory cell array 10 includes a stacked wiring structure. The stacked wiring structure is a structure in which stacked wiring (word lines WL0 to WL7, and select gate lines SGD and SGS) are stacked in the Z direction. The stacked wiring structure has memory regions MRa and MRb arranged in the X direction, and a lead-out region HR. Memory regions MRa and MRb are regions for setting memory cell transistors MT. Lead-out region HR is a region for setting contacts for electrically connecting the stacked wiring to the column decoder module 15. Lead-out region HR is located between memory regions MRa and MRb.

[0034] Each of the plurality of blocks BLK extends in the X direction, traversing the memory region MRa, the lead-out region HR, and the memory region MRb. The plurality of blocks BLK are arranged in the Y direction. The memory cell array 10 includes, for example, a plurality of components SLT and a plurality of components SHE.

[0035] Each component SLT extends in the X direction, traversing the memory region MRa, the lead-out region HR, and the memory region MRb. A plurality of component SLTs are arranged in the Y direction. Each component SLT, for example, has a structure filled with insulator. Each component SLT breaks the stacked wiring that separates adjacent components. In the memory cell array 10, the regions separated by component SLTs each correspond to one block BLK.

[0036] A plurality of component SHEs are included in memory region MRa, which is arranged in the Y direction, and in memory region MRb, which is also arranged in the Y direction. Each component SHE located in memory region MRa extends in the X direction across memory region MRa. Each component SHE located in memory region MRb extends in the X direction across memory region MRb. In the example of Figure 4, in each of memory regions MRa and MRb, three component SHEs are arranged between each of two adjacent component SLTs in the Y direction. Each component SHE has, for example, a structure filled with an insulator. Each component SHE will interrupt the select gate line SGD in the stacked wiring adjacent to that component SHE. In memory cell array 10, the region separated by a group of adjacent component SLTs and SHEs, or a group of two adjacent component SHEs, corresponds to one string cell SU.

[0037] Alternatively, the planar layout of the memory cell array 10 can also be other layouts. For example, the number of components SHEs arranged between two adjacent components SLTs can be designed to be any number. The number of string units SU in each block BLK can be changed based on the number of components SHEs arranged between two adjacent components SLTs.

[0038] Figure 5 is a top view corresponding to region V in Figure 4, showing an example of the planar layout of the memory cell array provided by the memory device of the first embodiment. In Figure 5, the boundary portion of the lead-out region HR and the memory region MRb in block BLK0 is shown.

[0039] First, the planar layout of the memory cell array 10 in the memory region MRb will be explained.

[0040] As shown in Figure 5, the memory cell array 10 is in the memory region MRb, for example, including a plurality of memory cylinders MP, a plurality of contacts CH and a plurality of bit lines BL.

[0041] Each memory column MP functions as a NAND string NS. A plurality of memory columns MP are arranged in a 19-row zigzag pattern in the area between two adjacent component SLTs. For example, a component SHE is overlapped with the memory columns MP in the 5th, 10th, and 15th rows from the top of the paper.

[0042] A plurality of bit lines BL are arranged in the X direction. Each bit line BL is configured such that each string cell SU overlaps with at least one memory column MP. In the example of Figure 5, two bit lines BL are overlapped with one memory column MP. The memory column MP is electrically connected to one of the overlapping bit lines BL via a contact CH. Alternatively, the contact CV between the memory column MP and the bit line BL that is connected to two different select gate lines SGD (i.e., overlapped with the component SHE) can be omitted.

[0043] Alternatively, the planar layout in the memory region MR can also be other layouts. For example, the number and arrangement of memory cylinders MP or components SHE located between two adjacent components SLT can be appropriately changed. The number of bit lines BL overlapping each memory cylinder MP can be designed to be arbitrary.

[0044] Next, the planar layout of the memory cell array 10 in the outgoing region HR will be described.

[0045] The memory cell array 10 includes a plurality of contacts CC in the lead-out region HR. Furthermore, the multilayer wiring in the lead-out region HR has a stepped portion and a bus portion HW. The stepped portion is the part of the multilayer wiring that does not overlap with the multilayer wiring of the upper layer in the Z1 direction. The bus portion HW is the part arranged in the Y direction with the stepped portion.

[0046] The stepped structure in the stepped portion of the stacked wiring constitutes a step structure. In the example of Figure 5, a step difference is formed between the select gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, ..., between the word line WL6 and the word line WL7, and between the word line WL7 and the select gate line SGD.

[0047] Except for the gate line SGD, the stacked wiring of memory region MRa and memory region MRb are continuously configured via the bus portion HW within the lead-out region HR. That is, the bus portion HW corresponds to the portion that continuously connects memory regions MRa and MRb along the component SLT.

[0048] The contact CC is a conductor used for the connection between the serial decoder module 15 and the stack-up wiring. A plurality of contacts CC corresponding to the block BLK are respectively connected to the step portion of the select gate lines SGS and SGD provided in the lead-out area HR, and the word lines WL0 to WL7. When the select gate line SGD on the memory area MRa side and the select gate line SGD on the memory area MRb side correspond to the same serial unit SU, they are electrically connected, for example, through an upper wiring layer (not shown).

[0049] 1.1.4 Cross-sectional structure of memory device Next, the cross-sectional structure of the memory device in the embodiment will be described.

[0050] FIG6 is a cross-sectional view along line VI-VI of FIG5, showing an example of the cross-sectional structure of the memory device of the first embodiment. FIG7 is a cross-sectional view along line VII-VII of FIG5, showing an example of the cross-sectional structure of the memory device of the first embodiment.

[0051] First, referring to Figures 6 and 7, the cross-sectional structure of the memory chip 100 will be described.

[0052] The memory chip 100 includes memory pillars MP1, insulating layers 101, 102, 103, 104, 105 and 106, insulators 107, 108 and 109, semiconductor layer 121, wiring layers 122, 123 and 124, conductive layers 127, 129 and 131, and conductors 125, 126, 128 and 130.

[0053] A semiconductor layer 121 is disposed on the upper surface of the insulating layer 101 in the Z1 direction. The semiconductor layer 121 is, for example, formed into a plate shape extending along the XY plane. The semiconductor layer 121 contains, for example, polysilicon and is used as a source line SL.

[0054] An insulating layer 102 and a wiring layer 122 are alternately deposited on the surface above the semiconductor layer 121 in the Z1 direction. The wiring layer 122 is, for example, formed into a plate shape extending along the XY plane. The wiring layer 122 contains, for example, tungsten and is used as a select gate line (SGS).

[0055] On the surface above the wiring layer 122 in the Z1 direction, eight insulating layers 103 and eight wiring layers 123 are alternately deposited layer by layer. Each of the eight wiring layers 123 is, for example, formed into a plate shape extending along the XY plane. The eight wiring layers 123 contain, for example, tungsten, and are used as character lines WL0 to WL7 in sequence from the side closest to the semiconductor layer 121.

[0056] On the surface above the uppermost wiring layer 123 in the Z1 direction, insulating layers 104 and wiring layers 124 are alternately stacked. Wiring layer 124 is, for example, formed into a plate extending along the XY plane. Wiring layer 124 contains, for example, tungsten and is used as a selective gate line (SGD).

[0057] The wiring layers 122, 123, and 124 described above constitute a multilayer wiring. Each of the wiring layers 122, 123, and 124 has a stepped portion in the lead-out region HR that does not overlap with the wiring layer above in the Z1 direction. The film thickness of the stepped portion of each of the wiring layers 122, 123, and 124 is, for example, thicker than the film thickness of other portions of each of the wiring layers 122, 123, and 124.

[0058] A conductive layer 127 is provided above the wiring layer 124 in the Z1 direction. The conductive layer 127 is formed, for example, in a linear shape extending in the Y direction. The conductive layer 127 contains, for example, copper and is used as a bit line BL.

[0059] The insulator 109 has a plate-like portion that extends along the XZ plane. The insulator 109 divides the insulating layers 102 to 104 and the wiring layers 122 to 124 and is used as a component SLT.

[0060] The memory pillar MP1 extends in the Z direction and penetrates the multilayer wiring structure of the memory chip 100 in the memory region MRb. The memory pillar MP1 includes, for example, a core film 140, a semiconductor film 141, and a multilayer film 142. The core film 140 is an insulator extending in the Z direction. One end of the core film 140 reaches below the wiring layer 122 in the Z1 direction. The other end of the core film 140 reaches above the wiring layer 124 in the Z1 direction. The semiconductor film 141 covers the core film 140. One end of the semiconductor film 141 is connected to the semiconductor layer 121. The multilayer film 142 covers the side of the semiconductor film 141.

[0061] FIG8 is a cross-sectional view along line VIII-VIII of FIG6, showing an example of the cross-sectional structure of the memory pillar of the memory device of the first embodiment. FIG8 shows a cross-section including the memory pillar MP1 and the wiring layer 123, and parallel to the XY plane. As shown in FIG8, the laminated film 142 includes, for example, a tunnel insulating film 143, a charge accumulation film 144, and a barrier insulating film 145.

[0062] The core film 140 is disposed, for example, in the central portion of the memory pillar MP1. A semiconductor film 141 surrounds the sides of the core film 140. A tunnel insulating film 143 surrounds the sides of the semiconductor film 141. A charge accumulation film 144 surrounds the sides of the tunnel insulating film 143. A barrier insulating film 145 surrounds the sides of the charge accumulation film 144. A wiring layer 123 surrounds the sides of the barrier insulating film 145. The semiconductor film 141 serves as a channel (current path) for the memory cell transistors MT0 to MT7, and the select transistors ST1 and ST2. The tunnel insulating film 143 and the barrier insulating film 145 each contain, for example, silicon oxide. The charge accumulation film 144 contains, for example, silicon nitride. Thus, the portion where the memory pillar MP intersects with the wiring layer 123 functions as the memory cell transistor MT. Similarly, the portion where the memory pillar MP1 intersects with the wiring layer 124 functions as the select transistor ST1. The portion where memory column MP1 intersects with wiring layer 122 functions as the select transistor ST2. Therefore, memory column MP1 functions as a NAND string NS.

[0063] Referring again to Figures 6 and 7, the cross-sectional structure of the memory chip 100 will be described.

[0064] A conductor 125 is disposed on the upper surface of the semiconductor film 141 in the Z1 direction within the memory pillar MP1. The conductor 125 has, for example, a columnar shape and is used as a contact CH. A conductor 126 is disposed on the upper surface of the conductor 125 in the Z1 direction. The conductor 126 has a columnar shape. The conductor 126 is connected to a corresponding conductive layer 127.

[0065] Conductor 128 extends in the Z direction through the stepped portion of the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 128, for example, reaches semiconductor layer 121. The other end of conductor 128, for example, reaches above wiring layer 124 in the Z1 direction. Conductor 128 has a columnar shape and is used as a contact CC.

[0066] An insulator 107 is provided between the conductor 128 and the semiconductor layer 121. The insulator 107 may contain, for example, silicon oxide. Thereby, the conductor 128 and the semiconductor layer 121 are electrically insulated.

[0067] FIG9 is a cross-sectional view along line IX-IX of FIG6, showing an example of the cross-sectional structure of the contacts of the memory device of the first embodiment. FIG9 shows a cross-section including the contacts CC and the wiring layer 123, and parallel to the XY plane.

[0068] As shown in FIG9, an insulator 108 is provided between the conductor 128 and the wiring layer lower in the Z1 direction of the corresponding wiring layer. The insulator 108 includes, for example, silicon oxide. Thereby, the conductor 128 is electrically insulated from the wiring layer lower in the Z1 direction of the corresponding wiring layer among the wiring layers 122, 123 and 124.

[0069] The conductor 128 and the corresponding wiring layer are electrically connected to each other by a thickened portion of the stepped surface. The diameter of the portion of the conductor 128 that contacts the corresponding wiring layer is larger than the other portions of the conductor 128. The diameter of the portion of the conductor 128 that contacts the corresponding wiring layer is, for example, the same as the diameter of the insulator 108.

[0070] Referring again to Figures 6 and 7, the cross-sectional structure of the memory chip 100 will be described.

[0071] A conductive layer 129 having a linear shape is provided on the upper surface of the conductor 128 in the Z1 direction. A conductor 130 having a columnar shape is provided on the upper surface of the conductive layer 129 in the Z1 direction.

[0072] The multilayer wiring structure of the memory chip 100, memory pillars MP1, conductors 125, 126, 128 and 130, and conductor layers 127 and 129 are covered, for example, by an insulating layer 105. An insulating layer 106 is disposed on the upper surface of the insulating layer 105 in the Z1 direction. The insulating layer 106 is in contact with the insulating layer 201 contained in the memory chip 200. The boundary between the insulating layer 106 and the insulating layer 201 corresponds to the bonding surface between the memory chip 100 and the memory chip 200.

[0073] A rectangular conductive layer 131 is provided, for example, on the upper surface of the conductor 130 in the Z1 direction. The conductive layer 131 is used as a bonding pad BP for the memory chip 100. The conductive layer 131 is disposed on the same layer as the insulating layer 106 and is in contact with the conductive layer 221 contained in the memory chip 200.

[0074] Next, while referring to Figures 6 and 7, the cross-sectional structure of the memory chip 200 will be described.

[0075] The memory chip 200 includes memory pillars MP2, insulating layers 201, 202, 203, 204, 205, 206 and 207, insulators 208, 209, 210 and 211, semiconductor layer 222, wiring layers 223, 224 and 225, conductive layers 228, 231 and 233, and conductors 226, 227, 229, 230 and 232.

[0076] A conductive layer 221 is provided on the same layer as the insulating layer 201. The conductive layer 221 is used as a bonding pad BP for the memory chip 200 on the bonding surface with the memory chip 100.

[0077] An insulating layer 202 and a semiconductor layer 222 are alternately deposited on the upper surface of the insulating layer 201 in the Z1 direction. The semiconductor layer 222 is, for example, formed into a plate shape extending along the XY plane. The semiconductor layer 222 contains, for example, polysilicon and is used as a source line SL.

[0078] A multilayer wiring structure of a memory chip 200 is provided on the upper surface of the semiconductor layer 222 in the Z1 direction. The multilayer wiring structure of the memory chip 200 includes, for example, insulating layers 203, 204, and 205, and wiring layers 223, 224, and 225. The multilayer wiring structure of the memory chip 200 is the same as that of the memory chip 100. That is, insulating layers 203, 204, and 205, and wiring layers 223, 224, and 225 have the same configuration as insulating layers 102, 103, and 104, and wiring layers 122, 123, and 124.

[0079] A conductive layer 228 is provided above the wiring layer 225 in the Z1 direction. The conductive layer 228 is formed, for example, in a linear shape extending in the Y direction. The conductive layer 228 contains, for example, copper and is used as a bit line BL.

[0080] The insulator 211 has a plate-like portion that extends along the XZ plane. The insulator 211 divides the insulating layers 203-205 and the wiring layers 223-225 and is used as a component SLT.

[0081] The memory pillar MP2 extends in the Z direction and penetrates the stacked wiring structure of the memory chip 200 in the memory region MRb. The memory pillar MP2 includes, for example, a core film 240, a semiconductor film 241, and a stacked film 242. The structure of the memory pillar MP2 is the same as that of the memory pillar MP1. That is, the core film 240, the semiconductor film 241, and the stacked film 242 have the same structure as the core film 140, the semiconductor film 141, and the stacked film 142.

[0082] A conductor 226 is disposed on the upper surface of the semiconductor film 241 in the Z1 direction within the memory pillar MP2. The conductor 226 has, for example, a columnar shape and is used as a contact CH. A conductor 227 is disposed on the upper surface of the conductor 226 in the Z1 direction. The conductor 227 has a columnar shape. The conductor 227 is connected to a corresponding conductor layer 228.

[0083] Conductor 230 extends in the Z direction through the stepped portion of the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 230, for example, reaches semiconductor layer 222. The other end of conductor 230, for example, reaches above wiring layer 235 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0084] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 230 and the semiconductor layer 222 are electrically insulated.

[0085] An insulator 210 is provided between the conductor 230 and the wiring layer lower in the Z1 direction of the corresponding wiring layer. The insulator 210 includes, for example, silicon oxide. Thereby, the conductor 230 is electrically insulated from the wiring layer lower in the Z1 direction of the corresponding wiring layer among the wiring layers 223, 224 and 235.

[0086] The conductor 230 and the corresponding wiring layer are electrically connected to each other by a thickened portion of the stepped surface. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is larger than the other portions of the conductor 230. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is, for example, the same as the diameter of the insulator 210.

[0087] A conductor 229 is disposed on the upper surface of the conductor layer 221 in the Z1 direction and extends in the Z direction. The upper end of the conductor 229 in the Z1 direction is connected to the other end of the conductor 230. An insulator 208 is disposed on the side surface of the conductor 229. Therefore, the conductor 229 is electrically insulated from the semiconductor layer 222, and electrically connects the conductor 230 to the conductor layer 221.

[0088] A conductive layer 231 having a linear shape is provided on the upper surface of the conductor 230 in the Z1 direction. A conductor 232 having a columnar shape is provided on the upper surface of the conductive layer 231 in the Z1 direction.

[0089] The multilayer wiring structure of the memory chip 200, memory pillars MP2, conductors 226, 227, 230 and 232, and conductor layers 228 and 231 are covered, for example, by an insulating layer 206. An insulating layer 207 is disposed on the upper surface of the insulating layer 206 in the Z1 direction. The insulating layer 207 is in contact with the insulating layer 301 contained in the circuit chip 300. The boundary between the insulating layer 207 and the insulating layer 301 corresponds to the bonding surface between the memory chip 200 and the circuit chip 300.

[0090] A rectangular conductive layer 233 is provided, for example, on the upper surface of the conductor 232 in the Z1 direction. The conductive layer 233 is used as a bonding pad BP of the memory chip 200 on the bonding surface with the circuit chip 300. The conductive layer 233 is disposed on the same layer as the insulating layer 207 and is in contact with the conductive layer 321 contained in the circuit chip 300.

[0091] Next, while referring to Figures 6 and 7, the cross-sectional structure of the circuit chip 300 will be described.

[0092] The circuit chip 300 includes insulating layers 301 and 302, a substrate 303, conductive layers 321, 323 and 325, conductors 322, 324 and 326, and a transistor TR.

[0093] A conductive layer 321 is disposed on the same layer as the insulating layer 301. The conductive layer 321 is used as a bonding pad BP on the bonding surface of the circuit chip 300 and the memory chip 200.

[0094] An insulating layer 302 and a substrate 303 are alternately deposited on the upper surface of the insulating layer 301 in the Z1 direction. The substrate 303 is, for example, a silicon substrate. Various circuits including transistors TR are formed on the substrate 303. The circuits in the transistor TR series decoder module 15 are illustrated in Figures 6 and 7.

[0095] Within the insulating layer 301, a conductor 322 having a columnar shape is disposed on the upper surface of the conductor layer 321 in the Z1 direction. A conductor layer 323 having a linear shape is disposed on the upper surface of the conductor 322 in the Z1 direction. A conductor 324 having a columnar shape is disposed on the upper surface of the conductor layer 323 in the Z1 direction. A conductor layer 325 is disposed on the upper surface of the conductor 324 in the Z1 direction. A conductor 326 having a columnar shape is disposed on the upper surface of the conductor layer 325 in the Z1 direction. A transistor TR is connected to the upper surface of the conductor 326 in the Z1 direction on the substrate 303.

[0096] According to the above configuration, the specific character lines WL of memory chips 100 and 200 are electrically connected via conductors 128 and 230 and are commonly connected to the transistor TR in the circuit chip 300.

[0097] Furthermore, in the examples of Figures 6 and 7, the electrical connection between the word lines WL of memory chips 100 and 200 and the circuit chip 300 is shown, but the connection between memory chips 100 and 200 and the circuit chip 300 is not limited to this. For example, although the illustrations are omitted in Figures 6 and 7, the bit lines BL and source lines SL of memory chips 100 and 200 are also electrically connected to the circuit chip 300.

[0098] 1.2 Manufacturing Method Figures 10 to 20 are cross-sectional views showing an example of the cross-sectional structure of the memory device during manufacturing of the first embodiment. Figures 10 to 17 correspond to the memory chip 200 in the cross-section shown in Figure 7. Figures 18 to 20 correspond to the cross-section shown in Figure 7.

[0099] First, memory chips 100 and 200 and circuit chip 300 are individually formed. Focusing on the formation process of memory chip 200, as shown in FIG10, an insulating layer 203 and a sacrificial member 251 are sequentially deposited on the upper surface of substrate 250 in the Z1 direction. On the upper surface of sacrificial member 251 in the Z1 direction, eight insulating layers 204 and eight sacrificial members 252 are sequentially and alternately deposited. On the upper surface of the uppermost sacrificial member 252 in the Z1 direction, an insulating layer 205 and a sacrificial member 253 are sequentially deposited. Insulating layers 203, 204, and 205, for example, contain silicon oxide. Sacrificial members 251, 252, and 253, for example, contain silicon nitride. This provides a multilayer structure corresponding to the multilayer wiring structure.

[0100] Next, as shown in FIG11, a stepped structure is formed in the region corresponding to the lead-out region HR of the laminated structure. When forming the stepped structure, the sacrificial member 253 and the insulating layer 204 are removed in the lead-out region HR. Furthermore, after thickening a portion of the stepped portion of each sacrificial member 251, 252, and 253 forming the stepped structure, the stepped structure is covered by the insulating layer 206. In addition, the thickened portion of a certain sacrificial member is formed in a manner that does not connect with the stepped portion of the sacrificial member in the upper layer in the Z1 direction. That is, there is an unthickened portion between the thickened portion of a certain sacrificial member and the non-stepped portion of the sacrificial member.

[0101] Subsequently, although the illustration is omitted, a structure corresponding to the memory pillar MP2 is formed. For example, a hole is formed in a predetermined area of ​​the multilayer structure where the memory pillar MP2 is formed. The hole penetrates the insulating layer 206 and the multilayer structure, reaching the substrate 250. Furthermore, the hole is filled by the sequential formation of the multilayer film 142, the semiconductor film 141, and the core film 140 within the hole. At this point, the end of the semiconductor film 141 on the substrate 250 side is covered by the multilayer film 142.

[0102] Next, as shown in FIG12, a hole H1 is formed in the predetermined area where the contact CC is formed. The hole H1 penetrates the insulating layer 206 and the laminated structure, reaching the substrate 250. In addition, the hole H1 penetrates the thickened stepped portion of the laminated structure. Thereby, the substrate 250 is exposed at the bottom of the hole H1. Furthermore, by oxidizing the portion of the substrate 250 exposed at the bottom of the hole H1, an insulator 209 is formed.

[0103] Next, as shown in FIG13, for example by wet etching, the portions of each sacrificial member 251 and 252 exposed in the hole H1 are removed. Thereby, the portions of each sacrificial member 251 and 252 disposed in the hole H1 form a recess.

[0104] Next, as shown in FIG14, the hole H1 is filled by sequentially forming an insulator 210 and a sacrificial member 254 within it. When the insulator 210 is formed, the depressions (small depressions) formed in the non-thick film portion of the sacrificial member within the hole H1 are filled by the insulator 210. On the other hand, the depressions (large depressions) formed in the thick film portion of the sacrificial member within the hole H1 are not filled by the insulator 210. That is, when the insulator 210 is formed, the large depressions within the hole H1 are maintained.

[0105] Next, as shown in FIG15, a gap SH is formed in a predetermined area of ​​the forming member SLT. The gap SH penetrates the insulating layer 206 and the multilayer structure, reaching the substrate 250. A replacement process for the multilayer structure is performed via the gap SH. In the replacement process for the multilayer structure, sacrificial members 251, 252, and 253 are selectively removed via the gap SH by wet etching with hot phosphoric acid or the like. Furthermore, a conductor is filled into the space where the sacrificial members 251, 252, and 253 have been removed via the gap SH. Subsequently, the conductor formed inside the gap SH is removed by an etch-back process. In this way, the conductor formed inside the gap SH is separated into a plurality of conductor layers. Based on the above, a wiring layer 223 is formed to function as a select gate line SGS, a plurality of wiring layers 224 are formed to function as word lines WL, and a wiring layer 225 is formed to function as a select gate line SGD. After the replacement treatment of the laminated structure, the gap SH is filled by the insulator 211 to form the component SLT.

[0106] Next, as shown in FIG16, a hole H2 is formed by removing the sacrificial member 254. Furthermore, a portion of the insulator 210 is removed through the hole H2. During the removal of the insulator 210, a portion of the insulator 210 remaining in the small recesses within the hole H2 is retained. On the other hand, a portion of the insulator 210 disposed within the large recesses of the hole H2, and the remaining portion of the insulator 210, are removed. As a result, the thickened wiring layers in wiring layers 223 and 224 are exposed within the hole H2, but the unthickened wiring layers are not exposed due to the remaining insulator 210.

[0107] Next, as shown in FIG17, a contact CC is formed by filling the hole H2 with a conductor 230. The conductor 230 selectively electrically connects to the thick-film wiring layer within the hole H2. On the other hand, the conductor 230 electrically insulates the unthickened wiring layer within the hole H2 by an insulator 210. Furthermore, the conductor 230 electrically insulates the substrate 250 within the hole H2 by an insulator 209. Subsequently, conductive layers 231, 232, and 233 of the memory chip 200 are formed.

[0108] Next, as shown in FIG18, the separately formed circuit chip 300 is bonded to the memory chip 200. During bonding, the conductive layer 233 of the memory chip 200 is electrically connected to the conductive layer 321 of the circuit chip 300.

[0109] Next, as shown in FIG19, the remaining portion of the memory chip 200 is formed. Specifically, for example, by first removing the substrate 250, the end of the stacked film 142 of the memory pillar MP2 is exposed. And, by removing the exposed end of the stacked film 142, the semiconductor film 141 is exposed. Next, a semiconductor layer 222 that functions as the source line SL is formed. Thereby, the semiconductor layer 222 is connected to the semiconductor film 141. Subsequently, the configuration of the semiconductor layer 222 in the Z2 direction above is formed.

[0110] Next, as shown in FIG20, the separately formed memory chip 100 is bonded to the memory chip 200. During bonding, the conductive layer 221 of the memory chip 200 is electrically connected to the conductive layer 131 of the memory chip 100.

[0111] Subsequently, the remaining portion of the memory chip 100 is formed. Based on the above, the memory device 3 is formed.

[0112] 1.3 Effects of the First Embodiment According to the first embodiment, the conductor 230 extends in the Z direction to reach the semiconductor layer 222 in a manner that intersects with wiring layers 223, 224, and 225. The conductor 230 is in contact with one of the wiring layers 223, 224, and 225, and is electrically insulated from the other wiring layers 223, 224, and 225 and the semiconductor layer 222. The conductor 230 electrically connects the substrate 303 to one of the wiring layers 122, 123, and 124. Thereby, the word lines WL disposed on the memory chip 100 and the word lines WL disposed on the memory chip 200 can be electrically connected via the conductor 230. Therefore, the stepped structure disposed on the memory chip 100 and the stepped structure disposed on the memory chip 200 can be arranged at a position that overlaps when viewed along the Z direction. Therefore, the volume density can be improved.

[0113] Furthermore, the conductor 128 extends in the Z direction to reach the semiconductor layer 121 in a manner intersecting with wiring layers 122, 123, and 124. The conductor 128 is connected to one of the wiring layers 122, 123, and 124, and is electrically insulated from the other wiring layers 122, 123, and 124 and the semiconductor layer 121. The conductor 128 electrically connects one of the wiring layers 122, 123, and 124 to the conductor 230. In this way, by setting the memory chips 100 and 200 to have the same structure, the memory chips 100 and 200 can be manufactured in the same process before bonding. Therefore, the manufacturing cost can be reduced compared to manufacturing the memory chips 100 and 200 in separate processes.

[0114] Furthermore, each of the multilayer wirings disposed on memory chips 100 and 200 has a stepped portion that does not overlap with the wiring layer on the substrate 303 side when viewed along the Z direction. Conductor 230 is in contact with one of wiring layers 223, 224, and 225 in the stepped portion. Conductor 128 is in contact with one of wiring layers 122, 123, and 124 in the stepped portion. The thickness of the wiring layer in the portion in contact with conductors 230 and 128 is greater than the thickness of the other portions. Therefore, when a stepped structure is provided in the lead-out region HR, conductors 230 and 128 can be formed as if the stepped structure extends through them.

[0115] 1.4 Examples of variations of the first implementation form The first implementation form can be applied in various ways.

[0116] In the first embodiment, the configuration in which the word lines WL of memory chip 100 and memory chip 200 are connected through a multilayer wiring structure via a contact CC has been described, but this is not the only possibility. For example, the word lines WL of memory chip 100 and memory chip 200 can also be connected via a contact that is separate from the contact CC and does not connect through a multilayer wiring structure. Hereinafter, the configuration that differs from the first embodiment will be described. The configuration that is the same as that in the first embodiment will be omitted from the description as appropriate.

[0117] 1.4.1 Planar Layout of Memory Cell Array Figure 21 is a top view showing an example of the planar layout of the memory cell array in a memory device according to a variation of the first embodiment. Figure 21 corresponds to Figure 4 of the first embodiment. In Figure 21, two blocks BLK0 and BLK1 of the plurality of blocks BLK in the memory cell array 10 are illustrated.

[0118] As shown in Figure 21, in the memory cell array 10, the region separated by three consecutive adjacent components SLT corresponds to one block BLK.

[0119] In the example of Figure 21, in each of the memory regions MRa and MRb, one component SHE is arranged between two adjacent components SLT in the Y direction. Furthermore, the area separated by a group of adjacent components SLT and SHE, or a group of two adjacent components SHE, corresponds to one serial cell SU. More specifically, the area separated by the first and second consecutive three adjacent components SLT and the component SHE disposed between them corresponds to serial cells SU0 and SU1 within a block BLK. The area separated by the second and third consecutive three adjacent components SLT and the component SHE disposed between them corresponds to serial cells SU2 and SU3 within a block BLK.

[0120] Furthermore, in the example of Figure 21, it is shown that the multilayer wiring configuration corresponding to one block BLK is interrupted by the second break of three consecutive adjacent SLT components. In this case, the two interrupted multilayer wiring configurations are electrically connected by wiring not shown. Also, not limited to the above example, it is also possible to have a discontinuous configuration in the X direction for the second break of three consecutive adjacent SLT components without completely interrupting the multilayer wiring configuration corresponding to one block BLK.

[0121] Figure 22 is a top view of region XXII in Figure 21, showing one example of the planar layout of the memory cell array in the memory device of the first embodiment. Figure 22 corresponds to Figure 5 in the first embodiment.

[0122] First, the planar layout of the memory cell array 10 in the memory region MRb will be explained.

[0123] As shown in Figure 22, the memory cell array 10 is in the memory region MRb, for example, including a plurality of memory cylinders MP, a plurality of contacts CH and a plurality of bit lines BL.

[0124] Each memory column MP functions as a NAND string NS. Multiple memory columns MP are arranged in a zigzag pattern of 9 rows in the area between two adjacent component SLTs. For example, a component SHE is arranged overlapping with the memory column MP in the 5th row from the top of the paper.

[0125] Next, the planar layout of the memory cell array 10 in the outgoing region HR will be explained.

[0126] The memory cell array 10 includes a plurality of contacts CC and CX, and wiring MK, in the lead-out area HR. Furthermore, the multilayer wiring in the lead-out area HR has a stepped portion, a bus portion HW, and an insulating portion. The insulating portion is the cut-through area of ​​the multilayer wiring. An insulating member OB is filled into the insulating portion. The stepped portion is formed within one of the regions separated by the member SLT in a block BLK. The insulating portion is formed within the other region separated by the member SLT in a block BLK.

[0127] The contact CC is a conductor used for the connection between the serial decoder module 15 and the stack-up wiring. A plurality of contacts CC corresponding to the block BLK are respectively connected to the step portion of the select gate lines SGS and SGD provided in the lead-out area HR, and the word lines WL0 to WL7. When the select gate line SGD on the memory area MRa side and the select gate line SGD on the memory area MRb side correspond to the same serial unit SU, they are electrically connected, for example, via the contact CC and the upper wiring layer (not shown).

[0128] The contact CX is a conductor used for connection between the serial decoder module 15 and the multilayer wiring in different memory chips. A plurality of contacts CX corresponding to the block BLK are configured in the component OB located in the lead-out area HR.

[0129] The wiring MK is used to connect the corresponding contacts CC and CX. The conductive paths led out from the stacked wiring in different memory chips are converged into a common conductive path through the wiring MK and then connected to the column decoder module 15.

[0130] 1.4.2 Cross-sectional view of memory device Figure 23 is a cross-sectional view along line XXIII-XXIII of Figure 22, showing one example of the cross-sectional structure of a memory device in a variation of the first embodiment. Figure 23 corresponds to Figure 7 in the first embodiment.

[0131] First, with reference to FIG23 on one side, the cross-sectional structure of the memory chip 200 will be described on the other side.

[0132] The memory chip 200 further includes an insulator 212 and a conductor 234.

[0133] Conductor 230 is disposed on the upper surface of the stepped portion of the corresponding wiring layer 223, 224 and 225 in the Z1 direction, and extends in the Z direction. The upper end of conductor 230 in the Z1 direction reaches, for example, above wiring layer 225 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0134] The insulator 212 has a portion forming a column. The insulator 212 is provided in such a way that it penetrates the insulator layers 203 and 204, as well as the wiring layers 223 and 224, and is used as a component OB.

[0135] Conductor 234 is provided in a manner that penetrates insulator 212 and extends in the Z1 direction. The upper end of conductor 234 in the Z1 direction reaches, for example, above wiring layer 225 in the Z1 direction. Conductor 234 has a columnar shape and is used as contact CX.

[0136] An insulator 209 is provided between the conductor 234 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 234 and the semiconductor layer 222 are electrically insulated.

[0137] A conductor 229 is disposed on the upper surface of the conductor layer 221 in the Z1 direction and extends in the Z direction. The upper end of the conductor 229 in the Z1 direction is connected to the conductor 234. An insulator 208 is disposed on the side surface of the conductor 229. Therefore, the conductor 229 is electrically insulated from the semiconductor layer 222, and the conductor 234 is electrically connected to the conductor layer 221.

[0138] The common conductive layer 231 is connected to the upper surface of the conductor 230 in the Z1 direction and the upper surface of the corresponding conductor 234 in the Z1 direction. The conductive layer 231 is used as wiring MK.

[0139] The other configurations of the memory chip 200 in the variation of the first embodiment are the same as those of the memory chip 200 in the first embodiment shown in FIG7. Furthermore, the configuration of the memory chip 100 in the variation of the first embodiment is the same as that of the memory chip 200 in the variation of the first embodiment described above.

[0140] 1.4.3 Effects of the Variation of the First Embodiment According to the variation of the first embodiment, the conductor 230 is disposed on the surface of one of the wiring layers 223, 224, and 225 on the side of the substrate 303, and extends in the Z direction. The conductor 234 extends in the Z direction in a manner that intersects with the wiring layers 223, 224, and 225 to reach the semiconductor layer 222. The conductor 234 is electrically connected to one of the wiring layers 223, 224, and 225 via the conductor 230, and is electrically insulated from the wiring layers 223, 224, and 225 and the semiconductor layer 222 other than the one layer mentioned above. The conductor 234 electrically connects the substrate 303 to one of the wiring layers 122, 123, and 124 without passing through the conductor 230. In this way, a conductor 234 that does not penetrate the stepped structure can be used to electrically connect the word line WL provided on the memory chip 100 and the word line WL provided on the memory chip 200. Therefore, similar to the first embodiment, the stepped structure provided on the memory chip 100 and the stepped structure provided on the memory chip 200 can be arranged at a position that overlaps when viewed along the Z direction.

[0141] 2. Second Embodiment Next, the memory device of the second embodiment will be described. The difference between the second embodiment and the first embodiment is that a stepped structure is not formed in the multilayer wiring structure. In the following description, the structure and manufacturing method that are different from the first embodiment will be mainly described. The description of the structure and manufacturing method that are the same as the first embodiment will be omitted as appropriate.

[0142] 2.1 Planar Layout of Memory Cell Array Figure 24 is a top view showing an example of the planar layout of the memory cell array provided in the memory device of the second embodiment. Figure 24 corresponds to Figure 5 in the first embodiment.

[0143] As shown in Figure 24, the planar layout of the memory region MRb in the second embodiment is the same as that in the first embodiment.

[0144] The stacked wiring of the memory cell array 10 does not have a stepped portion in the lead-out region HR. Therefore, all the stacked wiring in the lead-out region HR functions as the bus portion HW. Furthermore, in the lead-out region HR (the bus portion HW), a plurality of contacts CC corresponding to the select gate line SGS and the word lines WL0 to WL7 are configured respectively.

[0145] 2.2 Cross-sectional Structure of Memory Device Figure 25 is a cross-sectional view along line XXV-XXV of Figure 24, showing one example of the cross-sectional structure of the memory device in the second embodiment. Figure 26 is a cross-sectional view along line XXVI-XXVI of Figure 24, showing one example of the cross-sectional structure of the memory device in the second embodiment. Figures 25 and 26 correspond to Figures 6 and 7 in the first embodiment, respectively.

[0146] The memory chip 100 includes memory pillar MP1, insulating layers 101-106, insulators 107-109, 161, and 163, semiconductor layer 121, wiring layers 122-124, conductive layers 127, 129, and 131, and conductors 125, 126, 128, 130, and 162.

[0147] The structure of the insulating layer 101 and the semiconductor layer 121 is the same as that of the first embodiment.

[0148] The configuration of the multilayer wiring structure is the same as in the first embodiment, except that the insulating layers 102-104 and wiring layers 122 and 123 do not have stepped portions in the lead-out region HR. Therefore, the film thickness of wiring layers 122-124 is generally uniform.

[0149] The memory column MP1, insulator 109, conductors 125 and 126, and conductor layer 127 are configured the same as in the first embodiment.

[0150] Conductor 128 extends in the Z direction within the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 128, for example, reaches semiconductor layer 121. The other end of conductor 128, for example, reaches above wiring layer 124 in the Z1 direction. Conductor 128 has a columnar shape and is used as a contact CC.

[0151] An insulator 107 is provided between the conductor 128 and the semiconductor layer 121. The insulator 107 may contain, for example, silicon oxide. Thereby, the conductor 128 and the semiconductor layer 121 are electrically insulated.

[0152] An insulator 108 is provided between the conductor 128 and the wiring layer lower in the Z1 direction of the corresponding wiring layer. Thereby, the conductor 128 is electrically insulated from the wiring layer lower in the Z1 direction of the corresponding wiring layer among the wiring layers 122, 123 and 124.

[0153] The conductor 128 and the corresponding wiring layer are electrically connected to each other by side contact. The diameter of the portion of the conductor 128 that contacts the corresponding wiring layer is larger than the other portions of the conductor 128. The diameter of the portion of the conductor 128 that contacts the corresponding wiring layer is, for example, the same as the diameter of the insulator 108.

[0154] Furthermore, an insulator 161, a conductor 162, and an insulator 163 are provided between the conductor 128 and the corresponding wiring layer in the Z1 direction of the layered wiring structure.

[0155] FIG27 is a cross-sectional view along line XXVII-XXVII of FIG25, showing one example of the cross-sectional structure of the contact of the memory device of the second embodiment. FIG27 shows a cross-section including the contact CC and the wiring layer above the corresponding wiring layer in the Z1 direction, and parallel to the XY plane.

[0156] As shown in FIG. 27, the portion of the insulator 163 surrounding the conductor 128 is higher in the Z1 direction than the portion connected to the wiring layer. The conductor 162 surrounds the side of the insulator 163. The end of the conductor 162 is in contact with both the wiring layer and the conductor layer 128 at the connection portion between the conductor 128 and the wiring layer it surrounds. The conductor 162 is provided as a continuous film connected to the wiring layer. The insulator 161 surrounds the side of the conductor 162. Furthermore, a multilayer wiring structure higher in the Z1 direction than the wiring layer connected to the conductor 128 surrounds the side of the insulator 161.

[0157] According to the above configuration, the conductor 128 is electrically insulated from the insulating material 107, and is electrically insulated from the wiring layer below the connected wiring layer in the Z1 direction, and the insulating material 161 is electrically insulated from the wiring layer above.

[0158] The conductive layers 129 and 131, the conductor 130, and the insulating layers 105 and 106 are configured in the same way as in the first embodiment.

[0159] Next, the cross-sectional structure of the memory chip 200 will be described.

[0160] The memory chip 200 includes memory pillars MP2, insulating layers 201-207, insulators 208-211, 261 and 263, semiconductor layer 222, wiring layers 223-225, conductive layers 221, 228, 231 and 233, and conductors 226, 227, 229, 230, 232 and 262.

[0161] The structure of insulating layers 201 and 202, insulator 208, conductor layer 221, semiconductor layer 222 and conductor 229 is the same as in the first embodiment.

[0162] The configuration of the multilayer wiring structure is the same as in the first embodiment, except that the insulating layers 203-205 and wiring layers 223 and 224 do not have stepped portions in the lead-out region HR. Therefore, the film thickness of wiring layers 223-225 is generally uniform.

[0163] The memory column MP2, insulator 211, conductors 226 and 227, and conductor layer 228 are configured the same as in the first embodiment.

[0164] Conductor 230 extends in the Z direction within the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 230, for example, reaches semiconductor layer 222. The other end of conductor 230, for example, reaches above wiring layer 225 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0165] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 230 and the semiconductor layer 222 are electrically insulated.

[0166] An insulator 210 is provided between the conductor 230 and the wiring layer lower in the Z1 direction of the corresponding wiring layer. Thereby, the conductor 230 is electrically insulated from the wiring layer lower in the Z1 direction of the corresponding wiring layer among the wiring layers 223, 224 and 25.

[0167] The conductor 230 and the corresponding wiring layer are electrically connected to each other by side contact. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is larger than that of other portions of the conductor 230. The film thickness of the portion with a larger diameter than other portions of the conductor 230 is, for example, greater than the film thickness of the wiring layer.

[0168] Furthermore, an insulator 261, a conductor 262, and an insulator 263 are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0169] Similar to the memory chip 100, the insulator 263 surrounds the side of the conductor 230, specifically the portion higher in the Z1 direction than the connection portion with the wiring layer. The conductor 262 surrounds the side of the insulator 263, and the side of the portion having a larger diameter than other portions of the conductor 230 that is not in contact with the wiring layer. The end of the conductor 262 is in contact with both the wiring layer and the conductor 230 at the connection portion between the conductor 230 and the wiring layer it surrounds. The conductor 262 is provided as a continuous film with the connected wiring layer. The insulator 261 surrounds the side of the conductor 262. Furthermore, a multilayer wiring structure higher in the Z1 direction than the wiring layer connected to the conductor 230 surrounds the side of the insulator 261.

[0170] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0171] The configuration of the conductive layers 231 and 233, the conductive layer 232, the insulating layers 206 and 207 of the memory chip 200, and the configuration of the circuit chip 300 are the same as in the first embodiment.

[0172] According to the above configuration, the specific character lines WL of memory chips 100 and 200 are electrically connected via conductors 128 and 230 and are commonly connected to the transistor TR in the circuit chip 300.

[0173] 2.3 Manufacturing Method Figures 28 to 37 are cross-sectional views showing an example of the cross-sectional structure of the memory device during manufacturing of the second embodiment. Figures 28 to 37 correspond to the memory chip 200 in the cross-section shown in Figure 26.

[0174] First, memory chips 100 and 200 and circuit chip 300 are individually formed. Focusing on the formation process of memory chip 200, a multilayer structure corresponding to the multilayer wiring structure is formed on the upper surface of substrate 250 in the Z1 direction by means of a process identical to that in the first embodiment.

[0175] Next, as shown in FIG28, the sacrificial member 253 and the insulating layer 204 in the lead-out region HR are removed. And, a hole H3 is formed in the predetermined region where the contact CC is formed. The hole H3 reaches the insulating layer disposed on the upper surface of the sacrificial member (the fourth sacrificial member 252 from the paper in FIG28) located in the same layer as the wiring layer that is connected to the corresponding contact CC in the Z1 direction.

[0176] Next, as shown in FIG29, an insulator 261 is formed in the hole H3. The insulator 261 comprises, for example, silicon oxide.

[0177] Next, as shown in FIG30, the bottom of the hole H3 is selectively etched to remove the insulator 261 at the bottom of the hole H3 and the insulating layer (the third insulating layer 204 from the paper in FIG28) on the lower surface of the insulator 261 in the Z1 direction. Thereby, the sacrificial member located on the same layer as the wiring layer for connecting to the corresponding contact CC is exposed at the bottom of the hole H3.

[0178] Next, as shown in FIG31, a sacrificial member 271 and an insulator 263 are sequentially formed in the hole H3, and the hole H3 is filled. The sacrificial member 271 comprises, for example, silicon nitride. The insulator 263 comprises, for example, silicon oxide.

[0179] Next, as shown in FIG32, a hole H4 is formed in the predetermined area where the contact CC is formed. The hole H4 penetrates the insulator 263, the sacrificial member 271 and the laminated structure, reaching the substrate 250. Thereby, the substrate 250 is exposed at the bottom of the hole H4. Furthermore, the insulator 209 is formed by oxidizing the portion of the substrate 250 exposed at the bottom of the hole H4.

[0180] Next, as shown in FIG33, for example, by wet etching, the portions of each sacrificial member 251, 252, and 271 exposed in the hole H4 are removed. This forms a recess in the portion of each sacrificial member 251, 252, and 271 disposed in the hole H4. Furthermore, in the hole H4, the sacrificial member 271 is in contact with a sacrificial member corresponding to a predetermined wiring layer connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 271 and the sacrificial member in the laminated structure in contact with the sacrificial member 271 has a larger film thickness of the sacrificial member 271 in the Z direction than other recesses.

[0181] Next, as shown in FIG34, the hole H4 is filled by sequentially forming an insulator 210 and a sacrificial member 272 within it. The sacrificial member 272 includes, for example, silicon. When the insulator 210 is formed, depressions (small depressions) of the same size and thickness as the sacrificial members 251 and 252 are filled by the insulator 210. On the other hand, depressions larger than the film thickness of the sacrificial members 251 and 252 (in FIG34, the large depressions formed by removing the fourth layer of sacrificial members 252 and 271 from the paper surface) are not filled by the insulator 210.

[0182] Next, as shown in FIG35, a gap SH is formed in a predetermined area of ​​the forming member SLT. The gap SH penetrates the insulating layer 206 and the multilayer structure, reaching the substrate 250. A replacement process for the multilayer structure is performed via the gap SH. In the replacement process for the multilayer structure, sacrificial members 251, 252, 253 and 271 are selectively removed via the gap SH by wet etching with hot phosphoric acid or the like. Furthermore, a conductor is filled into the space where the sacrificial members 251, 252, 253 and 271 have been removed via the gap SH. Subsequently, the conductor formed inside the gap SH is removed by an etch-back process. In this way, the conductor formed inside the gap SH is separated into a plurality of conductive layers. Based on the above, a wiring layer 223 is formed to function as a selectable gate line SGS, a plurality of wiring layers 224 are formed to function as word lines WL, and a wiring layer 225 is formed to function as a selectable gate line SGD. After the replacement treatment of the laminated structure, the gaps SH are filled with insulator 211 to form the component SLT.

[0183] Furthermore, in the above replacement process, the sacrificial member 271 is replaced with the conductor 262. Therefore, the conductor 262 becomes a continuous film with the wiring layer obtained by replacing the sacrificial member located in the same layer as the large recess formed in the hole H4. As a result, the predetermined portion of the wiring layer connected to the contact CC is thickened.

[0184] Next, as shown in FIG36, a hole H5 is formed by removing the sacrificial member 272. Furthermore, a portion of the insulator 210 is removed through the hole H5. When removing the insulator 210, a portion of the insulator 210 remaining in the small recesses of the hole H5 is left. On the other hand, a portion of the insulator 210 in the large recesses of the hole H5, and the remaining portion of the insulator 210, are removed. As a result, the thickened portions of the wiring layers 223 and 224 are exposed within the hole H5, but the unthickened portions are not exposed due to the remaining insulator 210.

[0185] Next, as shown in FIG37, a contact CC is formed by filling the hole H5 with a conductor 230. The conductor 230 selectively electrically connects to the thick-film wiring layer within the hole H5. On the other hand, the conductor 230 electrically insulates the non-thick-film wiring layer within the hole H5 by an insulator 210. Furthermore, the conductor 230 electrically insulates the substrate 250 within the hole H5 by an insulator 209.

[0186] Subsequently, similar to the first embodiment, a memory device 3 is formed by bonding the circuit chip 300 and the memory chip 100.

[0187] 2.4 Effects of the Second Embodiment According to the second embodiment, viewed along the Z direction, the wiring layer on the substrate 303 side of the wiring layer that is connected to the conductor 230 surrounds the portion of the conductor 230 that is on the substrate 303 side of the wiring layer that is connected to the conductor 230. The conductor 262 is connected to the conductor 230 on the substrate 303 side of the wiring layer that is connected to the conductor 230, and is provided as a continuous film of the wiring layer. The conductor 262 is provided in a manner that intersects with the wiring layer on the substrate 303 side of the wiring layer that is connected to the conductor 230. In this way, for a multilayer wiring structure that does not have a stepped structure, the conductor 230 can also be used to electrically connect the word lines WL provided on the memory chip 100 and the word lines WL provided on the memory chip 200. Therefore, similar to the first embodiment, the stepped structure provided on the memory chip 100 and the stepped structure provided on the memory chip 200 can be arranged at a position where they overlap when viewed along the Z direction. Therefore, the integration density can be improved.

[0188] 2.4 Examples of variations of the second implementation form The second implementation form can be applied in various ways.

[0189] 2.4.1 First Variation of the Second Embodiment In the second embodiment, the case where sacrificial members 271 are formed on the bottom and side surfaces of the hole H3 and replaced with conductors 262 has been described, but it is not limited to this. For example, the sacrificial members replaced with conductors in the hole H3 may not be provided on the side surfaces of the hole H3. Hereinafter, we will mainly describe the configuration and manufacturing method that are different from the second embodiment. The configuration and manufacturing method that are the same as the second embodiment will be omitted from the description as appropriate.

[0190] 2.4.1.1 Cross-sectional view of memory device Figure 38 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first variation of the second embodiment. Figure 38 corresponds to an enlarged view of the contact CC and its surrounding area in the memory chip 200 of Figure 26 in the second embodiment. Furthermore, the configuration of this part of the memory chip 100 is also the same as that shown in Figure 38.

[0191] As shown in FIG38, in the first variation of the second embodiment, the memory chip 200 includes insulating layers 203, 204 and 206, insulators 208, 209, 210, 261 and 263, semiconductor layer 222, wiring layers 223 and 224, and conductors 229, 230 and 264 around the contact CC.

[0192] The insulating layers 203, 204 and 206, the insulators 208, 209 and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are configured in the same way as in the second embodiment.

[0193] Conductor 230 extends in the Z direction within the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 230, for example, reaches semiconductor layer 222. The other end of conductor 230, for example, reaches above wiring layer 225 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0194] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 230 and the semiconductor layer 222 are electrically insulated.

[0195] An insulator 210 is provided between the conductor 230 and the wiring layer lower in the Z1 direction of the corresponding wiring layer. Thereby, the conductor 230 is electrically insulated from the wiring layer lower in the Z1 direction of the corresponding wiring layer among the wiring layers 223, 224 and 25.

[0196] The conductor 230 and the corresponding wiring layer are electrically connected to each other by side contact. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is larger than that of other portions of the conductor 230. The film thickness of the portion with a larger diameter than other portions of the conductor 230 is, for example, greater than the film thickness of the wiring layer.

[0197] Furthermore, an insulator 261 and an insulator 263, as well as a conductor 264, are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0198] The insulator 263 surrounds the side of the conductor 230, and is located above the portion connected to the wiring layer in the Z1 direction. The insulator 261 surrounds the side of the insulator 263. Furthermore, a multilayer wiring structure located above the wiring layer connected to the conductor 230 in the Z1 direction surrounds the side of the insulator 261. The conductor 264 surrounds the side of the conductor 230 in such a way that it contacts either the conductor 230 or the wiring layer at the contact portion between the conductor 230 and the wiring layer. The conductor 264 is provided as a continuous film connected to the wiring layer.

[0199] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0200] 2.4.1.2 Manufacturing Method Figures 39 to 43 are cross-sectional views showing an example of the cross-sectional structure of the memory device during the manufacturing process of the first variation of the second embodiment. Figures 39 to 43 correspond to Figure 38.

[0201] First, the same structure as in FIG30 is formed by the same process as in the second embodiment. That is, a hole H3 is formed in the predetermined area of ​​the contact CC in the multilayer structure. After forming an insulator 261 in the hole H3, the sacrificial member directly below is exposed by etching the bottom of the hole H3.

[0202] Next, as shown in FIG39, a sacrificial member 273 is selectively grown on the sacrificial member exposed at the bottom of the hole H3. The sacrificial member 273 comprises, for example, silicon nitride. The film thickness of the sacrificial member 273 is, for example, less than the film thickness of the insulating layer 204 in the multilayer structure.

[0203] Next, as shown in FIG40, the hole H3 is filled by forming an insulator 263 inside the hole H3.

[0204] Next, as shown in FIG41, a hole H4 is formed in the predetermined area where the contact CC is formed. The hole H4 penetrates the insulator 263, the sacrificial member 273, and the multilayer structure, reaching the substrate 250. Thereby, the substrate 250 is exposed at the bottom of the hole H4. And, by oxidizing the portion of the substrate 250 exposed at the bottom of the hole H4, an insulator 209 is formed. Thereafter, for example, by wet etching, the portions of each sacrificial member 251 and 252 exposed in the hole H4 are removed. Thereby, the portions of each sacrificial member 251 and 252 disposed in the hole H4 form a recess. In addition, in the hole H4, the sacrificial member 273 is in contact with the sacrificial member of the predetermined wiring layer connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 273 and the sacrificial member in the multilayer structure in contact with the sacrificial member 273 is larger in the Z direction than other recesses.

[0205] Next, as shown in FIG42, the hole H4 is filled by sequentially forming an insulator 210 and a sacrificial member 272 inside the hole H4. When the insulator 210 is formed, a small depression of the same size as the film thickness of the sacrificial members 251 and 252 is filled by the insulator 210. On the other hand, a large depression that is larger than the film thickness of the sacrificial members 251 and 252 (in FIG42, a large depression formed by removing the fourth layer of sacrificial member 252 from the paper surface and the sacrificial member 251 connected to the sacrificial member 252) is not filled by the insulator 210.

[0206] Next, as shown in FIG43, a replacement process for the layered structure is performed. Thereby, sacrificial members 251, 252 and 253 are replaced with wiring layers 223, 224 and 225, respectively.

[0207] Furthermore, in the above replacement process, the sacrificial member 273 is replaced with the conductor 264. Therefore, the conductor 264 becomes a continuous film with the wiring layer located on the same layer as the large recess formed in the hole H4. As a result, the predetermined portion of the wiring layer connected to the contact CC is thickened.

[0208] Subsequently, similar to the second embodiment, a portion of the sacrificial member 272 and the insulator 210 is removed to form a contact CC. Furthermore, after a bonding process of the circuit chip 300 and the memory chip 100, a memory device 3 is formed.

[0209] 2.4.1.3 Effects of the First Variation of the Second Embodiment According to the first variation of the second embodiment, the sacrificial member 273 is formed by selective growth. Thereby, the conductor 264, which replaces the sacrificial member 273, is arranged in a manner that does not intersect with the wiring layer on the substrate 303 side that is in contact with the conductor 230. Therefore, the formation of a conductor in the structure between the portion of the conductor 230 on the substrate 303 side that is in contact with the corresponding wiring layer and the multilayer wiring can be suppressed. Therefore, unintentional short circuits between the conductor and the wiring layer can be suppressed.

[0210] 2.4.2 Second Variation of the Second Embodiment Furthermore, in the second embodiment, the case where the contact CC is connected to the wiring layer by a side has been described, but it is not limited to this. For example, the contact CC may also be connected to the upper surface of the wiring layer. Hereinafter, we will mainly describe the configuration and manufacturing method that differ from the second embodiment. Descriptions of configurations and manufacturing methods identical to those in the second embodiment will be appropriately omitted.

[0211] 2.4.2.1 Cross-sectional Structure of Memory Device Figure 44 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second variation of the second embodiment. Figure 44 corresponds to an enlarged view of the contact CC and its surrounding area in the memory chip 200 of Figure 26 in the second embodiment. Furthermore, the configuration of this part of the memory chip 100 is the same as that shown in Figure 44.

[0212] As shown in FIG44, in the second variation of the second embodiment, the memory chip 200 includes insulating layers 203, 204 and 206, insulators 208, 209, 210, 261, 263 and 265, sacrificial member 266, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 around the contact CC.

[0213] The insulating layers 203, 204 and 206, the insulators 208, 209 and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are configured in the same way as in the second embodiment.

[0214] Conductor 230 extends in the Z direction within the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 230, for example, reaches semiconductor layer 222. The other end of conductor 230, for example, reaches above wiring layer 225 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0215] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 230 and the semiconductor layer 222 are electrically insulated.

[0216] An insulator 210 is provided between the conductor 230 and the corresponding wiring layer, and between the wiring layer below the corresponding wiring layer in the Z1 direction. This provides electrical insulation between the conductor 230 and the wiring layer below the corresponding wiring layer in the Z1 direction among the wiring layers 223, 224, and 225. Furthermore, within the same layer as the corresponding wiring layer, the conductor 230 is separated from the wiring layer by the insulating material 210.

[0217] The conductor 230 and the corresponding wiring layer are electrically connected to each other by contacting each other on their upper surfaces in the Z1 direction. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is, for example, larger than the diameter of the insulator 210. The film thickness of the portion of the conductor 230 that has a diameter larger than that of the insulator 210 is, for example, larger than the film thickness of the wiring layer.

[0218] Furthermore, insulators 261, 263 and 265, and sacrificial member 266 are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0219] The portion of the insulator 263 surrounding the conductor 230 that is higher in the Z1 direction than the portion connected to the wiring layer. The sacrificial member 266 surrounds the side of the insulator 263 and the side of the conductor 230 that is connected to the wiring. The insulator 265 surrounds the side of the sacrificial member 266. The insulator 261 surrounds the side of the insulator 265. Furthermore, the multilayer wiring structure that is higher in the Z1 direction than the wiring layer connected to the conductor 230 surrounds the side of the insulator 261.

[0220] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0221] 2.4.2.2 Manufacturing Method Figures 45 to 50 are cross-sectional views showing an example of the cross-sectional structure of the memory device during the manufacturing process of the second variation of the second embodiment. Figures 45 to 50 correspond to Figure 44.

[0222] First, a layered structure is formed by a process identical to that in the second embodiment.

[0223] Next, as shown in FIG45, a hole H3 is formed in a predetermined area of ​​the contact CC in the multilayer structure. At the bottom of the hole H3, a sacrificial member corresponding to the predetermined wiring layer connected to the contact CC is exposed. Furthermore, after the insulator 261 is formed in the hole H3, the sacrificial member directly below is exposed by etching the bottom of the hole H3.

[0224] Next, as shown in FIG46, the hole H3 is filled by sequentially forming an insulator 265, a sacrificial member 266, and an insulator 263 within the hole H3. The insulator 265 comprises, for example, silicon oxide. The sacrificial member 266 comprises, for example, silicon nitride. The film thickness of the sacrificial member 266 is, for example, greater than the film thickness of the insulating layer 204 within the laminated structure.

[0225] Next, as shown in FIG47, a hole H4 is formed in the predetermined area where the contact CC is formed. The hole H4 penetrates the insulator 263, the sacrificial member 266, the insulator 265, and the multilayer structure, reaching the substrate 250. This exposes the substrate 250 at the bottom of the hole H4. Furthermore, an insulator 209 is formed by oxidizing the portion of the substrate 250 exposed at the bottom of the hole H4. Subsequently, for example, by wet etching, the portions of each sacrificial member exposed within the hole H4 are removed. This forms a recess in the portion where each sacrificial member is disposed within the hole H4. Additionally, as described above, the film thickness of the sacrificial member 266 is greater than the film thickness of the sacrificial member within the multilayer structure. Therefore, the recess formed by removing the sacrificial member 266 is larger in the Z direction than other recesses.

[0226] Next, as shown in FIG48, the hole H4 is filled by sequentially forming an insulator 210 and a sacrificial member 272 within it. When the insulator 210 is formed, small recesses of the same size and thickness as the sacrificial members 251 and 252 are filled by the insulator 210. On the other hand, large recesses of the same size and thickness as the sacrificial member 266 are not filled by the insulator 210.

[0227] Next, as shown in FIG49, a replacement process for the layered structure is performed. Thereby, sacrificial members 251, 252 and 253 are replaced with wiring layers 223, 224 and 225, respectively.

[0228] Next, as shown in FIG50, a hole H5 is formed by removing the sacrificial member 272. Furthermore, a portion of the insulator 210 is removed through the hole H5. When removing the insulator 210, a portion of the insulator 210 remaining in the small recess within the hole H5 is left. On the other hand, a portion of the insulator 210 in the large recess within the hole H5, and the remaining portion of the insulator 210, are removed. As a result, the sacrificial member 266 is exposed within the hole H5, but wiring layers 223 and 224 are not exposed. Subsequently, the sacrificial member 266 and the insulator 265 are further partially removed. As a result, the upper surface of the wiring layer in the Z1 direction is exposed in the space formed by removing the sacrificial member 266 and the insulator 265.

[0229] Subsequently, a contact CC is formed by filling the hole H5 with a conductor 230. Herein, the conductor 230 is connected to the portion of the corresponding wiring layer exposed in the hole H5. And, similar to the second embodiment, the memory device 3 is formed by bonding the circuit chip 300 and the memory chip 100.

[0230] 2.4.2.3 Effects of the Second Variation of the Second Embodiment According to the second variation of the second embodiment, the sacrificial member 266 is connected to the conductor 230 on the side of the wiring layer closer to the substrate 303 than the conductor 230. Thus, the conductor 230 is arranged to fill the space in which a portion of the sacrificial member 266 has been removed. This allows the diameter of the conductor 230 electrically connected to the wiring layer to be larger than other portions of the conductor 230. Therefore, the conductor 230 can be configured to be connected to the surface of the wiring layer on the substrate 303 side.

[0231] Furthermore, the insulator 263 is disposed between the conductor 230 and the sacrificial member 266 when viewed along the Z direction. In this way, the larger diameter portion of the conductor 230 can be confined to the portion in contact with the wiring layer.

[0232] 2.4.3 Third Variation of the Second Embodiment Furthermore, in the second variation of the second embodiment, the case where an insulator 263 is provided on the side of the contact CC has been described, but it is not limited to this. For example, a sacrificial member 266 may also be provided on the side of the contact CC. Hereinafter, the configuration and manufacturing method that differ from the second variation of the second embodiment will be mainly described. The configuration and manufacturing method that are the same as those in the variation of the second embodiment will be appropriately omitted from the description.

[0233] 2.4.3.1 Cross-sectional Structure of Memory Device Figure 51 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the third variation of the second embodiment. Figure 51 corresponds to Figure 44 in the second variation of the second embodiment. Furthermore, the configuration of this part of the memory chip 100 is also the same as that shown in Figure 51.

[0234] As shown in FIG51, in the third variation of the second embodiment, the memory chip 200 includes insulating layers 203, 204 and 206, insulators 208, 209, 210, 261 and 265, sacrificial member 266, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 around the contact CC.

[0235] The composition of insulating layers 203, 204 and 206, insulators 208, 209 and 210, semiconductor layer 222, wiring layers 223 and 224, and conductor 229 is the same as that of the second variation of the second embodiment.

[0236] Conductor 230 extends in the Z direction within the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 230, for example, reaches semiconductor layer 222. The other end of conductor 230, for example, reaches above wiring layer 225 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0237] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 230 and the semiconductor layer 222 are electrically insulated.

[0238] An insulator 210 is provided between the conductor 230 and its corresponding wiring layer, and between the wiring layer below the corresponding wiring layer in the Z1 direction. This provides electrical insulation between the conductor 230 and the wiring layer below the corresponding wiring layer in the Z1 direction among the wiring layers 223, 224, and 25. Furthermore, within the same layer as the corresponding wiring layer, the conductor 230 is separated from the wiring layer by the insulating material 210.

[0239] The conductor 230 and the corresponding wiring layer are electrically connected to each other by contacting each other on their upper surfaces in the Z1 direction. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is, for example, larger than the diameter of the insulator 210. The film thickness of the portion of the conductor 230 that has a diameter larger than that of the insulator 210 is, for example, the same as the film thickness of the multilayer wiring structure above the Z1 direction of the corresponding wiring layer.

[0240] Furthermore, insulators 261 and 265 and sacrificial member 266 are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0241] The sacrificial member 266 surrounds the side of the conductor 230, and is located above the portion connected to the wiring layer in the Z1 direction. The insulator 265 surrounds the side of the sacrificial member 266. The insulator 261 surrounds the side of the insulator 265. Furthermore, the laminated wiring structure located above the wiring layer connected to the conductor 230 in the Z1 direction surrounds the side of the insulator 261.

[0242] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0243] 2.4.3.2 Manufacturing Method Figures 52 to 56 are cross-sectional views showing an example of the cross-sectional structure of the memory device during the manufacturing process of the third variation of the second embodiment. Figures 52 to 56 correspond to Figure 51.

[0244] First, using the same process as the second variation of the second embodiment, a hole is formed in a predetermined area of ​​the contact CC in the multilayer structure. At the bottom of the hole, a sacrificial member corresponding to a predetermined wiring layer connected to the contact CC is exposed. Furthermore, after forming an insulator 261 inside the hole, the sacrificial member directly below is exposed by etching the bottom of the hole.

[0245] Next, as shown in FIG52, the hole is filled by sequentially forming an insulator 265 and a sacrificial member 266 within the hole H3. The film thickness of the sacrificial member 266 is, for example, the same as the film thickness of the upper portion of the sacrificial member in the Z1 direction of the predetermined wiring layer corresponding to the connection with the contact CC in the multilayer structure.

[0246] Next, as shown in FIG53, a hole H4 is formed in the predetermined area where the contact CC is formed. The hole H4 penetrates the sacrificial member 266, the insulator 265, and the multilayer structure, reaching the substrate 250. Herein, the substrate 250 is exposed at the bottom of the hole H4. And, by oxidizing the portion of the substrate 250 exposed at the bottom of the hole H4, the insulator 209 is formed. Thereafter, for example by wet etching, the portions of each sacrificial member exposed in the hole H4 are removed. Herein, the portions of each sacrificial member disposed in the hole H4 are formed into a recess. In addition, as described above, the film thickness of the sacrificial member 266 is the same as the film thickness of the upper portion of the sacrificial member in the multilayer structure corresponding to the predetermined wiring layer connected to the contact CC in the Z1 direction. Therefore, the recess formed by removing the sacrificial member 266 is larger in the Z direction than other recesses.

[0247] Next, as shown in FIG54, the hole H4 is filled by sequentially forming an insulator 210 and a sacrificial member 272 within it. When the insulator 210 is formed, a depression (small depression) of the same size as the film thickness of the sacrificial members 251 and 252 is filled by the insulator 210. On the other hand, a depression (large depression) of the same size as the film thickness of the sacrificial member 266 is not filled by the insulator 210.

[0248] Next, as shown in FIG55, a replacement process for the layered structure is performed. Thereby, sacrificial members 251, 252 and 253 are replaced with wiring layers 223, 224 and 225, respectively.

[0249] Next, as shown in FIG56, a hole H5 is formed by removing the sacrificial member 272. Furthermore, a portion of the insulator 210 is removed through the hole H5. When removing the insulator 210, a portion of the insulator 210 remaining in the small recess within the hole H5 is left. On the other hand, a portion of the insulator 210 in the large recess within the hole H5, and the remaining portion of the insulator 210, are removed. As a result, the sacrificial member 266 is exposed within the hole H5, but the wiring layers 223 and 224 are not exposed. Subsequently, the sacrificial member 266 and the insulator 265 are further partially removed. As a result, the upper surface of the wiring layer in the Z1 direction is exposed in the space formed by removing the sacrificial member 266 and the insulator 265.

[0250] Subsequently, a contact CC is formed by filling the hole H5 with a conductor 230. And, similar to the second embodiment, a memory device 3 is formed by bonding the circuit chip 300 and the memory chip 100.

[0251] 2.4.3.3 Effects of the Third Variation of the Second Embodiment According to the third variation of the second embodiment, the sacrificial member 266 is connected to the conductor 230 at both ends in the span and Z direction. Hereby, the process of forming a film of the insulator 263 in the hole H3 can be omitted.

[0252] 2.4.4 Fourth Variation of the Second Embodiment Furthermore, in the second embodiment, the replacement process of sacrificial member 271 with conductor 262 during the replacement process of sacrificial members 251, 252, and 253 with wiring layers 223, 224, and 225 has been described, but it is not limited to this. For example, sacrificial member 271 can be replaced by using a sacrificial member made of a different material than sacrificial members 251, 252, and 253, and the replacement process of the sacrificial member can be performed at a different time sequence than the replacement processes of sacrificial members 251, 252, and 253. Hereinafter, the configuration and manufacturing method different from the second embodiment will be mainly described. The configuration and manufacturing method identical to the second embodiment will be appropriately omitted from the description.

[0253] 2.4.4.1 Cross-sectional view of memory device Figure 57 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to the fourth variation of the second embodiment. Figure 57 corresponds to an enlarged view of the contact CC and its surrounding area in the memory chip 200 of Figure 26 in the second embodiment. Furthermore, the configuration of this part of the memory chip 100 is the same as that shown in Figure 57.

[0254] As shown in FIG57, in the fourth variation of the second embodiment, the memory chip 200 includes insulating layers 203, 204 and 206, insulators 208, 209, 210, 261 and 263, sacrificial member 267, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 around the contact CC.

[0255] The insulating layers 203, 204 and 206, the insulators 208, 209 and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are configured in the same way as in the second embodiment.

[0256] Conductor 230 extends in the Z direction within the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 230, for example, reaches semiconductor layer 222. The other end of conductor 230, for example, reaches above wiring layer 225 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0257] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 230 and the semiconductor layer 222 are electrically insulated.

[0258] An insulator 210 is provided between the conductor 230 and the wiring layer lower in the Z1 direction of the corresponding wiring layer. Thereby, the conductor 230 is electrically insulated from the wiring layer lower in the Z1 direction of the corresponding wiring layer among the wiring layers 223, 224 and 25.

[0259] The conductor 230 and the corresponding wiring layer are electrically connected to each other by side contact. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is larger than that of other portions of the conductor 230. The film thickness of the portion with a larger diameter than other portions of the conductor 230 is, for example, greater than the film thickness of the wiring layer.

[0260] Furthermore, insulators 261 and 263 and sacrificial member 267 are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0261] The insulator 263 surrounds the side of the conductor 230, specifically the portion higher in the Z1 direction than the portion connected to the wiring layer. The sacrificial member 267 surrounds the side of the insulator 263, and the side of the portion of the conductor 230 with a diameter larger than other portions, but not connected to the wiring layer. The insulator 261 surrounds the side of the sacrificial member 267. Furthermore, the laminated wiring structure, higher in the Z1 direction than the wiring layer connected to the conductor 230, surrounds the side of the insulator 261.

[0262] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0263] 2.4.4.2 Manufacturing Method Figures 58 to 63 are cross-sectional views showing an example of the cross-sectional structure of the memory device during the manufacturing process of the fourth variation of the second embodiment. Figures 58 to 63 correspond to Figure 57.

[0264] First, the same structure as in FIG30 is formed by the same process as in the second embodiment. That is, a hole H3 is formed in the predetermined area of ​​the contact CC in the multilayer structure. After forming an insulator 261 in the hole H3, the sacrificial member directly below is exposed by etching the bottom of the hole H3.

[0265] Next, as shown in FIG58, the hole H3 is filled by sequentially forming a sacrificial member 267 and an insulator 263 within the hole H3. The sacrificial member 267 may contain, for example, silicon or silicon carbide (SiOC).

[0266] Next, as shown in FIG59, a hole H4 is formed in the predetermined area where the contact CC is formed. The hole H4 penetrates the insulator 263, the sacrificial member 267, and the multilayer structure, reaching the substrate 250. This exposes the substrate 250 at the bottom of the hole H4. Furthermore, an insulator 209 is formed by oxidizing the portion of the substrate 250 exposed at the bottom of the hole H4. Subsequently, for example, by wet etching, the portions of each sacrificial member 251 and 252 exposed within the hole H4 are removed. This forms a recess in the portion of the sacrificial members 251 and 252 disposed within the hole H4. Furthermore, the sacrificial member 267 is not selectively etched away from the sacrificial members 251 and 252.

[0267] Next, as shown in FIG60, for example, by wet etching, the sacrificial member 267 exposed in the hole H4 is partially removed. Furthermore, within the hole H4, the sacrificial member 267 is in contact with a sacrificial member corresponding to a predetermined wiring layer connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 267 and the sacrificial member within the stacked structure in contact with the sacrificial member 267 has a larger film thickness than other recesses in the Z direction.

[0268] Next, as shown in FIG61, the hole H4 is filled by sequentially forming an insulator 210 and a sacrificial member 272 inside the hole H4. When the insulator 210 is formed, a small depression of the same size as the film thickness of the sacrificial members 251 and 252 is filled by the insulator 210. On the other hand, a large depression that is larger than the film thickness of the sacrificial members 251 and 252 (in FIG61, a large depression formed by removing the fourth layer of sacrificial member 252 from the paper surface and the sacrificial member 267 connected to the sacrificial member 252) is not filled by the insulator 210.

[0269] Next, as shown in FIG62, a replacement process for the multilayer structure is performed. Here, sacrificial members 251, 252, and 253 are replaced with wiring layers 223, 224, and 225, respectively. However, sacrificial member 267 is not replaced in the above replacement process. Therefore, the predetermined portion of the wiring layer connected to the contact CC, like other wiring layers, is not thickened.

[0270] Next, as shown in FIG63, a hole H5 is formed by removing the sacrificial member 272. Furthermore, a portion of the insulator 210 is removed through the hole H5. When removing the insulator 210, a portion of the insulator 210 remaining in the small recess within the hole H5 is left. On the other hand, a portion of the insulator 210 in the large recess within the hole H5, and the remaining portion of the insulator 210, are removed. Thus, within the hole H5, the predetermined wiring layer connected to the contact CC is exposed, but other wiring layers are not exposed.

[0271] Subsequently, a contact CC is formed by forming a conductor 230 inside the hole H5. And, similar to the second embodiment, a memory device 3 is formed by bonding the circuit chip 300 and the memory chip 100.

[0272] 2.4.4.3 Effects of the Fourth Variation of the Second Embodiment According to the fourth variation of the second embodiment, the sacrificial member 267 is in contact with the conductor 230 and the wiring layer on the side closer to the substrate 303 than the wiring layer that is in contact with the conductor 230. The sacrificial member 267 comprises silicon or silicon carbide. Thereby, the sacrificial member 267 can be removed in a different process than the sacrificial members 251, 252 and 253. Therefore, in the replacement process of the sacrificial members 251, 252 and 253 to the wiring layers 223, 224 and 225, the sacrificial member 267 is not removed and remains. Moreover, the sacrificial member 267 can be selectively removed in a desired amount through the hole H5. Therefore, the shape processing of the portion of the conductor 230 in contact with the wiring layer can be easily performed.

[0273] 2.4.5 Fifth Variation of the Second Embodiment Furthermore, in the fourth variation of the second embodiment, the case where sacrificial members 267 are formed on the bottom and side surfaces within the hole H3 has been described, but it is not limited to this. For example, the sacrificial member 267 may not be provided on the side surface of the hole H3. Hereinafter, the configuration and manufacturing method that differ from the fourth variation of the second embodiment will be mainly described. The configuration and manufacturing method that are the same as those in the fourth variation of the second embodiment will be appropriately omitted from the description.

[0274] 2.4.5.1 Cross-sectional view of memory device Figure 64 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the fifth variation of the second embodiment. Figure 64 corresponds to Figure 57 in the fourth variation of the second embodiment. Furthermore, the configuration of this part of the memory chip 100 is also the same as that shown in Figure 64.

[0275] As shown in FIG64, in the fifth variation of the second embodiment, the memory chip 200 includes insulating layers 203, 204 and 206, insulators 208, 209, 210, 261 and 263, sacrificial member 267, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 around the contact CC.

[0276] The structures of insulating layers 203, 204 and 206, insulators 208, 209 and 210, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 are the same as those of the fourth variation of the second embodiment.

[0277] Insulators 261 and 263 and sacrificial member 267 are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0278] The insulator 263 surrounds the side of the conductor 230, specifically the portion higher in the Z1 direction than the portion connected to the wiring layer. The sacrificial member 267 surrounds the side of the portion of the conductor 230 that is not connected to the wiring layer, specifically the portion having a diameter larger than other portions of the conductor 230. The insulator 261 surrounds the side of the insulator 261. Furthermore, the laminated wiring structure, higher in the Z1 direction than the wiring layer connected to the conductor 230, surrounds the side of the insulator 261.

[0279] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0280] 2.4.5.2 Manufacturing Method Figures 65 to 67 are cross-sectional views showing an example of the cross-sectional structure of the memory device during the manufacturing process of the fifth variation of the second embodiment. Figures 65 to 67 correspond to Figure 64.

[0281] First, the same structure as in FIG30 is formed by the same process as in the second embodiment. That is, a hole H3 is formed in the predetermined area of ​​the contact CC in the multilayer structure. After forming an insulator 261 in the hole H3, the sacrificial member directly below is exposed by etching the bottom of the hole H3.

[0282] Next, as shown in FIG65, the sacrificial member 267 is selectively grown within the hole H3. The hole H3 is filled by the formation of an insulator 263 within it. The sacrificial member 267 may contain, for example, silicon or silicon carbide (SiOC).

[0283] Next, as shown in FIG66, a hole H4 is formed in the predetermined area where the contact CC is formed. The hole H4 penetrates the insulator 263, the sacrificial member 267, and the multilayer structure, reaching the substrate 250. This exposes the substrate 250 at the bottom of the hole H4. Furthermore, an insulator 209 is formed by oxidizing the portion of the substrate 250 exposed at the bottom of the hole H4. Subsequently, for example, by wet etching, the portions of each sacrificial member 251 and 252 exposed within the hole H4 are removed. This forms a recess in the portion of the sacrificial members 251 and 252 disposed within the hole H4. Furthermore, the sacrificial member 267 is not selectively etched away from the sacrificial members 251 and 252.

[0284] Next, as shown in FIG67, the sacrificial member 267 exposed in the via H4 is partially removed, for example, by wet etching. Furthermore, within the via H4, the sacrificial member 267 is in contact with a sacrificial member corresponding to a predetermined wiring layer connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 267 and the sacrificial member within the stacked structure in contact with the sacrificial member 267 has a larger film thickness than other recesses in the Z direction.

[0285] Subsequently, similar to the fourth variation of the second embodiment, after the hole H4 is filled with an insulator and a sacrificial member, a replacement process from a multilayer structure to a multilayer wiring structure is performed. Furthermore, after removing a portion of the sacrificial member and the insulator that were filled into the hole H4, a conductor 230 is formed in the resulting space, thereby forming a contact CC.

[0286] Furthermore, similar to the second embodiment, the memory device 3 is formed by bonding the circuit chip 300 and the memory chip 100.

[0287] 2.4.5.3 Effects of the Fifth Variation of the Second Embodiment According to the fifth variation of the second embodiment, the sacrificial member 267 comprises silicon or silicon oxide. Therefore, the shape processing of the portion of the conductor 230 in contact with the wiring layer can be easily performed.

[0288] Furthermore, the sacrificial member 267 is formed by selective growth. In this way, the portion of the conductor 230 disposed to replace the sacrificial member 267 is disposed in a manner that does not intersect with the wiring layer on the substrate 303 side that is in contact with the conductor 230. Therefore, the formation of a conductor in the structure between the portion of the conductor 230 disposed on the substrate 303 side that is in contact with the corresponding wiring layer and the multilayer wiring can be suppressed. Therefore, unintentional short circuits between the conductor and the wiring layer can be suppressed.

[0289] 2.4.6 Sixth Variation of the Second Embodiment Furthermore, in the fourth variation of the second embodiment, the case where the contact CC is connected to the wiring layer from the side has been described, but it is not limited to this. For example, the contact CC may also be connected to the upper surface of the wiring layer. Hereinafter, we will mainly describe the configuration and manufacturing method that differ from the fourth variation of the second embodiment. Descriptions of the configuration and manufacturing method that are the same as those in the fourth variation of the second embodiment will be appropriately omitted.

[0290] FIG68 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the sixth variation of the second embodiment. FIG68 corresponds to FIG57 in the fourth variation of the second embodiment. Furthermore, the configuration of this part of the memory chip 100 is also the same as that shown in FIG68.

[0291] As shown in FIG68, in the sixth variation of the second embodiment, the memory chip 200 includes insulating layers 203, 204 and 206, insulators 208, 209, 210, 261 and 263, sacrificial member 267, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 around the contact CC.

[0292] The insulating layers 203, 204 and 206, the insulators 208, 209 and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are configured in the same way as in the second embodiment.

[0293] Conductor 230 extends in the Z direction within the lead-out region HR, penetrating the multilayer wiring structure. One end of conductor 230, for example, reaches semiconductor layer 222. The other end of conductor 230, for example, reaches above wiring layer 225 in the Z1 direction. Conductor 230 has a columnar shape and is used as a contact CC.

[0294] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 may contain, for example, silicon oxide. Thereby, the conductor 230 and the semiconductor layer 222 are electrically insulated.

[0295] An insulator 210 is provided between the conductor 230 and its corresponding wiring layer, and between the wiring layer below the corresponding wiring layer in the Z1 direction. This provides electrical insulation between the conductor 230 and the wiring layer below the corresponding wiring layer in the Z1 direction among the wiring layers 223, 224, and 225. Furthermore, within the same layer as the corresponding wiring layer, the conductor 230 is separated from the wiring layer by the insulating material 210.

[0296] The conductor 230 and the corresponding wiring layer are electrically connected to each other by contacting each other on their upper surfaces in the Z1 direction. The diameter of the portion of the conductor 230 that contacts the corresponding wiring layer is larger than that of the other portions of the conductor 230.

[0297] Furthermore, insulators 261 and 263 and sacrificial member 267 are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0298] The portion of the insulator 263 that surrounds the conductor 230 is higher in the Z1 direction than the portion connected to the wiring layer. The sacrificial member 267 surrounds the side of the insulator 263. The insulator 261 surrounds the side of the sacrificial member 267. Furthermore, the laminated wiring structure that is higher in the Z1 direction than the wiring layer connected to the conductor 230 surrounds the side of the insulator 261.

[0299] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0300] 2.4.6.2 Manufacturing Method Figures 69 to 72 are cross-sectional views showing an example of the cross-sectional structure of the memory device during the manufacturing process of the sixth variation of the second embodiment. Figures 69 to 72 correspond to Figure 68.

[0301] First, the same structure as in FIG59 is formed by the same process as in the fourth variation of the second embodiment. That is, a hole H3 is formed in the predetermined area where the contact CC is formed in the multilayer structure. After the insulator 261 is formed in the hole H3, the sacrificial member directly below is exposed by etching the bottom of the hole H3. And, the hole H3 is filled by the sacrificial member 267 and the insulator 263 formed in the hole H3. Then, a hole reaching the substrate 250 is formed in the predetermined area where the contact CC is formed. The insulator 209 is formed by oxidizing the portion of the substrate 250 exposed at the bottom of the hole. And, for example, the portions of each sacrificial member 251 and 252 exposed in the hole are removed by wet etching. Thereby, a recess is formed in the portion where each sacrificial member 251 and 252 is disposed in the hole H4. In addition, the sacrificial member 267 is not selectively etched away from the sacrificial members 251 and 252.

[0302] Next, as shown in FIG69, the hole is filled by the sequential formation of an insulator 210 and a sacrificial member 272 within the hole. When the insulator 210 is formed, each recess is filled by the insulator 210.

[0303] Next, as shown in FIG70, a replacement process for the multilayer structure is performed. Here, sacrificial members 251, 252, and 253 are replaced with wiring layers 223, 224, and 225, respectively. However, sacrificial member 267 is not replaced in the above replacement process. Therefore, the predetermined portion of the wiring layer connected to the contact CC, like other wiring layers, is not thickened.

[0304] Next, as shown in FIG71, a hole H5 is formed by removing the sacrificial member 272. Furthermore, a portion of the insulator 210 is removed through the hole H5. When removing the insulator 210, a portion of the insulator 210 remaining in the recess within the hole H5 remains. On the other hand, the remaining portion of the insulator 210 within the hole H5 is removed. Thus, each wiring layer is not exposed within the hole H5.

[0305] Next, as shown in FIG72, the sacrificial member 267 is partially removed through the hole H5. Thereby, in the hole H5, in the space formed by removing the sacrificial member 267, the upper surface of the wiring layer in the Z1 direction is exposed.

[0306] Subsequently, a contact CC is formed by filling the hole H5 with a conductor 230. Herein, the conductor 230 is connected to the portion of the corresponding wiring layer exposed in the hole H5. And, similar to the second embodiment, the memory device 3 is formed by bonding the circuit chip 300 and the memory chip 100.

[0307] 2.4.6.3 Effects of the Sixth Variation of the Second Embodiment According to the sixth variation of the second embodiment, the sacrificial member 267 comprises silicon or silicon oxide. Therefore, the shape processing of the portion of the conductor 230 in contact with the wiring layer can be easily performed.

[0308] Furthermore, the sacrificial member 267 is connected to the conductor 230 on the side of the wiring layer closer to the substrate 303 than the conductor 230. Thus, the conductor 230 is arranged to fill the space in which a portion of the sacrificial member 267 has been removed. This allows the diameter of the portion of the conductor 230 electrically connected to the wiring layer to be larger than the rest of the conductor 230. Therefore, the conductor 230 can be configured to be connected to the surface of the wiring layer on the substrate 303 side.

[0309] 2.4.7 Seventh Variation of the Second Embodiment Furthermore, in the sixth variation of the second embodiment, a sacrificial member 267 was formed on the bottom and side surfaces of the hole H3, and a portion of it was replaced by a conductor 230. However, this is not the only variation. For example, the sacrificial member 267 may not be provided on the side surface of the hole H3. Hereinafter, we will mainly describe the configuration and manufacturing method that differ from the sixth variation of the second embodiment. Descriptions of configurations and manufacturing methods identical to those in the sixth variation of the second embodiment will be appropriately omitted.

[0310] 2.4.7.1 Cross-sectional view of memory device Figure 73 is a cross-sectional view showing an example of the cross-sectional structure of memory device in the seventh variation of the second embodiment. Figure 73 corresponds to Figure 68 in the sixth variation of the second embodiment. Furthermore, the configuration of this part of memory chip 100 is the same as that shown in Figure 73.

[0311] As shown in FIG73, in the seventh variation of the second embodiment, the memory chip 200 includes insulating layers 203, 204 and 206, insulators 208, 209, 210, 261 and 263, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 around the contact CC.

[0312] The structures of insulating layers 203, 204 and 206, insulators 208, 209 and 210, semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230 are the same as those of the fourth variation of the second embodiment.

[0313] Insulators 261 and 263 are provided between the conductor 230 and the stacked wiring structure of the corresponding wiring layer in the Z1 direction.

[0314] The portion of the insulator 263 that surrounds the conductor 230 is located higher in the Z1 direction than the portion connected to the wiring layer. The insulator 261 surrounds the side of the insulator 263. Furthermore, the side of the insulator 261 is surrounded by a multilayer wiring structure located higher in the Z1 direction than the wiring layer connected to the conductor 230.

[0315] According to the above configuration, the conductor 230 and the dielectric insulator 210 are electrically insulated from the corresponding wiring layer in the Z1 direction and the lower wiring layer, and the dielectric insulator 261 is electrically insulated from the upper wiring layer.

[0316] 2.4.7.2 Manufacturing Method Figures 74 to 77 are cross-sectional views showing an example of the cross-sectional structure of the memory device during the manufacturing process of the seventh variation of the second embodiment. Figures 74 to 77 correspond to Figure 73.

[0317] First, a structure identical to that in FIG. 66 is formed using the same process as in the fifth variation of the second embodiment. That is, a hole is formed in a predetermined area where the contact CC is formed in the multilayer structure. After forming an insulator 261 in the hole, the bottom of the hole is etched to expose the sacrificial member directly below. Then, the sacrificial member 267 is selectively grown in the hole, and the hole is filled with an insulator 263. Subsequently, a hole reaching the substrate 250 is formed in the predetermined area where the contact CC is formed. The portion of the substrate 250 exposed at the bottom of the hole is oxidized to form an insulator 209. And, for example, the portions of each sacrificial member 251 and 252 exposed in the hole are removed by wet etching. In this way, a recess is formed in the portion where each sacrificial member 251 and 252 is disposed in the hole. In addition, the sacrificial member 267 is not selectively etched away from the sacrificial members 251 and 252.

[0318] Next, as shown in FIG74, the hole is filled by the sequential formation of an insulator 210 and a sacrificial member 272 within the hole. When the insulator 210 is formed, each recess is filled by the insulator 210.

[0319] Next, as shown in FIG75, a replacement process for the multilayer structure is performed. Here, sacrificial members 251, 252, and 253 are replaced with wiring layers 223, 224, and 225, respectively. However, sacrificial member 267 is not replaced in the above replacement process. Therefore, the predetermined portion of the wiring layer connected to the contact CC, like other wiring layers, is not thickened.

[0320] Next, as shown in FIG76, a hole H5 is formed by removing the sacrificial member 272. Furthermore, a portion of the insulator 210 is removed through the hole H5. When removing the insulator 210, a portion of the insulator 210 remaining in the recess within the hole H5 remains. On the other hand, the remaining portion of the insulator 210 within the hole H5 is removed. Thus, each wiring layer is not exposed within the hole H5.

[0321] Next, as shown in FIG. 77, the sacrificial member 267 is removed through hole H5. This exposes the upper surface of the wiring layer in the Z1 direction within the space formed by removing the sacrificial member 267 in hole H5. Furthermore, in the example of FIG. 77, although the sacrificial member 267 is completely removed, if the wiring layer is sufficiently exposed, the sacrificial member 267 may also partially remain.

[0322] Subsequently, a contact CC is formed by filling the hole H5 with a conductor 230. Herein, the conductor 230 is connected to the portion of the corresponding wiring layer exposed in the hole H5. And, similar to the second embodiment, the memory device 3 is formed by bonding the circuit chip 300 and the memory chip 100.

[0323] 2.4.7.3 Effects of the 7th Variation of the 2nd Embodiment According to the 7th variation of the 2nd embodiment, the sacrificial member 267 comprises silicon or silicon oxide. Therefore, the shape processing of the portion of the conductor 230 in contact with the wiring layer can be easily performed.

[0324] Furthermore, the sacrificial member 267 is connected to the conductor 230 on the side of the wiring layer closer to the substrate 303 than the conductor 230. Thus, the conductor 230 is arranged to fill the space in which a portion of the sacrificial member 267 has been removed. This allows the diameter of the portion of the conductor 230 electrically connected to the wiring layer to be larger than the other portions of the conductor 230. Therefore, the conductor 230 can be configured to be connected to the surface of the wiring layer on the substrate 303 side.

[0325] Furthermore, the sacrificial member 267 is formed by selective growth. Therefore, it is possible to suppress the formation of a conductor in the portion of the conductor 230 that is in contact with the corresponding wiring layer and closer to the substrate 303, due to unintentional etching of the sacrificial member 267 to a deeper depth, and in the structure between the conductor and the multilayer wiring. Therefore, unintentional short circuits between the conductor and the wiring layer can be suppressed.

[0326] 3. Other aspects: In the first and second embodiments described above, the case in which a single lead-out region HR is configured between two memory regions MRa and MRb has been explained, but it is not limited thereto. For example, a single memory region may also be configured between two lead-out regions.

[0327] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0005] Figure 1 is a block diagram showing an example of the configuration of a memory system including the memory device of the first embodiment. Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array provided by the memory device of the first embodiment. Figure 3 is a perspective view showing an outline of the bonding structure of the memory device of the first embodiment. Figure 4 is a top view showing an example of the planar layout of the memory cell array provided by the memory device of the first embodiment. Figure 5 is a top view corresponding to region V of Figure 4, showing an example of the planar layout of the memory cell array provided by the memory device of the first embodiment. Figure 6 is a cross-sectional view along line VI-VI of Figure 5, showing an example of the cross-sectional structure of the memory device of the first embodiment. Figure 7 is a cross-sectional view along line VII-VII of Figure 5, showing an example of the cross-sectional structure of the memory device of the first embodiment. Figure 8 is a cross-sectional view along line VIII-VIII of Figure 6, showing an example of the cross-sectional structure of the memory pillars provided by the memory device of the first embodiment. Figure 9 is a cross-sectional view along line IX-IX of Figure 6, showing an example of the cross-sectional structure of the contacts provided in the memory device of the first embodiment. Figure 10 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 11 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 12 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 13 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 14 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 15 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 16 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 17 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 18 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 19 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 20 is a cross-sectional view showing an example of the cross-sectional structure of the memory device of the first embodiment during manufacturing. Figure 21 is a top view showing an example of the planar layout of the memory cell array in a modified example of the memory device of the first embodiment. Figure 22 is a top view corresponding to region XXII of Figure 21, showing an example of the planar layout of the memory cell array in a modified example of the memory device of the first embodiment. Figure 23 is a cross-sectional view along line XXIII-XXIII of Figure 22, showing an example of the cross-sectional structure of the memory device of the modified example of the first embodiment. Figure 24 is a top view showing an example of the planar layout of the memory cell array in a memory device of the second embodiment.Figure 25 is a cross-sectional view along line XXV-XXV of Figure 24, showing one example of the cross-sectional structure of the memory device according to the second embodiment. Figure 26 is a cross-sectional view along line XXVI-XXVI of Figure 24, showing one example of the cross-sectional structure of the memory device according to the second embodiment. Figure 27 is a cross-sectional view along line XXVII-XXVII of Figure 25, showing one example of the cross-sectional structure of the contacts provided in the memory device according to the second embodiment. Figure 28 is a cross-sectional view showing one example of the cross-sectional structure of the memory device according to the second embodiment during manufacturing. Figure 29 is a cross-sectional view showing one example of the cross-sectional structure of the memory device according to the second embodiment during manufacturing. Figure 30 is a cross-sectional view showing one example of the cross-sectional structure of the memory device according to the second embodiment during manufacturing. Figure 31 is a cross-sectional view showing one example of the cross-sectional structure of the memory device according to the second embodiment during manufacturing. Figure 32 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second embodiment during manufacturing. Figure 33 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second embodiment during manufacturing. Figure 34 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second embodiment during manufacturing. Figure 35 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second embodiment during manufacturing. Figure 36 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second embodiment during manufacturing. Figure 37 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the second embodiment during manufacturing. Figure 38 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the first variation of the second embodiment. Figure 39 is a cross-sectional view showing an example of the cross-sectional structure of the memory device in the first variation of the second embodiment during manufacturing. Figure 40 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the first variation of the second embodiment. Figure 41 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the first variation of the second embodiment. Figure 42 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the first variation of the second embodiment. Figure 43 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the first variation of the second embodiment. Figure 44 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the second variation of the second embodiment. Figure 45 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the second variation of the second embodiment. Figure 46 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the second variation of the second embodiment. Figure 47 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the second variation of the second embodiment. Figure 48 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the second variation of the second embodiment.Figure 49 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the second variation of the second embodiment. Figure 50 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the second variation of the second embodiment. Figure 51 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the third variation of the second embodiment. Figure 52 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the third variation of the second embodiment. Figure 53 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the third variation of the second embodiment. Figure 54 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the third variation of the second embodiment. Figure 55 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the third variation of the second embodiment. Figure 56 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the third variation of the second embodiment. Figure 57 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fourth variation of the second embodiment. Figure 58 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fourth variation of the second embodiment. Figure 59 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fourth variation of the second embodiment. Figure 60 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fourth variation of the second embodiment. Figure 61 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fourth variation of the second embodiment. Figure 62 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fourth variation of the second embodiment. Figure 63 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fourth variation of the second embodiment. Figure 64 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fifth variation of the second embodiment. Figure 65 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fifth variation of the second embodiment. Figure 66 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fifth variation of the second embodiment. Figure 67 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the fifth variation of the second embodiment. Figure 68 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the sixth variation of the second embodiment. Figure 69 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the sixth variation of the second embodiment. Figure 70 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the sixth variation of the second embodiment. Figure 71 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the sixth variation of the second embodiment.Figure 72 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the sixth variation of the second embodiment. Figure 73 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the seventh variation of the second embodiment. Figure 74 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the seventh variation of the second embodiment. Figure 75 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the seventh variation of the second embodiment. Figure 76 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the seventh variation of the second embodiment. Figure 77 is a cross-sectional view showing an example of the cross-sectional structure of the memory device during manufacturing of the seventh variation of the second embodiment.

Claims

1. A memory device comprising: a substrate, a first semiconductor layer and a second semiconductor layer, which are spaced apart from each other and arranged sequentially in a first direction; a plurality of first wiring layers, which are spaced apart from each other between the substrate and the first semiconductor layer in the first direction and include the first layer; a plurality of second wiring layers, which are spaced apart from each other between the first semiconductor layer and the second semiconductor layer in the first direction and include the second layer; and a first memory pillar extending in the first direction, wherein the portion intersecting with each of the plurality of first wiring layers functions as a memory cell; The second memory pillar extends in the first direction and functions as a memory cell at the portion intersecting with each of the plurality of second wiring layers; and the first contact extends in the first direction in a manner intersecting with the plurality of first wiring layers to reach the first semiconductor layer, is in contact with the first layer, and is electrically insulated from the plurality of first wiring layers and the first semiconductor layer other than the first layer, thereby electrically connecting the substrate and the second layer.

2. The memory device of claim 1 further includes a second contact that extends in the first direction to the second semiconductor layer in a manner that intersects with the plurality of second wiring layers, is in contact with the second layer, and is electrically insulated from the plurality of second wiring layers and the second semiconductor layer other than the second layer, thereby electrically connecting the second layer and the first contact.

3. The memory device of claim 1, wherein each of the plurality of first wiring layers has a stepped portion that does not overlap with the wiring layer on the substrate side when viewed along the first direction, and the first contact is connected to the stepped portion of the first layer.

4. The memory device of claim 3, wherein the film thickness of the stepped portion of the first layer is greater than the film thickness of the portion of the first layer excluding the stepped portion.

5. The memory device of claim 4, wherein the diameter of the portion of the first contact that is in contact with the first layer is greater than the diameter of the portion that is not in contact with the first layer.

6. The memory device of claim 1, wherein, when viewed along the first direction, the layer of the plurality of first wiring layers that is closer to the substrate than the first layer surrounds the portion of the first contact that is closer to the substrate than the first layer.

7. The memory device of claim 6, wherein the diameter of the portion of the first contact that is in contact with the first layer is greater than the diameter of the portion that is not in contact with the first layer.

8. The memory device as claimed in claim 7, wherein the first contact is connected to the side of the first layer.

9. The memory device of claim 8 further includes a conductor, which is connected to the first contact on the side of the substrate closer to the first layer and is continuously disposed with respect to the first layer.

10. The memory device of claim 9, wherein the conductor is provided in such a manner that it intersects with the layer of the plurality of first wiring layers that is closer to the substrate than the first layer.

11. The memory device of claim 9, wherein the conductor is disposed in such a manner that it does not intersect with any of the plurality of first wiring layers that are closer to the substrate side than the first layer.

12. The memory device of claim 8 further includes a sacrificial member, which is connected to the first contact and the first layer on the side closer to the substrate than the first layer; the sacrificial member comprises silicon or silicon carbide.

13. The memory device of claim 12, wherein the sacrificial member is provided in such a manner that it intersects with the layer of the plurality of first wiring layers that is closer to the substrate side than the first layer.

14. The memory device of claim 12, wherein the sacrificial member is provided in such a manner that it does not intersect with any of the plurality of first wiring layers that are closer to the substrate side than the first layer.

15. The memory device of claim 7, wherein the first contact is in contact with the substrate side of the first layer.

16. The memory device of claim 15 further includes a sacrificial member, the sacrificial member being connected to the first contact on the side of the substrate closer to the first layer than the first layer, the sacrificial member comprising silicon nitride.

17. The memory device of claim 16 further includes an insulator disposed between the first contact and the sacrificial member when viewed along the first direction.

18. The memory device of claim 16, wherein the sacrificial member spans both ends of the first direction and is connected to the first contact.

19. The memory device of claim 15 further includes a sacrificial member, which is connected to the first contact on the side closer to the substrate than the first layer, and the sacrificial member comprises silicon or silicon oxide.

20. The memory device of claim 19, further comprising an insulator disposed between the first contact and the sacrificial member when viewed along the first direction.

21. A memory device comprising: a substrate, a first semiconductor layer, and a second semiconductor layer, which are spaced apart from each other and arranged sequentially in a first direction; a plurality of first wiring layers, which are spaced apart from each other between the substrate and the first semiconductor layer in the first direction and include the first layer; a plurality of second wiring layers, which are spaced apart from each other between the first semiconductor layer and the second semiconductor layer in the first direction and include the second layer; a first memory pillar extending in the first direction, the portion of which intersects with each of the plurality of first wiring layers functions as a memory cell; and a second memory pillar extending in the first direction, the portion of which intersects with each of the plurality of second wiring layers functions as a memory cell. The third contact is disposed on the substrate side of the first layer and extends in the first direction; and the fourth contact extends in the first direction to the first semiconductor layer in a manner that intersects with the plurality of first wiring layers, is electrically connected to the first layer via the third contact, and is electrically insulated from the plurality of first wiring layers and the first semiconductor layer other than the first layer, and electrically connects the substrate and the second layer without passing through the third contact.

22. The memory device of claim 21 further comprises a component for dividing the plurality of first wiring layers into a first part and a second part, wherein, when viewed along the first direction, the third contact is disposed at a position overlapping the first part, and the fourth contact is disposed at a position overlapping the second part.

Images