Semiconductor device with polymer liner and method for fabricating the same

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate having a front side and a back side parallel to the front side; a bonding dielectric disposed on the front side of the first substrate; a redistribution layer disposed between the bonding dielectric and the front side of the first substrate; a first dielectric layer disposed between the front side of the first substrate and the redistribution layer; a capping layer disposed between the redistribution layer and the bonding dielectric; a first conductive pad disposed between the capping layer and the bonding dielectric; a second dielectric layer disposed between the capping layer and the bonding dielectric, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature disposed in the bonding dielectric and the first conductive pad.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 917,487 (i.e., priority date "October 16, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the semiconductor device. In particular, it relates to a semiconductor device having a polymer pad and a method for fabricating the semiconductor device having the polymer pad. Prior Technology

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. As the semiconductor industry develops to advanced technology process nodes, the pursuit of higher component density, higher performance, and lower costs has brought about the challenge of integrating components of different sizes and complex features, especially for multi-stacked components.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a first substrate having a front side and a back side parallel to the front side; a bonding dielectric disposed on the front side of the first substrate; a redistribution layer disposed between the bonding dielectric and the front side of the first substrate; a first dielectric layer disposed between the front side of the first substrate and the redistribution layer; a capping layer disposed between the redistribution layer and the bonding dielectric; a first conductive pad disposed between the capping layer and the bonding dielectric; a second dielectric layer disposed between the capping layer and the bonding dielectric, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature disposed in the bonding dielectric and the first conductive pad, wherein the conductive feature includes conductivity through the bonding dielectric. The first substrate comprises: a second conductive pad exposed on its back side and an interconnect structure electrically connected to the second conductive pad and penetrating the first conductive pad; a second passivation layer disposed above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a through-substrate via (TSV) passing through the second passivation layer and the first substrate, wherein the TSV is electrically coupled to the conductive feature; a polymer pad disposed between the TSV and the first substrate, wherein an upper surface of the polymer pad is lower than the upper surface of the second passivation layer; a barrier layer disposed between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the interconnect structure and the TSV; and an adhesive layer disposed between the barrier layer and the TSV.

[0006] Another embodiment of this disclosure provides a semiconductor device including a first semiconductor wafer, comprising a first substrate having a front side and a back side parallel to the front side; a bonding dielectric disposed above the front side of the first substrate; and a second passivation layer disposed above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a redistribution layer disposed between the bonding dielectric and the front side of the first substrate; a first dielectric layer disposed between the front side of the first substrate and the redistribution layer; a capping layer disposed between the redistribution layer and the bonding dielectric; a first conductive pad disposed between the capping layer and the bonding dielectric; and a second dielectric layer disposed between the capping layer and the bonding dielectric. The second dielectric layer has one surface coplanar with one surface of the first conductive pad; a conductive feature is disposed in the bonding dielectric and the first conductive pad; a through-substrate via (TSV) is exposed through the second passivation layer and electrically coupled to the conductive feature; a polymer pad is disposed between the TSV and the first substrate; a barrier layer is disposed between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the conductive feature and the TSV; an adhesive layer is disposed between the barrier layer and the TSV; and a second semiconductor wafer is coupled to the first semiconductor wafer at a bonding interface and includes a second substrate coupled to the first substrate; wherein the polymer pad of the first semiconductor wafer is separated from the bonding interface.

[0007] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising forming a conductive feature and a bonding dielectric over a front side of a first substrate, wherein the conductive feature is formed in the bonding dielectric; forming a redistribution layer between the bonding dielectric and the front side of the first substrate; forming a second passivation layer over a back side of the first substrate; forming a first recess in an upper surface of the second passivation layer to expose the conductive feature; conformally forming an isolation pad on a sidewall of the first recess; performing a pulse etching operation to conformally form a polymer pad on the sidewall of the isolation pad, wherein an upper surface of the polymer pad is lower than the upper surface of the second passivation layer; conformally forming a barrier layer over the polymer pad and the isolation pad; conformally forming an adhesive layer over the barrier layer; and forming a conductive material in the first recess to form a through-substrate via (TSV).

[0008] In pursuit of higher component density, the distance between adjacent conductive via pairs (e.g., two through-substrate vias) is becoming increasingly smaller. This can lead to electrical interference, thus degrading component performance. Furthermore, smaller through-substrate vias may present reliability issues. For example, stress concentration problems can cause component defects. In addition, improving the yield of hybrid bonding is also important.

[0009] The design and fabrication methods of the semiconductor devices discussed in this disclosure are intended to solve the aforementioned problems. In particular, this disclosure provides semiconductor devices with polymer pads and methods for forming semiconductor devices with polymer pads.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] A more complete understanding of this disclosure can be obtained by referring to the detailed description and the claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description. Figure 1 is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure. Figures 2A to 2D are cross-sectional schematic diagrams illustrating intermediate stages in the formation of semiconductor elements according to some embodiments of this disclosure. Figure 2D' is an enlarged schematic diagram illustrating the dashed area A1 shown in Figure 2D of some embodiments disclosed herein. Figures 2E to 2F are cross-sectional schematic diagrams illustrating intermediate stages in the formation of semiconductor elements according to some embodiments of this disclosure. Figure 2F' is an enlarged schematic diagram illustrating the dashed area A1 shown in Figure 2F, which represents some embodiments of this disclosure. Figure 2G is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element according to some embodiments of this disclosure. Figure 2G' is a bias power-time diagram illustrating pulse etch operations in some embodiments of this disclosure. Figure 2G'' is a bias power-time diagram illustrating pulse etch operations in different embodiments of this disclosure. Figures 2H to 2L are cross-sectional schematic diagrams illustrating intermediate stages in the formation of semiconductor elements according to some embodiments of this disclosure. Figures 2M, 2N, 2O and 3 are cross-sectional schematic diagrams illustrating semiconductor elements of some embodiments of this disclosure. Figure 4 is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure. Figures 5A to 5C are cross-sectional schematic diagrams illustrating intermediate stages in the formation of semiconductor elements according to some embodiments of this disclosure. Figure 5D is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Figure 5E is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Figure 6 is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Implementation

[0012] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplification and clarity, and unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0013] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0014] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0015] In pursuit of higher component density, the distance between adjacent conductive vias (e.g., two through-substrate vias, TSVs) is becoming increasingly smaller. This can lead to electrical interference, thus degrading component performance. Furthermore, smaller TSVs may present reliability issues. For example, stress concentration problems can cause defects or anomalies in semiconductor components. In addition, improving the yield of hybrid bonding is also important.

[0016] Specifically, this disclosure provides a semiconductor device with polymer pads and a method for fabricating the semiconductor device with polymer pads. The performance and product yield of the device formed according to this fabrication method can be improved. For example, it can reduce electrical interference, improve the reliability of through-substrate vias, and improve the yield of hybrid bonding.

[0017] Figure 1 is a schematic flowchart illustrating a method S1 for fabricating a semiconductor device according to some embodiments of this disclosure. The fabrication method S1 includes multiple steps (S11, S12, S13, S14, S15, S16, S17, S18, S19, and S20), and the description and illustration are not intended to limit the order of the steps. In step S11, a conductive feature is formed on a front side of a first substrate. In step S12, the first substrate is thinned on a back side. In step S13, a second passivation layer is formed above the back side of the first substrate. In step S14, a first recess is formed in an upper surface of the second passivation layer to expose the conductive feature, and a recess portion is formed in a sidewall of the first substrate. In step S15, an isolation pad is formed in the first recess. In step S16, a pulse etching operation is performed to form a polymer pad in the first recess, wherein an upper surface of the polymer pad is lower than the upper surface of the second passivation layer. In step S17, a barrier layer and an adhesive layer are formed in the first recess. In step S18, a conductive material is formed in the first recess to form a through-substrate via (TSV). In step S19, a second substrate is coupled to the first substrate by performing a hybrid bonding operation. In step S20, an upper connector is formed above the conductive feature.

[0018] Figures 2A to 2L are cross-sectional schematic diagrams illustrating the various manufacturing stages constructed by the preparation method S1 of some embodiments of this disclosure. Figures 2M, 2N, 2O and 3 are cross-sectional schematic diagrams illustrating various components manufactured by performing the preparation method S1 according to some embodiments of this disclosure.

[0019] Figure 2A is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element according to some embodiments of this disclosure. Prior to step S11, a first substrate 100 having a first thickness T1 is provided, received, or formed. The first substrate 100 has a front side 100F and a back side 100B opposite to the front side 100F. The front side 100F and the back side 100B are parallel to each other. The front side 100F faces upwards, and the back side 100B faces downwards.

[0020] In step S11, a dielectric layer 162, a redistribution layer (RDL) 174, a capping layer 184, a dielectric layer 102b, a bonding dielectric 103, a conductive feature 210, a conductive pad 102c, and a first passivation layer 101 are formed over the front surface 100F of the first substrate 100. In some embodiments, the first passivation layer 101 is formed directly on the front surface 100F of the first substrate 100. In some embodiments, the redistribution layer 174 is formed over the front surface 100F of the first substrate 100. In some embodiments, the redistribution layer 174 includes a plurality of horizontal segments 1742 parallel to the front surface 100F of the first substrate 100 and a plurality of vertical segments 1744 formed over a periphery 1012 of the first passivation layer 101. In some embodiments, the horizontal segments 1742 and the vertical segments 1744 connected to the horizontal segments 1742 are integrally formed. In some embodiments, a dielectric layer 162 is formed between the front surface 100F of the first substrate 100 and the horizontal segment 1742 of the redistribution layer 174, and between the periphery 1012 of the first passivation layer 101 and the vertical segment 1744 of the redistribution layer 174. In some embodiments, a capping layer 184 is formed on the horizontal segment 1742 of the redistribution layer 174. One surface of the capping layer 184 is coplanar with one surface of the first passivation layer 101. In some embodiments, a conductive pad 102c is formed on the first passivation layer 101 and the capping layer 184. In some embodiments, a dielectric layer 102b is formed on the capping layer 184, and one surface of the dielectric layer 102b is coplanar with one surface of the conductive pad 102c. In some embodiments, a bonding dielectric 103 is formed above the front surface 100F of the first substrate 100. In some embodiments, the bonding dielectric 103 is formed on the dielectric layer 102b and the conductive pad 102c. In other words, a redistribution layer 174 is formed between the bonding dielectric 103 and the front surface 100F of the first substrate 100. A capping layer 184 is formed between the bonding dielectric 103 and the redistribution layer 174. A dielectric layer 102b is formed between the bonding dielectric 103 and the capping layer 184. A dielectric layer 162 is formed between the redistribution layer 174 and the front surface 100F of the first substrate 100. A conductive pad 102c is formed between the bonding dielectric 103 and the capping layer 184, and between the first passivation layer 101 and the bonding dielectric 103. In some embodiments, a conductive feature 210 is formed in the bonding dielectric 103 and the conductive pad 102c. In some embodiments, the conductive feature 210 includes a T-shaped conductive pad 202 exposed through the back surface 103B of the bonding dielectric 103, and an interconnect structure 201 electrically connected to the conductive pad 202 and passing through the conductive pad 102c to contact the first passivation layer 101. In other words, conductive feature 210 is formed on the first passivation layer 101. The conductive pad 202 and the interconnect structure 201 may include conductive materials, such as copper, aluminum copper, other types of metals, or other suitable materials.In some embodiments, a planarization operation, such as a chemical mechanical planarization (CMP) operation, may be performed on the bonding dielectric 103 during step S11, thereby making an exposed surface 202E of the conductive pad 202 coplanar with the back surface 103B of the bonding dielectric 103.

[0021] The first substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The first substrate 100 may include an elemental semiconductor, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient SiGe characteristic, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe characteristic to another ratio at another location of the gradient SiGe characteristic. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained through another material in contact with the SiGe alloy.

[0022] In some embodiments, the first substrate 100 may have a multilayer structure, or may include a multilayer compound semiconductor structure. In some embodiments, the first substrate 100 includes semiconductor elements, electronic components, electronic components, or combinations thereof. In some embodiments, the first substrate 100 includes transistors or functional units of transistors.

[0023] In some embodiments, for example, the first passivation layer 101 includes an insulating material, such as SiON, SiO2, SiCN, silicon-based material, nitride-based material, oxide-based material, carbide-based material, a combination thereof, or other suitable material.

[0024] Figure 2B is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element according to some embodiments of this disclosure. In step S12, a thinning operation is performed on the back surface 100B of the first substrate 100. For example, a thickness of the first substrate 100 is reduced from a first thickness T1 (as shown in Figure 2A) to a second thickness T2, wherein the second thickness T2 is less than the first thickness T1. In some embodiments, the thinning operation in step S12 includes grinding on the back surface 100B of the first substrate 100.

[0025] Figure 2C is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element according to some embodiments of this disclosure. In step S13, a second passivation layer 102 is formed over the back surface 100B of the first substrate 100. The second passivation layer 102 has an upper surface 102T facing away from the first substrate 100. In some embodiments, for example, the second passivation layer 102 comprises an insulating material, such as SiON, SiO2, SiCN, silicon-based materials, nitride-based materials, oxide-based materials, carbide-based materials, combinations thereof, or other suitable materials. In some embodiments, the first substrate 100 is flipped before step S13.

[0026] Figure 2D is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. Figure 2D' is an enlarged schematic diagram illustrating the dashed region A1 shown in Figure 2D according to some embodiments of this disclosure. In step S14, the fabrication technique of a first recess R1 includes recessing the upper surface 102T of the second passivation layer 102 and removing a portion of the second passivation layer 102, a portion of the first substrate 100, and a portion of the first passivation layer 101. The formation of the first recess R1 may include lithography and / or etching operations. In some embodiments, the etching operation includes repeating the following cycle: (1) depositing a thin film (not shown) by applying CF x plasma; (2) removing a bottom of the thin film by an anisotropic etching operation; and (3) performing a silicon etching operation using fluorine radicals in SF6 plasma. The above etching operation is more suitable for forming deep trenches than some other types of etching operations. After the etching operation, one sidewall 102SW of the second passivation layer 102, one sidewall 100SW of the first substrate 100, and one sidewall 162SW of the dielectric layer 162 are exposed in the first recess R1. Therefore, the exposed sidewall 102SW of the second passivation layer 102, the exposed sidewall 100SW of the first substrate 100, and the exposed sidewall 162SW of the dielectric layer 162 can be referred to as the sidewall of the first recess R1. A portion of the conductive feature 210 and a portion of the conductive pad 102c are located below the projected area of ​​the first recess R1. Additionally, a bottom BT of the first recess R1 may terminate at the conductive feature 210 and the conductive pad 102c. For example, a portion of the interconnect structure 201 and a portion of the conductive pad 210c are exposed at the bottom BT of the first recess R1.

[0027] Additionally, as shown in FIG2D', a recess 100U may also be formed in step S14. In some embodiments, during the above-described etching operation, a portion of the first substrate 100 near the back surface 100B of the first substrate 100 may be partially removed in a lateral direction. In the embodiment of the silicon-containing first substrate 100, the recess 100U formed near the back surface 100B of the first substrate 100 may be referred to as a "silicon undercut". The recess 100U is located in a peripheral region of the first recess R1 in the sidewall 100SW of the first substrate 100. A plurality of second recesses R2 are formed in the recess 100U in the sidewall 100SW of the first substrate 100 near the second passivation layer 102. A depth D1 of a second recess R2 (i.e., a distance measured from the deepest part of the second recess R2 to a hypothetical surface REF, wherein the hypothetical surface REF is aligned with the sidewall 102SW of the second passivation layer 102) can be between about 100 nm and about 500 nm. If the depth D1 is greater than about 500 nm, the first substrate 100 may suffer excessive material loss, which could lead to reliability issues.

[0028] Figures 2E and 2F are cross-sectional schematic diagrams illustrating intermediate stages in the formation of semiconductor devices according to some embodiments of this disclosure. In step S15, an isolation pad 206 (as shown in Figure 2F) is formed in a first recess R1. Step S15 includes a multi-step operation, including forming an isolation pad material layer 206M in the first recess R1 and over the upper surface 102T of the second passivation layer 102 (as shown in Figure 2E), and partially removing the isolation pad material layer 206M to form the isolation pad 206 (as shown in Figure 2F). In some embodiments, a blanket deposition is performed to form the isolation pad material layer 206M in the first recess R1 and over the upper surface 102T of the second passivation layer 102. The isolation pad material layer 206M includes (1) a top 206T located above the upper surface 102T of the second passivation layer 102; (2) a sidewall portion 206S, which is lined on the sidewall of the first recess R1 (i.e., lined with the sidewall 100SW of the first substrate 100, the sidewall 162SW of the dielectric layer 162, and the sidewall 102SW of the second passivation layer 102); and (3) a bottom 206B located at the bottom BT of the first recess R1 and above the interconnect structure 201.

[0029] In some embodiments, the material of the isolation pad material layer 206M includes oxide-based materials, nitride-based materials, or other suitable materials, which may be selected from materials with low dielectric constants.

[0030] Referring again to step S15, an etching operation is performed to remove the top 206T and bottom 206B of the isolation pad material layer 206M, wherein the remaining portion of the isolation pad material layer 206M, namely the sidewall portion 206S, constitutes the isolation pad 206. Thus, the isolation pad 206 is formed above the sidewall 100SW of the first substrate 100, above the sidewall 162SW of the dielectric layer 162, and above the sidewall 102SW of the second passivation layer 102. In some embodiments, an upper portion of the sidewall portion 206S of the isolation pad material layer 206M may also be partially removed, but this disclosure is not limited thereto.

[0031] Figure 2F' is an enlarged schematic diagram illustrating the dashed area A2 shown in Figure 2F, which discloses some embodiments. Referring to the discussion in Figures 2E and 2F, a bonding pad 206 is also formed in a second recess R2 within the recess 100U. The bonding pad 206 includes a plurality of protrusions 206P located in the second recess R2, wherein the protrusions 206P protrude toward the first substrate 100. The protrusions 206P are in solid contact with the first substrate 100. A height of the protrusions 206P may correspond to a depth D1 shown in Figure 2D', which is between approximately 100 nm and approximately 500 nm. The depth D2 may be greater than 100 nm, thereby enhancing the adhesion between the bonding pad 206 and the first substrate 100, thereby improving the reliability of the semiconductor device.

[0032] In step S16, a polymer pad 205 is formed in the first recess R1. The formation of the polymer pad 205 will be discussed below with reference to Figures 2G to 2H.

[0033] Figure 2G is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. A polymer material layer 205M is formed over a first recess R1 and the sidewall 206SW of an isolation pad 206. The formation of the polymer material layer 205M includes supplying a carbon-based chemical substance over the first recess R1. In some embodiments, the carbon-based chemical substance may be a carbon-rich gas, such as C4F8 or C4F6. In some alternative embodiments, the carbon-based chemical substance may be carbon monoxide (CO). The material of the polymer material layer 205M may be a fluorinated polymer, which also includes carbon. The dielectric constant of the polymer material layer 205M may be less than 3.5. The polymer material layer 205M is formed over the isolation pad 206. In some embodiments, the fabrication technique of the polymer material layer 205M includes a pulse etching operation comprising multiple repeated cycles: (1) partially removing the polymer material in a first state; and (2) depositing the polymer material in a second state. By appropriately controlling a removal rate in the first state and a deposition rate in the second state, the polymer material layer 205M can be formed into the desired shape. The pulse etching operation may include repeatedly changing the bias power over time, as discussed with reference to FIG. 2G' or FIG. 2G'', while controlling various factors or conditions of the pulse etching operation (e.g., temperature, etching time, etc.). Furthermore, the polymer material layer 205M can be formed in different ways at different locations. In some embodiments, the removal rate of the polymer material layer 205M near an opening in the first recess R1 may be greater than the removal rate of the polymer material layer 205M at a lower position in the first recess R1.

[0034] Figure 2G' is a bias power-time schematic diagram illustrating pulse etching operations of some embodiments of this disclosure. Figure 2G' depicts a first type of pulse etching operation. In the first type of pulse etching operation, a step of partially removing polymer material in a first state is first performed, followed by a step of depositing polymer material in a second state. In the first state, a higher bias power is applied, where the reactants are separated. In the second state, the bias power is reduced, causing the reactants to be in an atomic state and able to be deposited on a surface in solid form. The switching interval of the bias power in the first type of pulse etching operation can be between approximately 10⁻⁴ s and approximately 10 s. That is, the first state and the second state are alternately switched repeatedly, with a switching interval of approximately 10⁻⁴ s to approximately 10 s.

[0035] Figure 2G'' is a bias power-time diagram illustrating pulse etch operations in some embodiments of this disclosure. Figure 2G'' depicts a second type of pulse etch operation. The second type of pulse etch operation is similar to the first type of pulse etch operation discussed with reference to Figure 2G', except that the step of depositing polymer material in the second state is performed before the step of partially removing polymer material in the first state. The switching interval of the bias power in the second type of pulse etch operation can be between approximately 10⁻⁴ s and approximately 10 s. That is, the first state and the second state are alternately switched repeatedly, with a switching interval of approximately 10⁻⁴ s to approximately 10 s.

[0036] Referring back to Figure 2G, the shape of the polymer material layer 205M can be controlled by performing either the first type of pulse etch operation discussed in Figure 2G' or the second type of pulse etch operation discussed in Figure 2G''. Therefore, the initially deposited polymer material layer 205M includes a lower portion 205L and an upper portion 205H located above the lower portion 205L, wherein the upper portion 205H is adjacent to the upper surface 102T of the second passivation layer 102. During the pulse etch operation (i.e., the first or second type of pulse etch operation), the removal rate of the upper portion 205H is greater than the deposition rate of the upper portion 205H, while the deposition rate of the lower portion 205L is greater than the removal rate of the lower portion 205L. Furthermore, the removal rate of the polymer material at the bottom BT of the first recess R1 is greater than the deposition rate of the polymer material, so the interconnect structure 201 can remain exposed to the first recess R1 after the pulse etch operation. Figure 2H illustrates the result of the polymer material layer 205M being shaped into a polymer pad 205.

[0037] Figure 2H is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. A polymer pad 205, formed of a polymer material layer 205M, is deposited in a first recess R1. Therefore, the polymer pad 205 has an upper surface 205T that is lower than the upper surface 102T of the second passivation layer 102. A portion of an isolation pad 206 may be exposed above the polymer pad 205. In some embodiments, as shown in Figure 2H, the upper surface 205T of the polymer pad 205 is higher than the back surface 100B of the first substrate 100. In some embodiments, the polymer pad 205 includes a first portion 205FP laterally surrounded by the second passivation layer 102 and a second portion 205SP laterally surrounded by the first substrate 100 and a portion of the dielectric layer 162. The first portion 205FP is located above the second portion 205SP. The first portion 205FP is higher than the back surface 100B of the first substrate 100. In some embodiments, the polymer pad 205 has a thickness TK1 between about 50 nm and about 500 nm. The second portion 205SP of the polymer pad 205 is in direct contact with the conductive pad 102c. The material of the polymer pad 205 may include fluoropolymers, as well as carbon. The dielectric constant of the polymer pad 205 may be less than 3.5.

[0038] Figure 2I is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. In step S17, a barrier layer 204 is formed in a first recess R1. In some embodiments, the barrier layer 204 is fabricated using a blanket deposition technique. The barrier layer 204 is formed over the upper surface 102T of the second passivation layer 102, over a sidewall 205SW of the polymer pad 205, over the upper surface 205T of the polymer pad 205, over the sidewall 206SW of the isolation pad 206, and over the interconnect structure 201 exposed at the bottom BT of the first recess R1. In some embodiments, the barrier layer 204 may include cobalt, titanium, titanium nitride, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, nickel boride, tantalum nitride / tantalum bilayer, or other suitable materials.

[0039] In step S17, an adhesive layer AL is formed in the first recess R1. In some embodiments, the adhesive layer AL is fabricated using a blanket deposition technique. In some embodiments, the adhesive layer AL is fabricated using a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, sputtering, or other suitable deposition process. The adhesive layer AL is conformally formed over the barrier layer 204. In some embodiments, the adhesive layer AL may comprise, for example, titanium, tantalum, titanyl tungsten, or manganese nitride. The adhesive layer AL can improve the adhesion between the barrier layer 204 and the seed layer 203SD, as described below. In some embodiments, the adhesive layer AL has a thickness between about 5 nm and about 50 nm.

[0040] After performing step S17, a seed layer 203SD may be formed over the adhesive layer AL. In some embodiments, the seed layer 203SD has a thickness of approximately 10 nm to approximately 40 nm. In some embodiments, the seed layer 203SD comprises, for example, copper or ruthenium. In some embodiments, the fabrication technique of the seed layer 203SD includes deposition processes, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, sputtering, or other suitable deposition processes. In some embodiments, the seed layer 203SD may reduce the resistivity of the first recess R1 during the formation of a conductive material 203M, as described below.

[0041] In step S18, in order to form a through-substrate via (TSV) as described with reference to Figures 2J and 2K, conductive material 203M is formed in the first recess R1.

[0042] Figure 2J is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element according to some embodiments of this disclosure. In step S18, a conductive material 203M (e.g., copper or other types of metals, alloys, or the like) is formed in the first recess R1 and over the upper surface 102T of the second passivation layer 102. In some embodiments, the fabrication techniques for the conductive material 203M may include electroplating, electroless plating, sputtering, or other types of deposition operations.

[0043] Figure 2K is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. Step S18 also includes a planarization operation, such as a chemical mechanical planarization (CMP) operation. Through the planarization operation, excess portions of the conductive material 203M can be removed to form TSV 203, thereby forming a first semiconductor wafer 1A. After performing the planarization operation, an upper surface 203T of TSV 203 is coplanar with the upper surface 102T of the second passivation layer 102, an upper surface 204T of the barrier layer 204, an upper surface 203SDT of the seed layer 203SD, an upper surface ALT of the adhesive layer AL, and an upper surface 206TS of the isolation pad 206. Therefore, the upper surface 203T of TSV 203, the upper surface 102T of the second passivation layer 102, the upper surface 204T of the barrier layer 204, the upper surface 203SDT of the seed layer 203SD, the upper surface ALT of the adhesive layer AL, and the upper surface 206TS of the isolation pad 206 are collectively referred to as a first bonding surface BND1. In some embodiments, the upper surface 205T of the polymer pad 205 is separate from the first bonding surface BND1. Therefore, the polymer pad 205 is not exposed through the first bonding surface BND1. Furthermore, the barrier layer 204 is conformally fitted to one sidewall 203SW of TSV 203. The barrier layer 204 extends between the polymer pad 205 and TSV 203. The adhesive layer AL is conformally fitted to the barrier layer 204. The adhesive layer AL is disposed between the barrier layer 204 and TSV 203. The seed layer 203SD is conformally fitted to the adhesive layer AL. A seed layer 203SD is disposed between the adhesive layer AL and the TSV 203. In some embodiments, the seed layer 203SD comprises the same material as the TSV 203 and is referred to as a part of the TSV 203.

[0044] TSV 203 is electrically coupled to the interconnect structure 201 of the conductive feature 210. TSV 203 penetrates the second passivation layer 102 and the first substrate 100. TSV 203 may have a first portion 203A and a second portion 203B, wherein a width W1 of the first portion 203A is greater than a width W2 of the second portion 203B. The first portion 203A is located above the second portion 203B, and the second portion 203B penetrates the first substrate 100. In some embodiments, the width W1 of the first portion 203A is less than a width W3 of the conductive pad 202. In some embodiments, the width W1 of the first portion 203A is equal to or greater than the width W3 of the conductive pad 202.

[0045] The first semiconductor wafer 1A can be used for various types of semiconductor devices, such as dynamic random access memory (DRAM), three-dimensional integrated circuits (3DIC), memory stacks, logic stacks, memory elements, or the like. In some embodiments, the first semiconductor wafer 1A can be stacked with other semiconductor wafers or semiconductor structures to form a semiconductor device. Some embodiments will be discussed with reference to Figures 2L to 2M, 2N, 2O, and 3, respectively.

[0046] In step S19, the first semiconductor wafer 1A is coupled to the second semiconductor wafer 1A'. In some embodiments, the first semiconductor wafer 1A is bonded to the second semiconductor wafer 1A' by performing a hybrid bonding operation. In some embodiments, the configuration of the second semiconductor wafer 1A' may be similar to that of the first semiconductor wafer 1A. The second semiconductor wafer 1A' includes a second substrate 100' similar to the first substrate 100. The first substrate 100 of the first semiconductor wafer 1A is coupled to the second substrate 100' of the second semiconductor wafer 1A' by a hybrid bonding operation. In the examples shown in Figures 2L to 2M, 2N, 2O, and 3, the second semiconductor wafer 1A' is substantially the same as the first semiconductor wafer 1A, and the second substrate 100' is substantially the same as the first substrate 100. However, it should be understood that the design of the second semiconductor wafer 1A' may differ from the design of the second substrate 100'.

[0047] Figure 2L is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element according to some embodiments of this disclosure. Step S19 includes aligning a first semiconductor wafer 1A and a second semiconductor wafer 1A', wherein a first bonding surface BND1 of the first semiconductor wafer 1A faces a second bonding surface BND2 of the second semiconductor wafer 1A'. As shown in Figure 2L, the second bonding surface BND2 of the second semiconductor wafer 1A' is formed from the back surface 103B of the bonding dielectric 103. As in the first semiconductor wafer 1A, in the second semiconductor wafer 1A', the conductive pad 202 can be exposed through the back surface 103B of the bonding dielectric 103 of the second semiconductor wafer 1A'. However, unlike the first semiconductor wafer 1A, the conductive pad 202 of the second semiconductor wafer 1A' is exposed through the second bonding surface BND2.

[0048] Figure 2M is a cross-sectional schematic diagram illustrating a semiconductor element according to some embodiments of this disclosure. Step S19 includes coupling a first semiconductor wafer 1A to a second semiconductor wafer 1A'. First, at a first temperature (which may be around room temperature, for example, about 25°C), the first bonding surface BND1 of the first semiconductor wafer 1A and the second bonding surface BND2 of the second semiconductor wafer 1A' are bonded at a bonding interface INT. Second, the first semiconductor wafer 1A and the second semiconductor wafer 1A' are annealed at a second temperature greater than the first temperature, such that the first semiconductor wafer 1A can be bonded to the second semiconductor wafer 1A' through a hybrid bonding operation. In some embodiments, the second temperature is between about 200°C and about 350°C. The TSV 203 of the first semiconductor wafer 1A is in direct contact with the back surface 103B of the bonding dielectric 103 of the second semiconductor wafer 1A'.

[0049] Figure 2N is a cross-sectional schematic diagram illustrating a semiconductor element according to some embodiments of this disclosure. Step S20 includes forming an upper connector 305 over the conductive feature 210 of the first semiconductor wafer 1A. The intermediate semiconductor element shown in Figure 2M is flipped before step S20. Subsequently, the back side 103B of the bonding dielectric 103 of the first semiconductor wafer 1A faces upward. An upper passivation layer 301 is formed over the back side 103B of the bonding dielectric 103 of the first semiconductor wafer 1A. An opening OP1 is formed through the upper passivation layer 301 to expose the conductive pad 202 of the first semiconductor wafer 1A. An upper barrier layer 303 is formed over the conductive pad 202 of the first semiconductor wafer 1A and within the opening OP1. The upper connector 305 is formed over the upper barrier layer 303 and completely fills the opening OP1. After forming the upper connector 305, the semiconductor element 1B is obtained.

[0050] In some embodiments, the upper passivation layer 301 is a single-layer structure or a multilayer structure. In some embodiments, the upper passivation layer 301 includes polybenzoxazole, polyimide, benzocyclobutene, solder resist, the like, or combinations thereof. Polymer materials (e.g., polyimide) can have many advantageous properties, such as the ability to fill high aspect ratio openings, a relatively low dielectric constant (about 3.2), a simple deposition process, reduction of sharp features or steps in the underlying layer, and high temperature resistance after curing. Furthermore, some photosensitive polymer materials (e.g., photosensitive polyimide) can have all of the above properties, can be patterned like a photoresist mask, and can remain on a surface where a photosensitive polymer material has been deposited after patterning and etching as part of the passivation layer. In some other embodiments, the upper passivation layer 301 can be a dielectric layer. The dielectric layer may include, for example, a silicon nitride, a silicon oxide, a silicon oxynitride, silicon oxynitride, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, the like, or combinations thereof.

[0051] In some embodiments, the opening OP1 is formed through the upper passivation layer 301 to expose a portion of the back surface 103B of the bonding dielectric 103 between the conductive pad 202 and the first semiconductor wafer 1A. In some embodiments, one sidewall of the opening OP1 is substantially vertical. In some embodiments, the sidewall of the opening OP1 is tapered. It should be understood that, in the description of this disclosure, a surface is considered "substantially vertical" if a vertical plane exists and the deviation of that vertical plane does not exceed three times the root mean square roughness of the surface.

[0052] In some embodiments, an upper barrier layer 303 is formed above the conductive pad 202 and within the opening OP1. The upper barrier layer 303 has a thickness T3, which may be less than the thickness T4 of the upper passivation layer 301. The upper barrier layer 303 comprises, for example, aluminum fluoride. Due to the saturated bonding characteristics of aluminum fluoride, it is stable and can protect the underlying conductive pad 202 from corrosion caused by various semiconductor processes, particularly those involving fluoride ions. In some embodiments, the upper barrier layer 303 may also include zinc oxide, which can improve the electronic properties of the upper barrier layer 303. In some embodiments, the concentration of zinc oxide in the upper barrier layer 303 may be greater than the concentration of aluminum fluoride in the upper barrier layer 303.

[0053] In some embodiments, an upper connector 305 is formed above the upper barrier layer 303 and the upper passivation layer 301 and completely fills the opening OP1. A lower portion of the upper connector 305 extends into the upper passivation layer 301, completely filling the opening OP1, and is located above the upper barrier layer 303. An upper portion of the upper connector 305 protrudes from a plane coplanar with an upper surface of the upper passivation layer 301, covering the lower portion of the upper connector 305 and a portion of the upper surface of the upper passivation layer 301 near the opening OP1. In some embodiments, the upper connector 305 comprises, for example, a conductive material having low resistivity, such as tin, lead, silver, copper, nickel, bismuth, or an alloy thereof.

[0054] In some embodiments, the upper connector 305 is a solder joint. The solder joint comprises a material such as tin, or other suitable materials such as silver or copper. In embodiments where the solder joint is a tin solder joint, the solder joint is initially formed by vapor deposition, electroplating, printing, solder transfer, or ball placement, with a thickness of approximately 10 μm to approximately 100 μm. Once the tin layer is formed and fills the opening OP1 and protrudes above the upper passivation layer 301, a reflow process can be performed to shape the solder joint into a desired shape.

[0055] In some embodiments, the polymer pad 205 is separated from the bonding interface INT, thereby improving the reliability of the hybrid bonding operation in terms of adhesion between the first semiconductor wafer 1A and the second semiconductor wafer 1A', and mitigating or limiting the negative impact on the electronic performance of the semiconductor element 1B.

[0056] Traditional bonding operations face challenges caused by the expansion of conductive materials at mixed bonding temperatures. Deformation of the conductive material can result in uneven bonding surface profiles, leading to poor adhesion between the two wafers.

[0057] To address the aforementioned problems, this disclosure provides a semiconductor device having a polymer pad 205. In some embodiments, because the polymer pad 205 has high toughness, deformation of the TSV 203 can be reduced or the negative impact of TSV 203 deformation can be buffered. This reduces the degree of deformation of the TSV 203 (particularly in the vertical direction) and mitigates stress concentration in the TSV 203. As a result, the yield of hybrid bonding operations can be improved.

[0058] Figure 20 is a cross-sectional schematic diagram illustrating a semiconductor element according to some embodiments of this disclosure. The semiconductor element 1C shown in Figure 20 is similar to the semiconductor element shown in Figure 2M. The difference is that semiconductor element 1C comprises two or more stacked semiconductor wafers. For example, a first semiconductor wafer 1A is coupled to multiple second semiconductor wafers 1A' (see the discussion in Figures 2K to 2N). Mixed bonding operations can be repeated. It should be understood that as the number of stacked semiconductor wafers increases, the deformation of TSV 203 may worsen, thus exacerbating tolerance problems in mixed bonding. Therefore, this disclosure provides a solution to such problems for multi-wafer stack configurations.

[0059] Figure 3 is a cross-sectional schematic diagram illustrating a semiconductor element according to some embodiments of this disclosure. The semiconductor element 1D shown in Figure 3 is similar to the semiconductor element shown in Figure 2M. The difference is that the first semiconductor wafer 1A and the second semiconductor wafer 1A' may each have two or more TSV 203s.

[0060] In pursuit of higher component density, the distance between adjacent TSV 203s is becoming increasingly smaller. Therefore, adding polymer pads 205 can help reduce electronic interference, thereby improving component performance.

[0061] Figure 4 is a schematic flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of this disclosure. The fabrication method S1' includes multiple steps (S11, S12, S13, S14, S15, S16', S17, S18, S19, and S20), and the description and illustration are not intended to limit the order of the steps. In step S11, a conductive feature is formed in a first passivation layer over a front side of a first substrate. In step S12, the first substrate is thinned from a back side. In step S13, a second passivation layer is formed over the back side of the first substrate. In operation S14, a first recess is formed in an upper surface of the second passivation layer to expose the conductive feature, and a recess portion is formed in a sidewall of the first substrate. In step S15, an isolation pad is formed in the first recess. In step S16', a pulse etching operation is performed to form a polymer pad in the first recess, wherein an upper surface of the polymer pad is lower than the back side of the first substrate. In step S17, a barrier layer and an adhesive layer are formed in the first recess. In step S18, a conductive material is formed in the first recess to form a through-substrate via (TSV). In step S19, a second substrate is coupled to the first substrate by performing a hybrid bonding operation. In step S20, an upper connector is formed above the conductive feature.

[0062] Figures 5A to 5D are cross-sectional schematic diagrams illustrating the various manufacturing stages constructed by the preparation method S1' of some embodiments of this disclosure. Figures 5D, 5E, and 6 illustrate schematic diagrams of various components that can be manufactured by performing the operations of preparation method S1'. Furthermore, preparation method S1' is similar to preparation method S1 shown in Figure 1, but differs in that step S16' in preparation method S1' is different from step S16 in preparation method S1, as described below. In some embodiments, in preparation method S1', after performing steps S11, S12, S13, S14, and S15 (corresponding to the steps shown in Figures 2A to 2F'), step S16' is performed instead of step S16. Please refer to Figures 5A to 5D to discuss steps S16', S17, S18, S19, and S20 performed after step S15.

[0063] Figure 5A is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. A polymer material layer 205M is formed in a first recess R1 and over a sidewall 206SW of an isolation pad 206. The formation of the polymer material layer 205M includes performing the pulse etching operation discussed with reference to Figure 2G and Figure 2G' or Figure 2G''. The material of the polymer material layer 205M may include a fluorinated polymer, and may also include carbon. The dielectric constant of the polymer material layer 205M may be less than 3.5. The polymer material layer 205M is formed over the isolation pad 206.

[0064] The shape of the polymer material layer 205M can be controlled. Therefore, during initial deposition, the polymer material layer 205M includes a lower portion 205L and an upper portion 205H located above the lower portion 205L, wherein the upper portion 205H is adjacent to an upper surface 102T of the second passivation layer 102. During a pulse etching operation (i.e., a first or second type of pulse etching operation as described in Figures 2G to 2G''), the removal rate of the upper portion 205H is greater than the deposition rate of the upper portion 205H, and the deposition rate of the lower portion 205L is greater than the removal rate of the lower portion 205L. Furthermore, the removal rate of polymer material at a bottom BT of the first recess R1 is greater than the deposition rate of polymer material at the bottom BT; therefore, after performing the pulse etching operation, the interconnect structure 201 can remain exposed to the first recess R1.

[0065] Compared to the embodiment discussed with reference to FIG. 2G, the upper portion 205H in the embodiment discussed with reference to FIG. 5A extends to a position below the back surface 100B of the first substrate 100. FIG. 2 shows the result of forming the polymer material layer 205M as a polymer pad 205.

[0066] Figure 5B is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. A polymer pad 205, formed of a polymer material layer 205M, is deposited in a first recess R1. Therefore, the polymer pad 205 has an upper surface 205T that is lower than the upper surface 102T of the second passivation layer 102. A portion of an isolation pad 206 may be exposed above the polymer pad 205. In some embodiments, as shown in Figure 5B, the upper surface 205T of the polymer pad 205 is lower than the back surface 100B of the first substrate 100. In some embodiments, the polymer pad 205 has a thickness TK1 that is between about 50 nm and about 500 nm. The polymer pad 205 is in direct contact with the conductive pad 102c. The material of the polymer pad 205 may include a fluoropolymer. The dielectric constant of the polymer pad 205 may be less than 3.5.

[0067] Figure 5C is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor device according to some embodiments of this disclosure. Similar to the steps shown in Figures 2I to 2K, steps S17 and S18 of fabrication method S1' are performed. In step S17, a barrier layer 204 is formed in a first recess R1. In some embodiments, the barrier layer 204 is formed over a sidewall 205SW of a polymer pad 205, over the upper surface 205T of the polymer pad 205, over the sidewall 206SW of an isolation pad 206, and over the interconnect structure 201 exposed at the bottom BT of the first recess R1. An adhesive layer AL is conformally formed over the barrier layer 204. After performing step S17, a seed layer 203SD may be conformally formed over the adhesive layer AL. In step S18, the fabrication technique for a TSV 203 includes depositing a conductive material in the first recess R1 and then performing a planarization operation, such as a chemical mechanical planarization (CMP) operation. Therefore, a first semiconductor wafer 2A is formed.

[0068] The first semiconductor wafer 2A shown in Figure 5C is similar to the first semiconductor wafer 1A shown in Figure 2K, except that in the first semiconductor wafer 2A, the upper surface 205T of the polymer pad 205 is lower than the back surface 100B of the first substrate 100. The first semiconductor wafer 2A can be used for various types of semiconductor devices, such as dynamic random access memory (DRAM), three-dimensional integrated circuits (3DIC), memory stacks, logic stacks, memory elements, or the like. In some embodiments, the first semiconductor wafer 2A can be stacked with other semiconductor wafers or semiconductor structures to form a semiconductor device. Some embodiments will be discussed with reference to Figures 5D, 5E, and 6, respectively.

[0069] Figure 5D is a cross-sectional schematic diagram illustrating intermediate stages in the formation of semiconductor elements according to some embodiments of this disclosure. In steps S19 and S20, a first semiconductor wafer 2A is coupled to a second semiconductor wafer 2A', and an upper connector 305 is formed over the conductive pad 202 of the first semiconductor wafer 2A. In some embodiments, the first semiconductor wafer 2A is bonded to the second semiconductor wafer 2A' by performing a hybrid bonding operation. Next, an upper passivation layer 301, an upper barrier layer 303, and an upper connector 305 are formed over the back surface 103B of the bonding dielectric 103 of the first semiconductor wafer 2A, thereby obtaining the semiconductor element 2B. In some embodiments, the configuration of the second semiconductor wafer 2A' may be similar to that of the first semiconductor wafer 2A shown in Figure 5C or the first semiconductor wafer 1A shown in Figure 2K. The second semiconductor wafer 2A' includes a second substrate 100' similar to the first substrate 100 shown in Figure 2K. The first substrate 100 of the first semiconductor wafer 2A is coupled to the second substrate 100' of the second semiconductor wafer 2A' by a hybrid bonding operation. The details of the hybrid bonding operation are discussed above with reference to Figures 2L to 2M. The details of the formation of the upper passivation layer 301, the upper barrier layer 303, and the upper connector 305 are discussed above with reference to Figure 2N.

[0070] Figure 5E is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor element according to some embodiments of this disclosure. The semiconductor element 2C shown in Figure 5E is similar to the semiconductor element 2B shown in Figure 5D. The difference is that the semiconductor element 2C shown in Figure 5E comprises two or more stacked semiconductor wafers. For example, a first semiconductor wafer 2A is coupled to one or more second semiconductor wafers 2A'. In such embodiments, the hybrid bonding operation can be repeated.

[0071] Figure 6 is a cross-sectional schematic diagram illustrating a semiconductor element according to some embodiments of the present disclosure. The semiconductor element 2D shown in Figure 6 is similar to the semiconductor element 2B shown in Figure 5D. The difference is that in semiconductor element 2D, the first semiconductor wafer 2A and the second semiconductor wafer 2A' may each have two or more TSVs 203.

[0072] One embodiment of this disclosure provides a semiconductor device including a first substrate having a front side and a back side parallel to the front side; a bonding dielectric disposed on the front side of the first substrate; a redistribution layer disposed between the bonding dielectric and the front side of the first substrate; a first dielectric layer disposed between the front side of the first substrate and the redistribution layer; a capping layer disposed between the redistribution layer and the bonding dielectric; a first conductive pad disposed between the capping layer and the bonding dielectric; a second dielectric layer disposed between the capping layer and the bonding dielectric, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature disposed in the bonding dielectric and the first conductive pad, wherein the conductive feature includes conductivity through the bonding dielectric. The first substrate comprises: a second conductive pad exposed on its back side and an interconnect structure electrically connected to the second conductive pad and penetrating the first conductive pad; a second passivation layer disposed above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a through-substrate via (TSV) passing through the second passivation layer and the first substrate, wherein the TSV is electrically coupled to the conductive feature; a polymer pad disposed between the TSV and the first substrate, wherein an upper surface of the polymer pad is lower than the upper surface of the second passivation layer; a barrier layer disposed between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the interconnect structure and the TSV; and an adhesive layer disposed between the barrier layer and the TSV.

[0073] Another embodiment of this disclosure provides a semiconductor device including a first semiconductor wafer, comprising a first substrate having a front side and a back side parallel to the front side; a bonding dielectric disposed above the front side of the first substrate; and a second passivation layer disposed above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a redistribution layer disposed between the bonding dielectric and the front side of the first substrate; a first dielectric layer disposed between the front side of the first substrate and the redistribution layer; a capping layer disposed between the redistribution layer and the bonding dielectric; a first conductive pad disposed between the capping layer and the bonding dielectric; and a second dielectric layer disposed between the capping layer and the bonding dielectric. The second dielectric layer has one surface coplanar with one surface of the first conductive pad; a conductive feature is disposed in the bonding dielectric and the first conductive pad; a through-substrate via (TSV) is exposed through the second passivation layer and electrically coupled to the conductive feature; a polymer pad is disposed between the TSV and the first substrate; a barrier layer is disposed between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the conductive feature and the TSV; an adhesive layer is disposed between the barrier layer and the TSV; and a second semiconductor wafer is coupled to the first semiconductor wafer at a bonding interface and includes a second substrate coupled to the first substrate; wherein the polymer pad of the first semiconductor wafer is separated from the bonding interface.

[0074] Another embodiment of this disclosure provides a method for fabricating a semiconductor device, comprising forming a conductive feature and a bonding dielectric over a front side of a first substrate, wherein the conductive feature is formed in the bonding dielectric; forming a redistribution layer between the bonding dielectric and the front side of the first substrate; forming a second passivation layer over a back side of the first substrate; forming a first recess in an upper surface of the second passivation layer to expose the conductive feature; conformally forming an isolation pad on a sidewall of the first recess; performing a pulse etching operation to conformally form a polymer pad on the sidewall of the isolation pad, wherein an upper surface of the polymer pad is lower than the upper surface of the second passivation layer; conformally forming a barrier layer over the polymer pad and the isolation pad; conformally forming an adhesive layer over the barrier layer; and forming a conductive material in the first recess to form a through-substrate via (TSV).

[0075] In summary, this disclosure provides a semiconductor device with polymer pads and a method for fabricating the semiconductor device with polymer pads.

[0076] To address the issue of low yield caused by the expansion and deformation of conductive materials at high temperatures during hybrid bonding operations, this disclosure provides a semiconductor device with polymer pads. In some embodiments, due to the high toughness of the polymer pads, they can reduce TSV deformation or buffer the negative impact of TSV deformation. This reduces the degree of TSV deformation (especially in the vertical direction) and alleviates stress concentration within the TSV.

[0077] The shape of the polymer pads can be controlled by referring to the pulse etching operation conditions discussed in FIG2G, such as the first type of pulse etching operation shown in FIG2G' or the second type of pulse etching operation shown in FIG2G''. Thus, a first semiconductor wafer 1A with polymer pads 205 as shown in FIG2K, or a first semiconductor wafer 2A with polymer pads 205 as shown in FIG5C, can be obtained.

[0078] The first semiconductor wafer 1A and the first semiconductor wafer 2A can be stacked to form various types of devices, as shown in Figures 2M, 2N, 2O, 3, 5D, 5E and 6. The aforementioned semiconductor devices or semiconductor structures can be formed by bonding multiple substrates or wafers together using a hybrid bonding operation.

[0079] In pursuit of greater component density, the distance between adjacent TSV pairs is becoming increasingly smaller. Therefore, the configuration of polymer pads can help reduce electronic interference in semiconductor devices with higher component density (e.g., semiconductor device 1D shown in Figure 3, or semiconductor device 2D shown in Figure 6), thereby improving device performance.

[0080] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0081] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0082] 1A: First Semiconductor Wafer 1A': Second semiconductor wafer 1B: Semiconductor components 1C: Semiconductor components 1D: Semiconductor Components 2A: First Semiconductor Wafer 2A': Second semiconductor wafer 2B: Semiconductor components 2C: Semiconductor components 2D: Semiconductor Components 100: First base 100': Second base 100B: Back 100F: Front 100SW: Sidewall 100U: Recessed area 101: First passivation layer 1012: Periphery 102: Second passivation layer 102b: Dielectric layer 102c: Conductive pad 102SW: Sidewall 102T: Upper surface 103: Bonding Dielectric 103B: Back 162: Dielectric layer 162SW: Sidewall 174: Redistribution Layer (RDL) 1742: Horizontal segment 1744: Vertical Segment 184: Cover layer 201: Interconnection Structure 202: Conductive pad 202E: Exposed Surfaces 203: Through-substrate via (TSV) 203A: Part 1 203B: Part Two 203M: Conductive material 203SD: Seed Layer 203SDT: Top surface 203SW: Sidewall 203T: Upper surface 204: Barrier Layer 204T: Top surface 205: Polymer solder pad 205FP: Part 1 205H: Upper part 205L: lower part 205M: Polymer material layer 205SP: Part Two 205SW: Sidewall 205T: Upper surface 206: Isolation pad 206B: Bottom 206M: Isolation pad material layer 206P: Protrusion 206S: Sidewall portion 206SW: Sidewall 206T: Top 206TS: Top surface 210: Electrical conductivity characteristics 301: Upper passivation layer 303: Upper Barrier Layer 305: Upper Connector A1: Dashed line area A2: Dashed line area AL: Adhesive layer ALT: Upper surface BND1: ​​First bonding surface BND2: Second bonding surface BT: Bottom D1: Depth D2: Depth INT: Interface OP1: Opening R1: First depression R2: Second depression REF: Imaginary surface S1: Preparation method S1': Preparation method S11: Steps S12: Steps S13: Steps S14: Steps S15: Steps S16: Steps S16': Steps S17: Steps S18: Steps S19: Steps S20: Steps T1: First thickness T2: Second thickness T3: Thickness T4: Thickness TK1: Thickness W1: Width W2: Width W3: Width Z: Axis

Claims

1. A semiconductor element, comprising: A first substrate includes a front side and a back side parallel to the front side; a bonding dielectric is disposed on the front side of the first substrate; A redistribution layer is disposed between the bonding dielectric and the front side of the first substrate; a first dielectric layer is disposed between the front side of the first substrate and the redistribution layer; a capping layer is disposed between the redistribution layer and the bonding dielectric; a first conductive pad is disposed between the capping layer and the bonding dielectric; a second dielectric layer is disposed between the capping layer and the bonding dielectric, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; a conductive feature is disposed in the bonding dielectric and the first conductive pad, wherein the conductive feature includes a second conductive pad exposed through a back side of the bonding dielectric and an interconnect structure electrically connected to the second conductive pad and penetrating the first conductive pad; a second passivation layer is disposed above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a through-substrate via (TSV) passes through the second passivation layer and the first substrate, wherein the TSV is electrically coupled to the conductive feature; A polymer pad is disposed between the TSV and the first substrate, wherein an upper surface of the polymer pad is lower than an upper surface of the second passivation layer; a barrier layer is disposed between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the interconnect structure and the TSV; and an adhesive layer is disposed between the barrier layer and the TSV.

2. The semiconductor device as claimed in claim 1 further includes a seed layer disposed between the adhesive layer and the TSV.

3. The semiconductor device as claimed in claim 2 further includes an isolation pad disposed between the barrier layer and the second passivation layer and between the polymer pad and the first substrate.

4. The semiconductor device as claimed in claim 3, wherein the redistribution layer includes a plurality of horizontal segments parallel to the front side of the first substrate and a plurality of vertical segments parallel to a surface of the isolation pad.

5. The semiconductor element as claimed in claim 4, wherein the horizontal segments and the vertical segments connected to the horizontal segments are integrally formed.

6. The semiconductor element as claimed in claim 1, wherein the TSV includes a first portion and a second portion, wherein the second portion is disposed above the interconnect structure, and the first portion is disposed above the second portion and above the upper surface of the polymer pad.

7. The semiconductor element as claimed in claim 6, wherein a width of the first portion is greater than a width of the second portion.

8. The semiconductor device as claimed in claim 1, wherein the thickness of the polymer pad is between about 50 nanometers and 500 nanometers.

9. The semiconductor device as claimed in claim 3, wherein the adhesive layer comprises titanium, tantalum, titanium tungsten, or manganese nitride.

10. The semiconductor device as claimed in claim 3, wherein the seed layer comprises copper or ruthenium.

11. The semiconductor device as claimed in claim 3, wherein the barrier layer comprises cobalt, titanium, titanium nitride, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, nickel boride, or a tantalum nitride / tantalum bilayer.

12. The semiconductor device as claimed in claim 3, wherein the polymer pad comprises a fluoropolymer.

13. The semiconductor element as claimed in claim 7, wherein a width of the conductive pad is different from a width of the first portion.

14. A semiconductor element, comprising: A first semiconductor wafer includes a first substrate having a front side and a back side parallel to the front side; a bonding dielectric and a second passivation layer, the bonding dielectric being disposed above the front side of the first substrate and the second passivation layer being disposed above the back side of the first substrate, wherein the second passivation layer has an upper surface facing away from the first substrate; a redistribution layer disposed between the bonding dielectric and the front side of the first substrate; a first dielectric layer disposed between the front side of the first substrate and the redistribution layer; a capping layer disposed between the redistribution layer and the bonding dielectric; a first conductive pad disposed between the capping layer and the bonding dielectric; a second dielectric layer disposed between the capping layer and the bonding dielectric, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature disposed in the bonding dielectric and the first conductive pad. A through-substrate via (TSV) exposed through the second passivation layer and electrically coupled to the conductive feature; a polymer pad disposed between the TSV and the first substrate; a barrier layer disposed between the second passivation layer and the TSV, between the polymer pad and the TSV, and between the conductive feature and the TSV; an adhesive layer disposed between the barrier layer and the TSV; and a second semiconductor wafer coupled to the first semiconductor wafer at a bonding interface and including a second substrate coupled to the first substrate, wherein the polymer pad of the first semiconductor wafer is spaced apart from the bonding interface.

15. The semiconductor element as claimed in claim 14, wherein the conductive feature includes a second conductive pad exposed through a back side of the bonding dielectric, and an interconnect structure electrically connected to the second conductive pad and penetrating the first conductive pad.

16. The semiconductor element as claimed in claim 15 further includes a solder joint disposed above the conductive feature.

17. The semiconductor device as claimed in claim 16 further includes an upper barrier layer disposed between the solder joint and the conductive feature.

18. The semiconductor device as claimed in claim 17 further includes an upper passivation layer disposed over the back side of the bonding dielectric, wherein the upper barrier layer is disposed in the upper passivation layer.

19. The semiconductor device as claimed in claim 18, wherein the upper passivation layer comprises polybenzoxazole, polyimide, benzocyclobutene, solder resist, or a combination thereof.

20. The semiconductor device as claimed in claim 18, wherein the upper barrier layer comprises aluminum fluoride and zinc oxide.

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