Three-dimensional stacked wafers and their fabrication methods

Abstract

This invention discloses a three-dimensional stacked wafer and its fabrication method. The three-dimensional stacked wafer includes a substrate, a first storage module, and a logic module; the first storage module and the logic module are stacked sequentially on the substrate, with the first storage module disposed between the logic module and the substrate; the first storage module provides and stores the data required by the logic module, supporting the logic module in completing corresponding tasks; the logic module interacts with the outside world via the first storage module and the substrate. This invention avoids the impact of heat generated by the logic module on the storage module, significantly improves the power consumption tolerance of the logic module, and effectively reduces the number of conductive paths required in the storage module stack structure.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to a three-dimensional stacked wafer and its fabrication method. Prior Technology

[0002] With the explosive growth of large language models in AI applications, artificial intelligence software is placing higher demands on the chip design industry. Traditional chip architectures and supporting storage are far from meeting the high bandwidth and high capacity requirements of large language models. In order to meet the needs of the explosive development of AI, it is necessary to accelerate the research and development of new chip architectures and new storage technologies. Summary of the Invention

[0003] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a three-dimensional stacked wafer and its manufacturing method, which avoids the impact of heat generated by the logic module on the storage module, significantly improves the power consumption tolerance of the logic module, and can effectively reduce the number of conductive paths that need to be set in the stacked structure of the storage module.

[0004] To achieve the above objectives, according to one aspect of the present invention, a three-dimensional stacked wafer is provided, comprising a substrate, a first storage module, and a logic module; the first storage module and the logic module are stacked sequentially on the substrate, and the first storage module is disposed between the logic module and the substrate; the first storage module is used to provide and store the data required by the logic module, supporting the logic module to complete the corresponding work; the logic module interacts with the outside world through the first storage module and the substrate.

[0005] In some embodiments, the three-dimensional stacked wafer further includes one or more stacked second storage modules, which are disposed between the first storage module and the logic module to form a storage module stack structure with the first storage module; the one or more stacked second storage modules are used to provide and store the data required by the logic module to support the logic module in completing the corresponding work; the logic module interacts with the outside world through the storage module stack structure and the substrate.

[0006] In some implementations, the logic module is connected to the power supply via the storage module stack structure and to ground via the side opposite to the storage module stack structure.

[0007] In some implementations, the logic module is connected to ground via the storage module stack structure and connected to power via the side opposite to the storage module stack structure.

[0008] In some implementations, the logic module includes multiple stacked sub-logic modules, a first storage module, and one or more stacked second storage modules for providing and storing the data required by the multiple stacked sub-logic modules, supporting the multiple stacked sub-logic modules in completing their respective tasks.

[0009] In some implementations, sub-logic modules closer to the storage module stack have lower power, while sub-logic modules farther from the storage module stack have higher power.

[0010] In some embodiments, a first storage module is disposed directly or indirectly on a substrate, one or more stacked second storage modules are disposed directly or indirectly on the first storage module as a whole, and a logic module is disposed directly or indirectly on one or more stacked second storage modules.

[0011] In some embodiments, the aforementioned three-dimensional stacked wafer further includes external circuitry disposed on a substrate; the logic module obtains working instructions from the external circuitry through the substrate and the storage module stacking structure, completes the corresponding work, and transmits the processing results through the storage module stacking structure and the substrate.

[0012] In some embodiments, the aforementioned three-dimensional stacked wafer further includes a silicon interposer and external circuitry. The silicon interposer is disposed between the first storage module and the substrate, and the external circuitry is disposed on the silicon interposer. The logic module obtains working instructions from the external circuitry through the silicon interposer and the storage module stacking structure, completes the corresponding work, and transmits the processing results through the storage module stacking structure and the silicon interposer.

[0013] In some embodiments, the aforementioned three-dimensional stacked wafer further includes a silicon interposer and external circuitry. The silicon interposer is disposed between the first storage module and the substrate, and the external circuitry is disposed on the silicon interposer. The logic module obtains working instructions from the external circuitry through the silicon interposer and the substrate, via the storage module stacking structure, completes the corresponding work, and transmits the processing results through the storage module stacking structure, via the silicon interposer and the substrate.

[0014] In some embodiments, the aforementioned three-dimensional stacked wafer further includes a heat dissipation module, which is directly or indirectly disposed on the logic module.

[0015] In some implementations, the heat dissipation module forms a conductive connection with the logic module, and the logic module uses the heat dissipation module to connect to the power supply or ground.

[0016] In some implementations, the logic module and the heat dissipation module are connected by a conductive spacer layer.

[0017] According to another aspect of the present invention, a method for fabricating a three-dimensional stacked wafer is provided, comprising:

[0018] A first stacked structure is formed; the first stacked structure includes a logic structure and one or more second storage modules stacked sequentially on the logic structure;

[0019] A second stacked structure is formed using a first storage structure and a first stacking structure; the second stacked structure includes a first storage module and one or more second storage modules and logic modules stacked sequentially on the first storage module, wherein the first storage module is obtained by processing the first storage structure, and the logic module is obtained by processing the logic structure;

[0020] Connect the first storage module to the substrate.

[0021] In some embodiments, the first storage structure includes a first substrate and a first memory device and a first interconnect layer formed on the first substrate; processing the first storage structure to obtain a first storage module includes forming a silicon via through the first substrate of the first storage structure.

[0022] In some embodiments, the first storage structure includes a first substrate and a first memory device and a first interconnect layer formed on the first substrate; processing the first storage structure to obtain a first storage module includes: thinning the first substrate of the first storage structure to form a silicon via penetrating the thinned first substrate.

[0023] In some embodiments, the logic structure includes a second substrate and logic devices and a second interconnect layer formed on the second substrate; processing the logic structure to obtain a logic module includes: thinning the second substrate of the logic structure to form silicon vias through the thinned second substrate.

[0024] In some embodiments, the second storage module includes: a thinned third substrate, a second memory device and a third interconnect layer formed on the third substrate, and a fourth interconnect layer formed on the back side of the thinned third substrate.

[0025] In some embodiments, the method for fabricating the above-mentioned three-dimensional stacked wafer further includes: setting a heat dissipation module on the logic module.

[0026] In some implementations, a conductive spacer layer and a heat dissipation module are sequentially disposed on the logic module, and the logic module and the heat dissipation module are connected through the conductive spacer layer, so that the logic module can be connected to power or ground using the heat dissipation module.

[0027] In summary, compared with the prior art, the technical solution conceived by this invention has the following beneficial effects: By placing the storage module stack structure between the logic module and the substrate, and placing the logic module on top of the storage module stack structure, heat dissipation of the logic module is greatly facilitated. The logic module is closer to the heat dissipation module than the storage module stack structure, avoiding the impact of heat generated by the logic module on the storage module, and significantly improving the power consumption tolerance of the logic module. Furthermore, the logic module connects to power or ground on the side opposite to the storage module stack structure, avoiding the need to pass through the storage module stack structure for both power and ground connections. Therefore, the number of conductive paths (e.g., vias) that need to be set in the storage module stack structure can be effectively reduced. Simple Explanation of the Diagram

[0028] Figure 1 is a schematic diagram of a three-dimensional stacked wafer structure; Figure 2 is a schematic diagram of a three-dimensional stacked wafer according to an embodiment of the present invention; Figure 3 is a schematic diagram of the structure of a three-dimensional stacked wafer according to another embodiment of the present invention; Figure 4 is a schematic diagram of the structure of a three-dimensional stacked wafer according to another embodiment of the present invention; Figures 5A-5J are schematic diagrams illustrating the fabrication method of a three-dimensional stacked wafer according to an embodiment of the present invention; Figure 6 is a schematic diagram of the fabrication process of a three-dimensional stacked wafer according to an embodiment of the present invention. Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered exemplary in nature and not restrictive.

[0030] Stacking storage modules and logic modules in multiple layers can multiply the bandwidth and capacity of the system, thus fully meeting the requirements of large language models. Figure 1 shows a solution for three-dimensional stacked chips.

[0031] As shown in Figure 1, logic modules 103 and multiple storage modules 105 are stacked sequentially on a substrate 101. The storage modules 105 are positioned on top of the logic modules 103, and the logic modules 103 are positioned between the storage modules 105 and the substrate 101. This arrangement facilitates providing suitable power and ground to the logic modules 103 and allows for data transfer between the logic modules 103 and the outside world. However, the logic modules 103 generate a significant amount of heat during operation. This heat is primarily dissipated upwards through the side containing the storage modules 105. The storage modules 105 are highly sensitive to heat, and the multi-layered stacking further restricts heat dissipation. Especially during high-power operation of the logic modules 103, this stacking method results in severe heat accumulation, significantly reducing the power tolerance of the logic modules 103. Therefore, the three-dimensional stacked chip shown in Figure 1 cannot meet the power consumption and computing power requirements of large language models for logic modules.

[0032] To improve the power consumption tolerance of the logic module and reduce the adverse effects of heat accumulation on the storage module, it is necessary to further improve the three-dimensional stacked wafer shown in Figure 1.

[0033] As shown in Figure 2, the three-dimensional stacked wafer of this embodiment includes a substrate 201, a first storage module 203, one or more second storage modules 207, and a logic module 205. The first storage module 203, one or more second storage modules 207, and logic module 205 are stacked sequentially on the substrate 201. The first storage module 203 and one or more second storage modules 207 form a storage module stack structure, and the logic module 205 is disposed on the storage module stack structure. The storage module stack structure is disposed between the substrate 201 and the logic module 205.

[0034] One side of the first storage module 203 is electrically connected to the adjacent second storage module 207, and the other side of the first storage module 203 is electrically connected to the substrate 201. One side of the logic module 205 is electrically connected to the adjacent second storage module 207. When one side of the second storage module 207 is adjacent to another second storage module 207, one side of the second storage module 207 is electrically connected to the adjacent second storage module 207; when both sides of the second storage module 207 are adjacent to other second storage modules 207, both sides of the second storage module 207 are electrically connected to other second storage modules 207.

[0035] Furthermore, the logic module 205 forms a conductive connection with the first storage module 203 and one or more second storage modules 207, enabling the logic module 205 to interact with the first storage module 203 and one or more second storage modules 207. Specifically, the first storage module 203 and one or more second storage modules 207 provide and store the data required by the logic module 205, supporting the logic module 205 in completing corresponding tasks. In some embodiments, at least some of the first storage module 203 and one or more second storage modules 207 can also implement a small number of logic control functions, that is, at least some of these storage modules are a combination of storage medium and logic medium, which may be a one-dimensional structure, a two-dimensional structure, or a three-dimensional structure. In some embodiments, the functions that the logic module 205 can implement include one or more of the following: computation, control, interface, and data processing.

[0036] The logic module 205 forms a conductive connection with the first storage module 203 and one or more second storage modules 207, thereby forming a conductive path in the storage module stack structure, enabling the logic module 205 to interact with the outside world via the storage module stack structure. In some embodiments, the logic module 205 is connected to the power supply via the storage module stack structure and is connected to ground via the side opposite to the storage module stack structure. In other embodiments, the logic module 205 is connected to ground via the storage module stack structure and is connected to the power supply via the side opposite to the storage module stack structure.

[0037] In some embodiments, logic module 205 includes multiple stacked sub-logic modules, with adjacent surfaces of the stacked sub-logic modules forming a conductive connection. In some embodiments, sub-logic modules closer to the storage module stack have lower power, while sub-logic modules farther from the storage module stack have higher power, which helps dissipate heat from the higher-power sub-logic modules and reduces the impact of heat on the storage module.

[0038] In some implementations, one or more second storage modules 207 can be omitted, and the storage module stack structure can be replaced by a first storage module 203. That is, one side of the first storage module 203 forms a conductive connection with the logic module 205, and the other side of the first storage module 203 forms a conductive connection with the substrate 201. The above-described scheme of placing the logic module on top of the storage module is still applicable to the case of only one storage module.

[0039] In some embodiments, the above-mentioned methods of forming conductive connections include one or more of hybrid bonding connections and conductive bump connections. In some embodiments, the first storage module 203 may be directly or indirectly disposed on the substrate 201, and one or more second storage modules 207 as a whole may also be directly or indirectly disposed on the first storage module 203, and the logic module 205 may also be directly or indirectly disposed on one or more second storage modules 207. In some embodiments, "adjacent" refers to the closest neighbor, which can be either directly adjacent or indirectly adjacent. For example, two adjacent second storage modules 207 are directly adjacent when there are no other second storage modules 207 or other structures between them; two adjacent second storage modules 207 are indirectly adjacent when there are no other second storage modules 207 between them but other structures are provided; the second storage module 207 adjacent to the first storage module 203 refers to the second storage module 207 that is closest to the first storage module 203; the second storage module 207 adjacent to the logic module 205 refers to the second storage module 207 that is closest to the logic module 205.

[0040] In some embodiments, an external circuit (e.g., a GPU / CPU) is also disposed on the substrate 201. The external circuit and the first storage module 203 are connected to the substrate 201 through an external interface, and the substrate 201 is then connected to a circuit board (not shown in the figure) through external pins. At this time, the logic module 205 is connected to power or ground through the storage module stack structure and the substrate 201. Furthermore, the logic module 205 obtains working instructions from the outside (external circuit) through the substrate 201 and the storage module stack structure, completes the corresponding work, and transmits the processing results out (to the external circuit) through the storage module stack structure and the substrate 201.

[0041] In some embodiments, a silicon interposer is disposed between the first storage module 203 and the substrate 201 to provide high-density electrical connections. External circuitry (e.g., GPU / CPU) is also disposed on the silicon interposer. The external circuitry and the first storage module 203 are connected to the silicon interposer through an external interface. The silicon interposer is then connected to external pins through the external interface and the substrate 201, and finally connected to a circuit board (not shown in the figure) through the external pins. At this time, the logic module 205 is connected to power and ground through the storage module stack structure and the silicon interposer. Further, the logic module 205 obtains working instructions from the outside (external circuitry) through the silicon interposer (or through the silicon interposer and the substrate 201), via the storage module stack structure, completes the corresponding work, and transmits the processing results out (to the external circuitry) via the storage module stack structure and through the silicon interposer (or through the silicon interposer and the substrate 201).

[0042] In some embodiments, the substrate 201 is made of one or more of silicon, silicon-germanium, germanium, silicon-on-insulator (SOI) film, and organic materials. In some embodiments, the first storage module 203 is Flash, RRAM, DRAM, MRAM, or SRAM, and the second storage module 207 is Flash, RRAM, DRAM, MRAM, or SRAM.

[0043] The structure shown in Figure 2 facilitates heat dissipation of the logic module 205 through the opposite side of the storage module stack structure by placing the logic module 205 on top of the storage module stack structure. This avoids the heat accumulation caused by the blockage of heat conduction in both the vertical and horizontal directions of the logic module when it is between the storage module stack structure and the substrate. Moreover, it can significantly reduce the impact of the heat generated by the logic module on the storage module.

[0044] As shown in Figure 3, a heat dissipation module 301 is provided on the logic module 205. The heat dissipation module 301 ensures that the large amount of heat generated by the logic module 205 during high-power operation is dissipated in a timely manner, thus significantly improving the power tolerance of the logic module. In some embodiments, the heat dissipation module 301 can be directly or indirectly disposed on the logic module 205. Generally speaking, the positional relationship between the storage module stack structure, the logic module 205, and the heat dissipation module 301 only needs to ensure that the high-power logic module 205 is closer to the top heat dissipation module 301 than the storage module stack structure. In some embodiments, the heat dissipation module 301 forms a conductive connection with the logic module 205, and the logic module 205 uses the heat dissipation module 301 to connect to power or ground. In some embodiments, the logic module 205 and the heat dissipation module 301 are directly connected. In some embodiments, the logic module 205 and the heat dissipation module 301 are connected through a conductive spacer layer.

[0045] Further, as shown in Figure 4, the three-dimensional stacked wafer includes three second storage modules 207. A first storage module 203 includes a first substrate and a first interconnect layer 401 disposed on one side of the first substrate. A logic module 205 includes a second substrate and a second interconnect layer 402 disposed on one side of the second substrate. Each second storage module 207 includes a third substrate and a third interconnect layer 403 and a fourth interconnect layer 404 disposed on both sides of the third substrate. The first interconnect layer 401 of the first storage module 203 is bonded to the fourth interconnect layer 404 of the adjacent second storage module 207, and the second interconnect layer 402 of the logic module 205 is bonded to the third interconnect layer 403 of the adjacent second storage module 207.

[0046] When one side of the second storage module 207 is adjacent to another second storage module 207, the third interconnect layer 403 of the second storage module 207 is bonded to the fourth interconnect layer 404 of the adjacent second storage module 207, or the fourth interconnect layer 401 of the second storage module 207 is bonded to the third interconnect layer 403 of the adjacent second storage module 207. When both sides of the second storage module 207 are adjacent to other second storage modules 207, the third interconnect layer 403 of the second storage module 207 is bonded to the fourth interconnect layer 404 of the other second storage module 207 adjacent on one side, and the fourth interconnect layer 404 of the second storage module 207 is bonded to the third interconnect layer 403 of the other second storage module 207 adjacent on the other side.

[0047] In some implementations, when one or more second storage modules 207 are removed and only the first storage module 203 remains, the first interconnect layer 401 of the first storage module 203 is bonded to the second interconnect layer 402 of the logic module 205.

[0048] In some embodiments, the first interconnect layer 401 includes an insulating layer and a conductive structure formed therein; the second interconnect layer 402 includes an insulating layer and a conductive structure formed therein; the third interconnect layer 403 includes an insulating layer and a conductive structure formed therein; and the fourth interconnect layer 404 includes an insulating layer and a conductive structure formed therein. In some embodiments, bonding refers to the chemical bonding of the insulating layers at the interface of the two interconnect layers and the physical interdiffusion of the conductive structures at the interface of the two interconnect layers, thereby forming an adhesive interface between the interconnect layers.

[0049] The storage module stack structure also includes multiple through-silicon vias (TSVs). Specifically, the first storage module 203 includes multiple first TSVs 405 penetrating the first substrate, each second storage module 207 includes multiple second TSVs 407 penetrating the third substrate, and the logic module 205 includes multiple third TSVs 409 penetrating the second substrate. In some embodiments, forming a first TSV includes forming a hole structure penetrating the first substrate and filling the hole structure with an insulating material and a conductive material; forming a second TSV includes forming a hole structure penetrating the third substrate and filling the hole structure with an insulating material and a conductive material; forming a third TSV includes forming a hole structure penetrating the second substrate and filling the hole structure with an insulating material and a conductive material.

[0050] Through the conductive structures in the first to fourth interconnect layers and the first and second silicon vias, the logic module 205 forms a conductive connection with the first storage module 203 and one or more second storage modules 207, and forms a conductive path in the storage module stack structure, enabling the logic module 205 to exchange data with the first storage module 203 and one or more second storage modules 207, and to exchange signals with the outside world through the storage module stack structure. In some embodiments, the logic module 205 is connected to the power supply through the conductive structures in the first to fourth interconnect layers and the first and second silicon vias, and connected to ground through a third silicon via and a heat dissipation module. In some embodiments, the logic module 205 is connected to ground through the conductive structures in the first to fourth interconnect layers and the first and second silicon vias, and connected to the power supply through a third silicon via and a heat dissipation module.

[0051] Figures 5A-5J are schematic diagrams of a method for fabricating a three-dimensional stacked wafer according to an embodiment of the present invention, and Figure 6 is a flowchart of an example method 600 for fabricating a three-dimensional stacked wafer. First, referring to Figures 5A-5C, the formation process of the first storage structure, logic structure, and second storage structure required for fabricating a three-dimensional stacked wafer will be explained.

[0052] Forming a first storage structure includes forming a first memory device and a first interconnect layer on a first substrate. As shown in FIG5A, a first memory device is formed on a first substrate 501, and a first interconnect layer 503 is formed on the first memory device. The first interconnect layer 503 includes an insulating layer 505 and a plurality of conductive structures 507 formed in the insulating layer 505. Obviously, the side containing the first interconnect layer 503 is the front side of the first storage structure, and the side opposite to the first interconnect layer 503 is the back side of the first storage structure. In some embodiments, the first memory device, in addition to having a storage function, can also implement a small amount of logic control functions. In some embodiments, forming the first storage structure further includes forming a conductive structure inserted into the first substrate according to a preset thinning amount of the first substrate.

[0053] Forming a logic structure includes: forming logic devices and a second interconnect layer on a second substrate. As shown in FIG5B, logic devices are formed on a second substrate 509, and then a second interconnect layer 511 is formed on the logic devices. The second interconnect layer 511 includes an insulating layer 513 and a plurality of conductive structures 515 formed in the insulating layer 513. Obviously, the side containing the second interconnect layer 511 is the front side of the logic structure, and the side opposite to the second interconnect layer 511 is the back side of the logic structure. In some embodiments, the logic devices can perform one or more of the following functions: operation, control, interface, and data processing. In some embodiments, forming a logic structure further includes: forming conductive structures inserted into the second substrate according to a preset thinning amount of the second substrate.

[0054] One or more (e.g., three) second storage structures are formed using a method similar to that used to form the first storage structure. Specifically, a second memory device and a third interconnect layer are formed on a third substrate to form the second storage structure. As shown in FIG5C, a second memory device is formed on a third substrate 519, and then a third interconnect layer 521 is formed on the second memory device. The third interconnect layer 521 includes an insulating layer 523 and a plurality of conductive structures 525 formed in the insulating layer 523. Obviously, the side containing the third interconnect layer 521 is the front side of the second storage structure, and the side opposite to the third interconnect layer 521 is the back side of the second storage structure. In some embodiments, at least some of the second memory devices, in addition to having storage functions, can also implement a small amount of logic control functions. In some embodiments, forming the second storage structure further includes: forming a conductive structure inserted into the third substrate according to a preset amount of thinning of the third substrate.

[0055] Example method 600 begins with operation 601, as shown in FIG. 6, by inverting the second storage structure, aligning the third interconnect layer and the second interconnect layer, and combining the second storage structure and the logic structure such that the second storage structure and the logic structure form a conductive connection through the third interconnect layer and the second interconnect layer. As shown in FIG. 5D, the second storage structure 526 and the logic structure 527 are combined in a face-to-face manner to form a bonding interface 528. Specifically, forming the bonding interface 528 includes: chemically bonding the insulating layer 523 in the third interconnect layer 521 to the insulating layer 513 in the second interconnect layer 511 at the interface, and physically diffusing the conductive structure 525 in the third interconnect layer 521 to the conductive structure 515 in the second interconnect layer 511 at the interface.

[0056] Example method 600 continues with operation 603, as shown in FIG. 6, by thinning the third substrate of the second storage structure to form a silicon via penetrating the thinned third substrate, and forming a fourth interconnect layer on the thinned third substrate to form a second storage module. As shown in FIG. 5E, the third substrate 519 of the second storage structure 526 is thinned to obtain a thinned substrate 529, and a silicon via 531 penetrating the substrate 529 is formed. A fourth interconnect layer 533 is further formed on the substrate 529, thereby forming a second storage module 534. The fourth interconnect layer 533 includes an insulating layer 535 and a plurality of conductive structures 537 formed in the insulating layer 535. Clearly, the surface where the fourth interconnect layer 533 is located is the back side of the second storage module 534. In some embodiments, the third substrate is thinned until the conductive structure previously inserted into the third substrate is exposed, and this conductive structure forms a silicon via penetrating the thinned third substrate.

[0057] In some embodiments, the insulating layer in the first to fourth interconnect layers is one or more layers of insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the formation process of the conductive structure in the first to fourth interconnect layers includes: first forming openings in the insulating layer, and then filling the desired openings with a conductive material. In some embodiments, the conductive material used to fabricate the conductive structure includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicides, or combinations thereof. In some embodiments, filling the openings with a conductive material can be performed using ALD, CVD, PVD, and / or other suitable methods.

[0058] Example method 600 continues from operation 605, as shown in Figure 6. Similar to operations 601 and 603, more second storage modules are sequentially stacked on top of the second storage module to obtain a first stacked structure containing the logic structure and multiple second storage modules. As shown in Figure 5F, second storage modules 536 and 538 are sequentially stacked on top of second storage module 534. Second storage modules 536 and 534 are bonded together in a face-to-back manner to form an adhesive interface 540. Specifically, the third interconnect layer 542 of the second storage module 536 is bonded to the fourth interconnect layer 533 of the second storage module 534. Second storage modules 538 and 536 are bonded together in a face-to-back manner to form an adhesive interface 544. Specifically, the third interconnect layer 548 of the second storage module 538 is bonded to the fourth interconnect layer 546 of the second storage module 536. Similar to the second storage module 534, the second storage module 536 has a silicon via 552 that penetrates the substrate 550, and the second storage module 538 has a silicon via 556 that penetrates the substrate 554.

[0059] Example method 600 continues with operation 607, as shown in FIG6, by inverting the first storage structure, aligning the first interconnect layer and the fourth interconnect layer, and combining the first storage structure and the second storage module, such that the first storage structure and the second storage module form a conductive connection through the first interconnect layer and the fourth interconnect layer. As shown in FIG5G, the first storage structure 558 and the second storage module 538 are combined in a face-to-back manner to form a bonding interface 560. Specifically, the first interconnect layer 503 of the first storage structure 558 is bonded to the fourth interconnect layer 562 of the second storage module 538.

[0060] In some implementations, example method 600 continues with operation 609, as shown in FIG6, by thinning the first substrate of the first storage structure to form silicon vias penetrating the thinned first substrate, thereby forming a first storage module; thinning the second substrate of the logic structure to form silicon vias penetrating the thinned second substrate, thereby forming a logic module; the logic module, multiple second storage modules, and the first storage module form a second stacked structure. That is, when forming the silicon vias of the first storage module and the logic module, the substrate is thinned. By connecting power or ground on the side opposite to the storage module stacked structure, the number of silicon vias that need to be set in the storage module stacked structure is significantly reduced. Therefore, by reasonably controlling the amount of substrate thinning of the first storage module and the logic module, as well as the amount of substrate thinning of the multiple second storage modules, the thickness of each substrate can meet both the process and design requirements of the corresponding structure for silicon vias and the need to provide sufficient support strength for the second stacked structure.

[0061] As shown in Figure 5H, the first substrate 501 of the first storage structure 558 is thinned to obtain a thinned substrate 561, and a silicon via 563 is formed through the substrate 561, thereby forming the first storage module 564; the second substrate 509 of the logic structure is thinned to obtain a thinned substrate 566, and a silicon via 568 is formed through the substrate 566, thereby forming the logic module 570.

[0062] In some embodiments, the first substrate is thinned until a conductive structure previously inserted into the first substrate is exposed, the conductive structure forming a silicon via through the thinned first substrate. In some embodiments, the second substrate is thinned until a conductive structure previously inserted into the second substrate is exposed, the conductive structure forming a silicon via through the thinned second substrate.

[0063] In some embodiments, example method 600 continues with operation 611, as shown in FIG6, forming silicon vias through a first substrate of a first storage structure to form a first storage module; thinning a second substrate of a logic structure to form silicon vias through the thinned second substrate to form a logic module; the logic module, multiple second storage modules, and the first storage module form a second stacked structure. That is, the substrate is not thinned when forming the silicon vias of the first storage module, but is only thinned when forming the silicon vias of the logic module. This is because the storage module can tolerate larger silicon via structures than the logic module, especially after connecting power or ground on the side opposite to the storage module stacked structure, which significantly reduces the number of silicon vias required in the storage module stacked structure, including the first storage module. This allows the substrate of the first storage module to have a greater thickness, thereby providing sufficient support strength for the second stacked structure. Correspondingly, the substrate of the logic module can achieve a sufficient thinning level to meet the process and design requirements of the silicon vias in the logic module.

[0064] As shown in Figure 5I, a silicon via 572 is formed through the first substrate 501, thereby forming the first storage module 574; the second substrate 509 of the logic structure is thinned to obtain a thinned substrate 576, and a silicon via 578 is formed through the substrate 576, thereby forming the logic module 580.

[0065] In some embodiments, the second substrate is thinned until the conductive structure previously inserted into the second substrate is exposed, the conductive structure forming a silicon via through the thinned second substrate.

[0066] Example method 600 continues with operation 613, as shown in FIG6, forming a conductive connection between the back side of the first storage module and the substrate. Taking the example of thinning the substrate when forming the silicon vias of both the first storage module and the logic module, as shown in FIG5J, a conductive connection is formed between the back side of the first storage module 564 and the substrate 582 through conductive bumps 584, and the other side of the substrate 582 is then connected to the circuit board through conductive bumps.

[0067] In some embodiments, the first storage module further includes an interconnect layer formed on its back side, through which the first storage module forms a conductive connection with the substrate.

[0068] In some embodiments, an external circuit is also provided on the substrate, and the external circuit is electrically connected to the first storage module through a conductive structure in the substrate.

[0069] In some embodiments, a silicon interposer is introduced, and the back side of the first storage module is electrically connected to the silicon interposer. The silicon interposer and the substrate are electrically connected through conductive protrusions, and the other side of the substrate is connected to the circuit board through conductive protrusions. In some embodiments, an external circuit is also disposed on the silicon interposer, and the external circuit is electrically connected to the first storage module through conductive structures in the silicon interposer and the substrate.

[0070] In some embodiments, a heat dissipation module is disposed on the back of the logic module, and the back of the logic module and the heat dissipation module are electrically connected. This heat dissipation module serves two purposes: firstly, it connects to the power supply or ground; secondly, it dissipates the large amount of heat generated by the logic module during high-power operation. In some embodiments, the logic module also includes an interconnect layer formed on its back, through which the logic module and the heat dissipation module are electrically connected. In some embodiments, the logic module and the heat dissipation module are directly connected. In some embodiments, the logic module and the heat dissipation module are connected through a conductive spacer layer.

[0071] In the above method, the step of forming one or more second storage structures can be omitted. Correspondingly, the first storage structure is inverted, and the first storage structure and the logic module are combined so that the first storage structure and the logic module form a conductive connection through the first interconnect layer and the second interconnect layer.

[0072] It should be noted that the above method for fabricating three-dimensional stacked wafers is merely exemplary and should not be used to limit the present invention. The steps and / or order of the above method can be adjusted according to actual needs to obtain the same or similar technical effects. For example, the processes of forming the first storage structure and forming the logic module are independent of each other and have no sequential order. Furthermore, the step of combining the second storage structure and the logic module can be performed after the fabrication of the first storage structure is completed or before the fabrication of the first storage structure is completed.

[0073] This invention places the storage module stack structure between the logic module and the substrate, placing the logic module on top of the storage module stack structure. This greatly facilitates heat dissipation for the logic module, as it is closer to the heat dissipation module than the storage module stack structure. This avoids the heat generated by the logic module affecting the storage module, significantly improving the power consumption tolerance of the logic module. Furthermore, the logic module connects to power or ground on the side opposite the storage module stack structure, avoiding the need for both power and ground to pass through the storage module stack structure. Therefore, it effectively reduces the number of conductive paths (silicon vias) required in the storage module stack structure.

[0074] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the described specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0075] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly defined.

[0076] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more (two or more) executable instructions for implementing a particular logical function or process. Furthermore, the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functionality involved.

[0077] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0078] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. All or part of the steps of the methods in the above embodiments can be performed by a program instructing related hardware, the program being stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiments.

[0079] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be read-only memory, a magnetic disk, or an optical disc, etc.

[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0081] 101: Substrate 103: Logic Module 105: Storage Module 201: Substrate 203: First storage module 205: Logic Module 207: Second storage module 301: Heat dissipation module 401: First Interconnect Layer 402: Second Interconnect Layer 409: Third silicon through-hole 403: Third Interconnect Layer 404: Fourth Interconnect Layer 405: First silicon through-hole 407: Second silicon through-hole 501: First substrate 503: First Interconnect Layer 505: Insulation layer 507: Conductive Structure 509: Second substrate 511: Second Interconnect Layer 513: Insulation layer 515: Conductive Structure 519: Third substrate 521: Third Interconnect Layer 523: Insulation layer 525: Conductive structure 526: Second storage structure 527: Logic Module 528: Adhesive Interface 529: Substrate 531:Through silicon via 533: Fourth Interconnect Layer 534: Second storage module 535: Insulation layer 536: Second storage module 537: Conductive Structure 538: Second storage module 540: Adhesive Interface 542: Third Interconnect Layer 544: Adhesive Interface 546: Quad Interconnect Layer 548: Third Interconnect Layer 550: Substrate 552:Through silicon via 556:Through silicon via 558: First storage structure 560: Adhesive Interface 561 (Fig. 5H): Substrate 562: Fourth Interconnect Layer 563:Through silicon via 564: First storage module 566: Substrate 568:Through silicon via 570: Logic Module 572:Through silicon via 574: First storage module 578:Through Silicon Via 580: Logic Module 582: Substrate 584: Conductive bump 600: Method 601:603:605:607:609:611:613: Operation

Claims

1. A three-dimensional stacked wafer, comprising a substrate, a first storage module, a logic module, and one or more stacked second storage modules; the first storage module and the logic module are sequentially stacked on the substrate, the first storage module being disposed between the logic module and the substrate; the one or more stacked second storage modules are disposed between the first storage module and the logic module, forming a storage module stack structure with the first storage module; the first storage module is used to provide and store data required by the logic module, supporting the logic module in completing corresponding tasks; the one or more stacked second storage modules are used to provide and store data required by the logic module, supporting the logic module in completing corresponding tasks; the logic module interacts with the outside world via the storage module stack structure and the substrate.

2. The three-dimensional stacked wafer as described in claim 1, wherein, The logic module is connected to a power source via the storage module stack structure and is connected to ground via the side opposite to the storage module stack structure.

3. The three-dimensional stacked wafer as described in claim 1, wherein, The logic module is connected to ground via the storage module stack structure and is connected to a power supply via the side opposite to the storage module stack structure.

4. The three-dimensional stacked wafer as described in claim 1, wherein, The logic module includes multiple stacked sub-logic modules. The first storage module and the second storage module of the one or more stacks are used to provide and store the data required by the multiple stacked sub-logic modules, supporting the multiple stacked sub-logic modules to complete the corresponding work.

5. The three-dimensional stacked wafer as described in claim 4, wherein, Among the plurality of sub-logic modules, the sub-logic modules that are closer to the storage module stack structure have lower power, while the sub-logic modules that are farther from the storage module stack structure have higher power.

6. The three-dimensional stacked wafer as described in claim 1, wherein, The first storage module is disposed directly or indirectly on the substrate, the one or more stacked second storage modules are disposed directly or indirectly on the first storage module as a whole, and the logic module is disposed directly or indirectly on the one or more stacked second storage modules.

7. The three-dimensional stacked wafer as claimed in any one of claims 1 to 6, further comprising an external circuit disposed on the substrate; the logic module obtains working instructions from the external circuit through the substrate and via the storage module stack structure, completes the corresponding work, and transmits the processing results through the storage module stack structure and via the substrate.

8. The three-dimensional stacked wafer as claimed in any one of claims 1 to 6, further comprising a silicon interposer and an external circuit, the silicon interposer being disposed between the first storage module and the substrate, and the external circuit being disposed on the silicon interposer; the logic module obtaining working instructions from the external circuit through the silicon interposer and via the storage module stack structure, completing the corresponding work, and transmitting the processing results through the storage module stack structure and via the silicon interposer.

9. The three-dimensional stacked wafer as claimed in any one of claims 1 to 6, further comprising a silicon interposer and an external circuit, the silicon interposer being disposed between the first storage module and the substrate, and the external circuit being disposed on the silicon interposer; the logic module obtaining operating instructions from the external circuit through the silicon interposer and the substrate, via the storage module stack structure, completing the corresponding work, and transmitting the processing results through the storage module stack structure, via the silicon interposer and the substrate.

10. The three-dimensional stacked wafer as claimed in any one of claims 1 to 6, further comprising a heat dissipation module, the heat dissipation module being disposed directly or indirectly on the logic module.

11. The three-dimensional stacked wafer as described in claim 10, wherein, The heat dissipation module forms a conductive connection with the logic module, and the logic module uses the heat dissipation module to connect to the power supply or ground.

12. The three-dimensional stacked wafer as described in claim 11, wherein, The logic module and the heat dissipation module are connected by a conductive spacer layer.

13. A method for fabricating a three-dimensional stacked wafer, comprising: A first stacked structure is formed; the first stacked structure includes a logic structure and one or more second storage modules stacked sequentially on the logic structure; a second stacked structure is formed using the first storage structure and the first stacked structure; the second stacked structure includes a first storage module and one or more second storage modules and a logic module stacked sequentially on the first storage module, wherein the first storage module is obtained by processing the first storage structure, and the logic module is obtained by processing the logic structure; the first storage module is connected to a substrate.

14. The method for fabricating a three-dimensional stacked wafer as described in claim 13, wherein, The first storage structure includes a first substrate and a first memory device and a first interconnect layer formed on the first substrate; Processing the first storage structure to obtain the first storage module includes: forming a silicon via through the first substrate of the first storage structure.

15. The method for fabricating a three-dimensional stacked wafer as described in claim 13, wherein, The first storage structure includes a first substrate and a first memory device and a first interconnect layer formed on the first substrate; Processing the first storage structure to obtain the first storage module includes: thinning the first substrate of the first storage structure to form a silicon via penetrating the thinned first substrate.

16. The method for fabricating a three-dimensional stacked wafer as described in claim 13, wherein, The logic structure includes a second substrate and a logic device and a second interconnect layer formed on the second substrate; Processing the logic structure to obtain the logic module includes: thinning the second substrate of the logic structure to form a silicon via penetrating the thinned second substrate.

17. A method for fabricating a three-dimensional stacked wafer as described in any one of claims 13 to 16, wherein, The second storage module includes: a thinned third substrate, a second memory device and a third interconnect layer formed on the third substrate, and a fourth interconnect layer formed on the back side of the thinned third substrate.

18. A method for fabricating a three-dimensional stacked wafer as described in any one of claims 13 to 16, further comprising: A heat dissipation module is provided on the logic module.

19. The method for fabricating a three-dimensional stacked wafer as described in claim 18, wherein, A conductive spacer layer and a heat dissipation module are sequentially disposed on the logic module. The logic module and the heat dissipation module are connected through the conductive spacer layer, so that the logic module can be connected to power or ground using the heat dissipation module.

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