Semiconductor structure and fabrication method thereof

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate having an active region, a shallow trench isolation structure disposed in the substrate, word lines embedded in the substrate, a first barrier layer, a power function control structure, and a capping layer. Each word line includes an active portion overlapping with a corresponding plurality of the active region and a through portion overlapping a corresponding plurality of the shallow trench isolation structure. The first barrier layer is disposed on the top surface of the active portion and the top surface of the through portion. The power function control structure is disposed on the top surface of the first barrier layer and the active portion. The capping layer includes a first portion and a second portion. The first portion is located above the active portion. The second portion is located above the through portion.

Claims

1. A semiconductor structure, comprising: The substrate has multiple active regions; Multiple shallow trench isolation structures are configured in the substrate; Multiple character lines are embedded in the substrate, wherein each of the multiple character lines includes multiple active portions overlapping a plurality of corresponding active regions and multiple through portions overlapping a plurality of corresponding active regions in the multiple shallow trench isolation structures; a first barrier layer is disposed on the top surface of the multiple active portions and the top surface of the multiple through portions; Multiple power function control structures are configured on the top surface of the first barrier layer and the multiple active components; The cover layer includes: a plurality of first portions located above the plurality of active portions; a plurality of second portions located above the plurality of through portions, wherein the plurality of second portions extend into the substrate for a length longer than the plurality of first portions extend into the substrate; and a second barrier layer disposed on the top surface of the plurality of power function control structures and the first barrier layer, wherein the cover layer is disposed above the second barrier layer.

2. The semiconductor structure as claimed in claim 1, wherein the plurality of second portions and the plurality of through portions are embedded in the plurality of shallow trench isolation structures.

3. The semiconductor structure of claim 2, wherein the plurality of shallow trench isolation structures includes an isolation material, and at least a portion of the plurality of shallow trench isolation structures further includes a filling layer, wherein the isolation material includes an oxide, and the filling layer includes a nitride.

4. The semiconductor structure as claimed in claim 1, wherein each of the plurality of power function control structures comprises a multilayer structure.

5. A method for manufacturing a semiconductor structure, comprising: A substrate with multiple active regions is provided, and multiple shallow trench isolation structures are embedded in the substrate; A plurality of character lines are formed in the substrate, wherein each of the plurality of character lines includes a plurality of active portions overlapping a plurality of corresponding active regions and a plurality of through portions overlapping a plurality of corresponding shallow trench isolation structures; a first barrier layer is formed on the top surface of the plurality of active portions and the top surface of the plurality of through portions; The functional control material layer is formed above the multiple character lines; Remove a portion of the work function control material layer above the plurality of through portions, wherein the remaining portion of the work function control material layer forms a plurality of work function control structures above the plurality of active portions; And forming a capping layer over the plurality of active portions and the plurality of through portions.

6. The manufacturing method as claimed in claim 5, wherein the cover layer comprises: Multiple first portions are located above the multiple active portions; And a plurality of second portions, located above the plurality of through portions, wherein the plurality of second portions extend into the substrate by a length longer than the plurality of first portions extend into the substrate.

7. The manufacturing method as described in claim 5, further comprising: A second barrier layer is formed on the top surface of the plurality of power function control structures and on the first barrier layer; And the capping layer is formed above the second barrier layer.

8. The manufacturing method as described in claim 5, further comprising: A cutting mask layer is formed on the power function control material layer, wherein the cutting mask layer includes a plurality of openings that overlap with the plurality of through portions, and the cutting mask layer is located directly above the plurality of active portions; And using the cutting mask layer as a mask to etch the power function control material layer.

9. The manufacturing method as claimed in claim 8, wherein each of the plurality of openings spans the plurality of character lines.

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