Semiconductor module

Abstract

This invention provides a semiconductor module capable of more accurate temperature detection. The semiconductor module of the present invention includes: first to fourth semiconductor elements Q1 to Q4; a plurality of wiring patterns; a first power supply terminal 51; second power supply terminals 52 and 53; a first midpoint terminal 61; and a second midpoint terminal 62. The semiconductor module 1 constitutes a full-bridge circuit. The semiconductor module 1 further includes: a temperature sensing element 90; first and second temperature sensing wiring patterns 93 and 94; and first and second temperature sensing terminals T1 and T2. The temperature sensing element 90 is disposed in the region surrounded by the first switching path A and the second switching path B. The semiconductor module 1 is configured to reduce noise generated based on the parasitic capacitance between the second wiring pattern 20 and the first temperature sensing wiring pattern 93, and based on the parasitic capacitance between the fourth wiring pattern 40 and the first temperature sensing wiring pattern 93.

Description

Technical Field

[0001] This invention relates to a semiconductor module. Prior Technology

[0002] Previously, in the field of semiconductor module technology, semiconductor modules equipped with temperature sensing elements (such as thermistors) were known (see Non-Patent Document 1).

[0003] As shown in Figure 14, the conventional semiconductor module 900 includes an inverter circuit 910 and further includes a thermistor 920 at its edge. According to the conventional semiconductor module 900, the temperature inside the semiconductor module 900 can be detected by the thermistor 920.

[0004] [Preliminary Technology Document][Non-Patent Document 1] Datasheet for IGBT Module T Series CM35MXUA-24T. <URL:https: / / www.mitsubishielectric.co.jp / semiconductors / powerdevices / datasheets / igbt / t_series / cm35mxua-24t_e.pdf>

[0005] However, in the field of semiconductor module technology, there is a demand for more accurate temperature monitoring within semiconductor modules. For example, semiconductor modules using wide-bandgap semiconductor elements (e.g., SiC semiconductor elements) tend to generate more heat and operate at higher temperatures due to their higher power consumption compared to semiconductor modules using silicon semiconductor elements. Therefore, more accurate temperature monitoring is required in semiconductor modules using wide-bandgap semiconductor elements. Furthermore, temperature control is a universally important technology in the semiconductor module technology field. Therefore, the benefits of more accurate temperature monitoring can also be obtained in semiconductor modules using silicon semiconductor elements.

[0006] Therefore, the present invention was made in view of the above-mentioned problems, and its object is to provide a semiconductor module that can perform temperature detection more accurately than the past. Summary of the Invention

[0007] [1] A semiconductor module according to one embodiment of the present invention includes: first to fourth semiconductor elements; a plurality of wiring patterns; a first power terminal; a second power terminal; a first midpoint terminal; and a second midpoint terminal, wherein the semiconductor module constitutes a full-bridge circuit with the first semiconductor element and the third semiconductor element as the high side and the second semiconductor element and the fourth semiconductor element as the low side, characterized in that it further includes: a temperature sensing element having a first temperature sensing electrode and a second temperature sensing electrode; a first temperature sensing wiring pattern connected to the first temperature sensing electrode; a first temperature sensing terminal for connecting to a temperature sensing circuit and connected to the first temperature sensing wiring pattern; a second temperature sensing wiring pattern connected to the second temperature sensing electrode; and a second temperature sensing terminal for connecting to ground or a control system power supply and connected to the second temperature sensing wiring pattern, wherein the first semiconductor element and the fourth semiconductor element are connected together When the current path during conduction is defined as a first switching path, comprising a first current path from the first power supply terminal to the first midpoint terminal and a second current path from the second midpoint terminal to the second power supply terminal; and when the current path during conduction of the third semiconductor element and the second semiconductor element is defined as a second switching path, comprising a third current path from the first power supply terminal to the second midpoint terminal and a fourth current path from the first midpoint terminal to the second power supply terminal, the temperature sensing element is disposed in the area surrounded by the first and second switching paths, and the semiconductor module is configured to reduce noise generated by the parasitic capacitance between the wiring pattern constituting the common portion of the first and fourth current paths and the first temperature sensing wiring pattern, and by the parasitic capacitance between the wiring pattern constituting the common portion of the second and third current paths and the first temperature sensing wiring pattern.

[0008] [2] Furthermore, in a semiconductor module according to one embodiment of the present invention, the plurality of wiring patterns include: a first wiring pattern that mounts the first semiconductor element and is connected to the first power terminal; a second wiring pattern that mounts the second semiconductor element and is connected to the first midpoint terminal; a third wiring pattern that mounts the third semiconductor element and is connected to the first power terminal; and a fourth wiring pattern that mounts the fourth semiconductor element and is connected to the second midpoint terminal, wherein, when the semiconductor module is viewed from above, the first temperature detection wiring pattern is disposed between the second wiring pattern and the fourth wiring pattern.

[0009] [3] In addition, in a semiconductor module of one embodiment of the present invention (the semiconductor module of [2] above), it is preferable that the distance between the first temperature detection wiring pattern and the second wiring pattern is equal to the distance between the first temperature detection wiring pattern and the fourth wiring pattern.

[0010] [4] Furthermore, in a semiconductor module of one embodiment of the present invention (the semiconductor module of [2] above), it is preferable that the second power terminal is a terminal for connection with the ground, and the plurality of wiring patterns further include a fifth wiring pattern connected to the second power terminal, the fifth wiring pattern having an extension extending in the direction in which the first temperature detection wiring pattern is disposed.

[0011] [5] Furthermore, in a semiconductor module according to one embodiment of the present invention (the semiconductor module of [2] above), the second temperature detection wiring pattern is disposed between the first temperature detection wiring pattern and the second wiring pattern, or between the first temperature detection wiring pattern and the fourth wiring pattern. The semiconductor module further includes a capacitive coupling reduction wiring pattern disposed between the first temperature detection wiring pattern and the second wiring pattern and between the first temperature detection wiring pattern and the fourth wiring pattern on the side where the second temperature detection wiring pattern is not disposed.

[0012] [6] In addition, in a semiconductor module of one embodiment of the present invention (the semiconductor module of [5] above), it is preferable that the capacitive coupling reduces the wiring pattern and the ground connection.

[0013] [7] Furthermore, in a semiconductor module of one embodiment of the present invention (the semiconductor module of [6] above), it is preferred that the second power terminal is a terminal for connection to the ground, and the plurality of wiring patterns further include a fifth wiring pattern connected to the second power terminal, and the capacitive coupling reduction wiring pattern is connected to the fifth wiring pattern.

[0014] [8] Furthermore, in a semiconductor module of one embodiment of the present invention (the semiconductor module of [2] above), when the semiconductor module is viewed from above, the first temperature detection wiring pattern and the first temperature detection terminal are arranged at a position overlapping with a predetermined axis of symmetry. At least a portion of the first temperature detection terminal and the first temperature detection wiring pattern have a shape that is linearly symmetrical about the predetermined axis of symmetry. The structure formed by the first to fourth semiconductor elements, the first to fourth wiring patterns, the first power terminal, the second power terminal, the first midpoint terminal, and the second midpoint terminal, which are constituent elements of the semiconductor module, is symmetrical about the predetermined axis of symmetry.

[0015] [Invention Effects]

[0016] In the semiconductor module of the present invention, the temperature sensing element is disposed in a region close to the semiconductor element, which serves as a heat source, and surrounded by the first and second switching paths in the full-bridge circuit. Therefore, the semiconductor module of the present invention can perform temperature detection more accurately than before.

[0017] Furthermore, the semiconductor module of the present invention is configured to reduce noise generated based on the parasitic capacitance between the wiring pattern constituting the common portion of the first current path and the fourth current path and the first temperature sensing wiring pattern, and based on the parasitic capacitance between the wiring pattern constituting the common portion of the second current path and the third current path and the first temperature sensing wiring pattern. Therefore, according to the semiconductor module of the present invention, the parasitic capacitance between the first temperature sensing wiring pattern and the first current path on the first switching path, and the parasitic capacitance between the first temperature sensing wiring pattern and the second current path on the first switching path are balanced, thereby reducing noise generated during switching. Additionally, according to the semiconductor module of the present invention, the parasitic capacitance between the first temperature sensing wiring pattern and the third current path on the second switching path, and the parasitic capacitance between the first temperature sensing wiring pattern and the fourth current path on the second switching path are balanced, thereby reducing noise generated during switching. Thus, the semiconductor module of the present invention provides a semiconductor module with a stable output voltage for the temperature sensing element, enabling more stable temperature sensing. Simple Explanation of the Diagram

[0018] Figure 1 is a plan view of the internal structure of the semiconductor module 1 according to Embodiment 1. In Figure 1, to show the internal structure of the semiconductor module 1, only the outer edge of the sealing material M is shown, and the parts overlapping with other components are not shown. The same applies to the top view of other internal structures, the explanatory diagram of current paths, and the enlarged view of the main parts described later.

[0019] Figure 2 is an enlarged view of the main part of Figure 1.

[0020] Figure 3 is an equivalent circuit diagram of semiconductor module 1 in embodiment 1.

[0021] Figure 4 is an explanatory diagram of the current path of the semiconductor module 1 according to Embodiment 1. Additionally, Figure 4 shows an addition of a current path to the semiconductor module 1 shown in Figure 1; the structure of the semiconductor module in Figure 4 is the same as that in Figure 1. However, in Figure 4, the symbols representing the constituent elements shown in Figure 2 are omitted, and mainly the symbols of the constituent elements required to explain the current path are shown.

[0022] Figure 5 is a plan view of the internal structure of the semiconductor module 2 in Embodiment 2.

[0023] Figure 6 is an enlarged view of the main part of Figure 5.

[0024] Figure 7 is a plan view of the internal structure of the semiconductor module 3 in Embodiment 3.

[0025] Figure 8 is an enlarged view of the main part in Figure 7;

[0026] Figure 9 is a plan view of the internal structure of the semiconductor module 4 in Embodiment 4.

[0027] Figure 10 is an enlarged view of the main part of Figure 9.

[0028] Figure 11 is a plan view of the internal structure of the semiconductor module 1A of the comparative example.

[0029] Figure 12 is an illustration of the current path of the semiconductor module 1A in the comparative example.

[0030] Figure 13 is a graph showing the noise characteristics of the semiconductor module 3 according to Embodiment 3 and the semiconductor module 1A according to the comparative example. In Figure 13, the upper, middle, and lower graphs are arranged vertically to make the horizontal axis (time) of each graph consistent. The upper graph (the graph marked "Q2") shows the changes in voltage V and current I of the second semiconductor element Q2 when the full-bridge circuit is activated. The middle graph (the graph marked "Q4") shows the changes in voltage V and current I of the fourth semiconductor element Q4 when the full-bridge circuit 100 is activated. The lower graph (the curve marked "1A" and "1") shows the voltage change of the first temperature detection path TP1 when the full-bridge circuit is activated. In addition, the lower graph is divided into two graphs. The graph marked "1A" shows the voltage changes in the semiconductor module 1A of the comparative example. The graph marked with a "3" represents the voltage variation of the semiconductor module 3 in Embodiment 3. The voltage value is displayed on the left side of each graph, and the current value is displayed on the right side of the upper and lower graphs.

[0031] Figure 14 is the equivalent circuit diagram of the previous semiconductor module 900. Implementation

[0032] The semiconductor module of the present invention will now be described with reference to the embodiments shown in the accompanying drawings. In the embodiments described below, common reference numerals are used for constituent elements having exactly the same or substantially the same function, even if they differ to some extent in shape, and descriptions already provided are sometimes omitted. The embodiments described below do not limit the invention to the scope of the claims. Furthermore, not all elements and combinations thereof described in the embodiments are necessary for the solutions of the present invention.

[0033] [Implementation Method 1]

[0034] 1. Structure of Semiconductor Module 1

[0035] Embodiment 1: Semiconductor module 1, as shown in Figures 1 and 2, includes first to fourth semiconductor elements Q1 to Q4, multiple wiring patterns, a first power supply terminal 51, second power supply terminals 52 and 53, a first midpoint terminal 61, and a second midpoint terminal 62. The multiple wiring patterns include first to fifth wiring patterns 10 to 50 through which a main current (high current) flows. In semiconductor module 1, a full-bridge circuit 100 (see Figure 3) is configured with the first semiconductor element Q1 and the third semiconductor element Q3 on the high side and the second semiconductor element Q2 and the fourth semiconductor element Q4 on the low side. The full-bridge circuit 100 will be described later.

[0036] The semiconductor module 1 further includes a substrate 70, a temperature sensing element 90, other wiring patterns, other terminals, and a sealing material M. The other wiring patterns include first and second temperature sensing wiring patterns 93 and 94, first to fourth control wiring patterns 111 to 114, and first to fourth detection wiring patterns 121 to 124. Furthermore, the other terminals include first and second temperature sensing terminals T1 and T2, first to fourth control terminals T11 to T14, and first to fourth detection terminals T21 to T24.

[0037] The following explains each of the above-mentioned components.

[0038] In semiconductor module 1, the first to fourth semiconductor elements Q1 to Q4 are metal-oxide-semiconductor field-effect transistors (MOSFETs). The first to fourth semiconductor elements Q1 to Q4 have a source electrode S, a drain electrode D, and a gate electrode G, respectively.

[0039] When the first to fourth semiconductor elements Q1 to Q4 are vertical transistor elements, the drain electrode D exists on the surface of the first to fourth wiring patterns 10 to 40 of the first to fourth semiconductor elements Q1 to Q4. In semiconductor module 1, the case where the first to fourth semiconductor elements Q1 to Q4 are vertical transistor elements is illustrated. Therefore, as shown in FIG1, since the drain electrode D is not visible when semiconductor module 1 is viewed from above, the symbol "D" representing the drain electrode is not shown in the figures. In addition, the gate electrode G exists on the surface of the first to fourth semiconductor elements Q1 to Q4 on the source electrode S side.

[0040] Furthermore, the first to fourth semiconductor elements Q1 to Q4 can be appropriately modified as long as they do not change the spirit of the present invention. The first to fourth semiconductor elements Q1 to Q4 are not limited to MOSFETs, but can also be other semiconductor elements such as IGBTs (insulated gate bipolar transistors).

[0041] Furthermore, the first to fourth semiconductor elements Q1 to Q4 can be, for example, lateral transistor elements (e.g., GaN-HEMTs made of GaN-conducting Si materials, or other compound semiconductor transistor elements made of Ga2O3-conducting Si materials). Moreover, the first to fourth semiconductor elements Q1 to Q4 are not limited to transistor elements; they can also be modified configurations where transistor elements are appropriately replaced with diode elements corresponding to the circuit APP. If such a modified structure is adopted, the present invention can also be appropriately applied to totem-pole type bridgeless PFC circuits, etc.

[0042] The source electrode S of the first semiconductor element Q1 is connected to the second wiring pattern 20 via the first connecting member 81. The first connecting member 81 and the second to fourth connecting members 82 to 84 (described later) can, for example, be components made of aluminum wire. The drain electrode D of the first semiconductor element Q1 is connected to the first wiring pattern 10.

[0043] The source electrode S of the second semiconductor element Q2 is connected to the fifth wiring pattern 50 via the second connection member 82. The drain electrode D of the second semiconductor element Q2 is connected to the second wiring pattern 20.

[0044] The source electrode S of the third semiconductor element Q3 is connected to the fourth wiring pattern 40 via the third connection member 83. Additionally, the drain electrode D of the third semiconductor element Q3 is connected to the third wiring pattern 30.

[0045] The source electrode S of the fourth semiconductor element Q4 is connected to the fifth wiring pattern 50 via the fourth connection member 84. The drain electrode D of the fourth semiconductor element Q4 is connected to the fourth wiring pattern 40.

[0046] The first to fifth wiring patterns 10 to 50 in semiconductor module 1 are made of conductive material disposed or formed on the substrate of substrate 70. In addition, the other wiring patterns described later are the same as the first to fifth wiring patterns 10 to 50 in that the conductive material disposed or formed on the substrate of substrate 70 is the same.

[0047] In semiconductor module 1, a DCB (Direct Copper Bonding) substrate, in which metal (copper) is directly bonded to a substrate formed of ceramic (alumina, aluminum nitride, silicon nitride, etc.), is suitable as substrate 70.

[0048] Furthermore, the substrate in the semiconductor module of the present invention is not limited to a DCB substrate. Other ceramic substrates, copper substrates, or aluminum substrates, such as AMB (Active Metal Brazing) substrates, can also be used as substrates. In addition, metals other than copper (e.g., aluminum) can be used as materials for the multiple wiring patterns.

[0049] The first wiring pattern 10 houses a first semiconductor element Q1, and a first power supply terminal 51 is connected to the first wiring pattern 10. The second wiring pattern 20 houses a second semiconductor element Q2 and is connected to a first midpoint terminal 61. The third wiring pattern 30 houses a third semiconductor element Q3 and is connected to a first power supply terminal 51. The fourth wiring pattern 40 houses a fourth semiconductor element Q4 and is connected to a second midpoint terminal 62. The fifth wiring pattern 50 is connected to second power supply terminals 52 and 53.

[0050] The fifth wiring pattern 50 has an extension E extending in the direction in which the first temperature detection wiring pattern 93 is configured.

[0051] The first power supply terminal 51 and the second power supply terminals 52 and 53 are used to supply power to the full-bridge circuit. In the semiconductor module 1, it is assumed that the first power supply terminal 51 is the current input side (high voltage side) and the second power supply terminal 52 is the current output side (ground side).

[0052] The first power terminal 51 is a generally T-shaped component branching from the inner lead portion (the portion existing inside the sealing material M). The first power terminal 51 crosses the fifth wiring pattern 50 in a non-contact manner and is connected to the first wiring pattern 10 and the third wiring pattern 30.

[0053] The second power terminals 52 and 53 are respectively connected to the fifth wiring pattern 50. The second power terminals 52 and 53 are configured to sandwich the first power terminal 51. As described above, the second power terminals 52 and 53 are suitable for connection to a ground (not shown) terminal.

[0054] The first midpoint terminal 61 and the second midpoint terminal 62 are terminals connected to loads (not shown). The first midpoint terminal 61 is connected to the second wiring pattern 20, and the second midpoint terminal 62 is connected to the fourth wiring pattern 40.

[0055] The temperature sensing element 90 has a first temperature sensing electrode 91 and a second temperature sensing electrode 92, disposed in a region surrounded by a first switching path A and a second switching path B. The first and second switching paths A and B will be described later in the section concerning the full-bridge circuit 100 and current paths. In this specification, "temperature sensing element" refers to an element whose electrical characteristics (e.g., resistance) change with temperature. A thermistor may be suitable for use as the temperature sensing element 90.

[0056] The first temperature detection wiring pattern 93 is connected to the first temperature detection electrode 91. The second temperature detection wiring pattern 94 is connected to the second temperature detection electrode 92. In the semiconductor module 1, the second temperature detection wiring pattern 94 is disposed between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40.

[0057] The semiconductor module 1 is configured to reduce noise generated by parasitic capacitance between the wiring patterns constituting the common portion of the first current path P1 and the fourth current path P4 and the first temperature sensing wiring pattern 93, as well as by parasitic capacitance between the wiring patterns constituting the common portion of the second current path P2 and the third current path P3 and the first temperature sensing wiring pattern 93. To reduce noise generated by these two parasitic capacitances, "balancing the two parasitic capacitances" and "reducing the parasitic capacitance itself" become crucial.

[0058] As described below, in semiconductor module 1, the wiring pattern constituting the common portion of the first current path P1 and the fourth current path P4 is the second wiring pattern 20, and the wiring pattern constituting the common portion of the second current path P2 and the third current path P3 is the fourth wiring pattern. In semiconductor module 1, when viewed from above, the first temperature sensing wiring pattern 93 is disposed between the second wiring pattern 20 and the fourth wiring pattern 40.

[0059] Furthermore, in semiconductor module 1, the distance between the first temperature sensing wiring pattern 93 and the second wiring pattern 20 is equal to the distance between the first temperature sensing wiring pattern 93 and the fourth wiring pattern 40. In this specification, "equal distances" refers to the distances (shortest distances) being equal during the design phase. Therefore, in actual products, even if there is a difference between the two distances mentioned above, or a difference caused by undesirable events such as manufacturing errors, it can still be evaluated as substantially "equal distances".

[0060] The first temperature detection terminal T1 is used to connect to a temperature detection circuit (not shown), and it is connected to the first temperature detection wiring pattern 93. In this specification, "temperature detection circuit" refers to a circuit that includes a temperature detection element and is capable of detecting temperature based on changes in the electrical characteristics of that temperature detection element.

[0061] The second temperature sensing terminal T2 is for connection to ground or a control system power supply (not shown), and it is connected to the second temperature sensing wiring pattern 94. Here, "control system power supply" refers to a power supply device that provides power for operating the temperature sensing circuit. This control system power supply is different from the power supply (main power) that supplies power to the first and second power terminals. This control system power supply can also supply power to circuits and devices other than the temperature sensing circuit.

[0062] The first to fourth control wiring patterns 111 to 114 are respectively connected to the gate electrodes G of the first to fourth semiconductor elements Q1 to Q4 via connecting components such as aluminum wires. Furthermore, the first to fourth control wiring patterns 111 to 114 are respectively connected to the corresponding first to fourth control terminals T11 to T14. Therefore, it can be said that the gate electrodes G of the first to fourth semiconductor elements Q1 to Q4 are respectively connected to the first to fourth control terminals T11 to T14.

[0063] The first to fourth detection wiring patterns 121 to 124 are respectively connected to the source electrodes S of the first to fourth semiconductor elements Q1 to Q4 via connecting components such as aluminum wires. Furthermore, corresponding first to fourth detection terminals T21 to T24 are connected to the first to fourth detection wiring patterns 121 to 124. Therefore, it can be said that the source electrodes S of the first to fourth semiconductor elements Q1 to Q4 are also connected to the first to fourth detection terminals T21 to T24.

[0064] The sealing material M seals the first to fourth semiconductor elements Q1 to Q4, multiple wiring patterns, and temperature sensing element 90, and also seals the internal leads of the first power terminal 51, the second power terminals 52 and 53, the first midpoint terminal 61, the second midpoint terminal 62, the first temperature sensing terminal T1, and the second temperature sensing terminal T2. The sealing material M is, for example, made of resin.

[0065] Here, the shape and arrangement of the constituent elements in the semiconductor module 1 will be described. When viewed from above, the first temperature sensing wiring pattern 93 and the first temperature sensing terminal T1 are arranged at a position overlapping a predetermined axis of symmetry C. Furthermore, at least a portion of the first temperature sensing terminal T1 and the first temperature sensing wiring pattern 93 have a shape that is linearly symmetrical about the predetermined axis of symmetry C. The first temperature sensing terminal T1 in the semiconductor module 1 as a whole has a shape that is linearly symmetrical about the predetermined axis of symmetry C. Additionally, if only a portion of the first temperature sensing terminal T1 has a shape that is linearly symmetrical about the predetermined axis of symmetry C, it is preferable that this portion includes a portion connected to the first temperature sensing wiring pattern 93 of the first temperature sensing terminal T1, and more preferably, it includes an inner lead portion.

[0066] Furthermore, the structure formed by the first to fourth semiconductor elements Q1 to Q4, the first to fourth wiring patterns 10 to 40, the first power terminal 51, the second power terminals 52 and 53, the first midpoint terminal 61, and the second midpoint terminal 62, which are components of the semiconductor module 1, is symmetrical about a predetermined axis of symmetry C. Additionally, in the semiconductor module 1, the structure formed by the fifth wiring pattern 50, the substrate 70, the first to fourth control wiring patterns 111 to 114, the first to fourth detection wiring patterns 121 to 124, the first to fourth control terminals T11 to T14, the first to fourth detection terminals T21 to T214, and the sealing material M is also symmetrical about a predetermined axis of symmetry C.

[0067] 2. Full-bridge circuit 100 and current path in semiconductor module 1

[0068] Here, the full-bridge circuit 100 and current path of semiconductor module 1 will be described. In semiconductor module 1, as shown in Figures 3 and 4, a full-bridge circuit 100 is configured to exclusively form a first switching path A and a second switching path B through switching operations. In Figures 3 and 4, the first switching path A is indicated by a solid arrow, while the second switching path B is indicated by a dashed arrow.

[0069] In the full-bridge circuit 100 of semiconductor module 1, the first semiconductor element Q1 and the third semiconductor element Q3 are set as high sides, and the second semiconductor element Q2 and the fourth semiconductor element Q4 are set as low sides. In such a full-bridge circuit, the operation of both the first semiconductor element Q1 and the fourth semiconductor element Q4 being turned on and the operation of both the third semiconductor element Q3 and the second semiconductor element Q2 being turned on are alternately repeated.

[0070] Furthermore, when both the first semiconductor element Q1 and the fourth semiconductor element Q4 are turned on, both the third semiconductor element Q3 and the second semiconductor element Q2 are turned off; conversely, when both the third semiconductor element Q3 and the second semiconductor element Q2 are turned on, both the first semiconductor element Q1 and the fourth semiconductor element Q4 are turned off. The description of semiconductor element turn-off is omitted in the following explanation.

[0071] The first switching path A, as shown by the solid arrows in Figures 3 and 4, is the current path when both the first semiconductor element Q1 and the fourth semiconductor element Q4 are conducting. The first switching path A includes a first current path P1 from the first power terminal 51 to the first midpoint terminal 61 and a second current path P2 from the second midpoint terminal 62 to the second power terminals 52 and 53. The first current path P1 flows through the first power terminal 51, the first wiring pattern 10, the first semiconductor element Q1, the second wiring pattern 20, and the first midpoint terminal 61. The second current path P2 flows through the second midpoint terminal 62, the fourth wiring pattern 40, the fourth semiconductor element Q4, the fifth wiring pattern 50, and the second power terminals 52 and 53. However, in Figure 4, the second current path P2 is shown as flowing through the second power terminal 53 but not through the second power terminal 52; this representation is for the purpose of avoiding unnecessary complexity in the figures. In fact, the second current path P2 flows through both the second power supply terminals 52 and 53.

[0072] Additionally, the second switching path B, as shown by the dashed arrows in Figures 3 and 4, is the current path when both the third semiconductor element Q3 and the second semiconductor element Q2 are conducting. The second switching path B includes a third current path P3 from the first power terminal 51 to the second midpoint terminal 62 and a fourth current path P4 from the first midpoint terminal 61 to the second power terminals 52 and 53. The third current path P3 flows through the first power terminal 51, the third wiring pattern 30, the third semiconductor element Q3, the fourth wiring pattern 40, and the second midpoint terminal 62. Similarly, the fourth current path P4 flows through the first midpoint terminal 61, the second wiring pattern 20, the second semiconductor element Q2, the fifth wiring pattern 50, and the second power terminals 52 and 53. However, in Figure 4, the fourth current path P4 is shown as flowing through the second power terminal 52 but not through the second power terminal 53; this representation is for the purpose of avoiding unnecessary complexity in the figures. In fact, the fourth current path P4 flows through both the second power supply terminals 52 and 53.

[0073] Therefore, in semiconductor module 1, the wiring pattern that "constitutes the common portion of the first current path P1 and the fourth current path P4" that causes parasitic capacitance problems with the first temperature sensing wiring pattern 93 is the second wiring pattern 20 (see Figure 4). Additionally, in semiconductor module 1, the wiring pattern that "constitutes the common portion of the second current path P2 and the third current path P3" that causes parasitic capacitance problems with the first temperature sensing wiring pattern 93 is the fourth wiring pattern.

[0074] 3. Effects of Semiconductor Module 1 in Implementation Method 1

[0075] In the semiconductor module 1 of Embodiment 1, the temperature sensing element 90 is disposed in a region surrounded by the first switching path A and the second switching path B in the full-bridge circuit 100, and close to the semiconductor elements (second semiconductor element Q2 and fourth semiconductor element Q4) that serve as heat sources. Therefore, the semiconductor module 1 of Embodiment 1 is a semiconductor module capable of performing temperature detection more accurately than before.

[0076] Furthermore, the semiconductor module 1 in Embodiment 1 is configured to reduce noise generated based on the parasitic capacitance between the wiring pattern (second wiring pattern 20) constituting the common portion of the first current path P1 and the fourth current path P4 and the first temperature sensing wiring pattern 93, and based on the parasitic capacitance between the wiring pattern (fourth wiring pattern 40) constituting the common portion of the second current path P2 and the third current path P3 and the first temperature sensing wiring pattern 93. Therefore, according to the semiconductor module 1 of Embodiment 1, the parasitic capacitance between the first temperature sensing wiring pattern 93 and the first current path P1 on the first switching path A, and the parasitic capacitance between the first temperature sensing wiring pattern 93 and the second current path P2 on the first switching path A are balanced, thereby reducing noise generated during switching. Furthermore, according to the semiconductor module 1 of Embodiment 1, the parasitic capacitance between the first temperature sensing wiring pattern 93 and the third current path P3 on the second switching path B, and the parasitic capacitance between the first temperature sensing wiring pattern 93 and the fourth current path P4 on the second switching path B are balanced, thereby reducing noise generated during switching. Thus, the semiconductor module 1 of Embodiment 1 is a semiconductor module with a stable output voltage of the temperature sensing element 90 and capable of more stable temperature sensing.

[0077] Furthermore, in the semiconductor module 1 of Embodiment 1, when viewed from above, the first temperature sensing wiring pattern 93 is disposed between the second wiring pattern 20 and the fourth wiring pattern 40. Therefore, in the semiconductor module 1 of Embodiment 1, it is easy to achieve a balance between the parasitic capacitance between the first temperature sensing wiring pattern 93 and the first current path P1 on the first switching path A, and between the first temperature sensing wiring pattern 93 and the second current path P2 on the first switching path A. Furthermore, in the semiconductor module 1 of Embodiment 1, it is also easy to achieve a balance between the parasitic capacitance between the first temperature sensing wiring pattern 93 and the third current path P3 on the second switching path B, and between the first temperature sensing wiring pattern 93 and the fourth current path P4 on the second switching path B. Therefore, according to the semiconductor module 1 of Embodiment 1, noise generated during switching can be further reduced, the output voltage of the temperature sensing element 90 can be made more stable, and temperature sensing can be performed more stably.

[0078] Furthermore, in the semiconductor module 1 of Embodiment 1, the distance between the first temperature sensing wiring pattern 93 and the second wiring pattern 20 is equal to the distance between the first temperature sensing wiring pattern 93 and the fourth wiring pattern 40. Therefore, according to the semiconductor module 1 of Embodiment 1, it is easier to achieve a balance between the parasitic capacitance between the first temperature sensing wiring pattern 93 and the first current path P1 on the first switching path A, and between the first temperature sensing wiring pattern 93 and the second current path P2 on the first switching path A. Moreover, according to the semiconductor module 1 of Embodiment 1, it is easier to achieve a balance between the parasitic capacitance between the first temperature sensing wiring pattern 93 and the third current path P3 on the second switching path B, and between the first temperature sensing wiring pattern 93 and the fourth current path P4 on the second switching path B.

[0079] Furthermore, in the semiconductor module 1 of Embodiment 1, the second power terminals 52 and 53 are terminals for grounding, and the plurality of wiring patterns include a fifth wiring pattern 50 connected to the second power terminals 52 and 53. The fifth wiring pattern 50 has an extension E extending in the direction in which the first temperature sensing wiring pattern 93 is disposed. Therefore, according to the semiconductor module 1 of Embodiment 1, by bringing the grounded fifth wiring pattern 50 close to the first temperature sensing wiring pattern 93, the parasitic capacitance generated around the first temperature sensing wiring pattern 93 can be reduced.

[0080] Furthermore, in the semiconductor module 1 of Embodiment 1, when viewed from above, the first temperature sensing wiring pattern 93 and the first temperature sensing terminal T1 are arranged at a position overlapping a predetermined axis of symmetry C. Additionally, in the semiconductor module 1 of Embodiment 1, at least a portion of the first temperature sensing terminal T1 and the first temperature sensing wiring pattern 93 have a shape that is linearly symmetrical about the predetermined axis of symmetry C. Furthermore, in the semiconductor module 1 of Embodiment 1, the structure comprises the first to fourth semiconductor elements Q1 to Q4, the first to fourth wiring patterns 10 to 40, the first power terminal 51, the second power terminals 52 and 53, the first midpoint terminal 61, and the second midpoint terminal 62. Therefore, according to the semiconductor module 1 of Embodiment 1, by making the shapes of the first switching path A and the second switching path B approximately linearly symmetrical, it is easier to achieve a balance of the parasitic capacitance generated around the first temperature sensing wiring pattern 93.

[0081] [Implementation Method 2]

[0082] Embodiment 2 semiconductor module 2 has basically the same structure as semiconductor module 1 of Embodiment 1, but differs from semiconductor module 1 of Embodiment 1 in that it further incorporates capacitive coupling to reduce wiring patterns. Hereinafter, semiconductor module 2 will be described focusing on the differences from semiconductor module 1.

[0083] As shown in Figures 5 and 6, the semiconductor module 2 includes a capacitive coupling reduction wiring pattern 97. The capacitive coupling reduction wiring pattern 97 is disposed between the first temperature sensing wiring pattern 93 and the second wiring pattern 20, and between the first temperature sensing wiring pattern 93 and the fourth wiring pattern 40, on the side where the second temperature sensing wiring pattern 94 is not disposed. In the semiconductor module 2, the second temperature sensing wiring pattern 94 is disposed between the first temperature sensing wiring pattern 93 and the fourth wiring pattern 40. Therefore, the capacitive coupling reduction wiring pattern 97 in the semiconductor module 2 is disposed between the first temperature sensing wiring pattern 93 and the second wiring pattern 20.

[0084] Furthermore, although the illustration is omitted, semiconductor module 2 is configured with the same full-bridge circuit 100 as semiconductor module 1, and in use, it forms the same first switch path A and second switch path B as semiconductor module 1. The full-bridge circuit 100, the first switch path A, and the second switch path B are also the same in semiconductor modules 3 and 4, which will be described later.

[0085] Although the semiconductor module 2 of Embodiment 2 differs from the semiconductor module 1 of Embodiment 1 in that it further incorporates capacitive coupling to reduce wiring patterns, the temperature sensing element 90 is disposed in a region surrounded by the first switching path A and the second switching path B in the full-bridge circuit 100, and close to the semiconductor elements (second semiconductor element Q2 and fourth semiconductor element Q4) that serve as heat sources. Therefore, the semiconductor module 2 of Embodiment 2, like the semiconductor module 1 of Embodiment 1, is a semiconductor module capable of more accurate temperature sensing compared to the conventional one.

[0086] Furthermore, the semiconductor module 2 of Embodiment 2 includes a capacitive coupling reduction wiring pattern 97 disposed between the first temperature sensing wiring pattern 93 and the second wiring pattern 20, and between the first temperature sensing wiring pattern 93 and the fourth wiring pattern 40, on the side where the second temperature sensing wiring pattern 94 is not disposed. According to the semiconductor module 2 of Embodiment 2, as shown in the embodiments described later, the presence of the capacitive coupling reduction wiring pattern 97 can reduce the parasitic capacitance generated around the first temperature sensing wiring pattern 93.

[0087] Furthermore, since the semiconductor module 2 of Embodiment 2 has all the structures of the semiconductor module 1 of Embodiment 1, it also has the same effects as the semiconductor module 1 of Embodiment 1.

[0088] [Implementation Method 3]

[0089] The semiconductor module 3 of Embodiment 3 has basically the same structure as the semiconductor module 2 of Embodiment 2, but differs from the semiconductor module 2 of Embodiment 2 in that the capacitive coupling reduces the connection between the wiring pattern and the fifth wiring pattern. Hereinafter, the semiconductor module 3 will be described focusing on the differences from the semiconductor module 2.

[0090] As shown in Figures 7 and 8, the semiconductor module 3 includes a capacitive coupling reduction connection member 98. The capacitive coupling reduction connection member 98 is a conductive member (e.g., an aluminum wire) that connects the capacitive coupling reduction wiring pattern 97 and the fifth wiring pattern 50. Therefore, in the semiconductor module 3, the capacitive coupling reduction wiring pattern 97 is connected to the fifth wiring pattern 50.

[0091] The second power terminals 52 and 53 are grounding terminals and are connected to the fifth wiring pattern 50, thus reducing capacitive coupling in the semiconductor module 3 and grounding the wiring pattern 97.

[0092] Although the semiconductor module 3 of Embodiment 3 differs from the semiconductor module 2 of Embodiment 2 in that it reduces capacitive coupling and connects the wiring pattern to the fifth wiring pattern, the temperature sensing element 90 is surrounded by the first switching path A and the second switching path B in the full-bridge circuit 100. Therefore, the semiconductor module 3 of Embodiment 3, like the semiconductor module 2 of Embodiment 2, is a semiconductor module capable of performing temperature sensing more accurately than before.

[0093] Furthermore, according to the semiconductor module 3 of embodiment 3, since the capacitive coupling reduces the grounding of the wiring pattern 97, the parasitic capacitance generated around the first temperature detection wiring pattern 93 can be further reduced, as shown in the embodiment described later.

[0094] Furthermore, in the semiconductor module 3 of Embodiment 3, the second power terminals 52 and 53 are terminals for grounding, and the plurality of wiring patterns include a fifth wiring pattern 50 that connects the second power terminals 52 and 53. The capacitive coupling reduction wiring pattern 97 is connected to the fifth wiring pattern 50. Therefore, according to the semiconductor module 3 of Embodiment 3, the capacitive coupling reduction wiring pattern 97 can be grounded through the fifth wiring pattern 50.

[0095] Furthermore, since the semiconductor module 3 of Embodiment 3 has all the structures of the semiconductor module 2 of Embodiment 2, it also has the same effects as the semiconductor module 2 of Embodiment 2.

[0096] [Implementation Method 4]

[0097] The semiconductor module 4 of Embodiment 4 has a structure that is basically the same as that of the semiconductor module 3 of Embodiment 3, but as shown in Figures 9 and 10, it does not have the capacitive coupling reduction connection member 98, but has a connection wiring pattern 99. The connection wiring pattern 99 is a wiring pattern for connecting the capacitive coupling reduction wiring pattern 97 and the fifth wiring pattern 50.

[0098] The semiconductor module 4 in embodiment 4 has the same effect as the semiconductor module 3 in embodiment 3.

[0099] [Example]

[0100] The following is an explanation of the results of the inventors' analogy regarding the effects of the semiconductor module of the present invention.

[0101] The simulation was performed on semiconductor modules 1-4 of embodiments 1-4 and semiconductor module 1A of the comparative example.

[0102] As shown in Figures 11 and 12, although semiconductor module 1A has a structure substantially the same as semiconductor module 1 in Embodiment 1, the balance of parasitic capacitance between the second wiring pattern and the first temperature sensing wiring pattern and between the fourth wiring pattern and the first temperature sensing wiring pattern is not considered. The temperature sensing element 90, the first temperature sensing terminal T1, and the second temperature sensing terminal T2 in semiconductor module 1A are the same as their corresponding components in semiconductor module 1, but their positions differ. Furthermore, due to the aforementioned differences, semiconductor module 1A includes second wiring pattern 20A, fourth wiring pattern 40A, fifth wiring pattern 50A, first temperature sensing pattern 93A, and second temperature sensing pattern 94A with shapes different from their corresponding components in semiconductor module 1.

[0103] First, for semiconductor modules 1 to 4 in Embodiments 1 to 4 and semiconductor module 1A in Comparative Example, the difference between the parasitic capacitance between the first temperature detection wiring patterns 93, 93A and the second wiring patterns 20, 20A and the parasitic capacitance between the first temperature detection wiring patterns 93, 93A and the fourth wiring patterns 40, 40A (hereinafter referred to as "parasitic capacitance difference") was measured.

[0104] As a result, the difference in parasitic capacitance in semiconductor module 1A is 307fF. In addition, the difference in parasitic capacitance in semiconductor module 1 is 109fF, the difference in parasitic capacitance in semiconductor module 2 is 98fF, the difference in parasitic capacitance in semiconductor module 3 is 95fF, and the difference in parasitic capacitance in semiconductor module 4 is 97fF.

[0105] Based on the above results, it can be confirmed that in the semiconductor modules 1 to 4 of Embodiments 1 to 4, the parasitic capacitance balance around the first temperature detection wiring pattern 93 is better compared to the semiconductor module 1A of the comparative example. Furthermore, based on the above results, it is also confirmed that reducing the configuration of the wiring pattern 97 through capacitive coupling improves the parasitic capacitance balance, and reducing the connection between the wiring pattern 97 and ground through capacitive coupling further improves the parasitic capacitance balance.

[0106] Next, for semiconductor module 3 of Embodiment 3 and semiconductor module 1A of Comparative Example, the frequency of the turn-on and turn-off operation of the full-bridge circuit 100 was set to 20kHz, and the noise (voltage fluctuation) generated in the first temperature detection path TP1 (the current path from the first temperature detection electrode 91 to the first temperature detection terminal T1, see Figures 1 and 12) was measured during switching.

[0107] As a result, as shown in FIG13, in the semiconductor module 3 of Embodiment 3, the noise generated in the first temperature detection path TP1 is significantly reduced compared to the semiconductor module 1A of the comparative example. Therefore, in the semiconductor module 3 of Embodiment 3, the output voltage of the temperature detection element 90 becomes stable.

[0108] The present invention has been described above based on the various embodiments described above, but the present invention is not limited to the embodiments described above. It can be implemented in various ways without departing from the concept, for example, the following modifications can be made.

[0109] (1) The positions, sizes, shapes, etc. of the constituent elements described in the above embodiments and shown in the accompanying drawings are examples and may be modified within the scope of not impairing the effect of the present invention.

[0110] (2) In embodiments 3 and 4 above, the capacitive coupling reduction wiring pattern 97 is grounded through the fifth wiring pattern 50, but the present invention is not limited thereto. In the present invention, the capacitive coupling reduction wiring pattern may also be grounded without passing through the fifth wiring pattern. For example, this configuration can be achieved by connecting a dedicated terminal to the capacitive coupling reduction wiring pattern.

[0111] (3) In embodiments 2 to 4 described above, the second temperature detection wiring pattern 94 is disposed between the first temperature detection wiring pattern 93 and the fourth wiring pattern 40, and the capacitive coupling reduction wiring pattern 97 is disposed between the first temperature detection wiring pattern 93 and the second wiring pattern 20, but the present invention is not limited thereto. The configurations of the second temperature detection wiring pattern and the capacitive coupling reduction wiring pattern can also be reversed. In addition, in this case, it is also necessary to adjust the configuration of the temperature detection element and the second temperature detection terminal.

[0112] (4) In embodiments 3 and 4 above, the capacitive coupling reduction wiring pattern 97 is grounded, but the present invention is not limited thereto. The capacitive coupling reduction wiring pattern can be connected to a connection destination other than ground. The connection destination other than ground is preferably a voltage-stable connection destination. Various power supplies (main power supply, control system power supply, etc.) can be exemplified as voltage-stable wiring objects. By adopting this structure, the parasitic capacitance generated around the first temperature detection wiring pattern can also be further reduced.

[0113] 1, 2, 3, 4: Semiconductor modules 10: First wiring pattern 20: Second wiring pattern 30: Third wiring pattern 40: Fourth wiring pattern 50: Fifth wiring pattern 51: Power Terminal 1 52, 53: Second power supply terminal 61: First midpoint terminal 62: Second midpoint terminal 90: Temperature sensing element 91: First temperature sensing electrode 92: Second temperature sensing electrode 93: Wiring pattern for the first temperature detection 94: Wiring pattern for the second temperature detection 97: Capacitive coupling reduces wiring pattern 100: Full-bridge circuit A: Path of the first switch B: Second switch path P1: First current path P2: Second current path P3: Third current path P4: Fourth current path Q1: First semiconductor element Q2: Second semiconductor element Q3: Third semiconductor element Q4: The fourth semiconductor element T1: First temperature detection terminal T2: Second temperature detection terminal.

Claims

1. A semiconductor module, comprising: Semiconductor elements 1 through 4; Multiple wiring patterns; power terminal number 1; Second power terminal; First midpoint terminal; The semiconductor module, comprising a first semiconductor element and a third semiconductor element as the high side and a second semiconductor element and a fourth semiconductor element as the low side, and a second midpoint terminal, further includes: a temperature sensing element having a first temperature sensing electrode and a second temperature sensing electrode; a first temperature sensing wiring pattern connected to the first temperature sensing electrode; a first temperature sensing terminal for connection to a temperature sensing circuit and connected to the first temperature sensing wiring pattern; a second temperature sensing wiring pattern connected to the second temperature sensing electrode; and a second temperature sensing terminal for grounding or connection to a control system power supply and connected to the second temperature sensing wiring pattern. Wherein, when the first semiconductor element and the fourth semiconductor element are simultaneously turned on, i.e., the current path including the first current path from the first power terminal to the first midpoint terminal and the second current path from the second midpoint terminal to the second power terminal is used as the first switching path; and when the third semiconductor element and the second semiconductor element are simultaneously turned on, i.e., the current path including the third current path from the first power terminal to the second midpoint terminal and the fourth current path from the first midpoint terminal to the second power terminal is used as the second switching path, the temperature sensing element is disposed in the area surrounded by the first switching path and the second switching path, and the semiconductor module is configured to reduce noise based on the parasitic capacitance between the wiring pattern constituting the common portion of the first current path and the fourth current path and the first temperature sensing wiring pattern, and based on the parasitic capacitance between the wiring pattern constituting the common portion of the second current path and the third current path and the first temperature sensing wiring pattern.

2. The semiconductor module according to claim 1, wherein: The plurality of wiring patterns include: a first wiring pattern that mounts the first semiconductor element and is connected to the first power terminal; a second wiring pattern that mounts the second semiconductor element and is connected to the first midpoint terminal; a third wiring pattern that mounts the third semiconductor element and is connected to the first power terminal; and a fourth wiring pattern that mounts the fourth semiconductor element and is connected to the second midpoint terminal, wherein, when the semiconductor module is viewed from above, the first temperature sensing wiring pattern is disposed between the second wiring pattern and the fourth wiring pattern.

3. The semiconductor module according to claim 2, wherein: The distance between the first temperature detection wiring pattern and the second wiring pattern is equal to the distance between the first temperature detection wiring pattern and the fourth wiring pattern.

4. The semiconductor module according to claim 2, wherein: The second power terminal is a terminal for grounding, and the plurality of wiring patterns further include a fifth wiring pattern connected to the second power terminal, the fifth wiring pattern having an extension extending in the direction in which the first temperature sensing wiring pattern is disposed.

5. The semiconductor module according to claim 2, wherein: The second temperature sensing wiring pattern is disposed between the first temperature sensing wiring pattern and the second wiring pattern, or between the first temperature sensing wiring pattern and the fourth wiring pattern. The semiconductor module further includes a capacitive coupling reduction wiring pattern disposed between the first temperature sensing wiring pattern and the second wiring pattern, and on the side between the first temperature sensing wiring pattern and the fourth wiring pattern where the second temperature sensing wiring pattern is not disposed.

6. The semiconductor module according to claim 5, wherein: The capacitive coupling reduces the wiring pattern used for the grounding.

7. The semiconductor module according to claim 6, wherein: The second power terminal is a terminal for grounding, and the plurality of wiring patterns further include a fifth wiring pattern connected to the second power terminal, the capacitive coupling reduction wiring pattern being connected to the fifth wiring pattern.

8. The semiconductor module according to claim 2, wherein: When viewed from above, the first temperature sensing wiring pattern and the first temperature sensing terminal are arranged at a position overlapping a predetermined axis of symmetry. At least a portion of the first temperature sensing terminal and the first temperature sensing wiring pattern have a shape that is linearly symmetrical about the predetermined axis of symmetry. The structure formed by the first to fourth semiconductor elements, the first to fourth wiring patterns, the first power terminal, the second power terminal, the first midpoint terminal, and the second midpoint terminal, which are constituent elements of the semiconductor module, is symmetrical about the predetermined axis of symmetry.

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