Gate driving unit

Abstract

This application claims to protect a gate drive unit having a first terminal suitable for being configured as a control terminal, a second terminal suitable for being configured as a reference ground terminal, and a third terminal suitable for being configured as an output terminal. The gate drive unit can receive a pulse width modulation signal at the first terminal and provide a switching drive signal at the third terminal. The gate drive unit can detect or monitor a current signal flowing through the third terminal and control the logic state of the switching drive signal based on the pulse width modulation signal and the current signal.

Description

Technical Field

[0001] This application generally relates to electronic circuits, and more specifically, but not exclusively, to gate drivers for switching devices. Prior Technology

[0002] In power converter applications, gate drivers are typically used to drive power switching, such as power metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs). Isolated gate drivers are widely used in power conversion or power management applications to handle high power or high voltage. The most widely used isolated gate drivers are packaged in a compact and low-cost SOIC8 package, but these drivers do not provide monitoring or protection functions. Summary of the Invention

[0003] According to one embodiment of the present invention, a gate drive unit is provided, having a first terminal configured as a control terminal, a second terminal configured as a reference ground terminal, and a third terminal configured as an output terminal. The gate drive unit is adapted to receive a pulse-width modulation (PWM) signal at the first terminal and provide a switching drive signal at the third terminal. The gate drive unit can detect or monitor a current signal flowing through the third terminal and control the logic state of the switching drive signal based on the PWM signal and the current signal.

[0004] According to one embodiment of the present invention, a gate drive unit is also provided, having a first terminal configured as a control terminal, a second terminal configured as a reference ground terminal, and a third terminal configured as an output terminal of the gate drive unit. The gate drive unit may further include: a driver for generating a switching drive signal and providing it to the third terminal; and a drive control circuit coupled between the first terminal and the driver. The drive control circuit may be adapted to be configured to receive a pulse-width modulation (PWM) signal from the first terminal, and further configured to detect or monitor a feedback signal indicating a current signal flowing through the third terminal, and further configured to control the logic state of the switching drive signal based on the PWM signal and the current signal.

[0005] According to an embodiment of the present invention, a gate drive unit is also provided, comprising: a first terminal adapted to be configured as a control terminal for receiving a pulse width modulation (PWM) signal; a second terminal adapted to be configured as a reference ground terminal; a third terminal adapted to be configured as an output terminal of the gate drive unit to provide a switching drive signal; and a report terminal adapted to provide a report signal. The PWM signal may have a set logic state and a reset logic state, and the switching drive signal may have a logic state including a drive set logic state and a drive reset logic state. The gate drive unit may detect or monitor a current signal flowing through the third terminal and may be adapted to control the logic state of the switching drive signal based on the PWM signal and the current signal. The gate drive unit may also be adapted to set the report signal to a first report state or a second report state based on the PWM signal and the current signal. Simple Explanation of the Diagram

[0006] To better understand the present invention, embodiments of the invention will be described with reference to the following accompanying drawings, which are for illustrative purposes only. The drawings typically show only some features of the embodiments and are not necessarily drawn to scale. [Figure 1] schematically illustrates a gate drive unit 100 according to an embodiment of this application. [Figure 2] schematically shows a waveform diagram 200 of several signals of a gate drive unit 100 according to an embodiment of the present application. [Figure 3] schematically shows a block diagram of a power conversion device 300 according to an embodiment of the present application. [Figure 4] schematically shows a waveform diagram 400 of several signals of a gate drive unit 100 according to an alternative exemplary embodiment of the present application. [Figure 5] schematically shows a waveform diagram 500 of several signals of a gate drive unit 100 according to yet another alternative exemplary embodiment of the present application. [Figure 6] schematically illustrates an exemplary schematic diagram of a gate drive unit 600 according to an embodiment of this application. [Figure 7] schematically illustrates an exemplary schematic diagram of a gate drive unit 700 according to an embodiment of this application. [Figure 8] schematically shows a waveform diagram 800 of several signals of a gate drive unit 700 according to an embodiment of the present application. [Figure 9] schematically illustrates a gate drive unit 900 according to an embodiment of this application. [Figure 10] schematically illustrates a gate drive unit 1000 according to an embodiment of this application. [Figure 11] schematically illustrates a gate drive unit 1100 according to an embodiment of this application. [Figure 12] Schematic diagram 1200 showing waveforms of several signals of an exemplary embodiment of a gate drive unit including a reporting terminal according to the present application.

[0007] The same reference numerals in different schematic diagrams indicate the same or similar parts or features. Implementation

[0008] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details, such as example circuits and example values ​​of circuit elements, are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention, and that the invention may be practiced without one or more of these specific details, or using other methods, elements, materials, etc. In other embodiments, well-known circuits, materials, or methods are not specifically described to avoid obscuring the invention. Although the invention has been described by way of preferred embodiments, it should be understood that the invention is not limited to these embodiments. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of elements in the embodiments can be understood by those skilled in the art. Other variations and modifications to the embodiments disclosed herein do not depart from the spirit of the invention and the scope of the claims.

[0009] The phrases "an embodiment," "an example," "an example," and "an example" appearing in this specification do not necessarily refer to the same embodiment or example. Those skilled in the art should understand that the various specific features, structures, parameters, steps, etc., disclosed in one or more embodiments of this invention can be combined in any suitable manner. Furthermore, the terms "coupled" and "connected" mean a direct or indirect electrical or non-electrical connection. When an element is considered to be "connected" to another element, it can be a direct connection to the other element or there may be an intervening element present. "A / this / that" is not used specifically to refer to the singular but may encompass the plural form. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items. When a field-effect transistor (FET) or bipolar junction transistor (BJT) is used as an embodiment of a transistor, the scope of "gate," "drain," and "source" includes "base," "collector," and "emitter," respectively, and vice versa. Those skilled in the art should understand that the meaning of the above terms is not necessarily limiting but merely illustrative examples of these terms.

[0010] The terms “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0011] Furthermore, if the present invention involves descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0012] Figure 1 schematically illustrates a gate drive unit 100 according to an embodiment of the present invention. The gate drive unit 100 may be adapted to drive a switching device 101. For example, when used for power conversion, the gate drive unit 100 may be configured to drive the switching device 101 to perform on and off switching. The switching device 101 may include power switching devices such as power MOSFETs, IGBTs, etc. In the example of Figure 1, the switching device 101 is shown to include MOSFETs, but is not limited thereto.

[0013] According to an exemplary embodiment of the present invention, the gate drive circuit 100 may include a first terminal 11, a second terminal 12, and a third terminal 13. The first terminal 11 may be configured as a control terminal or a control node, the second terminal 12 may be configured as a reference ground terminal of the gate drive unit 100, and the third terminal 13 may be configured as an output terminal of the gate drive unit 100. The first terminal 11 may be configured to receive a pulse width modulation (CPWM) signal. The CPWM signal includes a logic signal having a reset logic state (e.g., logic low) and a set logic state (e.g., logic high). For ease of description and understanding, in the following text of this application, the transition of the CPWM signal from a set logic state (e.g., logic high) to a reset logic state (e.g., logic low) may be referred to as a first type transition edge of the CPWM signal, and the transition of the CPWM signal from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high) may be referred to as a second type transition edge of the CPWM signal.

[0014] The third terminal 13 can be configured to provide a switching drive signal DROUT for driving the switching device 101. The switching drive signal DROUT can include a logic signal having logic states including a drive reset logic state (e.g., logic low) applicable to configuring the switching device 101 to be off and a drive setting logic state (e.g., logic high) applicable to configuring the switching device 101 to be on. For ease of description and understanding, in this application, the time or moment when the switching drive signal DROUT changes (or resets) from the drive setting logic state (e.g., logic high) to the drive reset logic state (e.g., logic low) can be referred to as the reset time, and the time or moment when the switching drive signal DROUT changes (or sets) from the drive reset logic state (e.g., logic low) to the drive setting logic state (e.g., logic high) can be referred to as the set time. The switching drive signal DROUT can have a switching period Tsw, which is the time interval between every two adjacent reset times of the switching drive signal DROUT.

[0015] According to an exemplary embodiment of the present invention, the drive control circuit 102 is configured to be coupled between the first terminal 11 and the driver 103, and the drive control circuit 102 can be configured to control the driver 103 to generate a switching drive signal DROUT.

[0016] According to an exemplary embodiment of the present invention, the drive control circuit 102 is configured to receive a pulse width modulation signal (CPWM) from the first terminal 11. The drive control circuit 102 may also be configured to detect or monitor a feedback signal representing a current signal Io flowing through (e.g., into or out of) the third terminal 13. Here, "flowing into" the third terminal 13 can refer to the direction in which the current signal Io flows from the third terminal 13 into the gate drive unit 100, and "flowing out" the third terminal 13 can refer to the direction in which the current signal Io flows out of the third terminal 13 from the gate drive unit 100. For ease of description of embodiments of the present invention, the direction of the current signal Io "flowing out" from the third terminal 13 can be considered as a reference current direction; that is, a current in the same direction as the reference current can be considered a positive current, and a current in the opposite direction to the reference current can be considered a negative current. In one embodiment, the gate drive unit 100 or the drive control circuit 102 in the gate drive unit 100 can also be configured to control the logic state of the switching drive signal DROUT based on the pulse width modulation signal CPWM and the current signal Io. In other words, the gate drive unit 100 can also be used to control the reset time and set time of the switching drive signal DROUT according to the pulse width modulation signal CPWM and the current signal Io.

[0017] According to an exemplary embodiment of the present invention, the driver 103 may include a first drive switch 1031 and a second drive switch 1032 connected in series in a push-pull configuration, and a common connection terminal of the first drive switch 1031 and the second drive switch 1032 is coupled to a third terminal 13. However, this is merely an example and not intended to be limiting. According to an exemplary embodiment of the present invention, in practical use, the third terminal 13 of the gate drive unit 100 can be configured to be coupled to the control terminal G of the switching device 101, either through a resistor RG or without a resistor RG. In one example, the resistor RG may include parasitic resistance. The first terminal D of the switching device 101 can be coupled to the first power node N1, and the second terminal S of the switching device 101 can be coupled to the second power node N2. In an exemplary embodiment, the second terminal 12 of the gate drive unit 100 can be coupled to the second power node N2. There is a voltage drop VDS between the first terminal D and the second terminal S of the switching device 101. The voltage drop VDS can represent the potential difference (VN1-VN2) between the first power node N1 and the second power node N2. When the switching device 101 is turned off, the electrical conduction path (e.g., the current flow path) between the first power node N1 and the second power node N2 is blocked or interrupted. Once the switching device 101 is turned on, the electrical conduction path between the first power node N1 and the second power node N2 is established, allowing current to flow between them. Ideally, for switching power applications (e.g., switching mode power conversion applications), the voltage drop VDS is essentially zero during the on-state of the switching device 101. Therefore, technically, it is desirable to switch the switching device 101 from OFF to ON when the voltage drop VDS is essentially zero to reduce switching losses.

[0018] Figure 2 shows waveforms of several signals of the gate drive unit 100 according to an exemplary embodiment of the present invention. The gate drive unit 100 will now be described in conjunction with Figures 1 and 2.

[0019] According to an exemplary embodiment of the present invention, in each switching cycle Tsw, the gate drive unit 100 may be configured to reset the switching drive signal DROUT to a drive reset logic state (e.g., logic low) in response to a first type transition edge of the pulse width modulation signal CPWM, i.e., in response to the pulse width modulation signal CPWM changing from a set logic state (e.g., logic high) to a reset logic state (e.g., logic low). Please refer to the exemplary and illustrative waveforms in FIG2, which exemplarily show the switching drive signal DROUT being reset to the drive reset logic state (e.g., logic low) at time t0 in response to a first type transition edge of the pulse width modulation signal CPWM. For ease of description and understanding, it can be considered that at time t0, the gate drive unit 100 begins a switching cycle, which is referred to as the current switching cycle Tsw for ease of description. The operation within the current switching cycle Tsw will be described below as an example.

[0020] At reset time t0, the switching drive signal DROUT is reset to the drive reset logic state (e.g., logic low), and can be configured to turn off the switching device 101. Once the switching device 101 is turned off, the voltage drop VDS across the switching device 101 begins to rise, and the Miller current IMC begins to flow through the third terminal 13, for example, in this case, into the third terminal 13. When the switching drive signal DROUT is in the drive reset logic state (e.g., logic low), the current signal Io can include the Miller current IMC. The magnitude of the Miller current IMC can be proportional to the voltage drop VDS, thereby representing the slope or rate of change of the voltage drop VDS. That is, IMC = Cgd * dVDS / dt, where Cgd represents the capacitance between the control terminal G and the first terminal D of the switching device 101, and dVDS / dt is the mathematical expression for the rate of change of the voltage drop VDS. As shown in Figure 2, from the reset time t0 to the time t1 during the rise of the voltage drop VDS, the Miller current IMC flows into the third terminal 13, which can therefore be shown as a negative current (since the direction of the current signal Io "flowing out" of the third terminal 13 is defined as the reference current direction). This negative current first drops from zero to the valley value IMCVL, and then gradually rises back to zero.

[0021] After a first time interval T1 starting from the reset time t0, the voltage drop VDS across the switching device 101 begins to decrease at t2 (i.e., T1 = t2 - t0). The Miller current IMC can then begin to flow through the third terminal 13 again, for example, out of the third terminal 13 in this case. In other words, time t2 can refer to the moment when the voltage drop VDS across the switching device 101 begins to decrease in this example, or it can be referred to as the starting moment of the decrease in the switching voltage. In practical applications, when the gate drive unit 100 is configured to drive the switching device 101 to function as or at least as part of a power conversion device, the voltage drop VDS across the switching device 101 may begin to decrease due to the turn-off of another switch configured to work in conjunction with the switching device 101 (e.g., may include another switching device similar to or the same as the switching device 101).

[0022] Figure 3 shows a block diagram of a power conversion device 300 according to an embodiment of the present invention. The power conversion device 300 may, for example, include a first switch 301_1 and a second switch 301_2 connected in series between a system power supply terminal PS and a system ground terminal PGND. The first switch 301_1 and the second switch 301_2 have a common node SW. A first gate drive unit 302_1 may be configured to drive the first switch 301_1. A second gate drive unit 302_2 may be configured to drive the second switch 301_2. An inductive energy storage device Lo is coupled between the common node SW and the power conversion output terminal PO. A capacitive energy storage device Co may be coupled between the power conversion output terminal PO and the system ground terminal PGND. A system supply voltage VBUS may be provided to the system power supply terminal PS. The power conversion device 300 may be configured to provide a stable voltage Vo at the power conversion output terminal PO. In one embodiment, the first gate drive unit 302_1 can be implemented using the gate drive unit 100 and its variations described in the various embodiments of this application, and the first switch 301_1 can include a switching device similar to or the same as the switching device 101. Therefore, the descriptions of the gate drive units and switching devices 101 in the various embodiments of this application are applicable to the first gate drive unit 302_1 and the first switch 301_1. In one embodiment, the second gate drive unit 302_2 can be implemented using the gate drive unit 100 and its variations described in the various embodiments of this application, and the second switch 301_2 can include a switching device similar to or the same as the switching device 101. Therefore, the descriptions of the gate drive units and switching devices 101 in the various embodiments of this application are applicable to the second gate drive unit 302_2 and the second switch 301_2. In the example of the power conversion device 300, the first switch 301_1 can be referred to as another switch that works in conjunction with the second switch 301_2, and vice versa. Although the example shown in Figure 3 illustrates a buck power conversion topology for the power conversion device 300, those skilled in the art will understand that this is merely exemplary and not intended to be limiting. In alternative embodiments, the power conversion device 300 may have other topologies, such as a boost power conversion topology, a flyback power conversion topology, or a buck-boost power conversion topology, etc.

[0023] Referring to Figures 1 and 2, ideally, the pulse width modulation (CPWM) signal can change from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high) at time t2 (the start of the switching voltage drop). Therefore, in this specific example, the first time interval T1 can be considered as the duration or pulse width of the reset logic state (e.g., logic low) of the CPWM signal. However, as shown in Figure 2, in practical applications, there should be at least a minimum time delay td1 between the start of the switching voltage drop t2 and the moment when the CPWM signal changes from the reset logic state (e.g., logic low) to the set logic state (e.g., logic high) to avoid problems such as short circuits. The moment when the CPWM signal changes from the reset logic state (e.g., logic low) to the set logic state (e.g., logic high) can also be referred to as the moment when the second type of transition edge of the CPWM signal arrives.

[0024] As illustrated in Figure 2, starting from time t2, as the voltage drop VDS decreases, the Miller current IMC first rises from zero to the peak Miller current value IMCPK, and then gradually falls back to near zero. Typically, the switching device 101 is not turned on immediately at the edge of the second type of transition of the pulse width modulation signal (CPWM), but rather it is desirable to turn on the switching device 101 when the voltage drop VDS has decreased to near zero to achieve zero-voltage soft switching (ZVS), which helps reduce switching losses.

[0025] According to an exemplary embodiment, during the period when the switching drive signal DROUT is in a drive reset logic state (e.g., logic low) or at the moment when the pulse width modulation signal CPWM changes from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high), the gate drive unit 100 or the drive control circuit 102 may be configured to detect whether the voltage drop VDS across the switching device 101 has decreased to substantially zero based on the current signal Io (or Miller current IMC) flowing through the third terminal 13.

[0026] According to an exemplary embodiment, the gate drive unit 100 or the drive control circuit 102 may be configured to enable or set a first zero voltage detection (ZVD) time window WMCZVD during the period when the switching drive signal DROUT is in a drive reset logic state (e.g., logic low) or in response to the pulse width modulation signal CPWM changing from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high). The first ZVD time window WMCZVD may have a first window width, or a first window duration. In an exemplary embodiment, the gate drive unit 100 or the drive control circuit 102 may be configured to detect the direction of the current signal Io flowing through the third terminal 13 during the first ZVD time window WMCZVD. In an exemplary embodiment, the drive control circuit 102 may be configured to determine (that it has detected) that the current signal Io flows out of the third terminal 13 once the current signal Io rises to or exceeds a first predetermined threshold Ith1 during the first ZVD time window WMCZVD. For example, in one embodiment, the first predetermined threshold value Ith1 can be set within the range of 0.5A to 1A. Those skilled in the art will understand that the specific range given here is merely an example and is not intended to be limiting. In other embodiments, the first predetermined threshold value Ith1 can also be set to other values ​​according to the actual application parameters.

[0027] In an exemplary embodiment, during the first ZVD time window WMCZVD, the gate drive unit 100 or the drive control circuit 102 may also be configured to detect whether the current signal Io decreases to essentially zero after detecting the current signal Io flowing out from the third terminal 13. If the drive control circuit 102 detects the current signal Io decreasing to essentially zero after detecting the current signal Io flowing out from the third terminal 13 during the first ZVD time window WMCZVD, the drive control circuit 102 may further determine that it has identified the first detection event at time t3 (as exemplarily shown in FIG2) during the first ZVD time window WMCZVD. In one embodiment, when the gate drive unit 100 is configured to drive the switching device 101 in a practical application, the first detection event can indicate that the gate drive unit 100 or the drive control circuit 102 has detected, based on the current signal Io (or Miller current IMC), that the voltage drop VDS across the switching device 101 has decreased to essentially zero. This can also be referred to as the gate drive unit 100 or the drive control circuit 102 recognizing "MCZVD". In this application, "detecting that the voltage drop VDS across the switching device 101 has decreased to essentially zero based on the current signal Io (or Miller current IMC) flowing through the third terminal 13" can be referred to as "MCZVD".

[0028] In an alternative embodiment, the gate drive unit 100 or drive control circuit 102 may be configured to determine that a first detection event has been identified (e.g., still referring to time t3 shown in FIG2) once the current signal Io rises to or exceeds a first predetermined threshold Ith1 and then falls back to or below a second predetermined threshold Ith2 during the first ZVD time window WMCZVD. The first predetermined threshold Ith1 may be higher than the second predetermined threshold Ith2. For example, in one embodiment, the first predetermined threshold Ith1 may be set in the range of 0.5A to 1A, and the second predetermined threshold Ith2 may be set in the range of 0A to 0.1A. In an exemplary embodiment, the second predetermined threshold Ith2 may be set based on the first predetermined threshold Ith1. In an exemplary embodiment, the second predetermined threshold Ith2 may be set by setting a first hysteresis between the first predetermined threshold Ith1 and the second predetermined threshold Ith2. It will be understood by those skilled in the art that the specific ranges of the first predetermined threshold Ith1 and the second predetermined threshold Ith2 given herein are merely examples and are not limiting. In other embodiments, the first predetermined threshold value Ith1 and / or the second predetermined threshold value Ith2 may also be set to other values ​​according to the actual application parameters. The example of setting the second predetermined threshold value Ith2 based on the first predetermined threshold value Ith1 is only for the purpose of understanding the embodiments and is not a limitation.

[0029] According to an exemplary embodiment, the gate drive unit 100 or the drive control circuit 102 may also be configured to set the switching drive signal DROUT to a drive setting logic state (e.g., logic high) under the following conditions: A) the gate drive unit 100 or the drive control circuit 102 detects a first detection event during the first ZVD time window WMCZVD; B) the pulse width modulation signal CPWM is in a setting logic state (e.g., logic high), such that the switching drive signal DROUT can turn on the switching device 101. In this way, the gate drive unit 100 can control the setting time of the switching drive signal DROUT based on the current signal Io (or Miller current IMC) flowing through the third terminal 13 during each switching cycle Tsw and the logic state of the pulse width modulation signal CPWM. From the set time (e.g., time t3 in the current switching cycle Tsw), the gate drive unit 100 or the drive control circuit 102 can keep the switching drive signal DROUT in the drive set logic state (e.g., logic high) to drive the switching device 101 to turn on, until the switching drive signal DROUT is reset to the drive reset logic state (e.g., logic low), for example at time t4 (the reset time adjacent to the reset time t0), for example in response to the pulse width modulation signal CPWM changing from the set logic state (e.g., logic high) to the reset logic state (e.g., logic low), as shown in FIG2.

[0030] It is understood that, following the current switching cycle Tsw, which extends from reset time t0 to reset time t4 as exemplarily shown in Figure 2, the gate drive unit 100 initiates the next switching cycle Tsw at reset time t4. This switching cycle Tsw can extend from reset time t4 to time t8 (i.e., the next reset time immediately following reset time t4), as shown in Figure 2. For ease of description and understanding, the switching cycle Tsw from reset time t0 to reset time t4 can be referred to as or denoted as Tsw(t0~t4), and similarly, the switching cycle Tsw from reset time t4 to reset time t8 can be referred to as or denoted as Tsw(t4~t8). Those skilled in the art will understand that within the next switching cycle Tsw(t4~t8), there exist times t5, t6, and t7, which can be considered to correspond to times t1, t2, and t3 in the current switching cycle Tsw(t0~t4), respectively, as shown in Figure 2. Those skilled in the art will also understand that, as shown in FIG2, the operation and working principle of the gate drive unit 100 in the next switching cycle Tsw (t4~t8) can be similar to or the same as that described in the current switching cycle Tsw (t0~t4), and will not be repeated here. In the example of FIG2, more switching cycles Tsw are shown to illustrate a better understanding of the embodiments of the present invention. For example, FIG2 exemplarily shows the switching cycle Tsw from time t8 to time t12 immediately following the reset time t8, the switching cycle Tsw from time t12 to time t17 immediately following the reset time t12, and the switching cycle Tsw from time t17 to time t22 immediately following the reset time t17. For ease of description and understanding, these can be referred to or represented as Tsw(t8~t12), Tsw(t12~t17), and Tsw(t17~t22), respectively. In each switching cycle Tsw, the operation and working principle of the gate drive unit 100 can be similar to or the same as that described in the current switching cycle Tsw (t0~t4), and will not be repeated here.

[0031] Referring to the examples in Figure 2, in the switching cycles Tsw(t0~t4), Tsw(t4~t8), and Tsw(t8~t12), for each switching cycle Tsw, if the gate drive unit 100 or the drive control circuit 102 detects the first detection event within the first ZVD time window WMCZVD at a time later than the time when the pulse width modulation signal CPWM changes from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high), then the gate drive unit 100 or the drive control circuit 102 can immediately set the switching drive signal DROUT to the drive set logic state (e.g., logic high) after detecting the first detection event, for example, at times t3, t7, and t11 as shown in the examples in Figure 2. In such cases, at the moment when switching device 101 is turned on (e.g., the set times t3, t7, and t11 in Figure 2), the voltage drop VDS across switching device 101 may have decreased to essentially zero, which can be considered as substantially full ZVS, such as the case in switching cycles Tsw (t0~t4) and Tsw (t8~t12) shown in the example of Figure 2, or the voltage drop VDS across switching device 101 may have decreased significantly compared to the starting time of the voltage reduction (e.g., t6 in Figure 2), which can be considered as substantially partial ZVS, such as the case in switching cycles Tsw (t4~t8) shown in the example of Figure 2.

[0032] Therefore, for each switching cycle Tsw, if the gate drive unit 100 or the drive control circuit 102 detects the first detection event within the first ZVD time window WMCZVD after the pulse width modulation signal CPWM changes from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high), then the gate drive unit 100 or the drive control circuit 102 can determine that a substantially full ZVS or substantially partial ZVS has been detected. For both substantially full ZVS and substantially partial ZVS, switching losses can be beneficially reduced.

[0033] For each switching cycle Tsw, if the gate drive unit 100 or drive control circuit 102 detects the first detection event earlier than the moment when the pulse width modulation signal CPWM changes from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high) within the first ZVD time window WMCZVD, such as the case shown in the switching cycle Tsw (t12~t17) in the example of Figure 2, then the gate drive unit 100 or drive control circuit 102 can wait until the second type transition edge of the pulse width modulation signal CPWM arrives at time t16 after detecting the first detection event, and then set the switching drive signal DROUT to the drive set logic state (e.g., logic high). In such a case, at the moment when the switching device 101 is turned on (e.g., the set time t16 in Figure 2), the voltage drop VDS across the switching device 101 may oscillate and rise again, which can be considered substantially non-ZVS.

[0034] According to an exemplary embodiment, for each switching cycle Tsw, if the gate drive unit 100 or the drive control circuit 102 identifies the moment when the first detection event is detected during the first ZVD time window WMCZVD (e.g., moment t15 within the switching cycle Tsw (t12~t17) shown in FIG. 2) is earlier than the moment when the second type transition edge of the pulse width modulation signal CPWM arrives (e.g., moment t16 within the switching cycle Tsw (t12~t17) shown in FIG. 2), then the gate drive unit 100 or the drive control circuit 102 may also be configured to detect whether the current signal Io (or Miller current IMC) flows in the opposite direction to the direction of the current signal Io during the first ZVD time window WMCZVD (e.g., outflow from the third terminal 13) (e.g., inflow into the third terminal 13). For each switching cycle Tsw, if the gate drive unit 100 or the drive control circuit 102 detects a current signal Io (or Miller current IMC) flowing into the third terminal 13 after recognizing the first detection event, the gate drive unit 100 or the drive control circuit 102 may also be configured to determine that a second detection event has been recognized. This can help to more accurately identify substantially non-ZVS situations. In one embodiment, for each switching cycle Tsw, the gate drive unit 100 or the drive control circuit 102 may be configured to determine that it has recognized the second detection event once the current signal Io drops to or below a third predetermined threshold Ith3 (e.g., after recognizing the first detection event or after the first ZVD time window WMCZVD ends). The third predetermined threshold Ith3 may be lower than a second predetermined threshold Ith2.

[0035] According to an exemplary embodiment, for each switching cycle Tsw, the gate drive unit 100 or the drive control circuit 102 may also be configured to enable or set the maximum zero voltage detection (ZVD) time period tZVD_WAIT in response to the moment when the pulse width modulation signal CPWM changes from a reset logic state (e.g., logic low) to a set logic state (e.g., logic high). If the gate drive unit 100 or the drive control circuit 102 neither detects the first detection event during the first ZVD time window WMCZVD nor before the end of the maximum ZVD time period tZVD_WAIT, the gate drive unit 100 or the drive control circuit 102 can be further configured to force the switching drive signal DROUT to be set to the drive setting logic state (e.g., logic high). For example, in the case shown by the switching period Tsw (t17~t22) in the example of FIG2, when the maximum ZVD time period tZVD_WAIT expires and no first detection event is detected (i.e., MCZVD), the gate drive unit 100 or the drive control circuit 102 forces the switching drive signal DROUT to be set to the drive setting logic state (e.g., logic high) at time t20. In this case, at the time when the switching device 101 is turned on (e.g., the setting time t20 shown in FIG2), the voltage drop VDS across the switching device 101 may not have decreased significantly, and can be considered substantially non-ZVS.

[0036] Therefore, in an exemplary embodiment, for each switching cycle Tsw, if the gate drive unit 100 or the drive control circuit 102 identifies the first detection event in the first ZVD time window WMCZVD earlier than the second type transition edge of the pulse width modulation signal CPWM, or if the gate drive unit 100 or the drive control circuit 102 neither identifies the first detection event in the first ZVD time window WMCZVD nor identifies the first detection event before the end of the maximum ZVD time period tZVD_WAIT, then the gate drive unit 100 or the drive control circuit 102 can determine that a substantially non-ZVS situation has been identified. In an alternative exemplary embodiment, for each switching cycle Tsw, if a second detection event is detected after the first detection event is detected or after the first ZVD time window WMCZVD ends, or if the gate drive unit 100 or the drive control circuit 102 neither detects the first detection event during the first ZVD time window WMCZVD nor before the maximum ZVD time period tZVD_WAIT expires, then the gate drive unit 100 or the drive control circuit 102 may determine that a substantially non-ZVS situation has been detected.

[0037] According to an exemplary embodiment, for each switching cycle Tsw, the gate drive unit 100 or the drive control circuit 102 may also be configured to enable or set the first ZVD time window WMCZVD, for example by providing the first predetermined positive edge masking time tMCZVD_LEB, after a first predetermined positive edge masking time tMCZVD_LEB has elapsed since the switching drive signal DROUT was reset from the drive setting logic state (logo high in the example of FIG2) to the drive reset logic state (logo low in the example of FIG2).

[0038] According to an exemplary embodiment, the first window width of the first ZVD time window WMCZVD can be a first predetermined duration, which can be preset according to actual application requirements and application parameters, as shown in FIG2. According to an alternative exemplary embodiment, the gate drive unit 100 or the drive control circuit 102 can be configured to self-adjust the first window width of the first ZVD time window WMCZVD, instead of setting the first window width to the first predetermined duration. For example, in the embodiment illustrated in FIG4, for each switching cycle Tsw, the gate drive unit 100 or the drive control circuit 102 may also be configured to disable or reset the first ZVD time window WMCZVD when the gate drive unit 100 or the drive control circuit 102 has identified a first detection event (or has detected "MCZVD") or when the switching drive signal DROUT is set from a drive reset logic state (e.g., logic low in the FIG4 example) to a set logic state (e.g., logic high in the FIG4 example). This can be achieved, for example, by controlling the first ZVD time window signal EN_MCZVD as illustrated in FIG4. For example, in the alternative embodiment illustrated in FIG5, for each switching cycle Tsw, the gate drive unit 100 or drive control circuit 102 may also be configured to disable or reset the first ZVD time window WMCZVD, for example, by means of the first ZVD time window control signal EN_MCZVD illustrated in FIG5, after a predetermined delay time td2 from the moment the second type transition edge of the pulse width modulation signal CPWM arrives. Those skilled in the art will understand that, in addition to the examples described herein, there are many other alternative methods to enable or disable the first ZVD time window, all of which are within the spirit and scope of this application.

[0039] According to an exemplary embodiment, once the gate drive unit 100 or the drive control circuit 102 identifies a first detection event during the first ZVD time window WMCZVD, the gate drive unit 100 or the drive control circuit 102 may also be configured to reset or maintain the first flag signal FMCZVD to a first flag logic state (e.g., logic low in the example of FIG2). The gate drive unit 100 or the drive control circuit 102 may also be configured to set or maintain the first flag signal FMCZVD to a second flag logic state (e.g., logic high in the example of FIG2) if the first detection event is not identified during the first ZVD time window WMCZVD.

[0040] According to an exemplary embodiment, the gate drive unit 100 or the drive control circuit 102 may also be configured to provide a ZVS indication signal FLAG, and once the gate drive unit 100 or the drive control circuit 102 identifies a substantially full ZVS or substantially partial ZVS, reset or maintain the ZVS indication signal FLAG in a first indication logic state (e.g., logic low in the example of FIG2), and if the gate drive unit 100 or the drive control circuit 102 identifies a substantially non-ZVS, set or maintain the ZVS indication signal FLAG in a second indication logic state (e.g., logic high in the example of FIG2).

[0041] According to an exemplary embodiment, the gate drive unit 100 may further have a fourth terminal 14, which may be configured as a first power supply terminal of the gate drive unit 100. The fourth terminal 14 may be configured to provide a first power supply voltage VDD. The first power supply voltage VDD may be used to power the drive control circuit 102, driver 103, and other circuits of the gate drive unit 100. In practical applications, a first capacitor C1 may be coupled to the fourth terminal 14. In an exemplary embodiment, the first capacitor C1 and the second capacitor C2 may be connected in series between the fourth terminal 14 and the second terminal 12, and the common connection point N3 of the first capacitor C1 and the second capacitor C2 may be coupled to the second power supply node N2.

[0042] According to an exemplary embodiment, the gate drive unit 100 may further include a first fault detection and / or fault protection circuit 141. For example, in one embodiment, the first fault detection and / or fault protection circuit 141 may include a first undervoltage protection circuit UVLO1 and may be configured to detect whether a first power supply voltage VDD is lower than a first undervoltage threshold VUV1. In one embodiment, if the first power supply voltage VDD is lower than the first undervoltage threshold VUV1, the first undervoltage protection circuit UVLO1 may control the switching drive signal DROUT to lock in a drive reset logic state (e.g., logic low), for example, by means of an internal low-level effective clamping circuit provided in the driver control circuit 102.

[0043] According to an exemplary embodiment, the gate drive unit 100 may further include an isolation circuit 104, which may be configured to provide electrical isolation between the primary and secondary sides of the gate drive unit 100. The gate drive unit 100 may include a primary control circuit 105 located on the primary side. The drive control circuit 102 and the driver 103 may be located on the secondary side. The gate drive unit 100 may further include a fifth terminal 15 for use as a primary control terminal IN; a sixth terminal 16 for use as a primary reference ground terminal GND of the primary side circuit of the gate drive unit 100; and a seventh terminal 17 for use as a primary power supply terminal of the gate drive unit 100. The seventh terminal 17 may be used to provide a second power supply voltage VCC to the primary side circuit (e.g., the primary control circuit 105, etc.), and in practical applications, a third capacitor C3 may also be coupled to the seventh terminal 17. At this time, the second terminal 12 and the fourth terminal 14 can serve as the secondary-side reference ground terminal and the secondary-side power supply terminal of the gate drive unit 100, respectively, providing a reference ground potential VEE and a first power supply voltage VDD to the secondary-side circuitry of the gate drive unit 100 (e.g., drive control circuit 102 and driver 103). With this configuration, the gate drive unit 100 is suitable for power conversion applications requiring high power or high voltage processing. Those skilled in the art should understand that this is merely an example, and the isolation circuit 104, the primary-side circuitry (e.g., primary control circuit 105), and the relevant primary-side terminals (e.g., fifth terminal 15, sixth terminal 16, and seventh terminal 17) may be optional or unnecessary components for low-power or low-voltage applications.

[0044] In one exemplary embodiment, the fifth terminal 15 can be configured to receive a gate control signal PWMIN. The gate control signal PWMIN may include a logic signal having a logic state that switches between a reset logic state (e.g., logic low) and a set logic state (e.g., logic high) at a switching frequency. The gate drive unit 100 can be used to transmit the gate control signal PWMIN to the secondary side, for example, through a first signal isolation transmission channel CH1 in the isolation circuit 104, and the first terminal 11 can receive the signal transmitted to the secondary side as a pulse width modulation signal CPWM. In one embodiment, the gate control signal PWMIN may also be signal-processed by the primary control circuit 105 before being transmitted through the first signal isolation transmission channel CH1, as shown in FIG1. ​​However, in an alternative embodiment, the gate control signal PWMIN may be transmitted through the first signal isolation transmission channel CH1 without undergoing signal processing by the primary control circuit 105. Those skilled in the art will understand that, in embodiments that omit the isolation circuit 104 and the primary side circuit, the gate control signal PWMIN can be directly provided to, for example, the third terminal 13 and used as a pulse width modulation signal CPWM.

[0045] According to an exemplary embodiment, the primary control circuit 105 may include a primary fault detection and / or fault protection circuit 1051. For example, in one embodiment, the primary fault detection and / or fault protection circuit 1051 may include a second undervoltage protection circuit UVLO2 and may be configured to detect whether the second power supply voltage VCC is lower than a second undervoltage threshold VUV2. In one embodiment, if the second power supply voltage VCC is lower than the second undervoltage threshold VUV2, the second undervoltage protection circuit UVLO2 may force the switching drive signal DROUT to be locked in a drive reset logic state (e.g., logic low), for example by locking it through an internal low-level effective clamping circuit in the drive control circuit 102.

[0046] According to an exemplary embodiment, the primary control circuit 105 may further include a primary control signal processing circuit 1052, taking the primary control signal processing circuit 1052 shown in FIG1 as an example. According to an exemplary embodiment, the third terminal 13 (e.g., an output terminal) of the gate drive unit 100 may include a non-inverting output terminal OUT+ and an inverting output terminal OUT-. FIG6 shows an exemplary schematic diagram of the gate drive unit 600, which can be considered as an exemplary embodiment of the gate drive unit 100 according to an exemplary embodiment of the present application, wherein the third terminal 13 includes a non-inverting output terminal OUT+ and an inverting output terminal OUT-. The non-inverting output terminal OUT+ may be coupled to a common drive connection node N4, and may or may not be coupled through a first resistor RSRC. The inverting output terminal OUT- may be coupled to the common drive connection node N4, and may or may not be coupled through a second resistor RSNK. When the gate drive unit 100 is used in a practical application configuration, the common drive connection node N4 may be coupled to the control terminal G of the switching device 101. For this exemplary embodiment, a feedback signal representing the current signal Io flowing through the third terminal 13 can be detected or monitored on the inverting output terminal OUT-. In an exemplary embodiment, the non-inverting output terminal OUT+ can be configured to set the switching drive signal DROUT to a drive setting logic state (e.g., logic high) to drive the switching device 101 to turn on when a logic high signal is asserted at the non-inverting output terminal OUT+. When the switching drive signal DROUT needs to be reset to a drive reset logic state (e.g., logic low), the non-inverting output terminal OUT+ can be configured to have a high impedance state (e.g., high-z). The inverting output terminal OUT- can be configured to reset the switching drive signal DROUT to a drive reset logic state (e.g., logic low) to drive the switching device 101 to turn off when a logic low signal is asserted at the inverting output terminal OUT-. When the switching drive signal DROUT needs to be set to a drive setting logic state (e.g., logic high), the inverting output terminal OUT- can be configured to have a high impedance state (e.g., high-z).

[0047] According to an exemplary embodiment, the fifth terminal 15 of the gate drive unit 100 (e.g., a primary control terminal IN) may include a non-inverting input terminal IN+ and an inverting input terminal IN-. FIG7 shows an exemplary schematic diagram of a gate drive unit 700 according to an exemplary embodiment of the present invention, which can be considered as an exemplary embodiment of the gate drive unit 100, wherein the fifth terminal 15 includes a non-inverting input terminal IN+ and an inverting input terminal IN-. The non-inverting input terminal IN+ may be configured to receive, for example, a first gate control signal PWMIN+. The inverting input terminal IN- may be configured to receive, for example, a second gate control signal PWMIN-. In this case, the first gate control signal PWMIN+ and the second gate control signal PWMIN- define or determine the gate control signal PWMIN. In an exemplary embodiment, the non-inverting input terminal IN+ may be internally pulled to a reset logic state (e.g., logic low), while the inverting input terminal IN- may be internally pulled to a set logic state (e.g., logic high). Here, "internal" may refer to the interior of the gate drive unit 100. In an exemplary embodiment, when the first gate control signal PWMIN+ is in a set logic state (e.g., logic high) and the second gate control signal PWMIN- is in a reset logic state (e.g., logic low), the gate control signal PWMIN or the pulse width modulation signal CPWM can be in a set logic state (e.g., logic high); otherwise, the gate control signal PWMIN or the pulse width modulation signal CPWM can be in a reset logic state (e.g., logic low). In one embodiment, the gate drive unit 100 can also be configured to provide inverting input and non-inverting input overlap protection (also known as IN+ / IN- overlap protection), keeping the switching drive signal DROUT in a reset logic state as long as the second gate control signal PWMIN- is in a set logic state (e.g., logic high).

[0048] For this example, the gate drive unit 700 may include a primary control circuit 405, which can be considered a variation of the primary control circuit 105. In an exemplary embodiment, the primary control circuit 405 may include a primary fault detection and / or fault protection circuit 1051. The primary control circuit 405 may also include a primary control signal processing circuit 4052, which, in one embodiment, is exemplified by the primary control signal processing circuit 4052 shown in FIG7. In one embodiment, the primary control signal processing circuit 4052 may set an internal time delay tdd such that the set logic state (e.g., logic high) of the first gate control signal PWMIN+ and the set logic state (e.g., logic high) of the second gate control signal PWMIN- do not overlap.

[0049] Figure 8 shows a waveform diagram 800 according to an exemplary embodiment of the present invention, which shows the waveforms of several signals of a gate drive unit 700 having a third terminal 13 including a non-inverting output terminal OUT+ and an inverting output terminal OUT-, and a fifth terminal 15 including a non-inverting input terminal IN+ and an inverting input terminal IN-.

[0050] According to an exemplary embodiment, the gate drive unit 100 may further include a reporting terminal 18. The reporting terminal 18 can be used to provide a reporting signal RPT according to various operating states of the gate drive unit 100. The gate drive unit 100 may also be configured to adjust the reporting signal RPT based on a current signal Io. In one embodiment, the gate drive unit 100 may be configured to set the reporting signal RPT to a first reporting state during normal operation. The gate drive unit 100 may be considered to be in a normal operating state when no substantially non-ZVS conditions are identified and / or no fault events such as short-circuit events are detected.

[0051] Figure 9 schematically illustrates a gate drive unit 900 according to an embodiment of the present invention. For simplicity, elements or structures in the gate drive unit 900 that have substantially the same / similar functions as those in the gate drive unit 100 are identified using the same reference numerals as those in the gate drive unit 100. Those skilled in the art will understand that the gate drive unit 900 can be considered a variation of the gate drive unit 100, or an exemplary embodiment of the gate drive unit 100 further comprising a reporting terminal 18. Therefore, the above description of the gate drive unit 100 and drive control circuit 102 of various embodiments of the present invention with reference to Figures 1 to 8 also applies to the gate drive unit 900.

[0052] In an exemplary embodiment, the gate drive unit 900 may also be configured to report the ZVS status to the reporting terminal 18, for example, by providing the ZVS indication signal FLAG as the reporting signal RPT to the reporting terminal 18. In an alternative embodiment, the gate drive unit 900 may be configured to have a first reporting state for the reporting signal RPT during normal operation, and may also be configured to set the reporting signal RPT to a second reporting state according to the ZVS indication signal FLAG when the gate drive unit 900 identifies a substantially non-ZVS situation. The second reporting state is different from the first reporting state. Here, as shown in FIG9, when no substantially non-ZVS situation is identified, the gate drive unit 900 can be considered to be in a normal operating state. In one embodiment, the first reporting state may be a logic low signal, and the second reporting state may be a logic high signal. For example, the first reporting state may include or be embodied as a pulse signal, and the second reporting state may include or be embodied as a logic high signal or a logic low signal. Alternatively, in another embodiment, the first reporting state may include or be embodied as a first pulse signal at a first frequency, while the second reporting state may include or be embodied as a second pulse signal at a second frequency different from the first frequency. Those skilled in the art will understand that many other alternative methods exist for setting the first and second reporting states, which will not be listed exhaustively here. In one embodiment, the gate drive unit 900 may further include signal processing circuitry to provide a signal SP for setting the reporting signal RPT to either the first or second reporting state, at least in part based on the ZVS indication signal FLAG.

[0053] As shown in Figure 12, a first reporting state may include or be embodied as a pulse signal, and a second reporting state may include or be embodied as a logic high signal. It will be understood that Figure 12 shows a waveform diagram 1200 of several signal waveforms according to an exemplary embodiment of a gate drive unit having a reporting terminal 18 according to the present invention.

[0054] In an exemplary embodiment of the gate drive unit 900 equipped with isolation circuit 104, the reporting terminal 18 may be located on the primary side of the gate drive unit 900, which may be suitable for power conversion applications capable of handling high power or high voltage. In this case, the isolation circuit 104 in the gate drive unit 900 may further include a second isolation transmission channel CH2. The drive control circuit 102 may be coupled to the isolation circuit 104 to report the ZVS status to the reporting terminal 18 via the second isolation transmission channel CH2, for example, by transmitting the ZVS indication signal FLAG to the primary side of the gate drive unit 900 via the second isolation transmission channel CH2, or by transmitting the signal SP to the primary side via the second isolation transmission channel CH2 to set the reporting signal RPT to a first reporting state or a second reporting state.

[0055] Figure 10 schematically illustrates a gate drive unit 1000 according to an embodiment of the present invention. For simplicity, elements or structures in the gate drive unit 1000 that have substantially the same / similar functions as those in the gate drive unit 100 are identified using the same reference numerals as those in the gate drive unit 100. Those skilled in the art will understand that the gate drive unit 1000 can be considered a variant of the gate drive unit 100. The gate drive unit 1000 may include a drive control circuit 1002, which can be considered a variant of the drive control circuit 102. Therefore, the above description of the gate drive unit 100 and drive control circuit 102 of various embodiments of the present invention with reference to Figures 1 to 9 applies to both the gate drive unit 1000 and the drive control circuit 1002. Compared to the gate drive unit 100, the gate drive unit 1000 can also be configured to implement short-circuit detection.

[0056] According to an exemplary embodiment, when the gate drive unit 1000 is configured for practical application to drive the switching device 101, the gate drive unit 1000 or its drive control circuit 1002 may also be configured to monitor or detect whether a short-circuit event SC (e.g., a short circuit on the third terminal 13 or the switching device 101) has occurred based on a feedback signal representing the current signal Io flowing through the third terminal 13. In one embodiment, when the switching drive signal DROUT is in a drive setting logic state (e.g., logic high), the gate drive unit 1000 or its drive control circuit 1002 may also be configured to detect the direction of the current signal Io, and once the current signal Io is detected flowing into the third terminal 13, and the phenomenon of the current signal Io flowing into the third terminal 13 continues for a predetermined short-circuit detection time tSC, it is determined that a short-circuit event SC is occurring (or a short-circuit event SC is detected). In this case, the current signal Io may include the Miller current IMC flowing through the control terminal G of the switching device 101. As shown in Figure 12, during the switching period Tsw (t17~t22), at time t21, the gate drive unit 1000 or the drive control circuit 1002 can detect that the current signal Io (or Miller current IMC) is flowing into the third terminal 13, and at time t22, the phenomenon of the current signal Io flowing into the third terminal 13 continues for a predetermined short-circuit detection time tSC. Therefore, the gate drive unit 1000 or the drive control circuit 1002 can determine that in the example shown in Figure 12, a short-circuit event SC is occurring at time t22 (or a short-circuit event SC is detected).

[0057] According to an exemplary embodiment, when the switching drive signal DROUT is in a drive setting logic state (e.g., logic high), the gate drive unit 1000 or the drive control circuit 1002 of the gate drive unit 1000 can be configured to detect the direction of the current signal Io by monitoring or detecting whether the voltage V13 on the third terminal 13 is higher than the first power supply voltage VDD. In one example, if the voltage V13 on the third terminal 13 becomes higher than the first power supply voltage VDD, the gate drive unit 1000 or the drive control circuit 1002 can be configured to determine that it has detected the current signal Io flowing into the third terminal 13 or detected a short circuit event SC. In an alternative example, the gate drive unit 1000 or the drive control circuit 1002 can be configured to determine that a short circuit event SC has been detected if the voltage V13 on the third terminal 13 becomes higher than the first power supply voltage VDD (e.g., shown at time t22) and there is no voltage value lower than the first power supply voltage minus a predetermined hysteresis voltage value.

[0058] In an exemplary embodiment, the gate drive unit 1000 or the drive control circuit 1002 may also be configured to reset the switching drive signal DROUT to a drive reset logic state (e.g., logic low) upon detecting a short-circuit event SC, thereby shutting down the switching device 101. In the example shown in FIG12, at the moment t22 when the short-circuit event SC is detected, the switching drive signal DROUT is reset to the drive reset logic state (e.g., logic low), earlier than the moment t23 when the pulse width modulation signal CPWM changes from the set logic state (e.g., logic high) to the reset logic state (e.g., logic low).

[0059] In an exemplary embodiment, the gate drive unit 1000 or the drive control circuit 1002 may also be configured to provide a fault indication signal FLT that indicates a fault event (e.g., including a short-circuit event SC).

[0060] In one embodiment, the gate drive unit 1000 can be configured to have a first reporting state for the report signal RPT during normal operation, and can also be configured to set the report signal RPT to a second reporting state according to the ZVS indication signal FLAG when the gate drive unit 1000 detects a substantially non-ZVS situation, and can also be configured to set the report signal RPT to a third reporting state according to the fault indication signal FLT when a fault event (e.g., a short-circuit event SC) is detected. In the example of FIG10, when no substantially non-ZVS situation is detected and no fault event such as a short-circuit event is detected, the gate drive unit 1000 can be considered to be in a normal operating state. The first reporting state, the second reporting state, and the third reporting state are different from each other. For example, in one embodiment, the first reporting state may include or be embodied as a logic low signal, the second reporting state may include or be embodied as a logic high signal, and the third reporting state may include or be embodied as a signal with an amplitude different from the logic low signal and the logic high signal. For example, a first reporting state may include or be embodied as a pulse signal, a second reporting state may include or be embodied as a logic high signal (or a logic low signal), and a third reporting state may include or be embodied as a logic low signal (or a logic high signal), as shown in FIG12. Alternatively, in another embodiment, a first reporting state may include or be embodied as a first pulse signal of a first frequency, a second reporting state may include or be embodied as a second pulse signal of a second frequency different from the first frequency, and a third reporting state may include or be embodied as a third pulse signal of a third frequency different from the first and second frequencies. Those skilled in the art will understand that many other alternative methods exist for setting the first and second reporting states, which will not be detailed here. In one embodiment, similar to gate drive unit 900, gate drive unit 1000 may include signal processing circuitry to provide a signal SP, which is used to set the report signal RPT to a first, second, or third reporting state, at least in part, based on the ZVS indication signal FLAG and the fault indication signal FLT.

[0061] In an exemplary embodiment, for a gate drive unit 1000 provided with isolation circuit 104, the report terminal 18 may be located on the primary side of the gate drive unit 1000, which may be suitable for high-power or high-voltage power conversion applications. In this case, the isolation circuit 104 in the gate drive unit 1000 may further include a second isolation transmission channel CH2. The gate drive unit 1000 may transmit signal SP to the primary side through the second isolation transmission channel CH2 to set the report signal RPT to a first report state, a second report state, or a third report state.

[0062] Figure 11 schematically illustrates a gate drive unit 1100 according to an embodiment of the present invention. For simplicity, elements or structures in the gate drive unit 1100 that have substantially the same / similar functions as those in the gate drive unit 100 or gate drive unit 1000 are represented by the same reference numerals as those in the gate drive unit 100 or gate drive unit 1000. Those skilled in the art will understand that the gate drive unit 1100 can be considered a variation of the gate drive unit 100 or gate drive unit 1100. Therefore, the above description of the gate drive units 100 or gate drive units 1000 of various embodiments of the present invention with reference to Figures 1 to 10 applies to the gate drive unit 1100 in Figure 11. Compared to the gate drive unit 100 or gate drive unit 1000, the gate drive unit 1100 can also be configured to realize temperature sensing.

[0063] According to an exemplary embodiment, the gate drive unit 1100 may further include a temperature sensing input (TSI) terminal 19. The TSI terminal 19 may be configured to detect a temperature readout signal indicating the temperature of the switching device 101. In one embodiment, in practical applications, a temperature sensor 1101, such as an NTC thermistor or a temperature sensing diode, may be coupled between the TSI terminal 19 and the second terminal 12. The TSI terminal 19 may be used to provide a temperature sensing current ITS to the temperature sensor 1101 and to detect a temperature sensing voltage VTSI across the temperature sensor 1101 as a temperature readout signal. The gate drive unit 1100 may also be used to provide a temperature reporting signal TSO to the reporting terminal 18. The temperature reporting signal TSO may include a pulse width modulation signal having a pulse width (or pulse duration) TTS or a duty cycle DTS indicating the sensed temperature. The duty cycle DTS may refer to the ratio of the pulse width TTS to the switching period TTSO during each switching cycle of the temperature reporting signal TSO, i.e., DTS = TTS / TTSO.

[0064] According to an exemplary embodiment, similar to gate drive unit 900 or 1000, gate drive unit 1100 may also include signal processing circuitry, such as temperature sensing modulator (also known as TS (temperature sensing) modulator) 1102, which is adapted to generate temperature report signal TSO based on temperature readout signal (e.g., temperature sensing voltage VTSI across temperature sensor 1101 shown in FIG. 11).

[0065] According to an exemplary embodiment, similar to gate drive unit 1000, gate drive unit 1100 may be configured to have a first reporting state for the reporting signal RPT during normal operation (e.g., no substantially non-ZVS condition is identified and no fault event such as a short circuit is detected), wherein the first reporting state includes or is embodied in the temperature reporting signal TSO in this particular example. Gate drive unit 1100 may also be configured to set the reporting signal RPT to a second reporting state (e.g., embodied as a logic high signal in one embodiment) according to the ZVS indication signal FLAG when gate drive unit 1100 identifies a substantially non-ZVS condition. Gate drive unit 1100 may also be configured to set the reporting signal RPT to a third reporting state (e.g., embodied as a logic low signal in one embodiment) according to the fault indication signal FLT when a fault event (e.g., a short circuit event SC) is detected. Those skilled in the art can still understand this by referring to the illustrations in the example of FIG12. In one embodiment, the signal processing circuit (or TS modulator) 1102 may also be configured to provide a signal SP based at least in part on the temperature reporting signal TSO, the ZVS indication signal FLAG, and the fault indication signal FLT, for setting the reporting signal RPT to a first reporting state, a second reporting state, or a third reporting state.

[0066] In an exemplary embodiment, for a gate drive unit 1000 provided with isolation circuit 104, the report terminal 18 may be provided on the primary side of the gate drive unit 1100, which is suitable for power conversion applications capable of handling high power or high voltage. The TSI terminal 19 and signal processing circuitry may be provided on the secondary side of the gate drive unit 1100. In this case, the isolation circuit 104 in the gate drive unit 1100 may further include a second isolation transmission channel CH2. The gate drive unit 1100 can transmit the signal SP to the primary side via the second isolation transmission channel CH2 to set the report signal RPT to a first report state, a second report state, or a third report state.

[0067] The advantages of the various embodiments of the present invention are not limited to those described above. These and other advantages of the various embodiments of the present invention will become more apparent after reading the entire detailed description and studying the various figures in the accompanying drawings.

[0068] In summary, this application has described specific embodiments of the invention for illustrative purposes, but various modifications can be made without departing from the technical specifications. Multiple elements of one embodiment may be combined with other embodiments to supplement or replace elements of other embodiments. Therefore, the invention is not limited to the scope of the appended claims.

[0069] 11: First terminal 12: Second terminal 13: Third terminal 14: Fourth terminal 15: Fifth terminal 16: Sixth terminal 17: Seventh terminal 18: Reporting Terminal 19: Temperature sensing input terminal, TSI terminal 100: Gate drive unit 101: Drive switching device, switching device 102: Drive control circuit 103: Driver 104: Isolation Circuit 105: Primary control circuit 141: First fault detection and / or fault protection circuit 200: Waveform Diagram 300: Power conversion device 400: Waveform Diagram 405: Primary control circuit 500: Waveform Diagram 600: Gate drive unit 700: Gate Drive Unit 800: Gate Drive Unit 900: Gate drive unit 1000: Gate drive unit 1002: Drive control circuit 1031: First drive switch 1032: Second drive switch 1051: Primary fault detection and / or fault protection circuit 1052: Primary control signal processing circuit 1100: Gate drive unit 1101: Temperature sensor 1102: Temperature sensor modulator, TS modulator 1200: Waveform Diagram 4052: Primary control signal processing circuit 301_1: First Switch 301_2: Second Switch 302_1: First gate drive unit 302_2: Second gate drive unit B: First Detection Event C1: First capacitor C2: Second capacitor C3: Third capacitor CH1: Isolated Transmission Channel CH2: Second Isolation Transmission Channel Co: Capacitive energy storage device CPWM: Pulse Width Modulation Signal D: First end DROUT: Switching drive signal DTS: Duty Cycle EN_MCZVD: First ZVD time window control signal FLAG: ZVS indicator signal FLT: Fault Indication Signal FMCZVD: First Flag Signal G: Control Terminal GND: Primary reference ground IMC: Miller Current IMCVL: Valley Value IN: Primary control terminal IN-: Inverting input terminal IN+: Non-inverting input Io: Current signal Ith1: First predetermined critical value Ith2: Second predetermined critical value Ith3: Third predetermined critical value ITS: Temperature Sensing Current Lo: Inductive energy storage device MCZVD: First Detection Event N1: First power node N2: Second power node N3: Common connection point OUT-: Inverting output terminal OUT+: Non-inverting output terminal PGND: System ground terminal PO: Power conversion output terminal PS: System power supply PWMIN: Gate control signal PWMIN-: Second gate control signal PWMIN+: First gate control signal RG: Resistor device RPT: Report Signal RSNK: Second resistor RSRC: First resistor S: Second end SC: Short circuit event SP: Signal SW: Shared Node t0: Reset time, time t1: Time t11: Time t12: Reset time, time t17: Time t2: Time t22: Time t3: Time t4: Reset time, time t5: Time t6: Time t7: Time t8: Reset time, time td1: Delay tdd: Internal time delay tMCZVD_LEB: Positive edge occlusion time TSO: Temperature Reporting Signal Tsw: Switching cycle TTS: Pulse Width tZVD_WAIT: Maximum ZVD time period UVLO1: First undervoltage protection circuit UVLO2: Second undervoltage protection circuit V13: Voltage VBUS: System power supply voltage VCC: Second power supply voltage VDD: First power supply voltage VDS: Voltage drop VEE: Reference ground potential Vo: Stable voltage VTSI: Temperature Sensing Voltage VUV1: First undervoltage threshold VUV2: Second undervoltage threshold WMCZVD: First ZVD Time Window ZVD: Zero Voltage Detection

Claims

1. A gate drive unit, comprising: The first terminal is configured as a control terminal for receiving pulse width modulation signals with set logic state and reset logic state; The second terminal is configured as a reference ground terminal; The third terminal is configured as the output terminal of the gate drive unit to provide a switching drive signal, the switching drive signal having a logic state including a drive setting logic state and a drive reset logic state; wherein, the gate drive unit is further configured to detect a current signal flowing through the third terminal and to control the logic state of the switching drive signal based on the pulse width modulation signal and the current signal.

2. The gate drive unit as described in claim 1 is further configured to: reset the switching drive signal to a drive reset logic state in response to the pulse width modulation signal changing from a set logic state to a reset logic state.

3. The gate drive unit as claimed in claim 1, further configured to: determine, based on the current signal, whether a first detection event is identified during a first detection time window, wherein the first detection time window has a first window width and is enabled during the period when the switching drive signal is in a drive reset logic state.

4. The gate drive unit as described in claim 3, further configured to: set the switching drive signal to drive the setting logic state when the first detection event has been identified during the first detection time window and the pulse width modulation signal is in the setting logic state.

5. The gate drive unit as described in claim 3, further configured to: determine that the first detection event has been identified during the first detection time window if the current signal rises to or exceeds a first predetermined threshold and then falls back to or below a second predetermined threshold during the first detection time window.

6. The gate drive unit as described in claim 3 is further configured to enable the first detection time window after a first predetermined positive edge masking time, starting from the moment when the switching drive signal changes from its drive setting logic state to its drive reset logic state.

7. The gate drive unit as described in claim 3, further configured to: enable a maximum detection time period in response to the pulse width modulation signal changing from a reset logic state to a set logic state, and if the first detection event is not detected until the end of the maximum detection time period, set the switching drive signal to drive the set logic state.

8. The gate drive unit as described in claim 3, further configured to: enable a maximum detection period in response to the pulse width modulation signal changing from a reset logic state to a set logic state; and determine that a substantially non-zero voltage switching is detected when at least one of the following conditions is met: during the switching cycle of the switching drive signal, the moment when the first detection event is detected is earlier than the moment when the pulse width modulation signal changes from a reset logic state to a set logic state; or during the switching cycle of the switching drive signal, after the first detection event is detected, a second detection event is further detected in which the current signal drops to or below a third predetermined threshold; or the first detection event is not detected until the end of the maximum detection period.

9. The gate drive unit as claimed in claim 1, further configured to include a reporting terminal configured to provide a reporting signal.

10. The gate drive unit as described in claim 9, further configured to set the report signal to a first report state during normal operation.

11. The gate drive unit as described in claim 10, further configured to set the report signal to a second report state when a substantially non-zero voltage switching condition is detected.

12. The gate drive unit as described in claim 10 is further configured to set the report signal to a third report state when a short-circuit event is detected.

13. The gate drive unit as described in claim 10, further configured to: set the report signal to a second report state when a substantially non-zero voltage switching condition is detected, and set the report signal to a third report state when a short-circuit event is detected, wherein, The first report status, the second report status, and the third report status are different from each other.

14. The gate drive unit as claimed in claim 11 is further configured to determine that a substantially non-zero voltage switching is detected when at least one of the following conditions is met: During the switching cycle of the switching drive signal, the gate drive unit detects a first detection event earlier than the time when the pulse width modulation signal changes from a reset logic state to a set logic state; or during the switching cycle of the switching drive signal, after detecting the first detection event, a second detection event is further detected where the current signal drops to or below a third predetermined threshold; or the first detection event is not detected from the time the pulse width modulation signal changes from a reset logic state to a set logic state until the end of the maximum detection time period.

15. The gate drive unit as claimed in claim 12, further configured to determine that the short-circuit event is detected when at least one of the following conditions is met: during the switching drive signal being in a drive setting logic state, the current signal flows into the third terminal for a predetermined short-circuit detection time, or during the switching drive signal being in a drive setting logic state, the voltage on the third terminal is higher than the first power supply voltage on the fourth terminal of the gate drive unit.

16. The gate drive unit as described in claim 10, further comprising: The temperature sensing input terminal is configured to detect temperature readout signals; The gate drive unit is further configured to provide a temperature reporting signal having a pulse width modulated by the temperature read signal; wherein the gate drive unit is further configured to set the reporting signal to the first reporting state during normal operation, at which time the reporting signal represents the temperature reporting signal.

17. The gate drive unit as described in claim 16, further configured to: when the gate drive unit detects a substantially non-zero voltage switching condition, set the report signal to a second report state, the second report state being different from the first report state.

18. The gate drive unit as described in claim 16 is further configured to set the report signal to a third report state when a short-circuit event is detected.

19. The gate drive unit as described in claim 16, further configured to: set the report signal to a second report state when the gate drive unit detects a substantially non-zero voltage switching condition, and set the report signal to a third report state when the gate drive unit detects a short-circuit event, wherein, The first report status, the second report status, and the third report status are different from each other.

20. The gate drive unit as claimed in claim 1, wherein, When the switching drive signal is in the drive setting logic state, the gate drive unit is also configured to determine that it has detected the short circuit event when at least one of the following conditions is met: the current signal flows into the third terminal for a predetermined short circuit detection time, or the voltage on the third terminal is higher than the first power supply voltage on the fourth terminal of the gate drive unit.

21. The gate drive unit as described in claim 20, further configured to reset the switching drive signal to a drive reset logic state when the short-circuit event is detected.

22. The gate drive unit as claimed in claim 1, wherein the third terminal of the gate drive unit includes a non-inverting output and an inverting output; the non-inverting output is adapted to be coupled to a common drive connection node with or without a first resistor; The inverting output terminal is suitable for coupling to a common drive connection node with or without a second resistor; The shared drive connection node is configured to provide the switching drive signal; The current signal flowing through the third terminal is detected at the inverting output terminal.

23. The gate drive unit of claim 22, wherein the non-inverting output is configured to set the switching drive signal to a drive setting logic state when an assertion logic high is made at the non-inverting output; and is further configured to have a high impedance state when the switching drive signal is reset to a drive reset logic state; the inverting output is configured to reset the switching drive signal to a drive reset logic state when an assertion logic low is made at the inverting output; and is further configured to have a high impedance state when the switching drive signal is set to a drive setting logic state.

24. The gate drive unit as described in claim 1, further comprising: The fourth terminal is configured as the first power supply terminal of the gate drive unit for providing a first power supply voltage.

25. The gate drive unit as described in claim 1, further comprising: An isolation circuit is configured to provide electrical isolation between the primary and secondary sides of the gate drive unit; A fifth terminal is disposed on the primary side and configured to receive a gate control signal; the first terminal, the second terminal, and the third terminal are disposed on the secondary side; the isolation circuit includes a first signal isolation and a transmission channel, the first signal isolation and the transmission channel being configured to couple the fifth terminal to the first terminal for transmitting the gate control signal as the pulse width modulation signal to the secondary side.

26. The gate drive unit as claimed in claim 25, further comprising: The sixth terminal is located on the primary side and is used as the primary side reference ground terminal of the primary side circuit of the gate drive unit. And a seventh terminal, which is disposed on the primary side and is used as the primary power supply terminal of the gate drive unit.

27. The gate drive unit as claimed in claim 25, wherein, The fifth terminal includes a non-inverting input and an inverting input, wherein the non-inverting input is adapted to receive a first gate control signal, and the inverting input is adapted to receive a second gate control signal; wherein the first gate control signal and the second gate control signal together determine the gate control signal.

28. The gate drive unit as claimed in claim 27, wherein the isolation circuit is omitted and the gate control signal is provided as the pulse width modulation signal.

29. The gate drive unit as claimed in claim 25, further comprising: A reporting terminal, located on the primary side, is used to provide a reporting signal.

30. The gate drive unit as claimed in claim 29, further comprising: A temperature sensing input terminal is located on the secondary side for detecting temperature reading signals; The gate drive unit is further configured to provide a temperature reporting signal having a pulse width modulated by the temperature read signal; the gate drive unit is further configured to set the reporting signal to a first reporting state during normal operation, at which time the reporting signal represents the temperature reporting signal.

31. The gate drive unit as claimed in claim 1, wherein, The third terminal is coupled to the control terminal of the switching device, and the current signal includes the Miller current flowing through the control terminal of the switching device and represents the rate of change of voltage drop across the switching device.

32. A gate drive unit, comprising: The first terminal is configured as a control terminal; The second terminal is configured as a reference ground terminal; The third terminal is configured as the output terminal of the gate drive unit; The fourth terminal is configured as the power supply terminal of the gate drive unit; wherein the gate drive unit is configured to provide a switching drive signal through the third terminal, the switching drive signal having a logic state including a drive setting logic state and a drive reset logic state, and the gate drive unit is further configured to identify the operating state of the gate drive unit based on the current signal flowing through the third terminal.

33. The gate drive unit as claimed in claim 32, further configured to control the logic state of the switching drive signal based on the current signal and the pulse width modulation signal received at the first terminal.

34. The gate drive unit as described in claim 32, further comprising: The report terminal is used to provide report signals indicating the operating status.

35. A gate drive unit, comprising: The first terminal is configured as a control terminal for receiving pulse width modulation signals with set logic state and reset logic state; The second terminal is configured as a reference ground terminal; The third terminal is configured as the output terminal of the gate drive unit, and is used to provide a switching drive signal having a logic state including a drive setting logic state and a drive reset logic state. and a reporting terminal for providing a reporting signal; wherein the gate drive unit is configured to detect a current signal flowing through the third terminal and is further configured to adjust the fault reporting signal based on the current signal.

36. The gate drive unit as described in claim 35, further configured to set the report signal to a first report state during normal operation.

37. The gate drive unit as described in claim 35 is further configured to set the report signal to a second report state when a substantially non-zero voltage switching condition is detected.

38. The gate drive unit as described in claim 35, further configured to set the report signal to a third report state when a short-circuit event is detected.

39. The gate drive unit of claim 37 is further configured to determine that a substantially non-zero voltage switching is detected when at least one of the following conditions is met: The first detection event indicating that the current signal flows out of the third terminal and then substantially drops to zero is detected during the switching drive signal being in a drive reset logic state earlier than the moment when the pulse width modulation signal changes from the reset logic state to the set logic state during the switching cycle of the switching drive signal; or, within the switching cycle of the switching drive signal, after the first detection event is detected, a second detection event indicating that the current signal flows into the third terminal is detected; or, the first detection event is not detected from the moment the pulse width modulation signal changes from the reset logic state to the set logic state until the end of the maximum detection time period.

40. The gate drive unit as claimed in claim 38, further configured to determine that the short-circuit event is detected when at least one of the following conditions is met: during the switching drive signal being in a drive setting logic state, the current signal flows into the third terminal for a predetermined short-circuit detection time, or during the switching drive signal being in a drive setting logic state, the voltage on the third terminal is higher than the first power supply voltage on the fourth terminal of the gate drive unit.

41. The gate drive unit as described in claim 35, further configured to control the logic state of the switching drive signal based on the pulse width modulation signal and the current signal.

42. The gate drive unit as described in claim 41 is further configured to reset the switching drive signal to the drive reset logic state when the pulse width modulation signal changes from a set logic state to a reset logic state.

43. The gate drive unit as claimed in claim 41, further configured to: if a first detection event indicating the current signal flowing from the third terminal and then substantially decreasing to zero is detected during a first detection time window and the pulse width modulation signal is in a setting logic state, then set the switching drive signal to a drive setting logic state, wherein the first detection time window has a first window width and is enabled during the drive reset logic state of the switching drive signal.

44. The gate drive unit as claimed in claim 41, wherein: The gate drive unit is further configured to set the switching drive signal to drive the set logic state if neither a first detection event indicating a current signal flowing from the third terminal and then substantially decreasing to zero is detected during the first detection time window, nor a first detection event indicating a current signal flowing from the third terminal and then substantially decreasing to zero is detected from the moment the pulse width modulation signal changes from the reset logic state to the set logic state until the end of the maximum detection time period; wherein the first detection time window has a first window width and is enabled during the period when the switching drive signal is in the drive reset logic state.

45. The gate drive unit as claimed in claim 35, further comprising: The temperature sensing input terminal is configured to detect temperature readout signals; The gate drive unit is further configured to provide a temperature reporting signal having a pulse width modulated by the temperature read signal; the gate drive unit is further configured to set the reporting signal to a first reporting state during normal operation, at which time the reporting signal represents the temperature reporting signal.

46. ​​The gate drive unit as claimed in claim 35, further configured to determine that the short-circuit event is detected when at least one of the following conditions is met: the current signal flows into the third terminal for a predetermined short-circuit detection time during the period when the switching drive signal is in the drive setting logic state, or the voltage on the third terminal is higher than a first power supply voltage on the fourth terminal of the gate drive unit during the period when the switching drive signal is in the drive setting logic state; wherein, The gate drive unit is also configured to reset the switching drive signal to a drive reset logic state when the short-circuit event is detected.